Kreatryx Digital Circuits PDF

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Contents
Manual for K-Notes ................................................................................. 2
Number Systems and Boolean Algebra ................................................... 3
Combinational Logic Circuits ................................................................. 12
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Sequential Logic Circuits ....................................................................... 15
A/D and D/A Converters ....................................................................... 25
w.E
Microprocessor ..................................................................................... 31
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g.n
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© 2015 Kreatryx. All Rights Reserved.

Manual for K-Notes
Why K-Notes?
Towards the end of preparation, a student has lost the time to revise all the chapters
from his / her class notes / standard text books. This is the reason why K-Notes is
specifically intended for Quick Revision and should not be considered as comprehensive
study material.
ww What are K-Notes?
w.E
A 40 page or less notebook for each subject which contains all concepts covered in GATE
Curriculum in a concise manner to aid a student in final stages of his/her preparation. It
asy
is highly useful for both the students as well as working professionals who are preparing
En
for GATE as it comes handy while traveling long distances.
gin
When do I start using K-Notes?
(November end onwards). ee

It is highly recommended to use K-Notes in the last 2 months before GATE Exam
rin
How do I use K-Notes?
g.n
et
Once you finish the entire K-Notes for a particular subject, you should practice the
respective Subject Test / Mixed Question Bag containing questions from all the Chapters
to make best use of it.
© 2015 Kreatryx. All Rights Reserved.

Number Systems and Boolean Algebra

 Decimal : Radix = 10; Symbols = (0, 1, 2, 3…………9)
 Binary : Radix = 2; Symbols = (0, 1)
 Hexadecimal : Radix = 16; Symbols = (0, 1, 2……………., 9, A, B,……………., F)
 Octal : Radix = 8; Symbols = (0, 1, 2, …………….., 7)
For radix N, following digits are possible
ww 
(0, 1, 2, ………………, N-1)
To convert a number from radix ‘x’ to bare 10 or decimal.
w.E  
Eg. 136 x   ? 10  1.x2  3.x  6.x0  x2  3x  6
asy
Complimentary Number Representation
En
A – B = A + (- B)  A   compliment of  B 
For a base – r system

gin
r  1 's compliment  rn  r m  N
r 's compliment  rn  N
ee rin
Where r = base g.n
N = given number
n = no. of digits in integer part of N

et
m = no. of digits in decimal part of N
eg. For 378.67 10
N = 378.67 ; m = 3 ; n = 2 ; r = 10

Boolean Algebra
 Compliment
0 1
10
Represented as A  A
ww  
And A  A
w.E AND function
0.0  0 A.A  A
0.1  0
1.0  0
asy A.1  A
A.0  0
1.1  0
En A.A  0
 OR Function
gin
00 0
0 1  1
10 1
ee AAA
A 1  1
A0  A rin
11  1 AA 1
g.n
Laws of Boolean Algebra
1) Commutative Law
et
OR  A  A  B  A
AND  AB  BA
NAND  AB  BA
2) Associative Law
OR   A  B   C  A  B  C 
AND   A B  C  A B C 

3) Consensus Law
AB  AC  BC  AB  AC
4) Distributive Law
A. B  C   AB  AC
.
.
ww Dual : Convert all

10
0 1
w.E A + (BC) = (A+B)(A+C)
5) De – Morgan’s Law
 asy
NOR operation is same as bubbled AND
En
A  B  C...................  A.B.C..............

gin
NAND operation is same as bubbled OR
6) Transposition Law
ee
A  B  C...................  A  B  C..............
rin
A.B  AC   A  C   A  B 
g.n
Operator precedence
1) Parenthesis
et
2) NoT
 Decreasing priority
3) AND
4) OR
Minterms, Maxterms & Properties
Minterm : It is a standard product term i.e. a product term which contains all variables of a given
function either in normal form or compliment form.
Maxterm : it is standard sum term i.e. a sum term which contains all the variables of the function
either in normal or compliment form.

F (A, B, C) = min terms F  A,B,C   max terms

ABC=m  0,0,0  A+B+C=M
0 7
ABC=m  0,0,1  A+B+C=M
1 6
ABC=m 1,1,1  A+B+C=M
7 0
Properties

1) n – variable function  2n minterms & 2n max terms 
ww2) M  m & m  M
j j j j
w.E
3) m  M 2n 1i ; M  m 2n 1i ; D = indicates dual
iD   iD  
4)
a)
2n  1
 mi  1
asy
i0
En
b)
2n  1
j0
m 0
j gin
ee
Note : The output of XOR and XNOR gate contains half the total number of minterms.
rin
Forms of Boolean function
1) Sum of product (SOP) form = DNF (Distinjunctive Normal Form) g.n

2) Canonical SOP form = DCF (Disjunctive Canonical Form)
3) Product of sum (POS) form = CNF (Conjunctive Normal Form)
4) Canonical POS form = CCF (Conjunctive Canonical Form)
et
Eg. Convert F  A,B,C  A  AC  ABC to Canonical SOP form :
F  A  AC  ABC
 ABC  ABC  ABC  ABC  ABC  ABC

     
m m m m m m
0 1 2 3 4 6

F   m  0,1,2,3, 4,6   canonical SOP form
 M 5,7   canonical POS form
Karnaugh Map
3 – variable K – map
Octant  group of 8 minterms
ww
Quad  group of 4 min terms
w.E
Pair  group of 2 min terms
4 – variable k – map
All corners of k – map asy

(0, 2, 8, 10)  Quad En
gin
ee rin
g.n
Eg. F  A,B,C,D   m 0,1, 4,5,6,8,9,10,12,14,15
et
F  AC  AD  BD  BC  ABC

Eg. F  A,B,C   M  0,1,2,3, 4,7 

F  A B  C  B  C 
Implicant : it is the set of all adjacent min terms
ww Eg. Pair, quad, octants
w.E
Prime Implicant : It is an implicant which is not a subset of another implicant.
asy
Essential PI (EPI) : It is a prime implicant which contains at least one min terms which is not
covered by other prime implicant.
1) PI,Non PI
2) PI, EPI En
3) PI, EPI
4) PI, EPI
gin
5) PI, EPI
ee rin
Don’t care condition g.n
et
In a digital system, for a non – occurring input, the output can be taken as either one or zero
during simplification & it is called don’t care condition.
Eg. X  A,B,C,D   m 0,1  d 10,11,12,13,14,15 ;
X  ABC

Logic Gates
1) Equivalence Gate = Ex – NOR Gate
A B F
0 0 1
0 1 0
1 0 0
ww 1 1 1
F  A  B  AB  AB
w.E
2) Staircase connection = Ex – OR Gate
A B F
0 0 0 asy
0 1 1
1 0 1 En
1 1 0
gin
F  A  B  AB  AB

ee
In Ex – OR, output = 1 if input has odd no. of 1’s rin
 In Ex – NOR, output = 1, if input has even no. of 1’s
g.n
3) Inverter
A F
et
0 1 FA
1 0

4) AND GATE
A B F
0 0 0
0 1 0
1 0 0
1 1 1
ww
5) OR GATE
F=A.B
w.E A B F
0
0
0
1
0
1 asy
1
1
0
1 1
1
En
F=A+B gin
6) NAND GATE
A B F
ee rin
0 0 1
0 1 1 g.n
1 0 1
1 1 0
et
F  AB
This gate is equivalent to
10

7) NOR GATE
A B F
0 0 1
0 1 0
1 0 0
1 1 0
ww F  A B
This gate is equivalent to
w.E
asy
CODES :-
En
1) Binary coded decimal code (BCD) :-
gin
a) Each digit of decimal number is represented by binary equivalent.
b) It is 4 bit binary code.
c) eg.  943
decimal

9 4 3
1001 0100 0011
ee rin
 94310  100101000011 2
g.n
2) Gray Code :-
a) Only one bit in the code group changes when going from one step to the next.
et
b) For 3-bit
000  001  011  010  110  111  101  100
11

Combinational Logic Circuits
1) Half Adder
A B S C
0 0 0 0 S  A B
0 1 1 0 C  AB
1 0 1 0
1
ww 1 1 1 1 Half adder = 1 XOR Gate & 1 AND Gate

 w.E
To implement a half adder using NAND Gates, 5 NAND Gates are required.
To implement a half adder using NOR Gates, 5 NOR Gates are required.
2) Half Subtractor
A B D B
asy
0 0 0 0 D  A BEn
0
1
1
1
0
1
1
1
0
1
0
0
gin
B  A B  borrow

ee
To implement a half sub tractor 5 NAND or 5 NOR Gates are required.
rin
g.n
et
12

3) Full Adder :-
A B C S C
i i1
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1
1
1
ww
0
1
1
1
0
1
0
0
1
1
1
1
w.E
C = Carry input
i
C
i1
= Carry Output asy
S  A B  C
En
C
i1
 AB  BC  AC
i i
gin

4) Full Subtractor:-
ee
To implement full adder using NAND & NOR Gates 9 Gates are required.
rin
A B b
i D b
iH g.n
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
et
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
D  A B b
i
bi1  AB  Bbi  Abi
 To implement full sub tractor using NAND or NOR Gates 9 Gates are required.
13

Magnitude Comparator
For 2 bit Magnitude comparator
A  A1 A0 ; B  B1B0
A1 A0 B1 B0 A B A B A B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0
0ww 0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
w.E1
1
1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
asy
1
0
1 0 0 1 1 0 0
En
1
1
0
0
1
1
0
1
1
0
1
0
0
1 gin
1
1
1
1
1
1
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
ee rin
1 1 1 1 0 1
 A  B    A1  B1  .  A0  B0 
0
g.n
 A  B  A B   A
1 1 1
B1  A 0B0 et
 A  B  A B   A
1 1 1
B1  A 0B0
Decoder
2 – 4 decoder
 Active high output

0AB
1AB
2AB
3AB
14

 Active low output
0  A B
1  AB
2  A B
3  AB
 Each output of a decoder with active high output represents a min term & hence it can be used
 ww
to implement any SOP expression.
Each output of a decoder with active low output represents a max term and hence can be used
to implement any POS expression if AND Gate is used and SOP expression if NAND Gate is used.
w.E
Multiplexer
4 – 1 MUX
asy
F  ABI0  ABI1  ABI 2  ABI 3 En
2n  1 MUX requires n – select lines.
gin

ee rin
A 2n : 1 MUX can be used to implement any SOP expression with (n+1) variable with n variables
applied at select lines & n  1 th variable & its complement & 1 & 0 serve as input to MUX.
 
g.n
Sequential Logic Circuits
1) SR Latch
et
S R Q
n1
0 0 Qn
0 1 0
1 0 1
1 1 0
 S=1, R=1 and Qn+1=0 is impractical state
15

2) S R Latch
S R Q
n1
0 0 1
0 1 1
1 0 0
1 1 Q
n
 ww
S=1, R=1 and Qn+1 =1 is impractical state
w.E
3) Clocked SR Flip Flop
asy
En
gin
ee rin


When ClK = 0, the flip flop retains its previous state.
When ClK = 1
g.n
S R Q
n1
et
0 0 Qn
0 1 0
1 0 1
1 1
Ambiguous state
 Characteristics equations : Q  S  R.Q

n1 n
16

4) J – K Flip Flop
To convert SR flip flop to a JK flip flop.

S  j Q ; R  KQ
Characteristics equation
Q  jQ K Q
ww n1 n n
w.E
asy
J
0
K
0
Q
Qn
n1
En
0
1
1
0
1
0 gin
1 1 Q
n
ee rin
5) D – Flip Flop
g.n
et
D Qn+1
0 0
1 1
Characteristics equation Q D
n1
17

6) T – Flip Flop
T Qn+1 Characteristics equation

0
1 ww Qn
Q
n
Q
n1
 TQ
n
w.E
Asynchronous or direct input
asy
CLK P C Q En
0
0
0
1
r
1
0
r
1
0
n1
gin
1 1 1
ee rin
o\p depends on characteristic table of flip-flop
Types of Triggering
g.n
Preset and clear input when enabled set or reset the flip flop irrespective of the state of clock.
1) Level Triggered FF et
2) Edge Triggered FF
a) +ve edge triggered
b) – ve edge triggered
18

 Level triggered FF are called as latch and edge triggered FF are called as Flip Flops.
Race around Condition
 When a FF is in toggle mode, then due to propagation delay of gates involved in

construction of FF, output toggles multiple times instead of once & this is called as Race
around condition.
 This only occurs in level triggered FF.
 To avoid this problem, Master – slave configuration is used.
ww
Note: Whenever a FF is in toggle mode, output frequency is half of input frequency.
Applications of FF
w.E
1) Shift Register
asy
En
gin
ee rin
3 – bit shift Register g.n
Q Q Q  parallel output
2 1 0
P P P  parallel input
2 1 0
et
1) Serial input parallel output (SIPO)
ClK serial i / p Q2 Q1 Q0
0  0 0 0
1 1 1 0 0 Parallel output
2 0 0 1 0
3 1 1 0 1
For n – bit, time taken = nxT T=clock period
19

2) Serial input serial output (SISO)
ClK serial o / p Q2 Q1 Q0
0  0 0 0
1 1 1 0 0
2 0 0 1 0 Serial output
3 1 1 0 1
4   1 0
ww 5    1
w.E
For n – bits, time taken = (2n - 1)T, T = clock period
asy
3) Parallel input parallel output (PIPO)
En
Parallel input can be fed to register using preset enable and for input to propagate to parallel
output, it does not require any clock pulse.
4) Parallel input serial output (PISO)

gin
Suppose P P P  101 2
2 1 0
ee rin
ClK Q2 Q1 Q0 g.n

1
2
1


0
1

1
0
1
Serial output
et
For n – bits, (n-1) clock cycles are required.
20

COUNTERS
Asynchronous Counters
 Different ff are applied with different clocks.

 No. of stages in a counter are called as modules of a counter.
MOD – 5 Counter = 5 Stages
 n
2 N
ww N = no. of bits or no. of flip flop required

N = no. of stages in a counter
w.E
 If MOD – M and MOD – N counter are cascaded, resultant counter is MOD – (MN)
Ripple Counter
asy
En
gin
ClK Q
0 0
2
Q
0
1
Q
0
o
ee rin
1
2
0
0
0
1
1
0
g.n
3
4
0
1
1
0
1
0
et
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
This is a MOD – 8 up counter

In a n – bit ripple counter, propagation delay of each ff is t , then time period of ClK is
pd ff
1 1
t  nt => fClK  , f 
ClK pdff nt max n  t
pdff pdff
21

Note:
i) –ve edge trigger  Q as clock  up counter
ii) +ve edge trigger  Q as clock  up counter
iii) –ve edge trigger  Q as clock  down counter
iv) +ve edge trigger  Q as clock  down counter
BCD Counter (Decade Counter)


ww
4 Flip flops are required.
w.E
asy
En
gin
This counter counts from 0000 – 1001
ee rin
And as soon as count is incremented to 1010, then CLR input of ff is asserted and all ff are reset
to 0 and count again becomes 0000, so this counter counts from 0 – 9.
Ring Counter (Synchronous Counter)

g.n
The last FF output is connected to first FF input. et
22

ClK Q Q Q
2 1 0
0 0 0 0
1 0 0 1
2 1 0 0
3 0 1 0
4 0 0 1
A n – bit synchronous counter has n – status.
ww
Johnson Counter (Twisted Ring Counter)
w.E
asy
En
gin
ClK Q
0
1
0
1
2
Q
0
0
1
Q
0
0
0 ee rin
2
3
1
1
1
1
0
1
g.n
4
5
0
0
1
0
1
1
et
6 0 0 0
A n – bit Johnson counter has 2n states.

T = (2n) TCLK
Synchronous counter design for given sequence
 Suppose counting sequence is 0  3  1  2  0

 Using positive edge triggered D – FF
23

State diagram
ww
w.E
Excitation Table
Present state Next State D1 D0
Q
1
Q
0 Q
1
asy
Q
0
0
1
0
1
1
0
1
1 En 1 1
0 1
0
1
1
0
1
0
0
0
gin 1 0
0 0
D Q ; D Q
1 1 2 1
Q
0
ee rin
g.n
et
24

Conversion of different flip flops
From SR JK D T
Flip Flop Flip Flop Flip Flop Flip Flop
SR FF - S  JQ S=D S  TQ
R=kQ R D R = TQ
JK FF J=S - J=D J=T
K=R K D K=T
D FF - D  TQ
ww
T FF
D  S  RQ
T  SQ  RQ
D  JQ  kQ
T  JQ  kQ T DQ -
w.E
A/D and D/A Converters
Digital to Analog Converter (DAC)
asy
 Resolution
En
gin
The change in analog voltage corresponding one LSB increment in digital input.
 Re solution 
n
V
r
2 1 ee rin
V = reference voltage corresponding to logic 1
r
N = no. of bits g.n
V
analog
 Re solution  Decimal equivalent of binary i / p
et

1
%resolution   100%
n
2 1
 Resolution of R – 2R ladder type DAC is
V
Re solution  r
2n
25

1) Weighted Resister DAC (4 - bit)
ww
w.E V
3 R 3
V
2 2R 2
V
1 4R 1 0 8R
V
I  r b ; I  r b ; I  r b ; I  r b
0
0 3 2 1 0 f 
V
asy
8R f 0 1 
V   I  I  I  I R  r R b  2b  4b  8b
2 3
  En
LSB Resistance = 2n  1 MSB Resistance
2) R – 2R ladder
gin
a) 3 – bit Non – inverting R – 2R ladder
ee rin
g.n
et
 R  V n1  R 
V  1  f  V  r  2i b  1  f 
0  R  x 2n i R 
 1  i0  1 
 Resolution  Decimal  gain
26

b) 3 – bit R – 2R Inverting ladder
ww
w.E
V n1  R 
asy
V  r   2i b 
0
2n
i0  i
f 
i R R 
 En
gin
Analog to Digital Converter (ADC)
a) Counter Type ADC

ee rin
g.n
et

Maximum number of clock pulse required for n – bit conversion is 2n  1 

Maxm Conversion time = 2n  1 T 
CLK
27

b) Parallel Comparator Type

 n 
 2  1  comparators required


 For n – bit 2n resistors required
 n
2  n priority encoder

 This is called as Flash ADC.
ww
w.E
asy
En
gin
ee rin
g.n
et
 Fastest ADC of all
 For SAR & Dual slope ADC, refer EMMI K – Notes.
28

Logic Families
1) RTL (Resistor Transistor Logic)
(Wired AND Logic)
ww
w.E
asy
En (Basic NOR Gate)
gin
A B T
1
T
2
V
0
ee rin
0 0
0 1
cut  off
cut  off
cut  off
saturation
1
0 g.n
1 0 saturation cut  off
1 1 saturation saturation
0
0 et
2) DTL (Diode Transistor Logic)
29

A B T Y
1
0 0 OFF 1
0 1 OFF 1 NAND Gate
1 0 OFF 1
1 1 ON 0
 When all input are high then D & D are reverse biased and D , D . Become forward biased
A B 1 2
ww
and T becomes ON and output becomes low.
1
w.E
3) TTL (Transistor Transistor Logic)
asy
En
gin
ee rin
g.n
T : multi – emitter Transistor
1
A B T
1
T
2
T
3
T
4
Y
et
0 0 A C C S 1
0 1 A C C S 1
1 0 A C C S 1
1 1 A S S C 0
A : Active
C : Cut – off
S : Saturation
30

Microprocessor
The 8085 Microprocessor
 It is an 8 bit up (microprocessor)
 It is an 40 – PIN IC
 Its data – bus has 8 bits
 Its address bus has 16 bits
 It is capable of addressing 64 K of memory
ww
Address Bus:



w.E
It is 16 bits of length
It is unidirectional bus.
It is decided in to 2 parts namely
asy
Lower order address bus  A0  A7   is also called ”Line number “
En
Higher order address bus  A8  A15   is also called “page number “
gin
Interrupts and externally initiated operations: -



ee
The 8085 up has 5 interrupts signals that can be used to interrupt a program execution
rin
It also accepts external interrupts to provide acknowledgement (ack) to the external device.
Here TRAP, RST – 7.5, RST – 6.5, RST – 5.5, INTR are called Hardware interrupts.
1. INTR g.n



It is abbreviated as interrupt request
It is used as general purpose interrupt
It has least or 5th priority
et
 It is a non-vectored interrupt
 Address is provided by user or external device
 It is a level triggered signal.
2. INTA
 It is abbreviated as interrupt acknowledge
 It is an output signal.
3. TRAP
 It has highest priority
 It is the only non-maskable interrupt.
31

 It is a vectored interrupt.
 Also called RST 4.5
 This is both edge and level triggered signal.
 Its vectored address =  0024 H
Trick : since it is a RST – 4.5
Hexa  24  0024
So, 4.5 x 8 = 36 
decimal
 H  H
4. RST – 7.5
ww 

Is has 2 nd highest priority
It is maskable interrupt
It is a vectored interrupt.
w.E



It is edge triggered only
It vectored address =  003C H
5. RST – 6.5

asy
It has 3rd highest priority.
 It is a maskable interrupt.
En


It is a vectored interrupt.
It is level triggered. gin

6. RST – 5.5

It vectored address =  0034 H .
If has 4th highest priority.

ee rin


It is a maskable interrupt.
It is a vectored interrupt. g.n


It is level triggered
Its vectored address =  002C H et
8085 Microprocessor Flags
The flags are affected by the arithmetic and logic operations in the ALU :-
In most of these operations the result is stored in accumulator therefore the flags generally
reflect data conditions in the accumulator with some exceptions. The descriptions and
conditions of the flag as follows:
 Sign flag (S) :- After execution of an arithmetic or logic operation, if bit D 7 of the result (usually
in the accumulator ) is 1, the sign flag is set .
32

 Zero Flag (Z) : - The zero flag is set if the ALU operations result in 0, and the flag is reset if the
result is not 0. This flag is modified by the result in the accumulator as well as in other registers.
 Auxiliary carry flag (AC) : - In an arithmetic operation, when a carry is generated by digit D3 and
passed on to digit D4 the AC flag is set.
 Parity Flag (P) : After an arithmetic or logical, operation, if the result has an even number of 1s,
the flag is set. If it has an odd number of 1s, the flag is reset.

ww
Carry flag (CY) : If an arithmetic operation results in a carry, the carry flag is set; otherwise it is
reset.

w.E
asy
En

gin
Among the five flags, the AC flag is used internally for BCD arithmetic the instruction set does
not include any conditional jump instruction based on the AC flag of the remaining four flags,
ee
the Z and CY flags are those most commonly used.
REGISTERS
rin
g.n
General Purpose
Register (GPR)
B (8 bits)
Special Purpose
Register (SPR) et
C (8 bits ) User Not Accessible
User Accessible
D (8 bits)
→ Accumulator (8 bits) → Temporary Register (8 bits)
E (8 bits)
→SR (8 bits)
H( 8bits) → 1 R (8 bits)
→ PC (8 bits)
L (8 bits)
→SP (8 bits)
→ Increment / decrement
address latch (8 bits)
33

 Possible register pairs are :

 B – C (16 bits)
 D – E (16 bits)
 H – L (16 bits)
 Accumulator (A) : -
 It is a 8 – bits SPR and user accessible
ww
 It acts as one source of operand to the ALU and destinations to the result.
 During I/O data transfer, data is transferred between accumulator (A) and I/O device.

w.E
Status register (SR) :-
asy
 It is also called “ Flag registers”
 It is used to store ALU results
En
 “FLAGS” are used for testing of data conditions
 PSW (program status word) = Accumulator + flag register. Also PSW is a 16 bit register.
 Program counter (PC) :-

gin
ee
 It is a a 16 – bit SPR which is accessible
rin
 It is required to keep track of the address of the next instruction to be fetched from the
memory of execution.
g.n
 In other words we can say, PC provides the address of next instruction to memory which has
to be executed
et
 when a byte is fetched then PC automatically incremented by 1 to point to next memory
location.
 when the microprocessor is reset, the PC sets to 0
 Stock pointer :
It is a 16 bit SPR used as memory pointer SP provides the address of stack top or top address of
stack.
 A memory location in R/W memory is called “STACK”. It is a part of RAM, which is used
during subroutines PUSH and POP operations.
34

Instruction Set:
INSTRUCTION SYMBOLIC FORM EXAMPLE MACHINE T-STATE F LAGS

CYCLE AFFECTED
LXI rP , 16 bit Data rp  16 bit data Lx 1H, 2800 H MC=1+2=3 4T + (3T x 2) = NO FLAGS
10T are Affected
(load register pair rh  8 MSB’s of data i.e. |L| ← [00]
immediately) (H) ← [28]
rl  8 LSB’s of data
ww
LDA address (Load
accumulator direct)
A  address LDA 2400 H 1+3=4 4T + (3T x 3) =
13T
No flags are
Affected
(STORE w.E
STA address
accumulator direct)
|[address]| ← |A| STA 2000H MC=1+2+1
=4
4 T + (2x3T) +
3T = 13T
No flags are
affected
LHLD address (load

H – L pair direct)
asy
L  [|address|] LHLD2500 H MC = 1 + 4 4T + (4 x3T) =
16T – states
No flags are
affected
En
H  [|address + 1|]
=5
SHLD address
(Store H – L pair
 address   L
address  1  H gin SHLD 2500 H MC=1+2+2
=5
4T + (2 x 3T) +
(2 x 3T) =16 T
No flags are
affected
direct)
LDAX rP : (Load
accumulator
A  rp ee
LDAX B MC = 1 + 1
=2
states
4T + 3 T = 7T –
rin
States
No flags are
affected
indirect)
STAXrP : (store rp  A STAXD MC = 1 + 1 g.n
4T + 3T = 7T NO Flags
accumator indirect)
XCHG : (Exchange |H – L| ↔ |D – E| XCHG data

=2
MC = 1
et
4T states
are Affected
No flags are
the content of H – Affected
L pair D – E pair)
35


CYCLE AFFECTED
MOV r1 ,r2 (move r1  r2 MOV A, B 1 MC 4 T - STATE NO FLAGS
the content of one Affected
ww
register into
another register )
MOV r, M
w.E
(Move the content
r  M or
r  H  L
MOV B, M MC = 1 + 1
=2
4T + 3T = 7T No flags
Affected
of Memory to
register) asy
MOV M, r
(Move the content
M  r or
H  L  r En MOV M, C MC = 1 + 1
=2
4 T + 3 T = 7T No flags
affected
of register to
memory)
gin
MVI r, data
(Move immediate
r  data ee MVI A, 05 MC = 1 + 1
=2
4T + 3 T = 7 T
rin
No flags
affected
data to register)
g.n
et
36


CYCLE AFFECTED
MVl M, data H  L  data or LXI H, 2400 H MC = 1+ 1 + 1 4 T + 3T+3T No flags
MVl M, 08 = 10T –states are
(move immediate M  data =3
affected
data to memory) HLT  Halt
ww
ADD r (Add register
to accumulator)
A  A  r ADD B MC = 1 4T states All flags
are
w.E
ADC r : (Add
register with carry
A  A  r  cs ADC B MC = 1 4T – states
affected
All flags
are
to accumulator)
asy affected
ADD M : (add
memory to
A  M
or A  En
H  L 
ADD M MC = 1 + 1 =2 4T + 3 T = 7T
– States
All flags
are
accumulator)
ADC M : (add A  A  M  CS gin ADC M MC = 1 + 1 =2 4T + 3 T = 7T
affected
All flags
memory to
accumulator)
or A  A 
ee
H  L  CS
rin
– States are
affected
ADI data : A  A  data ADl 08 MC = 1 + 1 =2 4T + 3T = 7T All Flags

(Add immediate g.n are
Affected
data to
accumulator)
ACI data : |A| ← |A| + data ACI 08 MC = 1 + 1 =2
et
4T +3T = 7T All flags
+ |cs| are
(add with carry
Affected
immediate data to
accumulator)
SUB r : (subtract |A| ← |A| – |r| SUB 08 MC = 1 4T All flags
register from are
accumulator) affected
37


CYCLE AFFECTED
SBB r : (subtract A  A  r  cs MC = 1 4T All flags
register from are
accumulator with affected
Borrow)
SUB M : (subtract A  A  M MC = 1 + 1 =2 4T + 3T =7T All flags
ww
memory from
accumulator)
or A  A   H  L  states are
affected
w.E
SBB M : (subtract
memory from
A  A  M
or A  A   H  L 
MC = 1 + 1 =2 4T + 3 T = 7T
– States
All flags
are
accumulator alone
with borrow) asy affected
SUI data (subtract

immediate data
A  A  data
En MC = 1 + 1 =2 4T + 3 T = 7T
– States
All flags
are
from accumulator)
SBI data (subtract A  A  data  CS
gin MC = 1 + 1 =2 4T + 3T = 7T
affected
All Flags
immediate from
accumulator with
borrow)
ee rin
are
Affected
INR r (increment
register content by
|r| ← |r| + |01| MC = 1
g.n
4T All flags
are
1)
et Affected
except CY
INR M (increment |M| ← |M| + [01] Or MC= 1+1+1=3 4T+3T+3T All flags
memory content by are
[H – L] ← |[H – L]|+ [01] =10T
1) affected
except CY
38


CYCLE AFFECTED
INX rP : (increment rp  rp  0001 INX H MC = 1 4T All flags
the content of INX SP except CY
register pair by 1) INX C are affected
DCR M : M  M  01 MC = 1 + 1 +1 4T + 3T+3T All flags are
(Decrement the =10T affected
ww
content of memory
by 1)
or H  L  H  L  01 =3
except CY
flag
DCX rP:
w.E
(Decrement the
content of Memory
rp  rp  0001 DCX B
DCX SP
MC = 1 6T No flags are
affected
by )1
asy DCX H
DAA : (Decimal
adjust accumulator
DAA
En MC = 1 4T All flags are
affected
after addition)
DAD rP (Double H  L  H  L  rp gin MC = 1 + 2 =3 4T +(2 x 3T) Only carry
addition register
pair)
ANA r: (And |A|←|A|  |r|
ee MC = 1 rin
= 10T
4T – States
(CY) is
affected
All flags are
register with
accumulator) g.n Affected
AC=1,
ANA M : (And
memory with
|A| ← |A|  |M| MC = 1+1 =2
et
4T+3T=7T -
State
CY= 0
All flags are
affected AC
|A| ← |A|  |[H – L]|
accumulator) =1, CY = 0
39

INSTRUCTION SYMBOLIC FORM EXAMPLE MACHINE T-STATE FLAGS

CYCLE AFFECTED
ANI data : (And A  A  data MC = 1+1=2 4T +3T=7T All flags
immediate data affected AC
with accumulator) = 1, CY =0
ORA r (OR register A  A V M MC = 1 4T All flags are
with accumulator) affected CY
ww
ORA M : (OR A  A VM MC = 2 7T
= 0, AC = 0
CY = 0,
w.E
memory with
accumulator)
AC=0
ORI data (or data

immediate with asy
A  A V data MC = 2 7T CY = 0, AC
=0
accumulator)
XRA r : EXOR A  A V r En MC =1 4T All flags are
register with
accumulator gin affected
and AC = 0,
XRA M : EXOR
memory with
A  A V M ee MC =1
rin 4T
CY = 0
All flags are
affected
accumulator
g.n and AC = 0,
CY = 0
XRI data: EXOR
immediate data
with accumulator
A  A V data MC =2 7T
et All flags are
affected AC
=0, CY = 0
CMA : A  A MC = 1 4T No flags are
(Complement with affected
Accumulate)
CMP r: (Compare |A|←|A| – |r| MC = 1 4T All flags are
register with Affected
accumulator)
40


CYCLE AFFECTED
CMP M : (compare |A| ← |A| – |M| MC = 1+1 =2 4T+3T=7T All flags are
memory with affected
accumulator)
CPI data : (compare A  A  data MC =2 4T +3T=7T All flags
immediate data affected
ww
with accumulator)
CMC : CS  CS MC = 1 4T No flags are
w.E
(complement the
carry status)
affected
except carry
flag
STC (Set carry CS  1 asy MC = 1 4T NO flags
status)
En are affected
except CY
RST n: (Restart)  SP  1   PC gin

H
MC = 1+2=3 6T+(3T x
flag
No flags are
 SP  1  PCL
 SP   SP  2
ee rin
2)= 12T –
states
affected
Push rP: (Push the

PC  8 times
SP  1  rh MC =1+2=3 g.n
6T + (3T x No flags are
content of register
pair to stack)
 SP  2
SP  SP  2
 r
et
2) = 12T –
state
affected
POP rP : (POP the r  sp MC =1 +2=3 10T – state No flags are

content of register rh  sp  1 affected
pair which has
sp  sp  2
been saved from
stack)
SPHL : (move the H  L  SP MC = 1 6T No flags are
content of HL pair affected
to SP)
41


CYCLE AFFECTED
ww
XTHL : (Exchange
stock top with H –
| L | ↔ | SP |
| H | ↔ |SP| +1
MC = 5 4T + (3T x
2) + (3T x 2)
No flags are
Affected
L pair)
w.E
IN Port address : |A| ← |port | MC = 1+1+1
= 16 T
4T+3T+3T= No flags are
(Input to
accumulator from
I/O part)
asy =3
10T affected
Out port address : port   A En MC =3 4T+3T+3T= No flags are

(output to
accumulator to I/o gin 10T affected
part)
HLT : (Halt) HLT
ee MC = 1
rin 5 T – state No flags are
affected
PCHL :(jump to PC  H  L MC = 1 g.n

6T – state NO flags
address specified
by H – L pair)
Unconditional
PCH  H
PCL  L
MC = 1+2=3
et
4T+(2 x3T)=
are affected
JMP instruction 10T –states
RLC : (Rotate accumulator left)
Symbolic form :  n1    An 

A 
 A    A7 
 0
CS   A7 
The content of the accumulator is rotated left by one bet
42

RRC : (Rotate accumulator right)
Symbolic form : A7   A0 
CS  A0 
 An   An1 
ww
The content of the accumulator is rotated right by one bit
RAL : (Rotate accumulator left through carry)
w.E
Symbolic form :  n1    An 
A 
asy
CS   A7 
 A   CS 
En
 0
gin
The content of the accumulator is rotated left one bit through carry.
RAR : - (Rotate accumulator right through carry)
Symbolic form :
ee
 An   An1 
CS  A0  rin
 A   CS 
 7
g.n
The content of the accumulator is rotated right one bit through carry.
Conditional JMP instruction : -

et
OPCODE Operand Description
JC 16 – bit jump on carry (if result generate CY = 1)
JNC 16 – bit jump on carry (cy = 0)
JZ 16 – bit jump on zero (if result generate or Z = 1)
JNZ 16 – bit jump one no zero (Z = 0)
43

JP 16 – bit jump on plus (if D7 = 0, s =0)
JM 16 – bit jump on minus (if D7 =1 and S = 1)
JPE 16 – bit jump on even parity (p = 1)
JPO 16 – bit jump on odd parity (P = 0)
ww
Unconditional CALL instruction :
w.E
When it is executed, microprocessor will store address of next instruction is STACK
MC = 1 + 2 + 2 = 5
asy
6T + (3T x 2) + (3T x 2) = 18T – states
No flags are affected
Conditional CALL : En
gin
CC call subroutine if carry flag is set (CY =1)
ee
CNC call subroutine if carry flag is reset (CY = 0)
CZ call subroutine if zero flag is set (z = 1)

rin
CNZ call subroutine if zero flag is reset (z = 0)
CM call subroutine if sign flag is set (s =1, negative number) g.n

CP call subroutine if sign flag is reset (s =0, positive number)
CPE call subroutine if parity flag is set (P =1, even parity)

et
CPC call subroutine if parity flag is reset (P =0, odd parity)
Unconditional RET instruction :
It will change program – sequence from subroutine to main program.
MC = 1 + 2 = 3
4T + (3T x 2) = 10T – states
No flags are affected.
44

Conditional RET instruction :
RC Return if carry flag is set (CY =1)
RNC Return if carry flag is reset (CY = 0)
RZ Return if zero flag is set (z = 1)
ww RNZ Return if zero flag is reset (z = 0)
RM Return if sign flag is set (s =1, negative number)
w.E RP Return if sign flag is reset (s =0, positive number)
asy
RPE Return if parity flag is set (P =1, even parity)
RPC Return if parity flag is reset (P =0, odd parity)
En
RST n : (restart)
Symbolic form : [(Sp – 1) ← [PC]H]

gin
(Sp – 2) ← (PC)L
(Sp ) ← (Sp – 2)
ee rin
[PC] ← 8 times n g.n
MC = 1 + 2 =3
6 T + (3T x 2) = 12 T – states
et
No flags are affected
45

ww
w.E
asy
En
gin
eer
ing
.ne
t

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Manual for K-Notes

ww What are K-Notes?

(November end onwards). ee

© 2015 Kreatryx. All Rights Reserved.

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Number Systems and Boolean Algebra

For radix N, following digits are possible

To convert a number from radix ‘x’ to bare 10 or decimal.

For a base – r system

n = no. of digits in integer part of N

eg. For 378.67 10

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w.E AND function

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ww Dual : Convert all

w.E A + (BC) = (A+B)(A+C)

Minterms, Maxterms & Properties

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F (A, B, C) = min terms F  A,B,C   max terms

1) Sum of product (SOP) form = DNF (Distinjunctive Normal Form) g.n

 ABC  ABC  ABC  ABC  ABC  ABC

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F   m  0,1,2,3, 4,6   canonical SOP form

 M 5,7   canonical POS form

Octant  group of 8 minterms

All corners of k – map asy

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Eg. F  A,B,C   M  0,1,2,3, 4,7 

Implicant : it is the set of all adjacent min terms

ww Eg. Pair, quad, octants

Eg. X  A,B,C,D   m 0,1  d 10,11,12,13,14,15 ;

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1) Equivalence Gate = Ex – NOR Gate

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This gate is equivalent to

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This gate is equivalent to

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Combinational Logic Circuits

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For 2 bit Magnitude comparator

 Active high output

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 Active low output

 S=1, R=1 and Qn+1=0 is impractical state

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 Characteristics equations : Q  S  R.Q

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To convert SR flip flop to a JK flip flop.

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T Qn+1 Characteristics equation

a) +ve edge triggered

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Race around Condition

 When a FF is in toggle mode, then due to propagation delay of gates involved in

For n – bit, time taken = nxT T=clock period