Module 4 – Combinational Circuits

By

Prof. C. Prayline Rajabai

Assistant Professor

School of Electronics Engineering

VIT University

DLD - Module 4 - Combinational Circuits

Combinational Circuits
• Digital Logic Circuits may be combinational or sequential.
• A combinational circuit consists of ‘n’ input variables, logic gates, and ‘m’ output variables.
• The outputs of the combinational circuits are determined by the present combinations of the
input variables.
• Adders, multipliers, comparators, multiplexers, demultiplexers, encoders, decoders are few
examples of combinational circuits.

Block diagram of combinational circuit

DLD - Module 4 - Combinational Circuits
Design Procedure of Combinational Circuits
• Design of combinational circuit starts from the specification of the design and culminates to a
set of Boolean functions from which the logic diagram can be obtained.
• In general we have to do the following steps to design a combinational circuit
i. From the specification determine the required inputs and outputs and assign a symbol
to each inputs and outputs.
ii. Derive the truth table that defines the relation between the inputs and the outputs.
iii. Obtain the simplified Boolean function for each output as a function of input variables.
iv. Draw the logic circuit.

DLD - Module 4 - Combinational Circuits

Design of Half Adder
• A combinational circuit that performs the addition of two bits is called a half adder.
• The two bit binary inputs are given the symbols x and y
• The two outputs are sum and carry with the symbols S and C respectively.

Block diagram of Half Adder Truth Table of Half Adder

S = x’y + xy’ = x ⊕ y
C = xy

DLD - Module 4 - Combinational Circuits

Implementation of Half-Adder
S = x’y + xy’ = x ⊕ y
C = xy

DLD - Module 4 - Combinational Circuits

Design of Full Adder
• A combinational circuit that performs the addition of three binary bits (two binary bits and
a previous carry) is called a full adder.
• The three binary inputs are given the symbols x , y and z
• The two outputs are sum and carry with the symbols S and C respectively.

Block diagram of Full Adder

Truth Table of Full Adder

DLD - Module 4 - Combinational Circuits
K-Maps for Full Adder

DLD - Module 4 - Combinational Circuits

Implementation of Full Adder
Full-adder can be implemented with two half adders and one OR gate. Dotted block in the
below circuit indicates a half adder.
S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(x ⊕ y) + xy = z(xy’ + x’y) + xy = xy’z + x’yz + xy

DLD - Module 4 - Combinational Circuits

Binary Adder
• Digital circuit that produces the arithmetic sum of two ‘n’ bit binary numbers, n > 1.

• It can be designed connecting the full adders in cascade with the carry of each full adder
being connected to the input carry of the next full adder.

• Addition of ‘n’ bit requires ‘n’ full adders or 1 half adder and ‘n-1’ full adders

DLD - Module 4 - Combinational Circuits

Design of Half Subtractor
• A combinational circuit that performs the subtraction of two bits is called a half subtractor.
• The two bit binary inputs are given the symbols x and y
• The two outputs are Difference and Borrow with the symbols D and B respectively.

Block diagram of Half Subtractor Truth Table of Half Subtractor

D = x’y + xy’ = x ⊕ y
B = x’y

DLD - Module 4 - Combinational Circuits

Implementation of Half-Subtractor
D = x’y + xy’ = x ⊕ y
B = x’y

DLD - Module 4 - Combinational Circuits

Design of Full Subtractor
• A combinational circuit that performs the subtraction of three binary bits (two binary bits
and a previous borrow) is called a full subtractor.
• The three binary inputs are given the symbols x , y and z
• The two outputs are difference and borrow with the symbols D and B respectively.

Block diagram of Full Subtractor

D = x’y’z + x’yz’ + xy’z’ + xyz
B = x’y’z + x’yz’ + x’yz + xyz Truth Table of Full Subtractor
DLD - Module 4 - Combinational Circuits
K-Maps for Full Subtractor

D = x’y’z + x’yz’ + xy’z’ + xyz

B = x’y’z + x’yz’ + x’yz + xyz

K-map for D K-map for B

DLD - Module 4 - Combinational Circuits

Implementation of Full Subtractor
D = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
B = x’ (y ⊕ z) + yz = x’(y’z + yz’) + yz = x’y’z + x’yz’ + x’yz + xyz

DLD - Module 4 - Combinational Circuits

Adder-Subtractor
• Addition and subtraction operation can be combined into one circuit with one binary
adder and XOR gate with each full adder.

• M = 0 => Adder

• M = 1 => Subtractor

DLD - Module 4 - Combinational Circuits

Decoder
• Decoder is a combinational circuit which decodes a n bit binary code to a maximum of
m unique output codes.

• Usually represented as n:m line decoder

• “n” represents the number of inputs and “m” represents the number of outputs.

• “m ≤ 2n”. If there are any unused input combinations then the decoder may have less
than 2n outputs.

DLD - Module 4 - Combinational Circuits

Truth Table of 3:8 Line Decoder

DLD - Module 4 - Combinational Circuits

3:8 Decoder

DLD - Module 4 - Combinational Circuits

2:4 Decoder with Enable input
Truth Table

X1 X0 E Y0 Y1 Y2 Y3

X X 0 0 0 0 0

0 0 1 1 0 0 0

0 1 1 0 1 0 0

1 0 1 0 0 1 0

1 1 1 0 0 0 1

DLD - Module 4 - Combinational Circuits

Logic Diagram of 2:4 Decoder with enable

Y0 = EX1’X0’

Y1 = EX1’X0

Y0 = EX1X0’

Y0 = EX1X0

DLD - Module 4 - Combinational Circuits

4:16 Decoder using two 3:8 Decoder

DLD - Module 4 - Combinational Circuits

 Truth table for 4:16 decoder
w x y z D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D1 D1 D1 D1 D1
0 1 2 3 4 5
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

1 1 1 1 0 0 0 0DLD - Module
0 04 - Combinational
0 0 0
Circuits 0 0 0 0 0 0 1
Implementation of Full Adder using Decoder

DLD - Module 4 - Combinational Circuits

Exercise
• Construct a 4-to-16-line decoder with five 2-to-4-line decoders with enable.

• A combinational circuit is specified by the following three Boolean functions:

F1(A, B, C) = Ʃ(1, 4, 6)

F2(A, B, C) = Ʃ(3, 5)

F3(A, B, C) = Ʃ(2, 4, 6, 7)

Implement the circuit with a decoder

DLD - Module 4 - Combinational Circuits

Encoder
• Encoder is a combinational circuit that performs the inverse function of the decoder

• The encoder has 2n input lines and n output lines

• An octal to binary encoder has 8 inputs and 3 outputs (assume only one input is high (1) at a
given time). • An octal to binary encoder (8:3
encoder) can be implemented using
three OR gates.
x = D4+D5+D6+D7
y = D2+D3+D6+D7
z = D1+D3+D5+D7

• Limitation : If multiple inputs are high

output produces an undefined
combination.
Priority Encoder
• Priority encoder is an encoder circuit that includes the priority function.

• If more than one input is active, the higher-order input has priority over the lower-
order input.

• The higher value is encoded on the output

• A valid indicator V, is included to indicate whether or not the output is valid.

• Output is invalid when no inputs are active i.e., when V = 0

• Output is valid when at least one input is active i.e., when V = 1

Priority Encoder – Truth Table and K- Map
D0 D1 D2 D3 X Y V Boolean Functions
0 0 0 0 X X 0
x = D2 + D3
1 0 0 0 0 0 1
X 1 0 0 0 1 1 y = D 3 + D 1D 2’
X X 1 0 1 0 1 V = D0 + D1 + D2 + D3
X X X 1 1 1 1
Logic Circuit - Priority Encoder
Exercise
• Design a four-input priority encoder with input D0 having the highest priority and
input D3 the lowest priority and write the corresponding Verilog HDL code.

• Design a four-input priority encoder with input D1 having the highest priority, D0
having the next lower priority, D2 has the next lower priority and input D3 the
lowest priority. Write the corresponding Verilog HDL code.

DLD - Module 4 - Combinational Circuits

Multiplexers
• Combinational Circuit to select a binary information from one of the many input lines to single
output line

• 2n input lines and ‘n’ selection lines

• The bit combination of the selection line determines which input to be connected to the output

• Acts as a switch and allows conditional transfer of the input data

4:1 Multiplexer

Y = D0S0’S1’ + D1S0S1’ + D2S0’S1 + D3S0S1

Quadruple two-to-one-line multiplexer
Active low enable signal
– Circuit is active only when E = 0
Implementing Boolean Functions using Mux
• Boolean Function of n variables can be implemented using a mux with n-1 selection
input.

• First n-1 variables of the function is connected to the selection inputs of the multiplexer.

• Left out variable is used for the data inputs.

Implementing Boolean Functions using Mux
• F(x,y,z) = Ʃ(1,2,6,7)
• x and y are connected to the selection inputs of the multiplexer in the same order.
• x is connected to S1 and y is connected to S0
• z, z’, 0 and 1 are connected to the data inputs of the multiplexer
Exercise
• Construct a 16x1 Multiplexer with two 8x1 and one 2x1 multiplexers. Write
the Verilog HDL.

• Implement the following Boolean function with a Multiplexer

• F(A,B,C,D) = Ʃ(0,2,5,8,10,14)

• F(A,B,C,D) = ∏(2,6,11)

• Implement a full adder with two 4x1 Multiplexer

Three state Gates
• Three state gates – digital circuits that exhibit 3 states (1,0,z)

• Graphic symbol is shown below

• Multiplexers can be implemented with the tri state gates

Multiplexers with Tri state Gates
 De-Multiplexer
• De-Mux is a combinational circuit that receives input from a single line and directs it to one of
the 2n output lines based on the ‘n’ bit selection lines.

• A decoder with enable input can function as a de-multiplexer with the following considerations.

• The input of decoder can be considered as selection lines of the de-multiplexer

• The enable signal of the decoder can be considered as the data input of the de-multiplexer
Multiplier – 2 bit by 2 bit

DLD - Module 4 - Combinational Circuits

Multiplier – 4 bit by 3 bit

DLD - Module 4 - Combinational Circuits

Magnitude Comparator
• Magnitude comparators compare two multi-bit binary numbers

• Magnitude comparators allow for data comparison and can be built using and-or gates

• Greater/less than function requires more hardware than equality

• The comparison of two numbers gives the outputs: A>B, A=B, A<B

• Design Approaches
2n
• Truth table : 2 entries - too cumbersome for large n
• use inherent regularity of the problem
• reduce design efforts
• reduce human errors
Block Diagram of Magnitude Comparator

4 A<B
A
Magnitude A=B
4 Comparator
B
A>B
Magnitude Comparison
 Algorithm -> logic
 A = A3A2A1A0 ; B = B3B2B1B0

 A=B if A3=B3, A2=B2, A1=B1and A0=B0

 Test each bit:
 equality: xi= AiBi+Ai’Bi’ = (AiBi'+Ai'Bi)’

 (A=B) = x3x2x1x0

 More difficult to test less than/greater than

 (A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'

 (A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

 Start comparisons from high-order bits

 Implementation
 xi = (AiBi'+Ai'Bi)’
Logic Circuit for Magnitude Comparison

(A=B) = x3x2x1x0
(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0‘
(A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
Parity Generator
• A parity bit is an extra bit included with a binary message to make the number of 1’s
either odd or even.

• A circuit that generates the parity bit in the transmitter is called parity generator.
• It is very useful in systems requiring error detection and correction codes.

DLD - Module 4 - Combinational Circuits

Parity Checker
• The circuit that checks the parity in the receiver is called a parity checker.

DLD - Module 4 - Combinational Circuits

Thank you

DLD - Module 4 - Combinational Circuits