Designing of 16 bit Microprocessor

Kavita Singh1, Ishita Singhal2, Kratee Singh3

In guidance of Mrs. Neerja Singh
ECE department
ABES Engineering College, Ghaziabad
Abstract
Embedded microprocessor has been An ALU represents the fundamental
widely used as a tool for technological building block of the Central Processing
innovations and cost reduction. One of Unit of a computer. An ALU is a digital
common components in the processor is circuit which is used to perform
the Arithmetic and Logic Unit (ALU). Arithmetic, Logical and Shifting
Usually, ALUs are designed with a operations. Some of the operations
combinational and logical circuit performed in ALU are addition,
containing a number of functional multiplication, subtraction and logical
components for their respective operations. gates such as NOT, AND, and OR.
High speed and programmability of ALU
determines its overall performance. II. 16-BIT ALU
Therefore, for a CPU design to be This 16-bit ALU consists of
competitive, It’s ALU has to be fast, Arithmetic, Logical, Shift and
relatively inexpensive, optimized power Rotate operations.
consumption and flexible. a. 16-BIT ARITHMETIC UNIT
Arithmetic unit includes arithmetic
In this project, a modified ALU design operations such as addition,
using Verilog is introduced. The novelty of multiplication, increment and
the ALU is that, it shows comparison of decrement.
different multipliers that is Wallace b. 16-BIT LOGIC UNIT
multiplier and Dadda multiplier. The Logic unit includes logical
approach can be easily integrated into operations such as AND, OR,
main programs which effectively improve NOR, NAND, XOR, XNOR, NOT,
ALU speed. The results have been 2’s complement.
achieved using no complex hardware, and c. 16-BIT SHIFT AND
the implementation is straightforward. ROTATE UNIT
Shift unit includes shifting
. operations such as Logically Shift
KEYWORD – ALU, Wallace Multiplier, Left(LSL), logically shift
Xilinx, ISE Design Suite right(LSR).
Rotate unit includes Rotate Left,
I. Introduction Rotate Right.

A microprocessor controls all the functions

of Central Processing Unit of a computer
which is a combination of ALU, Memory
and the Control Unit.
III. FUNCTION TABLE OF ALU
We have designed and implemented a 16- 0 1 1 1 1 ADDER ARITHM
bit ALU. The Table 1 given below show ETIC
all its operations-
1 0 0 0 0 SUBTRA ARITHM
S S S S S FUNCTIO UNIT CTOR ETIC
4 3 2 1 0 N
1 0 0 0 1 MULTIPL ARITHM
0 0 0 0 0 AND LOGICA IER ETIC
L
Table 1: Operations performed in ALU
0 0 0 0 1 OR LOGICA
IV. SIMULATION AND
L
IMPLEMENTATION
0 0 0 1 0 NOT LOGICA
L

0 0 0 1 1 NAND LOGICA
L

0 0 1 0 0 NOR LOGICA
L

0 0 1 0 1 XOR LOGICA
L

0 0 1 1 0 XNOR LOGICA
L

0 0 1 1 1 INCREM ARITHM
ENT ETIC

0 1 0 0 0 DECREM ARITHM
ENT ETIC Fig 1: Waveform of multiplier

0 1 0 0 1 1’S ARITHM
COMP ETIC

0 1 0 1 0 2’S ARITHM
COMP ETIC

0 1 0 1 1 LSL SHIFT

0 1 1 0 0 LSR SHIFT

0 1 1 0 1 RL ROTATE

0 1 1 1 0 RR ROTATE
 • ALU with Wallace multiplier is
comparatively faster than ALU
with Dadda multiplier.
• Wallace delay is improved by 15%
than Wallace delay in reference
research papers
• Dadda delay is improved by 17%
than Dadda delay in reference
research papers
• ALU with Wallace delay is
improved by 79.3% than ALU with
Wallace delay in reference
research papers
• ALU with Dadda delay is
improved by 79.1% than ALU with
Dadda delay in reference research
papers

Powe Logi Sign Inp Lea Tota

r c al ut kage l
Pow Pow Pow Pow Pow
Fig 2: Simulation of ALU er( er( er( er( er(
V. RESULTS WITH W) W) W) W) W)
CONCLUSION Walla 0.00 0.00 0.00 0.08 0.08
ce 113 260 018 1 5
Delay(ns) Delay in
reference Dadd 0.00 0.00 0.01 0.08 0.09
research a 088 102 387 2 8
papers
Alu_ 0.00 0.00 0.00 0.08 0.08
Wallace 12.546 14.935 Walla 126 133 139 2 7
Dadda 10.500 12.761 ce

ALU_wallace 3.752 18.139 Alu_ 0.00 0.00 0.00 0.08 0.08

Dadd 130 123 190 2 7
ALU_dadda 3.781 18.137 a

Fig 2: Comparison of Delay Table 3: Comparison of Total

power
From this, it is concluded out that
 Wallace multiplier consumes less
• Dadda multiplier is faster than
power than Dadda multiplier.
Wallace multiplier.
  ALU with Wallace and ALU with  Dadda occupies lesser LUTs than
Dadda has same power. Wallace multiplier.
 ALU with Dadda multiplier
occupies lesser luts than ALU with
Delay Power PDP
(ns) (W) (nJ) Wallace multiplier.

WALLAC 12.54 0.085 1.06 References

E 6 6
[1] Khushboo Bais, Zoonubiya Ali
“Design of a high-speed Wallace tree
DADDA 10.50 0.098 1.02
9 multiplier” International journal of
0
engineering sciences & research
ALU_WA 3.752 0.087 0.32 technology(IJESRT) DIMAT, Raipur
LLACE 6 (C.G.), India

ALU_DA 3.781 0.087 0.32 [2] E. Prakash, R. Raju and Dr. R

DDA 8 Varatharajan “Effective Method for
Implementation of Wallace Tree multiplier
Table 4: Comparison of PDPs using Fast Adders” Journal of Innovative
Research and solutions(JIRAS) Sri
• Dadda multiplier has lesser PDP Lakshmi Aammal Engineering
than Wallace multiplier. College,Chennai-73
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LUTs
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[5]Sukhmeet Kaur and Nitika Munjal
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