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Reconfigurable Computing
CS G553

Lecture 9 –FPGA Fabrics

 Introduction
Basic Structures of FPGA – FPGA fabrics

Elements of FPGAs

Combinational/sequential Logic

Interconnect

I/O Pins

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 Terminology
Configuration: bits that determine logic function +
interconnect.

CLB: Combinational Logic Block = Logic Element.

LUT: LookUp Table (SRAM used for truth table).

I/O Block (IOB): I/O Pins + associated logic

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 FPGA Architecture

LE

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Interconnects

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 Logic Element

Input Connections Internal Function

Programmable

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 Logic Element

Typically > 4 inputs

Coarser Grained than Logic gates

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 Logic Element

Generally includes a register

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 Logic Element
May provide specialized logic

LUT

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Logic Element

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0
1 LUT
1
0
1
0
0
1

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 LUT

1
0
0
1
0
0

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LUT

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LUT

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 LUT
k
p w

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 LUT
k
p x
w
s
t
d

3 inputs and 1 3 inputs and 1

output output
x=kps’ w=x+t+d

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 LUT
kk
pp xx
w
w
ss
tt
dd

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 LUT
9-input Circuit

LUT

512x1LUT
9-input LUT LUT

LUT

1 , 512x1 Mem 4 , 8x1 Mem CKV

 LUT
LUT Typically has 2 or more outputs

Example: Partitioning among 3-input, 2-output LUTs

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LUT

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 LUT
Example: Implement 2x4 decoder using 3-input 2-output
LUTs

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Thank You for Attending
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