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Reconfigurable Computing
CS G553

Lecture 12 – Reconfigurable Computing Architectures


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Reconfigurable Architectures
Considerable Research into possible reconfigurable
architectures

Explore different design choices made for reconfigurable


computing architectures

How design choices affect both operation and


performance
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Reconfigurable Architectures
Computing applications have
• Data-flow
• Control flow
General Purpose processors
• Data plane
• Control plane
Reconfigurable Computers
• Reconfigurable fabric used to implement a portion of
dataflow
StaticallyProcessing
Reconfigurable
Dynamically Reconfigurable
Fabric - RPF
Reconfigurable
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Reconfigurable Processing Fabric - RPF


Static RPF : Configured between application runs

Dynamic RPF: Updated during application’s execution

RPF relatively symmetrical and can be broken into


similar cells that have same functionality

Processing Elements

RPF used to implement computationally intensive


kernels also called Virtual Instruction Configurations
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Reconfigurable Architectures
• Forces that drive a Reconfigurable Architecture
– Price
• Mass production 100K to millions
• Experimental 1 to 10’s

– Granularity of reconfiguration
• Fine grain
• Course Grain

– Degree of system integration/coupling


• Tightly
• Loosely
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Reconfigurable Architectures
• Performance metrics
– Computational
• Throughput
• Latency

– Power
• Total power dissipation
• Thermal

– Reliability
• Recovery from faults
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RPF Architectures
Different Systems have different Granularity

Fine Grained – Manipulate data at bit level

CLB CLB CLB CLB

CLB CLB CLB CLB Configurable Logic Block

CLB CLB CLB CLB

CLB CLB CLB CLB


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RPF Architectures
Different Systems have different Granularity

Fine Grained – Manipulate data at bit level

CLB CLB CLB

CLB CLB CLB CLB Configurable Logic Block

CLB CLB CLB CLB

CLB CLB CLB CLB


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RPF Architectures
Different Systems have different Granularity

Fine Grained – Manipulate data at bit level

CLB CLB

CLB Configurable Logic Block

CLB

CLB CLB CLB CLB


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RPF Architectures
Different Systems have different Granularity
Coarse Grained – Manipulate groups of bits via
complex functional units such as ALUs and
multipliers
ALU ALU ALU

ALU ALU ALU

ALU ALU ALU


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RPF Architectures
Different Systems have different Granularity
Coarse Grained – Manipulate groups of bits via
complex functional units such as ALUs and
multipliers
ALU ALU ALU

ALU ALU ALU

ALU ALU ALU


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RPF Architectures
Different Systems have different Granularity
Coarse Grained – Manipulate groups of bits via
complex functional units such as ALUs and
multipliers
ALU ALU ALU

ALU ALU ALU

ALU ALU ALU


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Fine Grained Architectures


Advantage – Allows data manipulation at bit level

Disadvantage – For large and complex calculations,


numerous PEs are required for implementation of
basic function.

Disadvantage – Much slower clock rates than are


possible if calculations mapped to fewer coarse
grained PEs
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Fine Grained Architectures


GARP Reconfigurable Processor

Memory On Chip Cache

I-cache D-cache

RPF
CPU RFU

Config
cache
MIPS Processor
Garp chip
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Fine Grained Architectures


GARP Reconfigurable Processor
Memory
RFU
control Execution
(1) (16, 2-bit)
I-cache D-cache

CPU RFU
N

Config
cache PE (Processing Element)
Garp chip CLBs Modelled after Xilinx
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Fine Grained Architectures


GARP Reconfigurable Processor
Fixed

Not
Fixed

Typically 32
Overflow, Error Checking, Status Checking, Wider Data
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Fine Grained Architectures


GARP Reconfigurable Processor

Operates on 2-bit
No connection between wires Data
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Fine Grained Architectures


GARP Reconfigurable Processor
Each PE in GARP’s RPF requires 64 Configuration bits
(8 bytes) to specify
Sources for inputs
PEs function
Any wires to be driven by PEs

If there are 32 rows, How many Configuration bytes?


6144

If bus width to memory is 128 bits, configuration


requires 384 memory accesses
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Fine Grained Architectures


GARP Reconfigurable Processor

Memory partial array configuration


Dynamically Reconfigurable

I-cache D-cache

CPU RFU Only one VIC


Controlled
Config
by CPU cache
Upto 4 VIC
Garp chip
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Fine Grained Architectures


GARP Reconfigurable Processor
User Source code in C Configurations in Textual
Language

Explicitly assign data and


High Level Language operations to rows and columns

Referenced using
Character array
Initializer
Configurator
Further instructions to invoke
GARP instructions that interfaced
with Reconfigurable array Configuration as collection of bits
Thank You for Attending
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