IET Circuits, Devices & Systems

Research Article

Efficient designs of reversible latches with ISSN 1751-858X

Received on 30th May 2018
Revised 11th February 2019
low quantum cost Accepted on 2nd April 2019
E-First on 3rd September 2019
doi: 10.1049/iet-cds.2018.5240
www.ietdl.org

Mojtaba Noorallahzadeh1, Mohammad Mosleh1

1Department of Computer Engineering, Dezful Branch, Islamic Azad University, Dezful, Iran
E-mail: Mosleh@iaud.ac.ir

Abstract: Reversible computing is one of the most promising technologies in the design of low-power digital circuits, optical
information processing, quantum computing, DNA computing, digital signal processing, and nanotechnology. The main purpose
of the design of reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible
circuits. A gate/block is reversible if the number of inputs and the number of outputs are equal and there is one-to-one
correspondence between them. Latches are considered as one of the most important digital structures that are widely used as
building blocks in the design of sequential circuits. Here, eight new reversible blocks are first offered. Then using some of them,
several effective designs of reversible D, T, and J-K latches are proposed. The results of the evaluations indicate that the
proposed latches are superior in terms of quantum cost (QC) than previous designs. Moreover, they are very close to or better
than the best previous designs in terms of criteria such as gate count (GC), constant inputs (CI), and garbage outputs (GO).

1 Introduction
One of the most important factors in the design of large-scale
integrated circuits is the problem of reducing power consumption
and energy dissipation. In dealing with thermodynamics, Landauer
showed that the design of logical and digital circuits, using the
conventional logic known as irreversible logic, causes unwanted
loss of electrical energy in the circuit [1]. It was also proved by him
that the thermal energy generated by the loss of a bit of information
during processing is equal to KTLn2 (Joule), where K is the
Boltzmann constant and T is the absolute temperature (Kelvin) [1].
Bennett proved that in order to avoid energy waste in
computational circuits, the processes should be reversible, i.e. if
reversible logic gates are used, there is no power consumption and
no energy is lost [2]. A gate is reversible if the number of input
lines and the number of output lines are equal and there is a one-to-
one correspondence between them [3, 4]. In other words, the input
vector can be retrieved through the output vector. In reversible
logic, feedback loops and fan-out (fan-out = 1) is not allowed
[3].The main application of the reversible logic in quantum
computations is due to the fact that quantum circuits must be
reversible [5]. This technique has been widely used in various
research fields such as optical computing, ultra-low-power CMOS
design, DNA computation, quantum computing, thermodynamic
technology, bioinformatics, and nanotechnology [5, 6]. In order to
properly synthesise the reversible circuits, it is necessary that
criteria such as gate count (GC), number of constant inputs (CI),
number of garbage outputs (GO), quantum cost (QC), and delay to
be optimised.The main focus of reversible logic circuits in the
design of combinational circuits was because of the agreement of
the names that feedback in reversible computation is not allowed.
Toffoli demonstrated that feedback is allowed in reversible
computation [7]. Accordingly, a sequential circuit is reversible if its
combinational part is reversible. Furthermore, it has been shown
that when building a reversible limited automatic machine, one can
make a reversible realisation of its transfer function and use it as a
combination component of the sequential circuit. Fredkin used this
concept to propose the first reversible sequential circuit design
called J-K latch, which had a feedback loop from the output [8].
Reversible latches can be used as the building blocks of memories
in quantum computers of the future [9].
In 2014, a new reversible gate called Pareek gate has been first
suggested by Pareek et al. [9] and then a reversible T latch has
been presented using the Pareek gate, FRG and FG with GC equal
to 3, CI and GO equal to 2, and QC equal to 13.
In 2005, Thapliyal et al. [10] proposed a reversible D latch
using four reversible new gates (NGs) and three Feynman gates
(FGs), which has GC and CI equal to 7 and GO and QC equal to 8
and 47, respectively. Also using four reversible Fredkin gates
(FRGs), two NG gates and four FG gates proposed reversible T
and J-K latches, which has GC and CI equal to 10 and GO and QC
equal to 12 and 46.
In 2006, Hari et al. [11], proposed a reversible D latch using
two reversible FRG and FG gates in which GC and GO criteria
were equal to 2 and the CI and QC criteria were equal to 1 and 6,
respectively. Also they proposed a reversible T latch using one
FRG gate and two FG gates in which the GC was equal to 3 and CI
equal to 2 as well as GO and QC criteria equal to 2 and 7,
respectively. They also proposed reversible J-K latch using three
FRG gates and one FG gate, in which the GC and GO were equal
to 4 and CI and QC were equal to 3 and 16, respectively.
Using one FRG and two FGs, a reversible D latch has been
proposed by Thapliyal and Ranganathan [12] in 2010, with GC
equal to 3, CI and GO equal to 2 as well as QC equal to 7. A
reversible J-K latch was also proposed using two FRG gates, two
FG gates and one NOT gate in which the GC is equal to 5, CI equal
to 2, GO equal to 3 and QC equal to 13.
In 2010, Sayem and Ueda [13], first suggested a new reversible
gate called Sayem gate (SG) and then presented a reversible D
latch using the SG and FG with GC, CI, and GO equal to 2. Also,
they presented a reversible J-K latch using one NOT gate, one FRG
gate, one SG gate and one FG gate, in which the GC was equal to
4, and GO was equal to 3 and CI equal to 2.
In 2011, Belayet et al. [14] provided a reversible D latch using
reversible Belayet–Mosharof–Eneyat (BME) and PG gates with
GC equal to 3 as well as CI and GO equal to 4.
In 2011, Biswas et al. [15] offered two different designs of
reversible D latch; In the first design, they used one FRG gate, two
FG gates and two PG gates with GC, CI and GO equal to 5 and QC
equal to 15. The second design consists of one FRG gate and one
PG gate with GC, CI and GO equal to 2 as well as QC equal to 9.
In 2013, a reversible D latch has been proposed by Mamun et
al. [16] using a reversible modified FRG2 (MFRG2) and a double
Feynman (DFG) gates with GC and CI equal to 2, and QC equal to
7.

IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815 806
© The Institution of Engineering and Technology 2019

Fig. 1  Quantum representation of NOT gate
Fig. 2  Quantum representation of CNOT gate
Fig. 3  Quantum realisation of controlled-V and controlled- V + gates
(a) Controlled-V gate, (b) Controlled- V + gate
Fig. 4  Quantum realisation of four integrated qubit gates
(a) Pattern 1, (b) Pattern 2, (c) Pattern 3, (d) Pattern 4
Fig. 5  Quantum realisation of the proposed reversible block, NMG1
In 2014 Mamun et al. [17] first proposed a reversible Mamun
gate (MG1) gate and then designed a reversible D latch with GC,
CI equal to 1 and GO equal to 2. Also, they proposed a reversible
Mamun gate (MG2) and then designed a reversible J-K latch using
one MG1 and one MG2, with GC and CI equal to 2 and GO equal
to 3.
In addition, in 2013, Ananthalakshmi and Sudha [18] first
proposed a reversible AS gate and then designed a reversible D
latch with GC, CI equal to 1, GO equal to 2 and QC equal to 6.
Also, they proposed a reversible D latch using the reversible AS
gate and FG gate that its GC, CI and GO was equal to 2 and its QC
was equal to 7.
In 2006, Thapliyal and Zwolinski [19] proposed a reversible D
latch using a reversible FRG and FG gates, with GC and GO equal
to 2, CI equal to 1 and QC equal to 6.
In 2016, Banik [20], proposed a reversible T latch using a
reversible RQCA gate and three FG gates, that it has GC equal to
4, CI and GO equal to 2 and QC equal to 7.
In 2013, Karthik al. [21], offered two different designs of a
reversible D latch. In the first design, they used a reversible KAS
gate in which GC, CI equal to 1 and GO equal to 2. The second
designs used one reversible KAS and one FG gates, with GC, CI
and GO equal to 2.
In 2012, Mamun et al. [22], first introduced a new reversible
gate called MFRG2; then, they designed the D latch using one
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815
© The Institution of Engineering and Technology 2019
MFRG2 gate and one FG gate. Their design had GC and GO equal
to 2, CI equal to 1 and QC equal to 6.
In 2012, Bhagyalakshmi and Venketesha [23] first presented
two new reversible gate called VB-1 and VB-2. They also designed
T latch using one VB-1 gate and one FG gate in which GC, CI and
GO criteria were equal to 3, 2 and 2, respectively. Moreover, they
introduced J-K latch using one VB-1 gate and one VB-2 gate in
which GC and CI were equal to 2 and GO was equal to 3.
In 2007, Thapliyal and Vinod [24] proposed a reversible T latch
using one FRG gate and one TG gate in which GC, CI and GO
were equal to 2 as well as QC was equal to 10. Also, they designed
a reversible J-K latch using one MFG gate and two FRG gates in
which GC and GO were equal to 3 as well as CI and QC were
equal to 2 and 15, respectively.
In 2014, Pareek [25] proposed a reversible T latch using the
Pareek gate and FG with GC, CI and GO equal to 2 and QC equal
to 8.
Here, eight new reversible blocks are initially presented, and
then, using some of them, several low QC designs of D, T and J-K
latches are proposed.
This paper is organised as follows: in Section 2, an introduction
to the reversible logic is provided. In Section 3, the proposed
designs are presented. In Section 4, the simulation results and
comparisons are given. Finally, the paper ends with conclusion
section.
2 Preliminaries
This section introduces some basic concepts of reversible logic
including basic quantum gates and evaluation criteria of reversible
circuits.
A gate/block is said reversible if it has the following two
conditions [26, 27] :
i. The number of inputs is equal to the number of outputs
ii. There is a one-to-one correspondence between the inputs and
the outputs (that is, each the input vector is uniquely retrieved
from the output vector).
2.1 Basic quantum gates
2.1.1 NOT gate: A NOT gate is a 1 × 1 quantum gate with QC
equal to 1 as shown in Fig. 1 [12].
2.1.2 Controlled-NOT gate (CNOT): The CNOT gate, which is
also known as the FG, is a 2 × 2 reversible gate that has the inputs
control (A) and target (B) and the produces the outputs P = A and
Q = A ⊕ B. The CNOT quantum representation is shown in Fig. 2.
As can be seen, if the control input is equal to 1 (A = 1), the output
Q will be the inverse of the target input B̄ ; otherwise, the target
input (B) is transferred unchanged to the output Q [28].
2.1.3 Controlled-V and controlled- V + gates: Controlled-V and
Controlled- V + gates are known as primary 2 × 2 quantum gates
and are shown in Figs. 3a and b, respectively [29].
V and V + matrices are provided in (1) and (2), respectively [30–
32]:
1+i 1 −i
V= (1)
2 −i 1
1−i 1 i
V+ = (2)
2 i 1
Also, V and V + matrices have the following properties [29, 30]:
V × V = NOT (3)
V+ × V = V × V+ = I (4)
V + × V + = NOT (5)
807
Table 1 Truth table of the proposed reversible block, NMG1
Input encoding A B C D P Q R S Output encoding
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 1
2 0 0 1 0 1 0 1 1 11
3 0 0 1 1 1 0 1 0 10
4 0 1 0 0 0 1 0 1 5
5 0 1 0 1 1 1 1 0 14
6 0 1 1 0 0 1 0 0 4
7 0 1 1 1 1 1 1 1 15
8 1 0 0 0 1 0 0 0 8
9 1 0 0 1 1 0 0 1 9
10 1 0 1 0 0 0 1 1 3
11 1 0 1 1 0 0 1 0 2
12 1 1 0 0 1 1 0 1 13
13 1 1 0 1 0 1 1 0 6
14 1 1 1 0 1 1 0 0 12
15 1 1 1 1 0 1 1 1 7

Table 2 Truth table of the proposed reversible block, NMG2

A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
C D P Q R S
0 0 0 0 1 0
0 1 0 0 1 1
1 0 0 0 0 0
1 1 0 0 0 1
0 0 0 1 0 0
0 1 0 1 0 1
1 0 0 1 1 0
1 1 0 1 1 1
0 0 1 1 0 1
0 1 1 1 0 0
1 0 1 0 1 1
1 1 1 0 1 0
0 0 1 1 1 1
0 1 1 1 1 0
1 0 1 0 0 1
1 1 1 0 0 0

As seen in Fig. 3, if the control input A is equal to 1 (A = 1),
controlled-V and controlled- V + gates result in V (B) and V + (B)
outputs, respectively. Otherwise, target input B will be transferred
without change to the output. Their QC is equal to 1.
The quantum realisation of the four integrated 2-qubit gates is
shown in Fig. 4. It should be mentioned that each dotted rectangles
in Fig. 4 is equivalent to a 2 × 2 gate and its QC is equal to 1 [31,
33, 34].
2.2 Evaluation criteria of reversible circuits
So far, several criteria have been introduced to evaluate the
synthesis of reversible circuits. In the following, some of the most
important criteria are presented.
2.2.1 Gate count (GC): A criterion that shows the total number
of reversible gates used in reversible circuit design [35].
2.2.2 Constant input (CI): This indicates the number of inputs
that should be set to a constant value (0 or 1) for the synthesis of
the logical function [36].
2.2.3 Garbage output (GO): This indicates unwanted outputs
which are added to make a function reversible [6].
2.2.4 Quantum cost (QC): This refers to the cost of reversible
circuits based on the number of elementary quantum gates. QC of
reversible 1 × 1 gates (such as the NOT gate) and 2 × 2 gates (such
as the Controlled-V, Controlled- V +, CNOT and integrated 2-qubit
gates) is considered to be equal to one [27, 29, 30, 32, 37].
2.2.5 Delay: Delay is considered as the maximum number of gates
in a critical path [6]. Delays in each of the 1 × 1 and 2 × 2 quantum
gates are equal to 1. For blocks of 3 × 3 or larger, the equivalent
quantum run can be replaced by 1 × 1 and 2 × 2 gates, using
quantum depth as a delay for that block [37].
2.2.6 Hardware complexity: This indicates the total number of
logical operations in a circuit. In the complexity of hardware, the
following terms are considered:
α = a two-input EX-OR gate calculation
β = a two-input AND gate calculation
δ   = a NOT calculation
T = total logical calculation
The logical calculation refers to the total number of XOR,
AND, and NOT counting in the circuit [36].
3 Proposed reversible designs
In this section, several proposed reversible logical blocks are
proposed and then using some of the proposed blocks, several
designs of D, T and J-K latches are suggested.

808 IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815
© The Institution of Engineering and Technology 2019
Table 3 Truth table of the proposed reversible block, NMG3
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Table 4 Truth table of the proposed reversible block, NMG4
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Table 5 Truth table of the proposed reversible block, NMG5
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
3.1 Proposed reversible blocks
3.1.1 Proposed block, NMG1: The truth table of the proposed 4  are equal to 5. In addition, its hardware complexity is 5α + 4β + 2 δ.
× 4 NMG1 block is shown in Table 1.
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815
© The Institution of Engineering and Technology 2019
C D P Q R S
0 0 0 0 1 1
0 1 0 0 1 0
1 0 0 0 0 0
1 1 0 0 0 1
0 0 0 1 0 0
0 1 0 1 0 1
1 0 0 1 1 1
1 1 0 1 1 0
0 0 1 0 0 0
0 1 1 0 0 1
1 0 1 1 1 1
1 1 1 1 1 0
0 0 1 0 1 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 0 1
C D P Q R S
0 0 0 0 0 0
0 1 0 0 0 1
1 0 0 0 1 0
1 1 0 0 1 1
0 0 1 1 1 1
0 1 1 1 1 0
1 0 1 1 0 1
1 1 1 1 0 0
0 0 1 0 1 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 0 1 0 0
0 0 1 0 0 0
0 1 1 0 0 1
1 0 0 1 1 1
1 1 0 1 1 0
C D P Q R S
0 0 0 0 1 0
0 1 0 0 1 1
1 0 0 1 0 0
1 1 0 1 0 1
0 0 0 1 1 0
0 1 0 1 1 1
1 0 1 1 0 1
1 1 1 1 0 0
0 0 1 0 1 1
0 1 1 0 1 0
1 0 0 0 0 0
1 1 0 0 0 1
0 0 1 1 1 1
0 1 1 1 1 0
1 0 1 0 0 1
1 1 1 0 0 0
The quantum realisation of the proposed reversible block
NMG1 is shown in Fig. 5. As seen, QC and the delay of this block
809
Table 6 Truth table of the proposed reversible block, NMG6
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
C D
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
P Q R S
0 0 0 0
0 0 0 1
0 1 1 0
0 1 1 1
0 1 0 0
0 1 0 1
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
0 0 1 0
0 0 1 1

Table 7 Truth table of the proposed reversible block, NMG7

A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
C P
0 1
1 1
0 0
1 0
0 0
1 0
0 1
1 1
Q R
0 0
0 1
1 0
0 1
0 0
1 1
1 0
1 1

Table 8 Truth table of the proposed reversible block, NMG8

A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
C P
0 1
1 1
0 0
1 0
0 0
1 0
0 1
1 1
Q R
0 1
0 0
1 0
0 1
0 0
1 1
1 1
1 0

3.1.2 Proposed block, NMG2: The truth table of the proposed 4  The quantum realisation of the proposed reversible block
× 4 NMG2 block is shown in Table 2. NMG5 is shown in Fig. 9. As seen, the QC and the delay of this
The quantum realisation of the proposed reversible block block are equal to 5. In addition, its hardware complexity is 4α + 
NMG2 is illustrated in Fig. 6. As observed, the QC and the delay 6β +  5δ.
of this block are equal to 6. In addition, its hardware complexity is
4α + 2β +  3δ. 3.1.6 Proposed block, NMG6: The truth table of the proposed 4 
× 4 NMG6 block is shown in Table 6.
3.1.3 Proposed block, NMG3: The truth table of the proposed 4  The quantum realisation of the proposed reversible block
× 4 NMG3 block is shown in Table 3. NMG6 is shown in Fig. 10. As it is seen, the QC and the delay of
The quantum realisation of the proposed reversible block this block are equal to 5. In addition, its hardware complexity is 4α 
NMG3 is shown in Fig. 7. As seen, the QC and the delay of this + 2β.
block are equal to 5. In addition, its hardware complexity is 6α + 
2β +  3δ. 3.1.7 Proposed block, NMG7: The truth table of the proposed 3 
× 3 NMG7 block is shown in Table 7.
3.1.4 Proposed block, NMG4: The truth table of the proposed 4  The quantum realisation of the proposed reversible block
× 4 NMG4 block is shown in Table 4. NMG7 is shown in Fig. 11. As it is seen, the QC and the delay of
The quantum realisation of the proposed reversible block this block are equal to 5. In addition, its hardware complexity is 2α 
NMG4 is shown in Fig. 8. As seen, the QC and the delay of this + 2β + 2 δ.
block are equal to 6. In addition, its hardware complexity is 6α + 
6β +  4δ. 3.1.8 Proposed block, NMG8: The truth table of the proposed 3 
× 3 NMG8 block is shown in Table 8.
3.1.5 Proposed block, NMG5: The truth table of the proposed 4  The quantum realisation of the proposed reversible block
× 4 NMG5 block is shown in Table 5. NMG8 is shown in Fig. 12. As seen, the QC and the delay of this

810 IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815
© The Institution of Engineering and Technology 2019
Table 9 Comparative characteristics of reversible D latch designs (a) with output Q and (b) with outputs Q and Q̄
Reference GC CI GO QC Ratio
(a)
design in [11] 2 1 2 6 1.2
design in [17] 1 1 2 Not reported —
design#1 in [18] 1 1 2 6 1.2
design in [19] 2 1 2 6 1.2
design#1 in [21] 1 1 2 Not reported —
design in [22] 2 1 2 6 1.2
proposed design#1 1 1 2 5 1
proposed design#2 1 1 2 6 1.2
— — — — — —
(b) —
design in [10] 7 7 8 47 7.83
design in [12] 3 2 2 7 1.16
design in [13] 2 2 2 Not reported —
design in [14] 3 4 4 Not reported —
design#1 in [15] 5 5 5 15 2.5
design#2 in [15] 2 2 2 9 1.5
design in [16] 2 2 2 7 1.16
design#2 in [18] 2 2 2 7 1.16
design#2 in [21] 2 2 2 Not reported —
proposed design#3 2 2 2 6 1

Table 10 Comparative characteristics of different reversible T latch designs (a) with output Q and (b) with outputs Q and Q̄
Reference GC CI GO QC Ratio
(a) —
design in [11] 3 1 2 7 1.16
proposed design #1 3 1 2 6 1
— — — — — —
(b) —
design in [10] 10 10 12 46 7.66
design in [9] 3 2 2 13 2.16
design in [20] 4 2 2 7 1.16
design in [23] 3 2 2 Not reported —
design in [24] 2 2 2 10 1.66
design in [25] 2 2 2 8 1.33
proposed design #2 2 2 2 6 1

Table 11 Comparative characteristics of different reversible J-K latch designs with outputs Q and Q̄
Reference GC CI GO QC Ratio
design in [10] 10 10 12 46 4.18
design in [11] 4 3 4 16 1.45
design in [12] 5 2 3 13 1.18
design in [13] 4 2 3 Not reported —
design in [17] 2 2 3 Not reported —
design in [23] 2 2 3 Not reported —
design in [24] 3 2 3 15 1.36
proposed design #1 2 2 3 12 1.09
proposed design #2 2 2 3 11 1

Fig. 6  Quantum realisation of the proposed reversible block NMG2 Fig. 7  Quantum realisation of the proposed reversible block NMG3

block are equal to 4. In addition, its hardware complexity is 4α +  3.2 Proposed reversible latches designs
2β +  3δ. In this section, using some of the proposed reversible blocks and
FG gate, three reversible latches D, T and J-K are proposed.

IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815 811
© The Institution of Engineering and Technology 2019
Fig. 8  Quantum realisation of the proposed reversible block NMG4 Fig. 16  First proposed reversible T latch using the proposed NMG8 block
and FG gates

Fig. 9  Quantum realisation of proposed reversible block NMG5

Fig. 17  Second proposed reversible T latch using the proposed NMG6
block and FG gate

Fig. 10  Quantum realisation of the proposed reversible block NMG6

Fig. 18  First proposed reversible J-K latch using the proposed NMG2 and
NMG4 blocks

Fig. 11  Quantum realisation of the proposed reversible block NMG7

Fig. 19  Second proposed reversible J-K latch using the proposed NMG2
and NMG5 blocks
Fig. 12  Quantum realisation of the proposed reversible block NMG8

Fig. 13  First proposed reversible D latch using the proposed NMG1 block

Fig. 14  Second proposed reversible D latch using the proposed NMG4
block

Fig. 15  Third proposed reversible D latch using the proposed NMG5
block and FG gate

The output equation of a D latch with inputs D and CLK is

Fig. 20  QCA layout of the proposed NMG1 block
expressed as Qt + 1  =  Qt. CLK  + D.CLK.
The first proposed reversible D latch is shown in Fig. 13 using
the reversible NMG1 block.

812 IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815
© The Institution of Engineering and Technology 2019
Fig. 21  Simulation results of the proposed NMG1 block

As seen in Fig. 13, the proposed reversible D latch has CI equal

to 1 and GO equal to 2. Since only one NMG1 block is used in the
design, its QC is 5.
In Fig. 14, the second proposed reversible D latch is illustrated
using the NMG4 block.
As seen in Fig. 14, the proposed reversible D latch also has CI
equal to 1 and GO equal to 2. Since only one NMG4 block is used
in the design, its QC is 6.
In Fig. 15, the third reversible D latch is shown using the
proposed reversible NMG5 reversible block and FG gate.
As seen in Fig. 15, the proposed reversible D latch has CI and
GO equal to 2. Moreover, since only one NMG5 block and one FG
gate is used in the design, its QC is 6.
The output equation of the T latch with inputs T and CLK can
be written as Qt + 1  = T⊕Qt.CLK⊕Qt. CLK. Moreover, it can be
easily demonstrated that the above equation is equal to Qt + 1  = 
(T.CLK)⊕Qt.
The first proposed reversible T latch is shown in Fig. 16 using
the proposed reversible NMG8 block and two FGs gates.
As seen in Fig. 16, the proposed reversible T latch has CI equal
to 1 and GO equal to 2. Moreover, since only one NMG8 block and
two FG gates is used in the design, its QC is 6.
In Fig. 17, the second proposed reversible T latch is illustrated
using the NMG6 block and FG gate.
As seen in Fig. 17, the proposed reversible T latch has CI and
GO equal to 2. Moreover, since only one NMG6 block and one FG
gate is used in the design, its QC is 6.
The characteristic equation of J-K latch is Qt + 1  =  CLK. Qt  +  Fig. 22  Comparison of different D latches in terms of
CLK JQ̄t + K̄Qt . The first proposed reversible J-K latch is shown (a) Gate counts, (b) Constant inputs, (c) Garbage outputs, (d) Quantum cost
in Fig. 18 using the proposed reversible NMG2 and NMG4 blocks.
As seen in Fig. 18, the proposed reversible J-K latch has CI In this section, first, the results of the implementation of the
equal to 2 and GO equal to 3. Moreover, since only one NMG2 and proposed reversible NMG1 block (for example) are presented
one NMG4 block is used in the design, its QC is 12. using the QCADesigner 2.0.3 simulator with ‘Bistable
In Fig. 19, the second proposed reversible J-K latch is Approximation’ engine [38]. In the following, the results of the
illustrated using the NMG2 and NMG5 blocks. proposed reversible latches with the existing designs will be
As seen in Fig. 19, the proposed reversible J-K latch has CI compared.
equal to 2 and GO equal to 3. Moreover, since only one NMG2 and As mentioned, the NMG1 block is consisted of two 2-input
one NMG5 block is used in the design, its QC is 11. AND, one 2-input XOR gate and two 3-input XOR gates.
In order to achieve a proper QCA layout, the QCA XOR gate
4 Simulation results and comparisons provided in reference [39] is used. In addition, for the
implementation of the 2-input AND gate, 3-input majority gate is
used whose one of its inputs has been set to zero value. The QCA

IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815 813
© The Institution of Engineering and Technology 2019
Fig. 23  Comparison of the different T latch designs in terms of
(a) Gate count, (b) Constant input, (c) Garbage outputs, (d) Quantum cost
layout of the NMG1 block is illustrated in Fig. 20. As can be seen,
it is consisted of 247 cells and occupied 0.36 μm2. It also requires
2.5 clocks to produce the correct outputs.
As can be seen in Fig. 20, wire crossing is performed using
through different zones of the clock in a single layer based on
Abedi clocking scheme [40].
The simulation results of the NMG1 block for all combination
of the inputs are shown in Fig. 21. It should be mentioned that all
parameters and simulation conditions have been set as their default
values in the QCADesigner software.
As can be seen in Fig. 21, for example, for input vector
(A,B,C,D) = (1,0,0,1) which is encoded with digit 9, the output
vector (P,Q,R,Q) = (1,0,0,1) is achieved correctly.
814
Fig. 24  Comparison of J-K latch properties in terms of
(a) Gate count, (b) Constant input, (c) Garbage outputs, (d) Quantum cost
In the following, we have evaluated the proposed D, T and J-K
latches with respect to the existing designs in terms of GC, CI, GO,
QC and Ratio criteria. Ratio criterion denoted the ratio of QC of
each existing design in comparison with QC of the proposed
design.
The evaluation results of the proposed D, T and J-K- latches are
provided in Tables 9–11, respectively.
In addition, the visual comparisons of the proposed designs
with other designs in terms of GC, CI, GO, and QC are presented
in Figs. 22–24, respectively.
As shown in Table 9 (a), the QC of the proposed design#1,
compared with the best previous design in [18], shows an
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815
© The Institution of Engineering and Technology 2019
improvement of 16.66%. In addition, its’ GC, CI and GO criteria
are smaller or equal to all of previous designs.
Also, based on evaluation results which are illustrated in
Table 9(b), the QC of the proposed design#3 is 87.23 and 14.28%
compared with the worst and best previous designs, respectively.
As shown in Table 10 (a), the QC of the proposed design#1,
compared with the previous design [11], shows an improvement of
14.28%.
Also, based on evaluation results which are given in Table 10
(b), the QC of the proposed design#2 is 86.95 and 14.28%
compared with the worst and best previous designs, respectively.
As shown in Table 11, the QC of the proposed designs #1and
#2, compared with the best previous design in [12], shows
improvements of 7.69 and 15.38%, respectively. In addition, their
other criteria are smaller or equal to all of previous designs.
5 Conclusion
Here, eight novel reversible blocks were first introduced. Then,
three effective D, T, and J-K latches were proposed by helping
some of the proposed reversible blocks and FG gate. The results of
the comparisons show that although the proposed latch designs are
very close to the best previous architectures in terms of GC, CI,
and GO criteria, they are superior to the QC criterion. Utilising the
proposed latch designs in the reversible sequential circuits such as
registers, counters, and RAM minimise the QC and delay criteria.
The scales are in the nano-metric area.
6 Acknowledgment
The presented paper is the result of an MSc dissertation entitled
‘Proposing a New Approach for Designing Reversible Memories’,
which was performed in Islamic Azad University of Dezful and the
authors hereby express their thanks.
7 References
[1] Landauer, R.: ‘Irreversibility and heat generation in the computing process’,
IBM J. Res. Dev., 1961, 183–191, pp. 183–191
[2] Bennett, C.H.: ‘Logical reversibility of computation’, IBM J. Res. Dev., 1973,
17, pp. 525–532
[3] Perkowski, M., Jozwiak, L., Kerntopf, P., et al.: ‘A general decomposition for
reversible logic’, 2001
[4] PourAliAkbar, E., Mosleh, M.: ‘An efficient design for reversible wallace
unsigned multiplier’, Theor. Comput. Sci., 2019, 773, pp. 43–52
[5] Babu, H.M.H., Mia, M.S.: ‘Design of a compact reversible fault tolerant
division circuit’, Microelectron. J., 2016, 51, pp. 15–29
[6] Biswas, A.K., Hasan, M.M., Chowdhury, A.R., et al.: ‘Efficient approaches
for designing reversible binary coded decimal adders’, Microelectron. J.,
2008, 39, pp. 1693–1703
[7] Toffoli, T.: ‘Reversible computing’. Int. Colloquium on Automata,
Languages, and Programming, Berlin, Heidelberg, 1980, pp. 632–644
[8] Fredkin, E., Toffoli, T.: ‘Conservative logic’, Int. J. Theor. Phys., 1982, 21,
pp. 219–253
[9] Pareek, V., Gupta, S., Jain, S.C., et al.: ‘A novel realization of sequential
reversible building blocks’. FUTURE COMPUTING 2014, The Sixth Int.
Conf. on Future Computational Technologies and Applications, Venice, 2014,
pp. 1–6
[10] Thapliyal, H., Srinivas, M., Zwolinski, M.: ‘A beginning in the reversible
logic synthesis of sequential circuits’, Military and Aerospace Applications of
Programmable Devices and Technologies International Conference
(MAPLD), USA, September 2005
[11] Hari, S.K.S., Shroff, S., Mahammad, S.N., et al.: ‘Efficient building blocks
for reversible sequential circuit design’. 49th IEEE Int. Midwest Symp. on
Circuits and Systems, 2006. MWSCAS'06, San Juan, Puerto Rico, 2006, pp.
437–441
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 806-815
© The Institution of Engineering and Technology 2019
[12] Thapliyal, H., Ranganathan, N.: ‘Design of reversible sequential circuits
optimizing quantum cost, delay, and garbage outputs’, ACM J. Emerg.
Technol. Comput. Syst. (JETC), 2010, 6, p. 14
[13] Sayem, A.S.M., Ueda, M.: ‘Optimization of reversible sequential circuits’,
arXiv preprint arXiv:1006.4570, 2010
[14] Ali, M.B., Hossin, M.M., Ullah, M.E.: ‘Design of reversible sequential circuit
using reversible logic synthesis’, Int. J. VLSI des. Commun. Syst. (VLSICS),
2011, 2, pp. 37–45
[15] Biswas, A.K., Jamal, L., Mottalib, M., et al.: ‘Design of a reversible parallel
loading shift register’, Dhaka Univ. J. Eng. Technol., 2011, 1, pp. 1–5
[16] Mamun, M., Al, S., Hossain, S.M.: ‘Design of reversible random access
memory’, arXiv preprint arXiv:1312.7354, 2013
[17] Mamun, M., Al, S., Mandal, I., et al.: ‘Efficient design of reversible
sequential circuit’, arXiv preprint arXiv:1407.7101, 2014
[18] Ananthalakshmi, A., Sudha, G.: ‘Design of 4-Bit reversible shift registers’,
WSEAS Trans. Circuits Syst., 2013, 12, pp. 376–385
[19] Thapliyal, H., Zwolinski, M.: ‘Reversible logic to cryptographic hardware: a
new paradigm’. 49th IEEE Int. Midwest Symp. on Circuits and Systems,
2006. MWSCAS'06, San Juan, Puerto Rico, 2006, pp. 342–346
[20] Banik, D.: ‘Design of low cost latches based on reversible quantum dot
cellular automata’. 2016 Sixth Int. Symp. on Embedded Computing and
System Design (ISED), Patna, India, 2016, pp. 181–186
[21] Karthik, S., Varghese, A., Sandhya, G.: ‘QCA estimation of low power
reversible circuits’, Quantum, 2013, 3, pp. 1273–1278
[22] Al Mamun, M.S., Mandal, I., Hasanuzzaman, M.: ‘Design of universal shift
register using reversible logic’, Int. J. Eng. Technol., 2012, 2, pp. 1620–1625
[23] Bhagyalakshmi, H., Venkatesha, M.: ‘Design of sequential circuit elements
using reversible logic gates’, World Appl. Program., 2012, 2, pp. 263–271
[24] Thapliyal, H., Vinod, A.P.: ‘Design of reversible sequential elements with
feasibility of transistor implementation’. IEEE Int. Symp. on Circuits and
Systems, 2007. ISCAS 2007, New Orleans, LA, USA, 2007, pp. 625–628
[25] Pareek, V.: ‘A new gate for optimal fault tolerant & testable reversible
sequential circuit design’, arXiv preprint arXiv:1410.2373, 2014
[26] Szyprowski, M., Kerntopf, P.: ‘An approach to quantum cost optimization in
reversible circuits’. 11th IEEE Conf. on Nanotechnology (IEEE-NANO),
2011, Portland, OR, USA, 2011, pp. 1521–1526
[27] Haghparast, M., Mohammadi, M., Navi, K., et al.: ‘Optimized reversible
multiplier circuit’, J. Circuits, Syst. Comput., 2009, 18, pp. 311–323
[28] Feynman, R.P.: ‘Quantum mechanical computers’, Found. Phys., 1986, 16,
pp. 507–531
[29] Barenco, A., Bennett, C.H., Cleve, R., et al.: ‘Elementary gates for quantum
computation’, Phys. Rev. A, 1995, 52, p. 3457
[30] Sen, B., Dutta, M., Some, S., et al.: ‘Realizing reversible computing in QCA
framework resulting in efficient design of testable ALU’, ACM J. Emerg.
Technol. Comput. Syst. (JETC), 2014, 11, p. 30
[31] Hung, W.N., Song, X., Yang, G., et al.: ‘Optimal synthesis of multiple output
boolean functions using a set of quantum gates by symbolic reachability
analysis’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2006, 25,
pp. 1652–1663
[32] Smolin, J.A., DiVincenzo, D.P.: ‘Five two-bit quantum gates are sufficient to
implement the quantum fredkin gate’, Phys. Rev. A, 1996, 53, p. 2855
[33] Morrison, M.A.: ‘Design of a reversible alu based on novel reversible logic
structures’, 2012
[34] Banerjee, A., Pathak, A.: ‘An algorithm for minimization of quantum cost’,
arXiv preprint arXiv:0910.2129, 2009
[35] Shoaei, S., Haghparast, M.: ‘Novel designs of nanometric parity preserving
reversible compressor’, Quantum Inf. Process., 2014, 13, pp. 1701–1714
[36] Islam, M.S., Rahman, M.M., Begum, Z., et al.: ‘Synthesis of fault tolerant
reversible logic circuits’. IEEE Circuits and Systems Int. Conf. on Testing and
Diagnosis, 2009. ICTD 2009, Chengdu, China, 2009, pp. 1–4
[37] Mohammadi, M., Eshghi, M.: ‘On figures of merit in reversible and quantum
logic designs’, Quantum Inf. Process., 2009, 8, pp. 297–318
[38] Walus, K., Dysart, T.J., Jullien, G.A., et al.: ‘QCADesigner: A rapid design
and simulation tool for quantum-dot cellular automata’, IEEE Trans.
Nanotechnol., 2004, 3, pp. 26–31
[39] Ahmadpour, S.-S., Mosleh, M., Heikalabad, S.R.: ‘A revolution in
nanostructure designs by proposing a novel QCA full-adder based on
optimized 3-input XOR’, Phys. B, 2018, 550, pp. 383–392
[40] Abedi, D., Jaberipur, G., Sangsefidi, M.: ‘Coplanar full adder in quantum-dot
cellular automata via clock-zone-based crossover’, IEEE Trans. Nanotechnol.,
2015, 14, pp. 497–504
815