EE 473/538 Communication ICs Winter 2019

Homework #1
Read all of Chapter 1 in Gray and Meyer, specifically focusing on P-N junctions, MOS
and BJT transistors.
Due at the beginning of class, Wednesday, Jan, 16th.

Gray & Meyer Problems.

1.1
1.2
1.3
1.8
1.15: For this problem, please perform the additional simulations and calculations:
a) Simulate in Cadence the ID-VDS curves using the device parameters given in the
problem.
b) Perform the same simulation (ID-VDS curves) using 65nm design kit which will be used
for the remainder of this class.
c) From your simulated I-V curves, estimate the early voltage VA and the device output
resistance when the device is in the saturation region for both part a) and b). Explain why
the results are different.
1.17
1.18