ZYNQ-7000 SOC

Zynq-7000 SoC Overview

 Zynq-7000 devices are equipped with dual-core
ARM Cortex-A9 processors with 28nm Artix-7 or
Kintex-7 based programmable logic for excellent
performance and maximum design flexibility.
 The ARM Cortex-A9 CPUs are the heart of the PS
and also include on-chip memory, external
memory interfaces and a rich set of peripheral
connectivity interfaces
 Zynq-7000 Family Highlights
 Complete ARM®-based processing system
• Application Processor Unit (APU)
 Dual ARM Cortex™-A9 processors
 Caches and support blocks
• Fully integrated memory controllers
• I/O peripherals
 Tightly integrated programmable logic
• Used to extend the processing system
• Scalable density and performance
 Flexible array of I/O
• Wide range of external multi-standard I/O
• High-performance integrated serial transceivers
• Analog-to-digital converter inputs
Block Diagram
 The PS and the PL
 The Zynq-7000 AP SoC architecture consists of two
major sections
• PS: Processing system
 Dual ARM Cortex-A9 processor based
 Multiple peripherals
 Hard silicon core
• PL: Programmable logic
 Shares the same 7 series programmable logic
Processing System (PS) Features &
Descriptions
 Processing System (PS)

The Processing System is mainly divided

into three parts

1. Application Processing Unit (APU)

2. Memory interfaces
3. I/O Peripherals
 Application Processing Unit(APU)
 The application processing unit (APU), located within the PS,
contains one processor for single-core devices or two processors for
dual-core devices.
 ARM Cortex-A9 processors with NEON co-processors
 Each processor has 32KB L1 cache for instruction and data.
 Can execute 32-bit ARM instructions, 16-bit and 32-bit Thumb
instructions
 To increase performance, there is a shared unified 512 KB level-two
(L2) cache for instruction and data.
8-way set associative
 Alongwith cache there is On Chip Memory (OCM) of 256 KB for that
provide low latency memory.
 Application Processing Unit(APU)
 Application Processing Unit has Snooping Control
Unit.
Maintain L1 cache coherency between two processors and
the ACP interface from the PL
Accelerator Coherency Port (ACP) facilitate communication
between PS(Programmable Logic) and APU
64 bit AXI interface to access L2 cache and On Chip Memory
 Cortex A9 Processor
 Major sub blocks within Cortex A9 processor are
• Central Processing Unit (CPU)
• L1 instruction and data cache
• Memory Management Unit (MMU)
• NEON co processor and core interfaces
 Central Processing Unit
 Each cortex A9-CPU issue two instructions in one
cycle
 Out of Order execution
 Dynamic branch prediction
 Can execute 32-bit ARM instructions, 16-bit and
32-bit Thumb instructions
 Level 1 Cache

 Each of the two Cortex-A9 processors has separate

32 KB level-1 instruction and data caches.
 Both cache are 4-way set associative
 The L1 instruction cache (I-Cache) is responsible
for providing instructions to processor
 The L1 data cache (D-Cache) is responsible for
holding the data used by processor
 Memory Management Unit (MMU)
 The MMU in the ARM architecture involves both
memory protection and address translation.
 MMU is responsible for the following operations
• Checking of virtual address and ASID (address space
identifier)
• Checking of domain access permissions
• Checking of memory attributes
• Virtual-to-physical address translation
• Mapping of accesses to cache, or external memory
 NEON
 The cortex A-9 NEON extends the Cortex-A9
functionality to provide support for the ARM v7
advanced SIMD and vector floating-point v3
(VFPv3) instruction sets.
 The Cortex-A9 NEON MPE features are:
• SIMD vector and scalar single-precision floating-point
computation
 Unsigned and signed integers
 Single bit coefficient polynomials
 Single-precision floating-point values
 Application Processing Unit(APU)
 Dual/Single ARM Cortex-A9 MP Core CPUs with
ARM v7
• Run time options allow single processor
• Asymmetrical multiprocessing (AMP) or Symmetrical
multiprocessing (SMP)
• NEON 128mb SIMD coprocessor and VFPv3 per MP Core
• 32 KB instruction and 32 KB data L1 cashes with parity per
MP Core
• 512 KB of shareable L2 cache with parity
• Private timers and watchdog timers
 Application Processing Unit(APU)
System Features
• System level control registers (SLCRs)
 Group of various registers that are used to control the PS behavior
• Snoop Control Unit (SLU) to maintain L1 & L2 coherency
• Accelerator coherency port (ACP) from PL(master) to
PS(slave)
 64b AXI slave port
 Can access the L2 and the OCM
 Transactions are data coherent with L1 and L2 caches
 Application Processing Unit(APU)
 256 KB on chip memory (OCM) with parity
• Dual ported
• Accessible by the CPUs, PL and the central interconnect
• At level of L2 but is not cacheable
 DMA controller
• Four channels for PS(memory to memory transitions)
• Four channels for PL (memory to PL, PL to memory)
 Application Processing Unit(APU)
 General interrupt controller (GIC)
• Individual interrupt masks
• Five CPU-private peripheral interrupts (PPI)
• Sixteen CPU private software generated interrupts (SGI)
 Watchdog timer, triple counter/timer
 Memory Interfaces
The memory interfaces includes multiple memory
technologies

 DDR Controller
• Support DDR3, DDR3L, DDR2, LPDDR-2
• 16b or 32b wide
• Uses up to 73 dedicated PS pins
• Obeys AXI ordering rules
 Memory Interfaces
 Quad-SPI Controller
• Single or dual
• 1x and 2x read support
• 32 bit AXI linear address mapping interface for read
operations
• 4 bit bidirectional I/O signals
• Maximum Quad-SPI clock at master mode is 100MHz
 Memory Interfaces
 Static Memory Controller (SMC)
• NAND controller
 8/16-bit I/O width with one chip select signal
 16-word read and 16-word write data FIFOs
 8-word command FIFO
• Parallel SRAM/NOR controller
 8-bit data bus width
 One chip select with up to 25 address signals
 Two chip selects with up to 25 address signals
 8-word command FIFO
 I/O Peripheral
To communicate with external word

 GPIO
• Up to 54 GPIO signals for device pins
routed through MIO
• 192 GPIO signals between the PS and PL
via the EMIO
 64 inputs, 128 outputs
• Programmable interrupts on individual
GPIO basis
 I/O Peripheral
 Gigabit Ethernet Controllers (2)
• RGMII interface using MIO pins and external PHY
• Additional interface using PL Select IO and external PHY with
additional soft IP in PL
• Built-in DMA with scatter-gather
 USB Controllers
 SD/SDIO Controllers(2)
 SPI Controller (2)
• Master or slave
 I/O Peripheral
 UART Controllers(2)
• Programmable baud rate generator
• 64-byte transmit and receive FIFOs
• Rx and Tx signals are on the MIO and EMIO interfaces

 CAN Controllers(2)
 I2C Controllers(2)
 Processing System Interconnect (1)
 Programmable logic to memory
• Two ports to DDR
• One port to OCM SRAM
 Central interconnect
• Enables other interconnects to
communicate
 Peripheral master
• USB, GigE, SDIO connects to DDR
and PL via the central
interconnect
 Peripheral slave
• CPU, DMA, and PL access to IOP
peripherals
Processing System Interconnect (2)
 Processing system master
• Two ports from the
processing system to
programmable logic
• Connects the CPU block to
common peripherals
through the central
interconnect
 Processing system slave
• Two ports from
programmable logic to the
processing system
 Memory Map
 The Cortex-A9 processor uses 32-
bit addressing
 All PS peripherals and PL
peripherals are memory
mapped to the aCortex-A9
processor cores
 All slave PL peripherals will be
located between
4000_0000 and 7FFF_FFFF
(connected to GP0) and
8000_0000 and BFFF_FFFF
(connected to GP1)
 Zynq AP SoC Memory Resources
 On-chip memory (OCM)
• RAM
• Boot ROM
 DDRx dynamic memory controller
• Supports LPDDR2, DDR2, DDR3
 Flash/static, memory controller
• Supports SRAM, QSPI, NAND/NOR FLASH
 PS Boots First
 CPU0 boots from OCM ROM; CPU1 goes into a sleep state
 On-chip boot loader in OCM ROM (Stage 0 boot)
 Processor loads First Stage Boot Loader (FSBL) from external flash
memory
• NOR
• NAND
• Quad-SPI
• SD Card
• JTAG; not a memory device—used for development/debug only
• Boot source selected via package bootstrapping pins
 Optional secure boot mode allows the loading of encrypted
software from the flash boot memory
 Configuring the PL
 The programmable logic is configured after the PS boots
 Performed by application software accessing the
hardware device configuration unit
• Bitstream image transferred
• 100-MHz, 32-bit PCAP stream interface
• Decryption/authentication hardware option for encrypted
bitstreams
 In secure boot mode, this option can be used for software memory load
• Built-in DMA allows simultaneous PL configuration and OS memory
loading
 PS-PL Interfaces
 AXI high-performance slave ports (HP0-HP3)
• Configurable 32-bit or 64-bit data width
• Access to OCM and DDR only
• Conversion to processing system clock domain
• AXI FIFO Interface (AFI) are FIFOs (1KB) to
smooth
large data transfers
 AXI general-purpose ports (GP0-GP1)
• Two masters from PS to PL
• Two slaves from PL to PS
• 32-bit data width
• Conversation and sync to processing system
clock domain
 PS-PL Interfaces
 One 64-bit accelerator coherence port (ACP) AXI slave interface
to CPU memory
 DMA, interrupts, events signals
• Processor event bus for signaling event information to the CPU
• PL peripheral IP interrupts to the PS general interrupt controller (GIC)
• Four DMA channel RDY/ACK signals
 Extended multiplexed I/O (EMIO) allows PS peripheral ports
access to PL logic and device I/O pins
 Clock and resets
• Four PS clock outputs to the PL with enable control
• Four PS reset outputs to the PL
 Configuration and miscellaneous
 PL Clocking Sources
 PS clocks
• PS clock source from external package pin
• PS has three PLLs for clock generation
• PS has four clock ports to PL
 The PL has 7 series clocking resources
• PL has a different clock source domain compared to the PS
• The clock to PL can be sourced from external clock capable pins
• Can use one of the four PS clocks as source
 Synchronizing the clock between PL and PS is taken care of
by the architecture of the PS
 PL cannot supply clock source to PS
 Summary
 The Zynq-7000 processing platform is a system on a chip
(SoC) processor with embedded programmable logic
 The processing system (PS) is the hard silicon dual core
consisting of
• APU and list components
 Two Cortex-A9 processors
 NEON co-processor
 General interrupt controller (GIC)
 General and watchdog timers
• I/O peripherals
• External memory interfaces
 Summary
 The programmable logic (PL) consists of 7 series devices
 AXI is an interface providing high performance through point-to-point
connection
 AXI has separate, independent read and write interfaces implemented with
channels
 The AXI4 interface offers improvements over AXI3 and defines
• Full AXI memory mapped
• AXI Lite
• AXI Stream
 Tightly coupled AXI ports interface the PL and PS for maximum performance
 The PS boots from a selection of external memory devices
 The PL is configured by and after the PS boots
 The PS provides clocking resources to the PL
 The PL may not provide clocking to the PS