A Compact Sub-circuit Modeling Methodology with

Spectre-like Simulation Accuracy

Abstract—A bias-dependent resistor-current source model of
MOSFET enabling the abstraction of a CMOS sub-circuit into its
Thevenin equivalent is proposed. Transient responses of CMOS
circuits including inverter, 2-input NAND, 2-input NOR, 2:1
Multiplexer, Latch and Differential amplifier using this method
are compared with Spectre [1] simulations. The simulation
waveforms for voltages and currents at internal and input/output
nodes correlate within 5% to spectre results. This modeling
can be very useful for co-simulations of Analog Mixed Signal
(AMS) designs since it captures all of the circuit behavior with
good accuracy and is inherently fast due to the abstraction of
transistor-level details to the sub-circuit level.
I. I NTRODUCTION
Devices and circuit modeling has been a premier research
interest for decades in the field of Electronics. Recent ap-
proaches use efficient look-up table (LUT) techniques [2], [3].
LUT approaches use pre-characterized device information e.g.
I-V/C-V data. Further, for LUT based simulation approach,
spline-based interpolation techniques for spanning the entire
voltage range have been proposed [4]. In yet another method
[5], along with the currents, charges are also tabulated from the
derivatives for accurate analog circuit simulation. Fast spice
simulators use look-up tables [6] to capture transistor IV and
CV characteristics at discrete operating points to bypass the
computationally-intensive physics-based complex equations.
In order to have a smooth transition between various regions
of MOS operation, a cubic spline interpolation technique is
adopted [6].
In the current work, we too use the LUT. However, the key
distinction in our approach is that we model the MOSFET
as a bias-dependent parallel combination of resistance and
current source. The extraction of the resistance and current
source value as a function of bias point is explained in section
II. The tool is developed in an attempt to obtain (i) very
accurate timing results for CMOS logic circuits using LUT
driven approach, (ii) yet with minimal computing burden,
thereby producing results faster. This approach eliminates
the transistor-level device equations completely thus reducing
simulation complexity and run times. LUT data for FETs is
obtained by running Spectre [1] simulations. Details such as
input capacitance, miller effect are also modeled. Abstraction
of the transistor-level CMOS sub-circuit into a simple bias-
dependent Thevenin equivalent for every internal/output node
of interest is carried out. This makes the design look like a
gate/block level netlist instead of a MOSFET level representa-
tion. This abstraction could be used in the simulation of larger
circuits by replacing the sub-circuits with the corresponding
abstracts.
Fig. 1 captures the abstraction brought in by this approach.
A transistor-level circuit as shown in Fig. 1(a) which in-
cludes the device and wire parasitics, is reduced to algorithm-
generated abstracts for the various sub-circuits as shown in
Fig. 1(b). The methodology can be readily used in layout
extracted contexts. The method can also support statistical
analyses (Monte Carlo)/ sensitivity analyses.
The paper is organized as follows. Section II describes the
modeling of FETs. A NAND gate is considered as an exam-
ple in section III for modeling. The algorithm is explained
in section IV. The simulation results are compared against
Spectre in section V. Hierarchical abstraction of a larger circuit
into a simple Thevenin equivalent is shown in section VI, and
conclusions are provided in Section VII.
II. MOSFET MODELING
MOSFETs are highly non-linear devices but using the
following procedure, we have converted the transistors and in
turn, the CMOS circuit problems, into equivalent linear circuits
which are then solved using linear circuit analysis methods.
MOSFET is modeled as a resistance in parallel with a
current source between drain and source terminals (Fig. 2(a)),
recognizing the dependence on the terminal voltages (bias).
The R and I values would vary widely across the range of
operating voltages, thus capturing the exact transistor behavior
at every bias point, and the same are derived from the device
I-V data at every bias point using the slope and intercept
(Fig. 2(b)).
The C-V data (C1, C2, C3 in Fig. 3) are extracted for VGS
and VDS sweeps of a MOSFET. A layout-extracted netlist
will contain parasitics from FEOL (front-end-of-line) and
BEOL (back-end-of-line) in the form of MOSFET models
(which include Layout Dependent Effects (LDE)), resistors
and capacitors. The LDE is captured by using the FET instance
from the extracted netlist in this C-V/I-V characterization. The
parasitics (R and C) in the extracted netlist are clubbed with
the bias-dependent device capacitances.
III. CMOS SUB - CIRCUIT M ODEL - 2- INPUT NAND GATE
WITH RC LOAD (A N EXAMPLE )
Fig. 4(a) shows the actual 2-input NAND circuit. Equivalent
model for Cds capacitance between output node (Vout ) and
internal node (Vint ) is shown in Fig. 4(b). The output-side
model includes the equivalent circuits for the FETs and also
the load impedance (Fig. 4(c)) . The equivalent model at the
output (drain) side is then reduced step-by-step using source
 VDD RP- Device / Wire Parasitic Resistance
VDD CP- Device / Wire Parasitic Capacitance VDD
V2
V5B V5
V1 VO1
V1 Mux
VO1
VDD QO
RP ,CP
V2
RP ,CP VO2
V2
VDD V3
VDD AO BO
V5 V5B
V3 V4
QO RP ,CP
Latch
BO
RP ,CP AO VO2
VDD
BO V5
V4
AO V5B
V3
RP ,CP RTh
Thevenin VTh
V5 Equivalent

(a) (b)
Fig. 1. (a) A representative transistor-level circuit block. (b) Circuit block with abstracted sub-circuits that include parasitic effects as well.

D D
play any role at steady state. Manually derived circuit
G
Rn In ID equations are used to calculate all the node voltages /
S
Vgs = 0.5V currents of the circuit at time t (for e.g., as shown in
S
NMOS Transistor Static Modeling
Fig. 5) when at least one input voltage changes by an
S S
Resistance (Rn)
= (dVds/dID) = (1/slope)
incremental value (0.01V).
G
5) The time value and the calculated voltage/current values
Rp Ip Current source (In)
= (ID | Vds = 0V) = y-intercept are written to the output text file.
D
D 6) The following parameters are computed for all the FETs:
0 0.4V 0.41V Vds
PMOS Transistor Static Modeling (i) Gate to source voltage (Vgs ), (ii) Drain to source
(a) (b) voltage (Vds ), (iii) Resistance value for the calculated Vgs
Fig. 2. (a) Bias dependent (f(Vgs , Vds ) static modeling of MOSFETs (b) and Vds using I-V data (Fig. 2), (iv) Current source value
Extracting FET equivalent model parameters from ID - VDS data. for the calculated Vgs and Vds using I-V data (Fig. 2), and
(v) all the parasitic capacitance values for the calculated
D Vgs and Vds using C-V data. Miller effect is also included
C1
1.20E-16 C-V Extraction @Vds=0.6 volts for Cgd. Further, the effective Cgd is computed based on
1.00E-16 the voltage swings on either nodes of the capacitance as
Capacitance ( F )

G C3
8.00E-17

6.00E-17
shown in Fig. 6.
ϭ
C2
4.00E-17 ϯ 7) The time value and the calculated voltage/current values
S Ϯ

C1 = capacitance between gate and drain

2.00E-17

0.00E+00
are written to the output text file.
C2 = capacitance between gate and source
C3 = capacitance between drain and source
0 0.2 0.4 0.6
Vgs( Volts)
0.8 1
8) Steps 6 through 8 are repeated to cover the entire time
(a) (b)
range from the input voltage vs. time data.
Fig. 3. (a) Lumped-parameter capacitance model of MOSFET (b) C-V curves
Steps 1 and 2 comprise the abstracted model of the sub-
for various capacitances of an as a function of Vgs, at a fixed Vds of 0.6V. circuit. Steps 3 - 8 are handled by scripts, which can be
replaced by calls to the abstracted model by a tool like Spectre.

transformation techniques to its final Thevenin equivalent V. R ESULTS

form, as shown in Fig. 5. This methodology is applied to various CMOS logic circuits
like inverter, 2-input NAND, 2-input NOR, 2:1 Multiplexer.
IV. A LGORITHM Table I summarizes the comparison results between the pro-
1) I-V and C-V data are read for PMOS and NMOS devices posed method and Spectre simulations for different 32nm
from text files and are subsequently stored in 2-D arrays. CMOS logic circuits. Different simulation conditions are also
2) The input impedance of the subsequent sub-circuit is considered for the various logic blocks so as to check for input-
fed-in as the load impedance (load resistance in series dependent delays. It is observed that the error in propagation
with load capacitance) to the sub-circuit being modeled. delays (TPLH (low-to-high) and TPHL (high-to-low)) and rise
3) Primary input voltage(s) versus time data is read from and fall times (TR and TF ) is within 5%. The transient voltage
text file, and is stored in 1-D arrays. / current waveforms at the internal node (Vint ) for a 2-input
4) Using the input voltage value(s) at t=0, (steady state NAND gate appear to be in good agreement with those from
condition of the circuit), output/intermediate node volt- Spectre, as seen in Fig. 7.
ages/currents of the circuit are calculated using KVL and The device characterization need for Step 1 of Section
KCL. The capacitances are disregarded as they do not IV can be a large effort if the circuit consists of several
 VDD

Vout Cdsbna Vint Rpa Ipa Rpb Ipb

RL
T2 Vout
T1
Vin1

Cdsbna Vint

Cgdna Vin1
Vin2

Cgdpb Vin2
Cgdpa Vin1

Cdsbpa

Cdsbpb

Cdsbna
Cgdpa
(PA)

Cgdpb

Cgdna
(PB)

.
CL

.
.
Vout
VC
T3 RL Rna Ina
Vin1 CL
(NA) Vout Iint-avg
Vint
Vint

Cdsbnb
Cgsbna Vin1

Cgsbn

Cgdnb
Cgdnb Vin2
.
Vin2 T4

.
Cdsbna Vint

a
Rnb Inb
(NB) Cdsbna

(a) (b) (c)

Fig. 4. (a) CMOS NAND gate with RC Load (b) Equivalent model for Cds between output node (Vout ) and internal node (Vint ) (c) Output-side model.

VDD VDD
RTh RL
Rpa Ipa Rpb Ipb
Rpa Ipa Rpb Ipb
RL VTh Cout CL
Vout RL
Vout
Cdsbna Vint

Cgdna Vin1
Cgdpb Vin2
Cgdpa Vin1

Cdsbpa

Cdsbpb

Cdsbna
Cgdpa

Cgdpb

Cgdna

. . . .
.

I out = (Cdsbna Vint + C gdpa Vin1 + C gdpb Vin 2 + C gdna Vin1 )

.

CL
.
.

Iout Cout CL
Cout = (Cdsbpa + Cdsbpb + Cdsbna
. + C gdpa + C gdpb + C gdna )
. .
'
I nb = ( I nb − C gsbna Vin1 − C gdnb Vin 2 + I int − avg )
Rna Ina
V DD
Iint-avg Rna Ina VTh = ( I p + + I out − I n ). RTh
Vint Rp
R p Rn
R R
Cdsbnb
Cgsbna Vin1

Cgsbna

Cgdnb

Vint RTh = , R p = pa pb , Rn = Rna + Rnb

Cgdnb Vin2

R p + Rn R pa + R pb
.

Rnb Inb
I’nb Rnb I na Rna + I nb
'
Rnb
I p = ( I pa + I pb ), I n =
Rna + Rnb

(a) (b) (c)

Fig. 5. Step-by-step circuit reduction for CMOS NAND gate with RC load to its Thevenin equivalent form.

1) Applying Miller effect to an inverter circuit :

1.4

Updated model 1.2 Vint 1.E-02

I_int
1 Vints (Spectre) 1.E-03 I_ints (Spectre)
Voltage ( V )

1.E-04
0.8
Current ( A )

1.E-05
Cgdp 0.6
1.E-06
Vin Vin C1inm Vout 0.4 1.E-07
0.2 1.E-08
Vout C1outm C2outm
Cgdn 0 1.E-09
0.0E+00 2.0E-10 4.0E-10 6.0E-10 8.0E-10 1.0E-09 1.E-10
-0.2 0.0E+00 2.0E-10 4.0E-10 6.0E-10 8.0E-10 1.0E-09
Time (sec)
C2inm Time ( sec )

(a) (b)
2) Effective capacitance estimation when both the terminals are switching Fig. 7. Comparison of transient simulation results at the intermediate node
(Vint ) for a 2-input NAND gate between proposed method and Spectre (a)
+∆V1 C -∆V2 Voltage (b) Current.
C (∆V1 + ∆V2) / ∆V1

Fig. 6. Inclusion of Miller effect in the MOSFET model.

VI. H IERARCHICAL ABSTRACTION AND CO - SIMULATION
A hierarchical abstraction of a larger circuit using sub-
circuits simulated through the algorithm is done. As an ex-
transistor types and sizes. Therefore, parallelization of the ample, a buffer circuit in 14nm FinFET technology is con-
characterization effort was important in this exercise, thus sidered that has an inverter driving another identical inverter.
making it independent of the number, type and sizes of In this case, the inverter (sub-circuit) is simulated using
devices. An ADC circuit with 47 different types / sizes of the proposed method to obtain VTH and RTH as a function
devices took 48 hours of wall clock time for characterization. of input voltage (Vin). This is fed in as the input to the
We expect the simulation time to be orders of magnitude lesser second inverter (which in-turn is reduced to its Thevenin
than when using conventional simulators like Spectre (Results equivalent) to obtain the final VTHN and RTHN values, thus
will be presented at the conference). modeling a buffer circuit hierarchically from its sub-circuits.
 TABLE I
C OMPARISON SUMMARY OF SIMULATION RESULTS BETWEEN PROPOSED METHOD AND S PECTRE FOR DIFFERENT CMOS SUB - CIRCUITS .

Circuit Condition Error in TPLH (%) Error in TPHL (%) Error in TF (%) Error in TR (%)
Inverter - 0.65 4.49 0.02 2.84
2-i/p NAND Top NFET switching 0.29 4.68 -0.14 2.96
2-i/p NAND Bottom NFET switching 0.59 4.55 0.59 3.11
2-i/p NOR Top PFET switching 0.5 2.84 -0.24 1.69
2-i/p NOR Bottom PFET switching 0.18 2.79 -0.53 1.66
2:1 Mux S=0V, A=0.6V, B=pulse -1.93 1.70 -2.00 0.16
2:1 Mux S=pulse, A=0V, B=1V -0.16 -0.91 -1.43 -2.36

VDD VDD VDD

RL
RL Vin Vo2
Vin Vo2
Vd12
Vout 0.80 Vout Vs Vin1
ŝƌĐƵŝƚĨŽƌ^ƉĞĐƚƌĞƐŝŵƵůĂƚŝŽŶ 0.70
CL
0.60

Voltage (V)
0.50
Vin1 Vin2
Vds 0.40
0.30 Vin1
ŝƌĐƵŝƚƌĞĚƵĐƚŝŽŶƵƐŝŶŐƉƌŽƉŽƐĞĚĂůŐŽƌŝƚŚŵ 0.20 Vout
0.10 Vcm
0.00
Vin RTH RTH RL Vin RTHN RL 0.00E+00 5.00E-10 1.00E-09 1.50E-09 2.00E-09
Vo1 Vo2 Vo2 VB
Time ( Sec)
VTH  VTH VTHN
> > (a) (b)
Fig. 10. (a) Circuit schematic of a single-stage differential amplifier. (b)
Transient output response of the amplifier
Fig. 8. Hierarchical abstraction of a buffer circuit.
VDD

1.2 Latch (Transient Simulation)

VDD CLK CLKB
1
The implementation methodology is shown in Fig. 8. The load CLKB
0.8 Qn-1 Qn = D Qn+1

Voltage (V)
CLK
voltage/current waveforms along with the comparison against Q
CLK
0.6 CLKB

CLKB 0.4 D
Spectre simulation of a composite buffer are shown in Fig. 9. 0.2 Q

An alternate approach to arrive at a Thevenin equivalent circuit 0

4.5E-10 6.5E-10 8.5E-10 1.1E-09 1.3E-09
-0.2
for a sub-circuit is to simulate the entire sub-circuit in Spectre Time (Sec)

at different input bias conditions, and tabulate VTH and RTH (a) (b)
as a function of input voltage (Vin). Fig. 11. (a) Circuit schematic of a CMOS latch. (b) Transient results showing
data capture and retain phases.
The abstraction methodology can also be extended to analog
circuit blocks. A differential amplifier (Fig. 10(a)) is modeled
using this method, and its transient output response for a VII. C ONCLUSION
sinusoidal input at a frequency of 1GHz is shown in Fig. 10(b). A simple LUT based methodology is shown to extract
The proposed method could thus be used in co-simulation of circuit responses for given input stimuli for a circuit netlist.
AMS designs. Further, the methodology has been proven to MOSFET abstraction using R and I appropriate to the region of
be functional for feedback-enabled circuits by considering a operation eliminates use of complex device equations circuit
CMOS latch as an example (fig. 11). during simulation thus improving run time and minimizing
convergence issues. This abstraction can be used for post-
layout parasitic extracted netlists too. This methodology is also
compatible for co-simulation of larger circuits for behavioral
1.3
simulations, wherein complex and larger sub-circuits are re-
Load Voltage Comparison Load Current Comparison
1.1 placed with corresponding abstracts.
0.9 Vin
3.0E-04 Cascade INV (Algorithm)

0.7
2.0E-04
Composite Buffer (Spectre)
R EFERENCES
Volts (V)

Cascaded INV
Current (A)

(Algorithm) 1.0E-04
0.5
Composite Buffer
0.0E+00
[1] Spectre circuit simulator, Cadence Design Systems, Inc.. Webpage: http:
0.3 (Spectre)
-1.0E-04
0 2E-10 4E-10 6E-10 8E-10
//www.cadence.com/products/cic/spectre circuit/pages/default.aspx
0.1

-2.0E-04
[2] B. R. Chawla, H. K. Grummel and P. Kozak, “MOTIS - An MOS timing
-0.1 0 2E-10 4E-10 6E-10 8E-10
Time (Sec)
Time (Sec) simulator,” in IEEE Trans. Circuits. Syst., Vol CAS-22, No. 12, pp. 901-
(a) (b) 910, Dec. 1975.
[3] T. Shima, H. Tamada, R. Luong, and M. Dang, “Table look-up MOSFET
Fig. 9. Comparison of simulation results for hierarchically abstracted buffer modeling system using a 2-D device simulator and monotonic piecewise
circuit between proposed method and Spectre (a) Load voltage (b) Load cubic interpolation,” in IEEE Trans. Comput.-Aided Des. Integr. Circuits
current Syst., vol. CAD-2, No. 2, pp. 121-126, Feb. 1983.
[4] W. M. Coughran, Jr., E. Grosse, and D. J. Rose, “Variation diminishing
splines in simulation,” in SIAM J. Sci. Stat. Comput., vol. 7, no. 2, pp.
696-705, Apr. 1986.
[5] A. Rofougaran and A. A. Abidi, “A table lookup FET model for accurate
analog circuit simulation,” in IEEE J. Solid-State Circuits, vol. 12, no. 2,
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[6] R. A. Thakker, C. Sathe, A. B. Sachid, M. S. Baghini, V. Ramgopal Rao,
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