2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

Functional Verification of DSP based On-board VLSI

Designs
Sourabh Jain1, Parimal Govani2, Kamal B Poddar3, A K Lal4, R M Parmar5
Space Applications Centre
Indian Space Research Organization
Ahmedabad, India
1
sourabhjain@sac.isro.gov.in, 2parimal@sac.isro.gov.in, 3kamal_p@sac.isro.gov.in,
4
aklal@sac.isro.gov.in, 5rmparmar@sac.isro.gov.in

Abstract— The Usage of Field Programmable Gate Arrays
(FPGA) and Application Specific Integrated Circuits (ASICs)
with complex functionalities such as Digital Signal Processing
(DSP) is increasing in onboard space applications. Verification of
these complex designs within limited schedule and resources is
challenging. In order to ensure reliable functioning of these
designs in all possible run time conditions, functional verification
is required to be carried out thoroughly. Development of an
automated self-checking verification environment or test
benches, including generation of bit-accurate golden reference
values, is complex and time consuming task even with the use of
state-of-the-art Hardware Verification Languages (HVLs) and
methodology such as System-Verilog (SV) and Universal
Verification Methodology (UVM) respectively.
This paper discusses a method for functional verification of
DSP based VLSI design using SV and Matlab. The architecture
of verification environment and technique for coupling of Matlab
with SV based verification environment and generation of bit-
accurate golden references, in real time is also discussed in detail,
along with two case studies.
Keywords— DSP, VLSI, UVM, predictor, coverage driven
verification, DPI
I. INTRODUCTION
To meet ever increasing functional requirements, digital
VLSI designs are getting complex. Design teams are packing
more & more logic gates onto a single chip to achieve desired
functionality and performance within the specified footprint.
Functional verification of such designs with tradition approach
of using directed test benches does not provide sufficient
confidence within given time schedule. Test benches written
in SV gives advantages in terms enabling constrained random
stimulus generation, self-checking and assertion based
verification along with defining functional coverage matrix.
Random testing improves productivity over manual testing, in
terms of number of test vectors produced and generates test
cases not explicitly thought by verification engineer. Binding
assertions to a design during simulation phase identifies
design flaws in real-time and reduces debugging time
significantly over non-assertion based design. Simulated
design’s output is compared with golden reference values
generated using HVL & verified automatically during run-
time. Functional simulation is considered complete when the
goal of 100% functional coverage is achieved.
In this SV based test bench, control signals output of the
designs are validated using assertions and data processing
functionalities of the designs are validated with predictor or
checker. These checkers are generally hand-coded using
higher level of abstraction by the verification engineer.
Development of checker for complex functionalities such
as DSP is complex. This becomes even more challenging for
an onboard design implementing multiple DSP IP cores
having functionalities such as sine–cosine lookup table, fixed
to floating point conversion & vice versa, FFT, FIR filter, etc.
DSP algorithms are available as standard functions in
MATLAB. If these functions can be used in the test bench as
golden reference models/checker, the test bench can be
simplified and overall efficiency of the verification can be
significantly improved. This paper discusses the verification
environment development using SV and methodology to
couple Matlab with SV.
II. PREDICTOR IN VERIFICATION ENVIRONMENT
Verification of a VLSI design consists of two major steps.
1. Stimulus generation
2. Analysis of the design response
In stimulus generation step, the design is configured in a
particular mode and stimulus is applied. In analysis part, the
actual verification is performed. A sample test bench
architecture performing both these operations automatically is
illustrated in Figure 1.
The test bench (verification environment) developed in SV
using UVM is composed of reusable verification environment
called verification components. Each component is
encapsulated, ready-to-use, and configurable which can be
used for verification of any interface protocol, design sub-
module or a full system. The verification components along
with device under test (DUT) is used to verify implementation
of the protocol or design architecture.

978-1-5090-0033-3/16/$31.00 ©2016 IEEE

 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
Figure 1: Verification Environment
The analysis component shown in Figure 2, consists of
components that observe behavior of the DUT. The major
parts for analysis component are coverage collection and
scoreboard. Scoreboard determines whether the design is
functioning properly or not. The scoreboard architecture
separates its tasks into two areas of concern viz. prediction and
evaluation. A predictor model, sometimes referred to as a
‘Golden Reference Model’, receives the same stimulus stream
as the DUT and produces known response transaction streams.
The predictor implements the DUT functionality at a higher
level of abstraction written in C, C++, SV or System-C. After
the correct functionality is predicted, the scoreboard can
evaluate the actual results observed on the DUT with the
predicted results.
III. USE OF MATLAB IN PREDICTOR
Matlab is proven industry standard for implementing DSP
algorithms. The DSP functions available or algorithms
developed using Matlab can be directly used to evaluate the
performance of the HDL designs. Such DSP functions will
have the same functionalities as the HDL designs. Figure 3
shows the usage of Matlab DSP function inside the predictor
component to generate the golden reference values. It
significantly simplifies the verification of complex design.
However, integrating Matlab DSP functions directly in
predictor is challenging task as it does not support HVL or
HDL constructs directly.
Following methods are explored to use Matlab functions in
verification environments -
A. Direct Programming Interface (DPI) and MATLAB
Engine :- Matlab can be interfaced with SV test bench using
DPI. A program written in ‘C’ language containing Matlab
engine routines makes the bridge between them.
B. HDL Verifier:- Matlab tool box named HDL verifier,
provides EDA link to get connection for supporting simulators
like Cadence IEV and Questasim
Figure 2: Analysis Component
Figure 3: Matlab in Predictor
C. MATLAB communication with TLM2 transactions:-
Both, UVM library and Matlab support TLM2 transactions
with System C environment. Utilizing this method, an
interface between UVM to System C TLM2 and System C
TLM2 to Matlab can be established.
Method A is independent of EDA simulator, configurable
and does not require any specific tool kit. Hence, it was
chosen for implementation.
DPI is an interface between SV and ‘C’, which allows
direct inter-language function calls on either side of the
interface. Matlab provides engine library functions, containing
routines that allow calling Matlab from programs written in
‘C’ and FORTRAN. The engine library contains nine routines
for controlling Matlab computation engine from a ‘C’
program. Table 1 summarizes these routines.
‘C’ program employing these routines can be used to
establish the link between SV and Matlab [1] as shown in
Figure 4.
Figure 5 shows a sample C program written for interface
between a SV test bench and a Matlab algorithm.
Table 1: Matlab engine routines
C Routines Matlab Functionality
eng{open|close} Used to Start/Close its engine
engEvalString Used for execution of its command
eng{get|put} Used to get/put its variable array value
from/to the engine
engOutputBuffer Used for reading its buffer text content
eng{get|set}Visible Used for making its engine visibility on /off
engOpenSingleUse Start for its engine session
 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
Figure 4: SV- Matlab Interface
Figure 5: Interface C program
System Verilog and Matlab have different data types.
Matlab’s default data type is a matrix double, whereas SV test
bench sends and receives data in binary format. Hence,
additional routines were developed in ‘C’ program to perform
the required conversion on the received data for compatibility
with target environment.
Here, Matlab files (.m) and C files are compiled into a
shared library which creates a shared library file (.so) and a
header file (.h). To communicate with the shared library,
Matlab requires usage of its existing matrix functions. The
compilation of ‘C’ file is done using gcc compiler and Matlab
API header files. The compiled unit is also stored in a shared
library.
IV. DSP CASE STUDY
The functional verification of two onboard IP core designs
are considered as case studies. In these case studies, Matlab
algorithms were used as golden reference in real-time. A
coverage driven functional simulation for both the designs.
A. Case-Study 1: Fast Fourier Transformation
The first design is an IP core of complex Fast Fourier
Transform (FFT) having transform length of 8192. It provides
unscaled output and uses the Cooley-Tukey algorithm for
computing the FFT. The Verification of this design was
carried out by using Matlab FFT algorithm of the same
transform size as a golden reference. Constrained random test
vectors generated using SV were applied on both DUT and
Matlab model. The DUT outputs were compared bit-by-bit
against Matlab output in real time.
Further, signal of a standard frequency with random noise
was generated in Matlab and applied to both reference model
as well as DUT for shape evaluation. The outputs from both
were plotted in Matlab in real time. Plotting of the DUT
response over the Matlab output revealed that the design
outputs were not exactly matching and there were minor
differences due to DUT introducing undesired frequency
components as shown in Figure 6.
Further debugging of DUT shown that these differences
are introduced by compression of the processed data due to
limited register length at every stage of processing and is
confirmed by the design team.
B. Case Study 2: Sine-cosine LUT
The another design is an IP core of sine cosine look up
table generator. In this design, the input angle widths is 16 bits
which provides resolution (step size) better than 0.005 and
output width is 10 bits long for better precision.
It was verified for all possible input angle values using
constrained random test vector by running Matlab algorithm in
a loop. Design output (sine /cosine values) were compared
with Matlab generated values. Angle values (16 bits)
generated by SV test bench, act as addresses for sine or cosine
LUT in the design. To get the angle value from the Matlab
algorithm for same input angle value, additional routines for
angle conversion operation were required to be developed in
‘C’. To make Matlab algorithm output (double - 64 bits long)
as DUT equivalent (10 bits), fixed point conversion of these
values was carried out in Matlab. Final output of DUT was
successfully compared and matched with Matlab output (i.e.
golden reference values).
V. ADVANTAGES
Use of MATLAB algorithm as a golden reference has
resulted in reduction of test bench code development time and
complexity. Comparison of outputs on MATLAB plots has
made debugging of complex DSP functions easier. Hence, the
overall efficiency of the functional verification was
considerably improved.
 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

Figure 6: FFT responses of DUT (green) and Matlab function (blue)

VI. CONCLUSION
An innovative automatic self-checking functional
verification method has been employed to ensure the
functional correctness of complex DSP based designs. Usage
of this approach enables verification of DSP based
functionalities in lesser time with higher coverage. Here,
Matlab is used to generate some specific input stimulus
signals, which are difficult to generate in SV. It is also feasible
to carry out extended analysis of the DUT output using
spectrum analysis, filtering at RTL level.
ACKNOWLEDGMENT
The work presented in this paper reflects the
interdependent efforts of many individuals. The authors wish
to acknowledge the contributions of entire design and
verification team, who provided their guidance in successful
implementation of this method. We would also like to express
our immense gratitude to Director SAC for providing the
opportunity to carry out this task.
REFERENCES
[1] Dhaval Modi, Integrating MATLAB with verification HDLs for
Functional Verification of Image and Video Processing ASIC”
International Journal of Computer Science & Emerging Technologies”
Volume 2, Issue 2, April 2011”
[2] Cookbook–UVM by Verification Academy Mentor graphics.
[3] Writing Testbenches using System Verilog by Janick Bergeron
Synopsys, Inc.
[4] SystemVerilog for Verification -A Guide to Learning the Testbench
Language Features by Chris Spear