Prathyusha Institute of Technology and Management

Department of Information Technology

EC6504 - MIRCOPROCESSORS AND MICROCONTROLLERS

UNIT 3
I/O INTERFACING
Memory interfacing and I/O interfaces with 8085 – parallel communication interface
(8255) – serial communication interface (8251) – timer (8253)-keyboard/display
controller (8279) – interrupt controller (8259) – DMA controller (8237) – applications –
stepper motor – temperature control.

PART A
Memory and I/O Interfacing
1. Why interfacing is needed for 1/O devices?
Generally I/O devices are slow devices. Therefore the speed of I/O devices does not
match with the speed of microprocessor. And so an interface is provided between system
bus and I/O devices.
2. What is the difference between CPU bus and system bus?
The CPU bus has multiplexed lines but the system bus has separate lines for each
signal. (The multiplexed CPU lines are demultiplexed by the CPU interface circuit to
form system bus).
3. What does memory-mapping mean?
The memory mapping is the process of interfacing memories to microprocessor
and allocating addresses to each memory locations.
4. What is interfacing?
An interface is a shared boundary between the devices which involves sharing
information. Interfacing is the process of making two different systems communicates
with each other.
5. What is meant by I/O Mapped I/O?
In I/O mapped I/O, the 8085 uses IO/M signal to distinguish between I/O read/write
and memory read / write operations. The 8085 has separate instructions IN and OUT for
I/O data transfer. When 8085 executes IN or OUT instruction, it places device address
(port number) on the demultiplexed low order address bus as well as the high order
address bus. In other words, the higher order address bus duplicates the contents of the
demultiplexed low-order address bus, when 8085 microprocessor executes IN or OUT
instruction.
Example : If the device address is 60H then the contents on A15 to A0 will be as follows:
A7 A6 A5 A4 A3 A2 A1 A0 Device
A15 A14 A13 A12 A11 A10 A9 A8 Address
0 1 1 0 0 0 0 0 60H

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 The address or port number can be any of the 256 combinations of eight bits, from
00H to FFH. Therefore, the 8085 can communicate with 256 different I/O devices.
6. What is meant by Memory Mapped I/O?
In memory mapped I/O, the I/O devices are assigned and identified by 16 bit
addresses. The memory related instructions transfer the data between an I/O device and
the microprocessor, as long as I/O port is assigned to the memory address space rather
than to the I/O address space. The register associated with the I/O port is simple treated as
a memory location. Thus I/O device becomes a part of the system’s memory map and
hence its name.In memory mapped I/O every instruction that refers to a memory location
can control I/O.
Instructions Interpretation
MOV r,M Input from a port to specified register
LDA address Input from a port to accumulator
7. Comparison between Memory mapped I/O and I/O mapped I/O
Memory mapped I/O I/O mapped I/O
In this device address is 16 bit. Thus In this I/O device address is 8-bit. Thus
A0 to A15 lines are used to generate A0 to A7 or A8 to A15 lines are used to
Device address generate device address

MEMR and MEMW control signals are IOR and IOW control signals are used to
used to control read and write I/O control read and write I/O operations.
operations
Instructions available are LDA addr, STA Instructions available are IN andOUT
addr, LDAX rp, MOV M,R etc.
Data transfer is between any register and Data transfer is between accumulator and
I/O device I/O device
Maximum number of I/O devices are Maximum number of I/O devices are 256
65,536 (theoretically)
Decoding 16 bit address may require Decoding 8 bit address will require less
more hardware hardware
8. What is memory mapping? What is I/O mapping?
The assignment of memory addresses to various registers in a memory chip is
called as memory mapping.
The assignment of addresses to various I/O devices in the memory chip is called
as I/O mapping.
9. What is the drawback in memory mapped I/0?
When I/O devices are memory mapped, some of the addresses are allotted to
I/O devices and so the full address space cannot be used for addressing memory (i.e.,
physical memory address space will be reduced). Hence memory mapping is useful only
for small systems, where the memory requirement is less

10. What is a programmable peripheral device?

If the functions performed by a peripheral device can be altered or changed by a
program instruction then the peripheral device is called programmable device. Usually
the programmable devices will have control registers. The device can be programmed by
sending control word in the prescribed format to the control register.
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 11. What is a port? and what is the need for Port?
The port is a buffered I/O, which is used to hold the data transmitted from the
microprocessor to I/O device or vice-versa.
The I/O devices are generally slow devices and their timing characteristics do not
match with processor timings. Hence the I/O devices are connected to system bus through
the ports.
INTEL 8255(parallel communication interface)
1. Write a short note on INTEL 8255.
The INTEL 8255 is a I/O port device consisting of 3 numbers of 8 -bit parallel
I/O ports (port-A, port-B and port-C.) The ports can be programmed to function either as
a input port or as a output port in different operating modes. It requires 4 internal
addresses and has one logic LOW chip select pin.
 Port-A : 8-bits
 Port-B : 8-bits
 Port-CU : 4-bits
* Port-CL : 4-bits
2. Explain the working of a handshake output port
In handshake output operation, the processor will load a data to port. When the
port receives the data, it will inform the output device to collect the data. Once the output
device accepts the data, the port will inform the processor that it is empty. Now the
processor can load another data to port and the above process is repeated.
3. What is handshake port and specify the bit which differentiates between I/O
mode and the BSR mode in 8255?
The port used for exchanging the signals between I/O devices and port or
between port and processor for checking or informing various condition of the device is
called
handshake port.

D7 D0
0/1

BS/R I/O mode

If D7=1,I/O mode
= 0,BSR mode

BSR (bit set/reset) Mode:

1. The BSR mode is concerned only with the eight bits of port c, which can be set or
reset by writing an appropriate control word in the control register.
2. DY=0 is active the BSR.
3. Port c can be used.

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4. What are the basic modes of operation of 8255?
There are two basic modes of operation of 8255, They are:
1. I/O mode.
2. BSR mode.
In I/O mode, the 8255 ports work as programmable I/O ports, while In BSR mode only
port C (PC0-PC7) can be used to set or reset its individual port bits. Under the IO mode
of operation, further there are three modes of operation of 8255, So as to support different
types of applications, viz. mode 0, mode 1 and mode 2.
 Mode 0 - Basic I/O mode
 Mode 1 - Strobed I/O mode
 Mode 2 - Strobed bi-directional I/O.

5. Write the features of mode 0 in 8255?

1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower) are
available. The two 4-bit ports can be combined used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configurations are
possible.
6. What are the features used mode 1 in 8255?
Two groups – group A and group B are available for strobed data transfer.
1. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
2. The 8-bit data port can be either used as input or output port. The inputs and outputs
both are latched.
3. Out of 8-bit port C, PC0-PC2 is used to generate control signals for port B and
PC3=PC5 are used to generate control signals for port A. The lines PC6, PC7 may be
used as independent data lines.
7. What are the signals used in input control signal & output control
signal?
Input control signal
 STB (Strobe input)
 IBF (Input buffer full)
 INTR(Interrupt request)
Output control signal
 OBF (Output buffer full)
 ACK (Acknowledge input)
 INTR(Interrupt request)

8. What are the features used mode 2 in 8255?

The single 8-bit port in-group A is available.
1. The 8-bit port is bi-directional and additionally a 5-bit control port is available.
2. Three I/O lines are available at port C, viz PC2-PC0.
3. Inputs and outputs are both latched.
4. The 5-bit control port C (PC3=PC7) is used for generating/accepting handshake
signals for the 8-bit data transfer on port A.

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9. What is a control word? What is the purpose of control word written to control
register in 8255?
It is a word stored in a register (control register) used to control the operation of a
program digital device.The control words written to control register specify an I/O
function for each I.O port. The bit D7 of the control word determines either the I/O
function of the BSR function.
USART(serial communication interface)
1. What are the various programmed data transfer methods?
i) Synchronous data transfer
ii) Asynchronous data transfer
iii) Interrupt driven data transfer
2. What is synchronous data transfer?
It is a data method which is used when the I/O device and the microprocessor match in
speed. To transfer a data to or from the device, the user program issues a suitable
instruction addressing the device. The data transfer is completed at the end of the
execution of this instruction.
For synchronous data transfer scheme, the processor does not check the readiness
of the device after commands have been issued for read/write operation. From this
scheme the processor will request the device to get ready and then read/Write to the
device immediately after the request. In some synchronous schemes a small delay is
allowed after the request.
3. What is asynchronous data transfer?
It is a data transfer method which is used when the speed of an I/O device does
not match with the speed of the microprocessor. Asynchronous data transfer is also called
as Handshaking.
In asynchronous data transfer scheme, first the processor sends a request to the device
for read/write operation. Then the processor keeps on polling the status of the device.
Once the device is ready, the processor executes a data transfer instruction to complete
the process.
4. What is baud rate?
The baud rate is the rate at which the serial data are transmitted. Baud
rate is defined as l /(The time for a bit cell). In some systems one bit cell has one data bit,
then the baud rate and bits/sec are same.
5. What is USART? What is the use of 8251 chip?
The device which can be programmed to perform Synchronous or
Asynchronous serial communication is called USART (Universal Synchronous
Asynchronous Receiver Transmitter). The INTEL 8251A is an example of USART.
The INTEL 825lA is used for converting parallel data to serial or vice versa. The
data transmission or reception can be either asynchronously or synchronously. The 8251A
can be used to interface MODEM and establish serial communication through MODEM
over telephone lines.8251 chip is mainly used as the asynchronous serial interface
between the processor and the external equipment.
6. What are the different types of method for data transmission?
The data transmission between two points involves unidirectional or bi-directional
transmission of meaningful digital data through a medium. There are basically there
modes of data transmission

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 (a) Simplex
(b) Duplex
(c) Half Duplex
In simplex mode, data is transmitted only in one direction over a single communication
channel. For example, a computer (CPU) may transmit data for a CRT display unit in this
mode.
In duplex mode, data may be transferred between two transreceivers in both directions
simultaneously.
1.half duplex mode, on the other hand, data transmission may take place in either
direction, but at a time data may be transmitted only in one direction. For example, a
computer may communicate with a terminal in this mode. When the terminal sends data
(i.e. terminal is sender). The message is received by the computer (i.e the computer is
receiver). However, it is not possible to transmit data from the computer to terminal and
from terminal to the computer simultaneously.
2.Full duplex mode: Data flow in both direction. For example,Telephone
7. What is the use of modem control unit in 8251?
The modem control unit handles the modem handshake signals to coordinate the
communication between the modem and the USART.
8. What are the control words of 8251A and what are its functions?
The control words of 8251A are Mode word and Command word. The mode word
informs 8251 about the baud rate, character length, parity and stop bits. The command
word can be sending to enable the data transmission and reception.
9. What is the information that can be obtained from the status word of 8251?
The status word can be read by the CPU to check the readiness of the transmitter or
receiver and to check the character synchronization in synchronous reception. It also
provides information regarding various errors in the data received. The various error
conditions that can be checked from the status word are parity error, overrun error and
framing error.
8257(DMA controller)
1. What is DMA? How DMA is initiated?
The direct data transfer between I/O device and memory is called DMA.
When the I/O device needs a DMA transfer, it will send a DMA request signal to
DMA controller. The DMA controller in turn sends a HOLD request to the processor.
When the processor receives a HOLD request, it will drive its tri-stated pins to high
impedance state at the end of current instruction execution and send an acknowledge
signal to DMA controller. Now the DMA controller will perform DMA transfer.

2. What are I/O Transfer Techniques?

 Program controlled I/O or Polling control
 Interrupt program controlled I/O or interrupt driven I/O
 Hardware controlled I/O
 I/O controlled by handshake signals
 I/O controlled by ready signal.

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3. What is meant by Program controlled I/O or Polling control?
In Program controlled I/O, the transfer of data is completely under the control of the
microprocessor program. This means that the data transfer takes place only when an I/O
transfer instructions executed. In most of the cases it is necessary to check whether the
device is ready for data transfer or not. To check this, the microprocessor polls the status
bit associated with I/O device.

4. What is meant by Interrupt program controlled I/O or interrupt driven I/O?

In Interrupt program controlled approach, when a peripheral is ready to transfer
data, it sends an interrupt signal to the microprocessor. This indicates that the I/O data
transfer is initiated by the external I/O device. When interrupted, the microprocessor
stops the execution of the program and transfers the program control to an interrupt
service routine. This interrupt service routine performs the data transfer. After the data
transfer, it returns control to the main program at the point it was interrupted.

5. What is meant by Hardware controlled I/O?

To increase the speed of data transfer between memory and I/O, the hardware
controlled I/O is used. It is commonly referred to as DMA. The hardware which controls
this data transfer is commonly known as DMA controller.

6. What is bus contention?

If two devices drives the data bus simultaneously then it is called Bus Contention. It
may lead to following undesirable events.
 Damaging one or both the IC chip
 The high current may cause a voltage spike in the supply system leading to data loss.

7. What is Block and Demand transfer mode DMA?

In Block transfer mode, the DMA controller will transfer a block of data and relieve
the bus for processor. After sometime another block of data is transferred by DMA and
so on.
In Demand transfer mode the DMA controller will complete the entire .data transfer
at a stretch and then relieve the bus to processor.

8. What is HOLD and HLDA and how it is used?

Hold and hold acknowledge signals are used for the Direct Memory Access
(DMA) type of data transfer. The DMA controller place a high on HOLD pins in order to
take control of the system bus. The HOLD request is acknowledged by the 8085 by
driving all its tristated pins to high impedance state and asserting HLDA signal high.

9. Give the register organization of 8257?

The 8257 perform the DMA operation over four independent DMA channels.
Each of the four channels of 8257 has a pair of two 16-bit registers. DMA address
register and terminal count register. Also, there are two common registers for all the
channels; namely, mode set registers and status register. Thus there are a total of ten
registers. The CPU selects one of these ten registers using address lines A0- A3.

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10. What is the function of DMA address register?
Each DMA channel has one DMA address register. The function of this register is
to store the address of the starting memory location, which will be accessed by the DMA
channel. Thus the starting address of the memory block that will be accessed by the
device is first loaded in the DMA address register of the channel. Naturally, the device
that wants to transfer data over a DMA channel, will access the block of memory with the
starting address stored in the DMA Address Register.

11. What is the use of terminal count register?

Each of the four DMA channels of 8257 has one terminal count register. This 16-
bit register is used for ascertaining that the data transfer through a DMA channel ceases
or stops after the required number of DMA cycles.

12. What is the function of mode set register in 8257?

The mode set register is used for programming the 8257 as per the requirements
of the system. The function of the mode set register is to enable the DMA channels
individually and also to set the various modes of operation.

INTEL 8259(interrupt controller)

1. What is an Interrupt?
Interrupt is a signal send by an external device to the processor so as
to request the processor to perform a particular task or work.
2. What is the usage of IIR (Interrupt Request Register)?
IIR is the register available in programmable interrupt controller (8259).it is user to
Store all the interrupt levels which are requesting service. IRR is cascaded with in-service
register (ISR).

3. Define Macro
Macro is a group of instruction. The macro assembler generates the code in the program
each time where the macro is called. Macros are defined by MACRO & ENDM
directives. Creating macro is similar to creating new opcodes that can be used in the
program
INIT MACRO
MOV AX, data
MOV DS
MOV ES, AX
ENDM
4. Define ISR
Interrupt means to break the sequence of operation. While the CPU is executing a
program an interrupt breaks the normal sequence of execution of instructions & diverts
its execution to some other program. This program to which the control is transferred is
called the interrupt service routine.
5. Define BIOS
The IBM PC has in its ROM a collection of routines, each of which perform some
specific function such as reading a character from keyboard, writing character to CRT.
This collection of routines is referred to as Basic Input Output System or BIOS.

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6. Compare PROCEDURE & MACRO
Procedure
Accessed by CALL & RET instruction
during program execution
Machine code for instruction is put only
once in the memory
With procedures less memory is required
Parameters can be passed in registers,
memory locations or stack
Macro
Accessed during assembly with name
given to macro when defined
Machine code is generated for instruction
each time when macro is called
With macro more memory is required
Parameters passed as part of statement
which calls macro

7. What is the need for interrupt controller?

The interrupt controller is employed to expand the interrupt inputs. It can
handle the interrupt request from various devices and allow one by one to the processor.

8. List some of the features of INTEL 8259 (Programmable Interrupt Controller)

1. It manage eight interrupt request
2. The interrupt vector addresses are programmable.
3. The priorities of interrupts are programmable.
4. The interrupt can be masked or unmasked individually.
5.
9. Give the different types of command words used in 8259a?
The command words of 8259A are classified in two groups
1. Initialization command words (ICWs)
2. Operation command words (OCWs)

10. Give the operating modes of 8259a?

(a) Fully Nested Mode
(b) End of Interrupt (EOI)
(c) Automatic Rotation
(d) Automatic EOI Mode
(e) Specific Rotation
(f) Special Mask Mode
(g) Edge and level Triggered Mode
(h) Reading 8259 Status
(i) Poll command
(j) Special Fully Nested Mode
(k) Buffered mode
(l) Cascade mode

11. What do you mean by polling in 8085?

Polling is an algorithm to identify the interrupted device. When multiple devices
interrupt the processor through one interrupt, then a polling scheme is necessary to
identify the interrupting device. In this scheme, each device will have a status which is
checked by the processor one by one. When a device want to interrupt the processor, it
asserts the status flag high. If processor recognizes the interrupt then it will execute an
Interrupt Service Routine (ISR).

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 The processor has to execute the following steps in order to process the interrupts:
 Branch to interrupt polling routine.
 Identify the device that caused the interrupt.
 Branch to ISR associated with this device and execute ISR.
 Enable the interrupt system
 Return to main program.
The polling can be performed either by software or by hardware. In software polling,
the entire polling is governed by processor instruction. In hardware polling, the hardware
takes care of checking status of interrupting devices and allowed one by one to the
processor.
8279(keyboard/Display interface)
1. What are the tasks involved in keyboard interface?
The task involved in keyboard interfacing is sensing a key actuation, debouncing the
key and generating key codes (Decoding the key). These task are performed software if
the keyboard is interfaced through ports and they are performed by hardware if the
keyboard is interfaced through 8279.

2. How a keyboard matrix is formed in keyboard interface using 8279?

The return lines, RLo to RL7 of 8279 are used to form the columns of keyboard
matrix. In decoded scan the scan lines SLo to SL3 of 8279 are used to form the rows of
keyboard matrix. In encoded scan mode, the output lines of external decoder are used as
rows of keyboard matrix.

3. Define scan counter?

The scan counter has two modes to scan the key matrix and refresh the display. In
the encoded mode, the counter provides binary count that is to be externally decoded to
provide the scan lines for keyboard and display. In the decoded scan mode, the counter
internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on
SL0-SL3.The keyboard and display both are in the same mode at a time.

4. What is the output modes used in 8279?

8279 provides two output modes for selecting the display options.
1.Display Scan: In this mode, 8279 provides 8 or 16 character-multiplexed
displays those can be organized as dual 4-bit or single 8-bit display units.
2. Display Entry:8279 allows options for data entry on the displays. The display
data is entered for display from the right side or from the left side.

5. What are the modes used in keyboard modes?

1. Scanned Keyboard mode with 2 Key Lockout.
2. Scanned Keyboard with N-key Rollover.
3. Scanned Keyboard special Error Mode.
4. Sensor Matrix Mode.

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 6. What are the modes used in display modes?
1. Left Entry mode: In the left entry mode, the data is entered from the left side
of the display unit.
2. Right Entry Mode: In the right entry mode, the first entry to be displayed is
entered on the rightmost display.

7. List the major components of the keyboard/Display interface.

The 8279 is a programmable Keyboard/Display interface
a. Keyboard section
b. Scan section
c. Display section
d. CPU interface section

8. What is Key bouncing?

Mechanical switches are used as keys in most of the keyboards. When a key is
pressed the contact bounce back and forth and settle down only after a small time delay
(about 20ms). Even though a key is actuated once, it will appear to have been actuated
several times. This problem is called Key Bouncing.( Microprocessor must wait until the
key reach to a steady state; this is known as Key bounce.)

9. What is the use of stepper motor?

A stepper motor is a device used to obtain an accurate position control of rotating
shafts. A stepper motor employs rotation of its shaft in terms of steps, rather than
continuous rotation as in case of AC or DC motor.

10. What is scanning in keyboard and what is scan time?

The process of sending a zero to each row of a keyboard matrix and reading the
columns for key actuation is called scanning. The scan time is the time taken by the
processor to scan all the rows one by one starting from first row and coming back to the
first row again.

11. What is scanning in display and what is the scan time?

In display devices, the process of sending display codes to 7 -segment LEDs to display
the LEDs one by one is called scanning ( or multiplexed display). The scan time is the
time taken to display all the 7-segment LEDs one by one, starting from first LED and
coming back to the first LED again.

8253(TIMER)
1. What are the modes of operations used in 8253?
Each of the three counters of 8253 can be operated in one of the following six
modes of operation.
1. Mode 0 (Interrupt on terminal count)
2. Mode 1 (Programmable monoshot)
3. Mode 2 (Rate generator)
4. Mode 3 (Square wave generator)

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5. Mode 4 (Software triggered strobe)
6. Mode 5 (Hardware triggered strobe)

2. What are the different types of write operations used in 8253?

There are two types of write operations in 8253
(1) Writing a control word register
(2) Writing a count value into a count register
The control word register accepts data from the data buffer and initializes the counters, as
required. The control word register contents are used for
(a) Initializing the operating modes (mode 0-mode4)
(b) Selection of counters (counter 0- counter 2)
(c) Choosing binary /BCD counters
(d) Loading of the counter registers.
The mode control register is a write only register and the CPU cannot read its contents.

3. What is assembler?
The assembler translates the assembly language program text which is given as
input to the assembler to their binary equivalents known as object code. The time
required to translate the assembly code to object code is called access time. The
assembler checks for syntax errors & displays them before giving the object code.

4. What is loader?
The loader copies the program into the computer’s main memory at load time and
begins the program execution at execution time.

5. What is linker?
A linker is a program used to join together several object files into one large
object file. For large programs it is more efficient to divide the large program modules
into smaller modules. Each module is individually written, tested & debugged. When all
the modules work they are linked together to form a large functioning program.

6.What is the count value needed to program the 8254 to generate a delay of ms and
what is the function of gate signal in timer?
Assume clock frequency of 8254=2.6 MHZ
Time required for 1 T state = 1 = 0.385μ sec

2.6 x 106
Number of T-states required for 0.5 ms = 0.5x10-3 = 1300
0.385 x10-6
ii) The gate signal in 8254 is used as the gate input of counters.CLK0,CLK1 gate
signals are given to counter 0, counter 1, counter 2 respectively

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7. Compare 8253and 8254
8253
1. Operating frequency 0 - 2.6 MHz.
2. Uses N-MOS technology
3. Read-Back command not available
4. Reads and writes of the same
counter can not be interleave
8254
Operating frequency 0 - 10 MHz.
Uses H-MOS technology.
Read-Back command available.
Reads and writes of the same
counter can be interleaved

PART B
1. Explain memory interfacing with an example

Interfacing: An interface is a shared boundary between the devices which involves

sharing information. Interfacing is the process of making two different systems
communicates with each other. Memory is an essential component of microcomputer
system; it stores binary instructions and data for the microprocessor. They can be
classified in two groups: prime (or main) memory and storage memory. The R/W
memory is made up of registers, and each register can use this memory to hold programs
and store data. On the other hand, the ROM stores information permanently in the form
of diodes.
Memory mapping: The assignment of memory addresses to various registers in a
memory chip is called as memory mapping.

The requirements of a memory chip.

1. A memory chip requires address lines to identify a memory register, a chip select
CS signal.
2. The number of address lines required is determined by the number of registers in
a chip (2n)
3. If additional address lines are available in a system, chip select signal is used.
4. The control signal Read ( RD ) enables the output buffer. The control signal Write
( WR ) enables the input buffer.
Memory Map and Address
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 Typically, in an 8- bit microprocessor system, 16 address lines are available for
memory. It is capable of identifying 216 (65,536) memory registers, each register with a
16 bit address. The entire memory addresses can range from 0000 to FFFF in Hex.
The MPU writes into and Reads from Memory.
1. Places the 16 bit address on the address of the memory location where a byte is to
be stored. The interfacing logic of the memory chip decodes the address and
selects the memory register to be written into.
2. Places the byte on the data bus.
3. Send the control signal Memory. Write to enable the input buffer of the memory
and then stores the byte.
To read from memory the step are similar to that of writing into memory, except the
order of step 2 and 3.
2. The MPU send the control signal Memory Read to enable the output buffer of the
memory chip.
3. The memory chip places the data byte on the data bus, and the MPU reads the
data byte.

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2. Explain in detail about 8255 with neat diagram and Explain pin detail about 8255
PROGRAMMABLE INPUT-OUTPUT PORT (8255)

The parallel input-output port chip 8255 is also called as programmable peripheral
input-output port. The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher
capability microprocessors.

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 It has 24 input/output lines which may be individually programmed in two groups
of twelve lines each, or three groups of eight lines. The two groups of I/O pins are named
as Group A and Group B. Each of these two groups contain a subgroup of eight I/O lines
called as 8-bit port and another subgroup of four lines or a 4-bit port. Thus group A
contains an 8-bit port A along with a 4-bit port, C upper.

The port A lines are identified by symbols PA 0 – PA7 while the port C lines are
identified as PC4 – PC7. Similarly, Group B contains an 8-bit port B, containing lines PB 0
– PB7 and a port C with lower bits PC0 – PC3. The port C upper and port C lower can be
used in combination as an port 8-bit port C. Both the port Cs are assigned the same
address. Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit I/O
ports from 8255. All of these ports can function independently either as input or as output
ports. This can be achieved by programming the bits of an internal register of 8255 called
as control word register (CWR).

The 8-bit data bus buffer is controlled by the read/write control logic. The
read/write control logic manages all of the internal and external transfers of both data and
control words. RD,WR, A1, A0 and RESET are the inputs, provided by the
microprocessor to the READ/WRITE control logic of 8255. The 8-bit, 3-state
bidirectional buffer is used to interface the 8255 internal data bus with the external
system data bus. This buffer receives or transmits data upon the execution of input or
output instructions by the microprocessor. The control words or status information is also
transferred through the buffer.

16
PA0 – PA7: These are eight port A lines that as either latched output or buffered input lines
depending upon the control word loaded into the control register.
PC7 – PC4: Upper nibble of port C lines. They may act as either output latches or input
buffers lines. This port also can be used for generation of handshake lines in mode 1 or
mode 2.
PC3 – PC0: These are the lower port C lines, other details are the same as PC7 – PC4 lines.
PB0 – PB7: These are the eight port B lines which are used ass latched output lines or
buffered input lines in the same way as port A.
RD: This is the input line driven by the microprocessor and should be low to indicate
read operation, to 8255.
WR: This is the input line driven by the microprocessor and should be low to indicate
Write operation, to 8255.

CS: This is chip select line. If this line goes low, it enables the 8255 to respond to RD and
WR signals, otherwise Rd and WR signals are neglected.The CS signal is the master chip
select, and A0 and A1 specify one of the i/o ports or the control registers.

Port-A cs A0 A1 SELECTED
0 0 0 PORT-A
0 0 1 PORT-A
CU Port-c 0 1 0 PORT-A
8255 A 0 1 1 Control register
CL 1 X X 8255A is not
Port-B selected

CS lines goes low when A7=1, A6 through A2 are at 0.

17
A1-A0 : These are the address input lines and are driven by the microprocessor. These
lines (A1-A0) with RD, WR, and CS form the following operations for 8255. These
address lines are used for addressing any one of the four registers, i.e. three ports and a
control word register.In case of 8086 systems, if the 8255 is to be interfaced with lower
order data bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.

D0-D7: These are the data bus lines those carry data or control word to/from the
microprocessor.

RESET: Logic high on the line clears the control word register of 8255. All ports are set
as input ports by default after reset.

3. Explain the mode of operation of 8255

MODES OF OPERATION OF 8255

There are two basic modes of operation of 8255 viz. I/O mode and Bit Set-Reset
mode (BSR). In I/O mode, the 8255 ports work as programmable I/O ports, while in the
BSR mode only port C (PC0 – PC7) can be used to set or reset its individual port bits.

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0
0/1

(Bit set/Reset) I/O Mode

Mode-0
Mode-1
Mode-2
If D7=1,bits D6-D0 determines i/o functions in various mode.
If bit D7=0, port C operates in the bit Set , Reset mode. BSR control word does not
affect the functions of port A and B.
To communicate with peripherals through the 8255A, three steps are necessary:
1.Determine the address of port A,B and C and of the control register according to the
chip select logic and address lines A0 and A1.
2. Write a control word in the control register.
3. Write i/o instruction to communicate with peripherals through port A,B and C.
BSR Mode:
In this mode, any of the 8-bis of port C can be set or reset depending on B0 of the
control word. The bit to be set or reset is selected by bit select flags B 3, B2 and B1 of the
CWR as given below in the table.

18
 B3 B2 B1 Selected bits of port C

0 0 0 B0

0 0 1 B1
0 1 0 B2
0 1 1 B3
1 0 0 B4
1 0 1 B5
1 1 0 B6
1 1 1 B7
1.MODE 0: To function as simply an input or an output port
In this port A & B are used as two simple 8-bit I/O port and Port C will be on no
effect.
1. Output are latched
2. Inputs are not latched
3. Ports do not have handshake or interrupt capability

2.Mode 1: Input or Output with handshake

This is also called strobe I/O mode. In Mode 1: handshake signals are
exchanged between the MPU and peripherals prior to data transfer. The features of this
mode include the following:
1. Two ports (A and B) function as 8-bit I/O ports. They can be configured
either as input or output ports.
2. Each port uses three lines from port C as handshake signals. The remaining
two lines of port C can be used for simple I/O functions.
3. Input and output data are latched.
4. Interrupt logic is supported.

In the 8255, the specific lines from port C used for handshake signals vary
according to the I/O function of a port. Therefore input and output functions in
Mode 1 are discussed separately.

19
MODE 1:INPUT CONTROL SIGNALS : The handshaking signals ports are activated
when Port B and port B are configured as input ports.
Port –A uses the upper three signals PC3 , PC4 and PC5.
Port-B uses the lower three signals PC2 , PC1 and PC0.
The functions of the signals are as follows :
1.STB(strobe i/p) : generated by peripheral devices h indicate that it has transmitted a
data oa bye of data .
2. IBF(Input Buffer Full): it acknowledge by 8255 A that the input latch has recived the
data byte .
3.INTR (Interrupt Request): this is an o/p signal generated if STB,SBF and INTE are
all at logic 1.
4.INTE(Interrupt Enable): It is used to enable or disable the generation of the INTR
signal, through some specified c port . INTEA PC4 & INTEB PC2

Control Word :
To set up port A and port B as input ports mode 1

1 0 1 1 1/0 1 1 X
I/O port-B
mode
Port B mode 1

Port A Mode 1
Port A input
PC6,7 1=I/P & 0=O/p

Status words

20
I/O I/O IBFA INTEA INTRA IBFB INTEB INTRB X

Mode 1: OUTPUT CONTROL SIGNALS: Indicates to an o/p peripherals that new

data are ready to be read.
OBF :( Output Buffer Full): This is an o/p signal from a peripheral that when a MPU
wires a data into the o/p latch of the 8255A.
Ack : Which give the acknowledge the when the peripherals receives the data from the
8255A port.
INTR(Interrupt request) This signal can be used to interrupt the MPU to request the next
data byte for output.
INTE Interrupt enable:This is an internal flip flop to a port and needs to be set to
generate the INTR signal.

Control Word :
To set up port A and port B as input ports mode 1

1 0 1 1 1/0 1 1 X
I/O port-B o/p
mode
Port B mode 1

Port A Mode 1
Port A output
PC4,5 1=I/P & 0=O/p

status words
D7 D6 D5 D4 D3 D2 D1 D0
21
OBFA INTEA 1/0 1/0 INTRA INTEB OBFB INTRB

Mode 2: Bidirectional Data Transfer

This is also called strobe bi-directional I/O mode. This mode is used primarily
in applications such as data transfer between two computers of floppy disk controller
interface. In this mode, Port A can be configured as the bidirectional port and port B
either in Mode 0 or Mode 1. Port A uses five signals from port C as handshake signals for
data transfer. The remaining three signals from port C can be used as simple I/O or as
handshake for port B.

4. Explain in detail about 8251 with neat diagram and Explain pin detail about
8251

PROGRAMMABLE COMMUNICATION INTERFACE 8251 USART

Intel’s 8251A is a universal synchronous asynchronous receiver and transmitter.
This chip converts the parallel data into a serial stream of bits suitable for serial
transmission. It is also able to receive a serial stream of bits and convert it into parallel
data bytes to be read by a microprocessor.

Architecture of 8251:

The data buffer interfaces the internal bus of the circuit with the system bus. The
read write logic controls the operation of the peripheral depending upon the operations
initiated by the CPU. This unit also selects one of the two internal addresses those are
control address and data address at the behest of the c/d SIGNAL. The modem control
unit handles the modem handshake signals to coordinate the communication between the
modem and the USART. The transmit control unit transmits the data byte received by the
data buffer from the CPU for further serial communication.

This decides the transmission rate which is controlled by the TXC input
frequency. This unit also derives two transmitter status signals namely TXRDY and
TXEMPTY. These may be used by the CPU for handshaking. The transmit buffer is a
parallel to serial converter that receives a parallel byte for conversion into a serial signal
and further transmission onto the communication channel. The receive control unit
detects a break in the data string while the 8251 is in asynchronous mode. In synchronous
mode, the 8251 detects the SYNC characters using SYNDET/BD pin.

22
SIGNAL DESCRIPTIONS OF 8251A:
D0 –D7: This is an 8-bit data bus used to read or write status, Command word or data from
or to the 8251A.
C/ D – Control Word/ data: This input pin, together with RD and WR inputs, informs the
8251A that the word on the data bus is either a data or control word/status information. If
this pin is 1, control/status is on the bus, otherwise data is on the bus.

23
RD: This is an active-low input to 821A is used to inform it that the CPU is reading either
data or status information from its internal registers.
WR: This is active-low input to 8251A is used to inform it that CPU is writing data or
control word to 8251A.
CS: This is an active-low chip select input of 8251A. If it is high, no read or write
operation can be carried out on 8251. The data bus is tristated if this pin is high.
CLK: This input is used to generate internal device timings and is normally connected to
clock generator output. This input frequency should be at least 30 times greater than the
receiver or transmitter data bit transfer rate.
RESET: A high on this input forces the 8251A into an idle state. The device will remain
idle till this input signal again goes low and a new set of control word is written into it.
The minimum required reset pulse width is 6 clock states, for the proper reset operation.

TXC – Transmitter clock Input: This transmitter clock input controls the rate at which the
character is to be transmitted. The baud rate (1x) is equal to the TXC frequency in
synchronous transmission mode. In asynchronous mode, the baud rate is one of the three
fractions, i.e. 1, 1/16, or 1/64 of the TXC. The serial data is shifted out on the successive
negative edge of the TXC.
TXD – Transmitted data output: This output pin carries serial stream of the transmitted
bits along with other information like start bit, stop bits and parity bit, etc.

RXC – receiver Clock Input: This receiver clock input pin controls the rate at which the
character is to be received. In synchronous mode, the baud rate is equal to the RXC
frequency. In asynchronous mode, the baud rate is one of the three fractions, i.e. 1, 1/16
and 1/64th of the RXC frequency. The received data is read into the 8251 on rising edge of
RXC.
RXD – Receive Data Input: This input pin of 8251A receives a composite stream of the
data to be received by 8251A.
RXRDY – Receiver Ready Output: This output indicates that the 8251A contains a
character to be read by the CPU. The RXRDY signal may be used either to interrupt the
CPU or may be polled by the CPU.
TXRDY – Transmitter Ready: This output signal indicates to the CPU that the internal
circuit of the transmitter is ready to accept a new character for transmission from the
CPU. The TXRDY signal is set by a leading edge of write signal if a data character is
loaded into it from the CPU.

DSR – Data Set Ready: This input may be used as a general purpose one bit inverting
input port. Its status can be checked by the CPU using a status read operation. This is
normally used to check if the Data Set is ready when communicating with a modem.

DTR – Data Terminal Ready: This output may be used as a general purpose one bit
inverting output port. This can be programmed low to indicate the modem that the
receiver is ready to receive a data byte form the modem. This signal is used to
communicate with a modem.

24
RTS – Request to send Data: This output also may be used as a general purpose one bit
inverting output port that can be programmed low to indicate that the receiver is ready to
receive a data byte form the modem. This signal is used to communicate with a modem.

CTS – Clear to Send Data: If the clear to send input line is low, the 8251A is enabled to
transmit the serial data provided the enable bit in the command word is set to ‘1’.
TXE – Transmitter Empty: If the 8251A, while transmitting, has no characters to
transmit, the TXE output goes high and it automatically goes low when a character is
received from the CPU, for further transmission. The TXE signal can be used to indicate
the end of a transmission mode.
SYNDET/BD – Synch Detect/Break Detect: This pin is used in the synchronous mode
for detecting SYNC characters (SYNDET) and may be as either input or output. This can
be programmed using the control word. After resetting, it is in the output mode. When
used as an output, the SYNDET pin will go high to indicate that the 8251A has located a
SYNC character in the receive mode. The SYNDET signal is automatically reset upon a
following status read operation. When this is used as input, a positive going signal will
cause the 8251A to start assembling a data character on the rising edge of the next RXC.
In asynchronous mode, the pin acts as a break detect output. This goes high whenever the
RXD pin remains low through two consecutive stop bit sequences.

5. Explain the mode of operation of 8251

Description of 8251A operating modes:

The control words of 8251A are divided into two functional types:
1. Mode Instruction Control word
2. Command Instruction Control Word

Mode Instruction Control Word :

This defines the general operational characteristics of 8251A. After internal or external
reset, this must be written to configure the 8251A as per the required operation. Once this
has been written into 8251A, SYNC characters or command instructions may be
programmed further as per the requirements.
Items set by mode instruction are as follows:
• Synchronous/asynchronous mode
• Stop bit length (asynchronous mode)
• Character length
• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)

25
Command Instruction Format:
Items to be set by command are as follows:
• Transmit Enable/Disable
• Receive Enable/Disable
• DTR, RTS Output of data.
• Resetting of error flag.
• Sending to break characters
• Internal resetting
• Hunt mode (synchronous mode)

26
 6. Draw the pin diagram and functional block diagram of 8257 programmable
DMA controller and explain the function of each pin and block in detail.

The direct memory access or DMA mode of data transfer is the fastest amongst
all the modes of data transfer. In this mode, the device may transfer data directly to/from
memory without any interference from the CPU. The device requests the CPU (through a
DMA controller) to hold its data, address and control bus, so that the device may transfer
data directly to/from the memory.

Intel’s 8257 is a four channel DMA controller designed to be interfaced with their
family of microprocessors. The 8257, on behalf of the devices, requess the CPU for bus
access using local bus request input I.e. HOLD in minimum mode. In maximum mode of
the microprocessor RQ/GT pin is used as bus request input. On receiving the HLDA
signal or RQ/GT signal from the CPU, the requesting device gets the access of the bus,
and it completes the required number of DMA cycles for the data transfer and then hands
over the control of the bus back to the CPU.

The chip supports four DMA channels, i.e. four peripherals can be
independently request for DMA data transfer through these channels at a time. The DMA
controller has 8-bit internal data buffer, a read/write unit, a control unit, a priority
resolving unit along with a set of registers.

27
Register organization of 8257: The 8257 performs the DMA operation over four
independent DMA channels. Each of the four channels of 8257 has a pair of two 16-bit
registers, namely, DMA address register and terminal count register. Also, there are two
common registers for all the channels namely mode set register and status register. The
CPU selects one of these registers using A0 – A3.
DMA address register: Each DMA channel has one DMA address register. The function
of this register is to a store the address of the starting memory location, which will
accessed by the DMA channel. Thus the starting address of the memory block which will
be accessed by the device is first loaded in the DMA address register of the channel.
Naturally, the device that wants to transfer data over a DMA channel, will access the
block of memory with the starting address stored in the DMA address register.

Terminal Count Register: This 16-bit register is used for ascertaining that the data
transfer through a DMA channel ceases or stops after the required number of DMA
cycles. Thus this register should be written before the actual DMA operation starts. The
low order14-bits of the terminal count register are initialised with the binary equivalent of
the number of required DMA cycles minus one. After each DMA cycle, the terminal
count register content will be decremented by one and finally it becomes zero after the
required number of cycles is over. The bits 14 and 15 of this register indicate the type of
the DMA operation. If the device wants to write data into the memory, the DMA
operation is called DMA write operation.

Mode Set register: It is used for programming the 8257 as per the requirements of the
system. Its function is to enable the DMA channels individually and also to set the
various modes of operation. A DMA channel should not be enabled till the DMA Address
register and the terminal count register contain valid information, otherwise, an unwanted
DMA request may initiate a DMA cycle, probably destroying the valid memory data.

28
29
7. Draw the functional block diagram of 8253 Timer and explain the each block in
detail.

Intel’s programmable counter/timer device (8253) facilitates the generation of

accurate time delays.
The programmable timer device 8253 contains three independent 16-bit counters,
each with a maximum count rate of 2.6MHz. It is thus possible to generate three totally
independent delays or maintain three independent counters simultaneously. All the three
counters may be independently controlled by programming the three internal command
registers.

The 8-bit, bi-directional data buffer interfaces internal circuit of 8253 to

microprocessor systems bus. Data is transmitted or received by the buffer upon the
execution of IN or OUT instruction. The read/write logic controls the direction of data
buffer depending upon whether it is a read or a write operation. It may be noted that IN
instruction reads data while OUT instruction writes data to a peripheral.

The three counters available in 8253 are independent of each other in operation,
but they are identical to each other in organization. These are all 16-bit presettable, down
counters, able to operate either in BCD or in hexadecimal mode. The mode control word
register contains the information that can be used for writing or reading the count value
into of from the respective count register using the IN and OUT instructions.
30
 A0, A1 are the address input pins and are required internally for addressing the
mode control word register and the three counter registers. A low on the CS line enables
the 8253. No operation will be performed by 8253 till it is enabled.

Control Word Register: The 8253 can operate in any one of the six different modes.
A control word must be written in the respective control word register by the
microprocessor to initialize each of the counters of 8253 to decide its operating mode.
The control word format along with the definition of the bit is shown below:
SC1 SC0 RL1 RL0 M2 M1 M0 BCD

Control Word Format D7 D6 D5 D4 D3 D2 D1 D0

RL-Read/Load Bit definitions

SC-Select Counter Bit Definitions

SC1 SC0 OPERATION RL1 Select

RL0 BitOPERATION
M M M Mode Definitions
0 0 Select Counter 0 2 1 0 0 0 Latch counter for ‘ON THE
0 1 Select Counter 1 FLY’ reading
1M2 0M1 MSelect
0 Counter
Selected 2
mode 0 1 Read/Load LSB only
0 0 0 Mode 0 1 0 Read/Load MSB only
1 1 Illegal
0 0 1 Mode 1 1 1 Read/Load LSB first and then
X 1 0 Mode 2 MSB
X 1 1 Mode 3
1 0 0 Mode 4 HEX/BCD Bit Definition
1 0 1 Mode 5
BCD Operation
0 Hexadecimal Count
MODE 0 1 BCD Count
This mode of operation is generally
called as interrupt on terminal count. In this mode, the output is initially low after the
mode is set. The output remains low even after the count value is loaded in the counter.
The counter starts decrementing the count value after the falling edge of the clock, if the
GATE input is high. The process of decrementing the counter continues at each falling
edge of the clock till the terminal count is reached, i.e. the count becomes zero. When the
terminal count is reached, the output goes high and remains high till the selected control
word register or the corresponding count register is reloaded with a new mode of
operation or a new count, respectively. This high output may be used to interrupt the
processor whenever required, by setting suitable terminal count.
The GATE signal is active high and should be high for normal counting. When
GATE goes low counting is terminated and the current count is latched till the GATE
again goes high.

31
 1. Mode 0 (000): Interrupt on Terminal Count
2. Mode 1 (001): Hardware-Triggered One Shot
3. Mode 2 (x10): Rate Generator
4. Mode 3 (x11): Square Wave Generator
5. Mode 4 (100): Software Triggered Strobe
6. Mode 5 (101): Hardware Triggered Strobe

MODE 1
This mode of operation of 8253 is called as programmable one-shot mode. In this
mode, the 8253 can be used as a monostable multivibrator. The duration of the
quasistable state of the monostable multivibrator is decided by the count loaded in the
count register. The gate input is used as trigger input in this mode of operation. Normally
the output remains the suitable count is loaded in the count register and a trigger is
applied. After the application of the trigger, the output goes low and remains low till the
count becomes zero. If another count is loaded when the output is already low, it does not
disturb the previous count till a new trigger pulse is applied at the GATE input. The new
counting starts after the new trigger pulse.

32
MODE 2
This mode is called either rate generator or divide by N counter. In this mode,if N
is loaded as the count value, then, after N pulses, the output becomes low only for one
clock cycle. The count N is reloaded and again the output becomes high and remains high
for N clock pulses. The output is normally high after initialization or even a low signal on
GATE input force the output high. If GATE goes high, the counter starts counting down
from the initial value. The counter generates an active low pulse at the output initially,
after the count register is loaded with a count value. The duration of these active low
pulses are equal to one clock cycle. The number of input clock pulses between the two
low pulses at the output is equal to the count loaded.

MODE 3
In this mode, the 8253 can be used as a square wave generator. In terms of
operation this mode is similar to mode 2. When, the count N loaded is even, then for the
count, the output remains high and for the remaining half it remains low. If the count
loaded is odd, the first clock pulse decrements it by 1 resulting in an even count value.
Then the output remains high for half of the new count and goes low for the remaining
half. This procedure is repeated continuously resulting in the generation of a square wave.
In case of odd count, the output is high for longer duration and low for a shorter duration.
The difference of one clock cycle duration between the two periods is due to the initial
decrementing of the odd count. In general, if the loaded count value ‘N’ is odd, then for
(N+!)/2 pulses the output remains high and for (N-1)/2 pulses it remains low.

MODE 4
This is mode of operation of 8253 is named as Software triggered strobe. After the
mode is se, the output goes high. When a count is loaded, counting down starts. On
terminal count, the output goes low for one clock cycle, and then it again goes high. This
low pulse can be used as strobe, while interfacing the microprocessor with other
peripherals. The count is inhibited and the count is latched, when the GATE signal goes
low. If a new count is loaded in the count register while the previous counting is in
progress, it is accepted from the next clock cycle. The counting then proceeds according
to the new count.

33
MODE 5
This mode of operation also generates a strobe in response to the rising edge at
the trigger input. This mode may be used to generate a delayed strobe in response to an
externally generated signal. Once this mode is programmed and the counter is loaded, the
output goes high. The counter starts counting after the rising edge of the trigger input
(GATE). The output goes low for one clock period, when the terminal count is reached.
The output will not go low until the counter content becomes zero after the rising edge of
any trigger. The GATE inoput in this mode is used as trigger input.

8. Draw the pin diagram and functional block diagram of 8259 programmable
Interrupt controller and explain the function of each pin and block in detail.

Interrupt Request Register (IRR): The interrupts at IRQ input lines are handled by
Interrupt Request Register internally. IRR stores all the interrupt requests in it in order to
serve them one by one on the priority basis.

34
IN-service Register (ISR):This stores all the interrupt requests those are being served,
i.e. ISR keeps track of the requests being served.
Priority Resolver: This unit determines the priorities of the interrupt requests
appearing simultaneously. The highest priority is selected and stored into the
corresponding bit of ISR during INTA pulse. The IR0 has the highest priority while the
IR7 has the lowest priority, normally in fixed priority mode. The priorities however may
be altered by programming the 8259A in rotating priority mode.

Interrupt Mask Register (IMR): This register stores the bits required to mask the
interrupt inputs. IMR operates on IRR at the direction of the Priority resolver.
Interrupt Control Logic:This block manages the interrupt and interrupt acknowledge
signals to be sent to the CPU for serving one of the eight interrupt requests. This also
accepts the interrupt acknowledge (INTA) signal from CPU that causes the 8259A to
release vector address on to the data bus.

Data Bus Buffer: This tristate bi-directional buffer interfaces internal 8259A bus to
the microprocessor system data bus. Control words, status and vector information pass
through data buffer during read/write operations.

Read/Write Control Logic:

This circuit accepts and decodes commands from the CPU. This block also allows the
status of the 8259A to be transferred on to the data bus.

Cascade Buffer/Comparator:This block stores and compares the ID’s of all the 8259As
used in the system. The three I/O pins CAS0-2 are outputs when the 8259A is used as a
master. The same pins act as inputs when the 8259A is in slave mode. The 8259A in
master mode sends the ID of the interrupting slave device on these lines. The slave thus
selected, will send its preprogrammed vector address on the data bus during the next
INTA pulse.

Pin decription

35
CS: This is an active – low chip select signal for enabling RD and WR operations of
8259A. INTA function is independent of CS.

WR: This pin an active-low write enable input to 8259A. This enables it to command
words from CPU.

RD: This pin is an active – low read enable input to 8259A. A low on this line enables
8259A to release status onto the data bus of CPU.

D7 – D0: These pins form a bi-directional data bus that carries 8-bit data either to control
word or from status word registers. This also carries interrupt vector information.

CAS0 – CAS2 Cascade Lines: A single 8259A provides eight vectored interrupts. If more
interrupts are required, the 8259A is used in cascade mode. In cascade mode, a master
8259A along with eight slaves 8259A can provide upto 64 vectored interrupt lines. These
three lines act as select lines for addressing the slaves 8259A.

PS/EN: This pin is a dual purpose pin. When the chip is used in buffered mode, it can be
used as buffer enable to control buffer transreceivers. If this is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master (SP = 1) or
a slave (EN = 0).

INT: This pin goes high whenever a valid interrupt request is asserted. This is used to
interrupt the CPU and is connected to the interrupt input of CPU.

IR0 – IR7 (Interrupt requests): These pins act as inputs to accept interrupt requests to the
CPU. In edge triggered mode, an interrupt service is requested by raising an IR pin from
a low to a high state and holding it high until it is acknowledged, and just by latching it to
high level, if used in level triggered mode.

INTA (Interrupt Acknowledge): This pin is an input used to strobe-in 8259A interrupt
vector data on to the data bus. In conjunction with CS, WR and RD pins, this selects the
different operations like writing command words, reading status word, etc.

The device 8259A can be interfaced with any CPU using either polling or
interrupt. In polling, the CPU keeps on checking each peripheral device in sequence to
ascertain if it requires any service from the CPU. If any service request is noticed, the
CPU serves the request and then goes on to the next device in sequence. After all the
peripheral devices are scanned as above the CPU again starts from the first device. This
type of system operation results in the reduction of processing speed because most of the
CPU time is consumed in polling the peripheral devices.

In the interrupt driven method, the CPU performs the main processing task till it
is interrupted by a service requesting peripheral device. The net processing speed of this

36
type of systems is high because the CPU serves the peripheral only if it receives the
interrupt request. If more than one interrupt requests are received at a time, all the
requesting peripherals are served one by one on priority basis. This method of interfacing
may require additional hardware if number of peripherals to be interfaced is more than
the interrupt pins available with the CPU.

9.Describe the operation of 8259 programmable interrupt controller

Interrupt Sequence in an 8086 system

The interrupt sequence in an 8086 m- 8259A system is described as follows:

1. One or more IR lines are raised high that set corresponding IRR bits.
2. 8259A resolves priority and sends an INT signal to CPU.
3. The CPU acknowledges with INTA pulse.
4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set
and the corresponding IRR bit is reset. The 8259A does not drive data bus during
this period.
5. The 8086 will initiate a second INTA pulse. During this period 8259A releases an
8-bit pointer on to data bus from where it is read by the CPU.
6. This completes the interrupt cycle. The ISR bit is reset at the end of the second
INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise
ISR bit remains set until an appropriate EOI command is issued at the end of
interrupt subroutine.
7.
Command Words of 8259A:
The command words of 8259A are classified in two groups, viz. initialization
command words (ICWs) and operation command words (OCWs).
Initialization Command Words (ICWs):
Before it starts functioning, the 8259A must be initialized by writing two to four
command words into the respective command registers. These are called as initialization
command words (ICWs). If A0 = 0 and D4 = 1, and the control word is recognized as
ICW1. It contains the control bits for edge/level triggered mode, single/cascade mode, call
address interval and whether ICW4 is required or not, etc. If A0 = 1, the control word is
recognized as ICW2. The ICW2 stores details regarding interrupt vector addresses.
Once ICW1 is loaded, the following initialization procedure is carried out
internally.
a) The edge sense circuit is reset, i.e. by default 8259A interrupts are edge sensitive.
b) IMR is cleared.
c) IR& input is assigned the lowest priority.
d) Slave mode address is set to 7.
e) Special mask mode is cleared and status read is set to IRR.
f) If IC4 = 0, all the functions of ICW 4 are set to zero. Master/slave bit in ICW 4 is
used in the buffered mode only.
In an 8086 based system A15 = A11 of the interrupt vector address are inserted in place of
T7 – T3 respectively and the remaining three bits (A 8, A9 and A10) are selected depending
upon the interrupt level, i.e. from 000 to 111 for IR0 to IR7.

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ICW1 and ICW2 are compulsory command words in initialization sequence of 8259A and
ICW3 and ICW4 are optional. The ICW3 is read only when there are more than one
8259Asin the system, i.e. cascading is used (SNGL = 0). The SNGL bit in ICW 1 indicates
whether the 8259A is in cascade mode or not.

In master mode [i.e. SP = 1 or in buffer mode M/S = 1 in ICW 4], the 8-bit slave
register will be set bit wise to ‘1’ for each slave in the system. The requesting slave will
then release the second byte of a CALL sequence.

IN slave mode [i.e. SP = 0 or if BUF = 1 and M/S = 0 in ICW 4] bits D2 to D0

identify the slave, i.e. 000 to 111 for slave 1 to slave8. The slave compares the cascade
inputs with these bits and if they are equal, the second byte of the CALL sequence is
released by it on the data bus.

ICW4 :The use of this command word depends on the IC4 bit of ICW1. If IC4 = 1, ICW4 is
used, otherwise it is neglected. The bit functions of ICW4 are described as follows:
SFMN: Special fully nested mode is selected, if SFNM = 1.
BUF: If BUF = 1, the buffered mode is selected. In the buffered mode, SP/EN acts as
enable output and the master/slave is determined using the M/S bit of ICW4.
M/S: If M/S = 1, 8259A is a master. If M/S = 0, 8259A is a slave. If BUF = 0, M/S is to
be neglected.
AEOI: If AEOI = 1, the automatic end of interrupt mode is selected.
μPM: If the μPM bit is 0, the Mcs-85 system operation is selected and and if μPM = 1,
8086/88 operation is selected.

38
39
Operation Command Words:
Once 8259A is initialized, it is ready for accepting the interrupts but 8259A has its
own ways of handling the received interrupts called as modes of operation. These modes

40
of operations can be selected by programming, i.e. writing three internal registers called
as operation command word registers.
The data written into them is called as operation command words. In the three
operation command words OCW1, OCW2 and OCW3, every bit corresponds to some
operational feature of the mode selected, except for a few bits those are either ‘1’ or ‘0’.
The three operation command words are shown below:

OCW1 is used to mask the unwanted interrupt requests. If the mask bit is ‘1’, the
corresponding interrupt request is masked, and if it is ‘0’, the request is enabled.
In OCW2 the three bits, namely R, SL, and EOI control the end of interrupt, the rotate
mode and their combinations as shown in the above figure. The three bits L 2, L1, and L0
in OCW2 determine the interrupt level to be selected ofr operation, if the SL bit is active,
i.e.’1’.
In OCW3, if the ESMM bit, i.e. enable special mask mode bit is set to ‘1’, the SMM bit is
enabled to select or mask the special mask mode. When ESMM bit is ‘0’, the SMM bit is
neglected. If the SMM bit, i.e. special mask mode bit is ‘1’, the 8259A will enter special
mask mode provided ESMM = 1. If ESMM = 1 and SMM = 0, the 8259A will return to
the normal mask mode.

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Three methods (MODES) of DMA operation: (a) byte; (b) burst; (c) block.

10. With block diagram describe the structure and operation of a keyboard/display
controller

Intel’s 8279 is a general purpose keyboard display controller that simultaneously drives
the display of a system and interfaces a keyboard with the CPU leaving the CPU free for
its routine task. The keyboard display interface scans the keyboard to identify if any key
has been pressed and sends the code if the pressed key to the CPU. This also transmits the
data received from the CPU to the display device. The controller performs both of these
operations without involving the CPU.

The 8279 is a 40 pin drive with two major segments, Keyboard and Display. The
keyboard can be connected to a max of 64 – contact ky matrix. Keyboard entries are
denounced and stored in the internal FIFO RAM and an interrupt signal is generated with
each entry. The display segment can provide a 16 character (byte) scanned display. This
segment contains 16 x 8 R/w memory (RAM), which can be used to read or write
information for the display purposes. This 16-byte display RAM can be used either as an
integrated block of 16 x 8 bits or 16 x 4 bits of 2 blocks. The internal architecture of 8279
is shown in the fig.

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 The keyboard display controller 8279 is provided with a) set of four scan lines
and eight return lines for interfacing keyboards b) a set of eight output lines for
interfacing the display.

I/O Control and Data Buffers: The I/O control section controls the flow of data
to/from the 8279. The data buffers interface the external bus of the system with internal
bus of 8279. The I/O section is enabled only if CS is low. The pins A 0, RD and WR select
the command, status or read/write operations carried out by the CPU with 8279.

Control and Timing register and Timing Control: These registers store the
keyboard and display modes and other operating conditions programmed by CPU. The
registers are written with A0 = 1 and WR = 0. The Timing and Control unit controls the
basic timings for the operation of the circuit. Scan counter divide down the operating
frequency of 8279 to derive scan keyboard and scan display frequencies.

Scan Counter:The scan counter has two modes to scan the key matrix and refresh the
display. In the encoded mode, the counter provides binary count that is to be externally

43
decoded to provide the scan lines for keyboard and display. In the decoded scan mode,
the counter internally decodes the least significant 2 bits and provided a decoded 1 out of
4 scan on Sl0 – SL3 scan lines may drive upto 4 displays. The keyboard and display both
are in the same mode at a time.

Return Buffers and Keyboard debounce and Control: This section scans for a key
closure rowwise. If a key closure is detected, the keyboard debounce unit debounces the
key entry. After the debounce period, if the key continues to be detected. The code of the
key is directly transferred to the sensor RAM along with SHIFT and CONTROL key
status.

FIFO/Sensor RAM and Status Logic: In keyboard or strobed input mode, this
block acts as 8-byte first-in first-out (FIFO) RAM. Each key code of the pressed key is
entered in the order of the entry and in the mean time read by the CPU, till the RAM
becomes empty. The status logic generates an interrupt request after each FIFO read
operation till the FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor
RAM. Each row of the sensor RAM is loaded with the status of the corresponding row of
the sensors in the matrix. If a sensor changes its state, the IRQ line goes high to interrupt
the CPU.

Display Address Registers and Display RAM: The display address registers hold
the address of the word currently being written or read by the CPU to or from the display
RAM. The contents of the registers are automatically updated by 8279 to accept the next
data entry by CPU. The 16-byte display RAM contains the 16-bytes of data to be
displayed on the sixteen 7-segment displays in the encoded scan mode.

SIGNAL DESCRIPTION OF 8279

SIGNAL DESCRIPTIONS OF 8279:

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 DB0 - DB7: These are bi-directional data bus lines. The data and command words to
snd from the CPU are transferred on these lines.

CLK: This is a clock input used to generate internal timings required by 8279.

RESET: A high on this line resets 8279. After resetting 8279, it is in sixteen 8-bit
display, left entry encoded scan, 2-key lock out mode.

CS Chip Select: A low on this, line enables 8279 for normal read or write
operations. Otherwise, this in should remain high.

A0: A high on this line indicates the transfer of a command or status information. A
low on this line indicates the transfer of data. This is used to select one of the internal
registers of 8279.

RD, WR (Input/Output) READ/WRITE: These input pins enable the data buffers to
receive or send data over the data bus.

IRQ: This interrupt output line goes high when there is data in the FIFO sensor RAM.
The interrupt line goes low with each FIFO RAM read operation but if the FIFO RAM
further contains any key-code entry to be read b the CPU, this pin again high to generate
an interrupt to the CPU.

Vss, Vcc: Thses are the ground and power supply lines for the circuit.

SL0 – SL3 – Scan Lines: These lines are used to scan the keyboard matrix and
display digits. These lines can be programmed as encoded or decoded, using the mode
control register.

RL0 – RL7 - Return Lines:These are the input lines which are connected to one
terminal of keys, while the other terminal of the keys are connected to the decoded scan
lines. These are normally high, but pulled low when a key is pressed.

SHIFT:The status of the shift input line is stored along with each key code in FIFO, in
scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled low with
a key closure.

CNTL/STB – CONTROL/STROBED I/P MODE: In keyboard mode, this line is

used as a control input and stored in FIFO on a key closure. The line is s strobe line that
enters the data into FIFO RAM, in strobed input mode. It has an internal pull up. The line
is pulled down with a key closure.

BD- Blank Display: This output pin is used to blank the display during digit switching
or by a blanking command.
OUTA0 – OUTA3 and OUTB0 – OUTB3: These are the output ports for two 16x4 (or
one 16x8) internal display refresh registers. The data from these lines is synchronized

45
with the scan lines to scan the display and keyboard. The two 4-bit ports may also be
used as one 8-bit port.

Modes of Operation of 8279:

I) Input or Keyboard Mode.

II) Output or Display Mode.
I) Input or Keyboard Mode
8279 provides 3 input modes.
Which are
a) Scanned Keyboard Mode
b) Scanned Sensor Matrix Mode.
c) Strobed Input Mode.

a) Scanned Keyboard Mode :- This mode allows a key matrix to be interfaced using
either encoded or decoded scan. In encoded scan an 8 x 8 keyboard or in decoded scan a
4 x 8 keyboard can be interfaced. The code of the pressed key along with the status of the
control and shift is stored into the FIFO RAM. This can be performed in 3 methods,
which are
1) Scanned Keyboard Mode with 2 key LOCKOUT.
2) Scanned Keyboard with N – Key Rollover.
3) Scanned Keyboard Special error Mode.

1) Scanned Keyboard Mode with 2 Key LOCKOUT.

In this mode of operation when a key is pressed a debounce logic comes into
operation. The other key are checked for closure during the next two [debounce cycle]
keyboard scans and if no other key is pressed the first pressed key is identified and the
key code of this identified key is entered into the FIFO RAM along with the SHIFT and
CONTROL status. Provided the FIFO is not full. If the FIFO have no space then the data
will not be entered and the error flag is set. If the FIFO has one free byte then the above
code is entered and 8279 generates and interrupt to the CPU to inform about the key
closure. If other key is found closed during the two scans no entry to the FIFO is made. If
two key pressed with in a debounce cycle no key is recognized.

2) Scanned Keyboard with N-Key Rollover

In this mode each key press is treated independently. When a key is pressed the
debounce circuit waits for keyboard scans and check whether the key is still pressed. If it
is still pressed the code of the pressed key is entered into the FIFO RAM. Here any
number of keys can be pressed simultaneously or not, here the keys are sensed in the
order of depression.

3) Scanned Keyboard Special Error Mode

46
 This mode is valid under the N-key Rollover Mode. This mode is programmed
using error mode set command. If during a single denounce period [debounce cycle] two
keys are found pressed, that is considered as simultaneous depression and an error flag is
set in this case. This error flag if set prevents the further writing in FIFO but allows the
generation of interrupts to CPU for FIFO READ. This error flag can be read by reading
the FIFO Status word. This error flag can be reset or the FIFO can be cleared by using
the clear command with CF = 1 [clear FIFO]

B] Scanned Sensor Matrix Mode

In this mode a sensor matrix can be interfaced with 8279 using encoded or
decoded scans. With encoded or decoded scans. With encoded scan 8 x 6 sensor matrix or
with decoded scan 4 x 8 Sensor matrix can be interfaced. The sensor codes are stored in
the sensor RAM. This can be performed as

1) Sensor Matrix Mode:- In the sensor matrix mode 8 bit FIFO RAM act as an 8
x 8 memory matrix. The status of the sensor matrix is fed in to sensor RAM matrix. Thus
the sensor RAM contains the Row wise and Column wise status of the sensors in the
Sensor Matrix. The IRQ line goes high if any change in the sensor value is detected and
this IRQ line is reset by the data read operation.

2) Output or Display Mode :- 8279 provides two output mode for the display

a) Display Scan b) Display Entry

a) Display Scan
In this mode 8279 provide 8 or 16 character multiplexed display and can be
organized as dual 16 x 4 or single 16 x 8 display units.

b) Display Entry
This mode provides two options for data entry on the displays. First one is
known as left entry mode and the second as right entry mode. This left entry mode is also
known as typewriter mode and right entry mode is known as calculator mode.

1) Left Entry Mode

In this mode data is entered from the left side of the display unit. Address
0 of the display RAM contains the left most display character and the
address 15 of the RAM contains the right most display character. The
display RAM address is on the auto increment mode. The first entry is
displayed on the left most display and the sixteenth entry on the right most
display. The seventeenth entry is again displayed at the leftmost display
section.
2) Right Entry Mode
In this mode the first display character is entered on the right most display.
The next entry is also placed on the right most display by shifting the
previous display by one display position. The left most display character

47
 is shifted out of the display at the seventeenth entry and is lost ie., it
pushed out of the display RAM.

11. Interface stepper motor with 8085

THEORY: A motor in which the rotor is able to assume only discrete stationary angular
position is a stepper motor. The rotary motion occurs in a step-wise manner from
one equilibrium position to the next. Stepper Motors are used very wisely in
position control systems like printers, disk drives, process control machine tools,
etc. The basic two-phase stepper motor consists of two pairs of stator poles.
Each of the four poles has its own winding. The excitation of any one winding
generates a North Pole. A South Pole gets induced at the diametrically opposite
side. The rotor magnetic system has two end faces. It is a permanent magnet
with one face as South Pole and the other as North Pole. The Stepper Motor
windings A1, A2, B1, B2 are cyclically excited with a DC current to run the
motor in clockwise direction. By reversing the phase sequence as A1, B2, A2,
B1, anticlockwise stepping can be obtained.

2-PHASE SWITCHING SCHEME:

In this scheme, any two adjacent stator windings are energized. The switching
scheme is shown in the table given below. This scheme produces more torque.

ANTICLOCKWISE CLOCKWISE
STEP A1 A2 B1 B2 DATA STEP A1 A2 B1 B2 DATA
1 1 0 0 1 9h 1 1 0 1 0 Ah
2 0 1 0 1 5h 2 0 1 1 0 6h
3 0 1 1 0 6h 3 0 1 0 1 5h
4 1 0 1 0 Ah 4 1 0 0 1 9h

ADDRESS DECODING LOGIC: The 74138 chip is used for generating the address
decoding logic to generate the device select pulses, CS1 & CS2 for selecting the IC
74175.The 74175 latches the data bus to the stepper motor driving circuitry. Stepper
Motor requires logic signals of relatively high power. Therefore, the interface circuitry
that generates the driving pulses use silicon darlington pair transistors. The inputs for the
interface circuit are TTL pulses generated under software control using the
Microcontroller Kit. The TTL level of pulse sequence from the data bus is translated to
high voltage output pulses using a buffer 7407 with open collector.

HARDWARE DESCRIPTION: The hardware setup consists of a microprocessor/

Microcontroller motherboard and stepper motor interface board. The motherboard
consists of 8085 /8051MPU/ MCU, 8KB EPROM, 8KB RAM, Keyboard and display
controller 8279, 21-key Hex-keypad and six numbers of seven segment LEDs and Bus
Expansion connector. The stepper motor interface consists of driver transistors for stepper
motor windings and address decoding circuit. The microprocessor/ Microcontroller
output the binary sequence through data bus, which are converted to current pulses by the

48
driver transistors and used to drive stepper motor. The software for the system is
developed in 8085 /8051assembly language.

Address/
AD0-AD7 Control Transistor driver
8085/8051 LATCH Address/
CPU Decoder CS

50 Pin Expansion Connector

EPROM

D0-D7
8KB Stepper driver

A0-A7
D0-D3

Connector
System bus Latches M

RAM 8279
Keyboard Buffer
8KB LED indication for
Display output binary sequence
Display
Keyboard
C D E F int
8 9 A B Go
4 5 6 7 Nxt
0 1 2 3 Sub

Fig1. Block diagram of stepper motor interface

12. Interface Traffic light controller with 8085

HARDWARE DESCRIPTION:

The 8085’8051 Microprocessor/ Microcontroller is a popular Microprocessor/

Microcontroller used in Industries for various applications. Such as traffic light control,
temperature control, stepper motor control, etc. The traffic lights are interfaced to
Microprocessor/ Microcontroller system through buffer and ports of programmable
peripheral Interface 8255. So the traffic lights can be automatically switched ON/OFF in
desired sequence. The Interface board has been designed to work with parallel port of
Microprocessor/ Microcontroller system.

The hardware of the system consists of two parts. The first part is Microprocessor /
Microcontroller based system. Microprocessor/ Microcontroller as CPU and the
peripheral devices like EPROM, RAM, Keyboard & Display Controller 8279,
Programmable as Peripheral Interface 8255, 26 pin parallel port connector, 21 keys Hexa
key pad and six number of seven segment LED’s.
The second part is the traffic light controller interface board, which consist of 36
LED’s in which 20 LED’s are used for vehicle traffic and they are connected to 20 port
lines of 8255 through Buffer. Remaining LED’s are used for pedestrian traffic. The
traffic light interface board is connected to Main board using 26 core flat cables to 26-pin

49
Port connector. The LED’s can be switched ON/OFF in the specified sequence by the
Microprocessor/ Microcontroller. The block diagram of the system is shown in fig.1. The
layout of the traffic light is shown in fig 2.

26 pin port connector

26 pin port connector
26 pin
FRC cable

Traffic light interface board

Buffer
8085 AD0-AD7 Latch A0-A7
8255
/8051 PPI
D0-D7

CPU

System Bus

8279 Anode driver

EPROM RAM keyboard
Display Display
Fig 1: Block diagram of Traffic Light Controller
Controller
Stop PW

Stop PE
Go PE
Go PW

Stop PN NORTH Stop PN

Go PN Decoder Go PN
Keyboard
Cathode driver
Warning W

Stop N
Warning N
FL W

Warning E
Stop W

Go N
FR N
FL N
Stop E

ST N
FR E
ST W

ST E
WEST

EAST
Go W
FR W

FL E

ST S FR S
FL S
Go S
Stop PW

Warning S
Stop PE
Go PE
Go PW

Stop S
Stop PS Stop PS
Go PS Go PS
SOUTH
FIG.2: LAYOUT OF TRAFFIC LIGHTS

50