Pedagogical and Technological University of Colombia

Electronics Engineering School

Digital Electronics 1 Course
Laboratory Exercises
Laboratory Exercise 3
Basic Logic Gates – Physical Implementation
The principal aim of this exercise is to recognize some physical features of real logic gates, and to check its impact
on the operation of the circuits.

Introduction
Most of the simulation tools offers a plenty of advantages, like fast designing and checking. However, there are
some aspects that should be studied from the real implantation of the circuits. Through the development of this
laboratory exercise, the student should be able to understand and interpret some of that features that the simulation
doesn’t show them completely.

Logic Families
Depending on the technology used to build digital integrated circuits, they are classified in a set of groups called
“Logic Families”. There are two principal logic families, CMOS (complemented MOSFET) and TTL (transistor-
transistor logic).

• CMOS technology is based on MOSFET transistors. Because of this, a CMOS gate input needs a minimum
amount of current to be excited (due to the isolated input in the MOSFETs). The power consumption is
proportional to operation frequency, because of the parasitic capacitance, which makes them slower too.

• TTL chips are built with bipolar transistors. This fact makes them to need more current than CMOS chips
to be excited and their power consumption is about the same regardless of the frequency. Nevertheless,
power consumption in TTL chips is highest than in CMOS chips in the most cases.

Fan-In and Fan-Out

Fan-In is associated directly to the number of inputs to a logic gate, the image below shows a Fan-In = 3 AND gate.
The higher the Fan-In of a gate, the slower it is.

Fig. 1 Fan-In = 3 AND gate

Fan-Out is the maximum number of digital inputs that the output of a single gate can feed. This is usually calculated
from same logic family gates. When a gate outputs a high logical level (1), it behaves as a source of current, and the
inputs of the gates connected to it are sinks of current. When a gate outputs a low logical level (0), it behaves as a
sink of current, and the inputs of the gates connected to it are sources of current. The following figures show these
situations:
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
IOH IIH IOL IIL

IIH IIL

IIH IIL

(a) (b)
Fig. 2 a) Gate as a source of current; b) Gate as a sink of current

Where: IOH: output current when high, IIH: input current when high, IOL: output current when low, I IL: input current
when low. These parameters are found in the datasheet. Since these values are usually different for low and high
states, there are two possible Fan-Out calculations:

𝐼𝐼𝐻
𝐹𝑎𝑛𝑂𝑢𝑡 =
𝐼𝑂𝐻

𝐼𝐼𝐿
𝐹𝑎𝑛𝑂𝑢𝑡 =
𝐼𝑂𝐿

The actual value of Fan-Out corresponds to the least of these calculations.

Propagation Delay
It is the time taken by a gate, to change the state of one of its outputs since the changing of one of its inputs. Taking
into account that a change of state is really a ramp, the change of state is established when the signal crosses 50% of
the maximum value. There are two propagation time measurements, when the selected output goes from high low to
(tPHL) and vice versa (tPLH).

50% VH 50% VH
Input

50% VH 50% VH
Output

tPHL tPLH

Fig. 3 Propagation delay waveform

 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
Part I
Implement on protoboard the design developed for the Part III of the Laboratory Exercise 2, using dip-switches as
the inputs and a LED as the alarm output. Verify the truth table and check the propagation times from each input to
the output. Analyze and explain.

Part II
Assume that you want to install several alarms in different locations of the house (4 in total), to do that, you decide
to add two cascaded NOT TTL gates for each output alarm and connect all of them to the original output. Does it
still work? What happens with the original output voltage when you add the new outputs, one by one? Analyze and
explain the behavior.

Part III
The design has changed, and now you need to connect an alarm 800m away. To avoid the signal attenuation, you
decide to install “amplification stations” every 100m, based on two cascaded NOT gates (you don’t have to use
pieces of 200m of wire, you just must implement the stations). Check the propagation times from each input to the
output of each station. Analyze and explain.