Analysis and Implementation of a Bidirectional
Converter with High Conversion Ratio
1
Lin, B.-R., Senior Member, IEEE, 2Chen, J.-J., and 1Hsieh, F.-Y.
1
Department of Electrical Engineering
2
Graduate School of Engineering Science and Technology
National Yunlin University of Science and Technology, Yunlin 640, Taiwan, ROC
ABSTRACT—A bidirectional dc converter with high conversion
ratio is presented in this paper to have the capability of
bidirectional power flow. Two boost conversion stages are adopted
in the converter to achieve high voltage step-up conversion. The
other power flow direction can also be achieved in the proposed
converter with low voltage step-down conversion. Comparison
with the conventional boost converter with narrow turn-off period,
the proposed converter has wide conversion ratio so that the
higher or lower output voltage can be achieved. To reduce the
switching losses and limit the voltage stress on the power switch,
the boost type of active snubber is used in the converter. The
resonance based on the output capacitance of power switch and
resonant inductance at the transition interval will make the power
switches to turn on at zero voltage switching (ZVS). The circuit
configuration, principle operation, system analysis, and design
consideration of the proposed converter are presented. Finally,
experiments conducted on a laboratory prototype are presented to
verify the effectiveness of the proposed converter.
Index Terms—active snubber, dc converters, soft switching.
I. INTRODUCTION
T he high performance bidirectional dc converters have been
widely studied for many industrial applications, such as car
auxiliary power supplies [1], hybrid electric vehicle [2-3],
battery-charged/discharged dc converter in UPS system [4] and
fuel-cell based dc converter [5-7]. Conventional converter with
high voltage step-up can be easily implemented with the
isolation transformer. However, a converter without
transformer is not easily realized by conventional boost
converter due to the narrow allowed duty cycle. The switching
losses on the power devices are the other drawback. The high
step-down buck converters are presented in [8-9]. The cascade
boost converters and coupled-inductor converters with high
step-up have been proposed in [10-11] for non-isolated
applications. However, the switching losses of switches are still
high enough. The passive or active snubber [12-13] can be used
for reducing the voltage surge of switch to improve the
converter efficiency.
A bidirectional dc converter with high conversion ratio is
presented in this paper to achieve bidirectional power flow
capability. In the proposed converter, two boost conversion
stages are used to achieve high conversion ratio. The power
flow is transferred from low voltage side to high voltage side if
the converter is operated in the boost mode. On the other hand,
the power flow is transferred from high voltage side to low
voltage side if the converter is operated in the buck mode. To
further reduce the switching losses on the power switches, the
active snubber circuit is adopted in the converter to achieve
zero voltage switching (ZVS) of power switches. The circuit
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configuration, operational principle, steady state analysis and
design consideration of the proposed converter are presented in
detail. Finally, experimental results, taken from a laboratory
prototype are presented to demonstrate the circuit performance
and to verify the feasibility of the proposed converter.
iL1 L1 D2 iS3 S3
iD2
S1
iS1 L2
C1 D1 C3
iL2
iD1 vC2 C2
S2
iS2
Fig. 1. Circuit configuration of the proposed bidirectional converter.
II. PROPOSED BIDIRECTIONAL DC CONVERTER
A. Circuit configuration
Fig. 1 gives the circuit configuration of the proposed
converter with high conversion ratio. The proposed converter
can be operated in the boost mode to deliver dc power from low
voltage side to high voltage side by controlling the switch S2.
The circuit components vlow, L1, D2, S1, C2 and S2 are
operated as a boost converter with vC2/vlow=1/(1-D) where D is
the duty cycle of switch S2. The circuit components of the other
boost converter include C2, L2, S2, S3 and C3. The voltage
conversion of this boost converter is vhigh/vC2=1/(1-D) where D
is the duty cycle of switch S2. Therefore, the total voltage
conversion ratio between high voltage side and low voltage side
is vhigh/vlow=1/(1-D)2. On the other hand, the power flow from
high voltage side to low voltage side can be achieved by
controlling the switches S1 and S3. In the buck mode, The
circuit components vhigh, S1, L2, S3 and C2 are operated as a
buck converter with the conversion ratio vC2/vhigh=D where D is
the duty ratio of switch S3. The circuit components C2, S1, D1,
L1 and vlow are operated as a buck conversion with vlow/vC2=D
where D is the duty ratio of S1. Since the duty ratios of S1 and
S3 equal D, the total conversion ratio of the proposed converter
in buck mode operation is vlow/vhigh=D2. The proposed
bidirectional converter with high voltage gain can be used in
fuel cell based dc-dc converter or battery charged/discharged
converter in UPS system.
B. Circuit operation
To simplify the discussion of the circuit operation during one
switching cycle, some assumptions are made as follows.
Capacitances of C1, C2 and C3 are large enough such that the
capacitor voltages vlow, vC2 and vhigh are constant. All diodes
and switches are ideal. There are two operation modes in the
proposed converter for boost and buck modes respectively.
When the proposed converter is operated in the boost mode, the
switches S1 and S3 are off. The power is delivered from low
voltage side to high voltage side by controlling the duty cycle D
of switch S2. The corresponding equivalent circuits and key
waveforms for boost mode operation are given in Figs. 2 and 3.
iL1 L1
S1
iS1
C1 D1
iL2
iD1 vC2
(a) (b)
Fig. 2 Equivalent circuit of the proposed converter in boost mode operation (a)
S2 on (b) S2 off.
vS2,gs
iL1
iL2
-iS1
iS2
iD2
-iS3
T
DT
Fig. 3 Key waveforms of the proposed converter in boost mode operation.
When switch S2 is turned on (Fig. 2(a)), the low voltage
source vlow will charge inductor L1 through the path
C1-L1-D2-S2. The inductor current iL1 increases. In the mean
time, the capacitor C2 delivers the power to inductor L2
through the path C2-L2-S2. The inductor current iL2 increases.
The diode D1 is blocking and switches S1 and S3 are in the off
state. The inductor voltages vL1=vlow and vL2=vC2. When switch
S2 is turned off (Fig. 2(b)), the energy stored in inductor L1 is
delivered to capacitor C2 through the path C1, L1, anti-parallel
diode of S1 and C2. The inductor voltage vL1=vlow-vC2. The
inductor current iL1 decreases. The energy stored in inductor L2
is delivered to high voltage side through the path C2, L2,
anti-parallel diode of S3 and vhigh. The inductor voltage
vL2=vC2-vhigh. The inductor current iL2 decreases. The diodes D1
and D2 are blocking when S2 is turned off. Based on the
voltage-second balance on inductors L1 and L2 respectively,
one can obtain the voltage ratios of the proposed converter in
the boost mode.
vC2=vlow/(1-D), vhigh=vC2/(1-D), vhigh=vlow/(1-D)2 (1)
When the proposed converter is operated in the buck mode,
the switch S2 is off. The dc power is delivered from high
voltage side to low voltage side by controlling the duty cycle D
of switches S1 and S3 simultaneously. The corresponding
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equivalent circuits and key waveforms for buck mode operation
are given in Figs. 4 and 5. When switches S1 and S3 are turned
on (Fig. 4(a)), the dc power is delivered from high voltage side
vhgih to capacitor C2 through the path C3-S3-L2-C2. The
inductor voltage vL2=vC2-vhigh<0. Therefore the inductor current
iL2 decreases. In the mean time, the energy stored in capacitor
C2 is delivered to low voltage side vlow through the path
C2-S1-L1-C1. The inductor voltage vL1=vlow-vC2<0 so that the
D2 iS3 S3 inductor current iL1 decreases. The diodes D1 and D2 are
blocking and switch S2 is off. When switches S1 and S3 are
iD2
turned off (Fig. 4(b)), the inductor current iL2 flows through the
L2
C3 anti-parallel diode of S2, L2 and C2. The inductor voltage
C2 vL2=vC2 so that the inductor current iL2 increases. The inductor
S2
iS2
current iL1 flows through D1, L1 and C1. The inductor voltage
vL1=vlow so that the inductor current iL1 increases. Based on the
voltage-second balance on inductors L1 and L2 respectively,
one can obtain the voltage ratios of the proposed converter in
the buck mode.
vC2=Dvhig, vlow=DvC2, vlow=D2vhigh (2)
vhigh
vlow
(a) (b)
Fig. 4 Equivalent circuit of the proposed converter in buck mode operation (a)
S1 and S3 on (b) S1 and S3 off.
t
Fig. 5 Key waveforms of the proposed converter in buck mode operation.
III. ZVS BIDIRECTIONAL DC CONVERTER
In order to reduce the switching losses on S2, an active
snubber circuit including clamp capacitor Cc, auxiliary Sa and
resonant inductor Lr can be added in the circuit to create a
resonance. Fig. 6 shows the ZVS bidirectional dc converter
with three kinds of active snubber. Switch S2 and Sa are
switched in a complementary way with a short delay time.
When dc power is transferred from high voltage side to low
voltage side (buck mode), the ZVS bidirectional converter is
the same operation behavior as shown in Fig. 4. When dc power
is transferred from low voltage vlow to high voltage vhigh (boost
mode), the switches S2 and Sa are turned on at ZVS. In Fig. 6(a),
the clamp capacitor voltage vCc is greater than the low side
voltage vlow. However, the clamp capacitor voltage
vCc=Dvlow/(1-D) in Figs. 6(b) and 6(c). The operation behaviors
of three kinds of ZVS bidirectional converter shown in Fig. 6
are almost the same. Therefore, only the operation principle of
circuit configuration shown in Fig. 6(a) is discussed. When
switch S2 is turned off, the positive inductor current iLr will
flow through the anti-parallel diode of the auxiliary switch Sa
and clamp capacitor Cc. Therefore the drain voltage of auxiliary
switch vDa,ds is zero. At this instant, the auxiliary switch Sa can
be turned on at ZVS. If the auxiliary switch Sa is turned on, the
inductor current iLr decreases from positive to negative value.
When the auxiliary switch Sa is turned off, the negative
inductor current iLr will flow through resonant capacitor Cr. The
capacitor Cr is discharged from positive voltage to zero voltage.
When the capacitor voltage vCr=0, the anti-parallel diode of the
switch S2 is turned on. Then switch S2 can be turned on at this
instant to achieve ZVS. During one switching period, there are
eight operation modes of the proposed ZVS converter in boost
mode operation. The corresponding equivalent circuits for each
operation mode are given in Fig. 7. Fig. 8 shows the time
sequence of key waveforms in the boost mode operation. The
following description explains the detailed operation principle
of the proposed topology.
(a)
(b)
(c)
Fig. 6 ZVS bidirectional converter (a) with boost type of active snubber (b) and
(c) with buck-boost type of active snubber.
Mode 1 [t0≤t<t1]: In this mode, switch S2 is on, auxiliary switch
Sa is off, and diode D2 is on. The inductor voltages vL1+vLr=vin
and vL2+vLr=vC2. Since, Lr<<L1 and L2, the inductor currents
iL1 and iL2 increase. The switch currents iS2=iL1+iL2 and iSa=0.
This mode ends at time t1 when switch S2 is turned off.
Mode 2 [t1≤t<t2]: Main switch S2 is turned off at time t1. The
positive inductor current iLr will charge capacitor Cr from zero
voltage to vC2+vLr≈vC2. The capacitance of Cr is small enough
such that the capacitor Cr is linearly charged. The inductor
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currents iL1 and iL2 are almost constant in this mode. This mode
ends at time t2 when the capacitor voltage vCr=vC2. At time t2, the
anti-parallel diode of switch S1 and diode D2 are both on to
commutate the inductor current iL1. The time interval in this
mode is given as:
Cv
Δt12 = t 2 − t1 ≈ r C2 (3)
i Lr (t1 )
Mode 3 [t2≤t<t3]: This mode starts at time t2 when the
anti-parallel diode of S1 and diode D2 are both on. The current
iS1 decreases from zero and the diode current iD2 decreases. This
mode ends at time t3 when the capacitor voltage vCr equals vCc
and the anti-parallel diode of Sa is on.
Mode 4 [t3≤t<t4]: This mode starts at time t3 when vCr=vCc and
the anti-parallel diode of Sa is on. Since the anti-parallel diode
of S1 and diode D2 are on, the inductor voltage vL2 equals zero
and the inductor voltage vLr=vC2-vCc<0. Thus the inductor
current iLr decreases. This mode ends at time t4 when the diode
current iD2=0 and the anti-parallel diode of S3 is on.
Mode 5 [t4≤t<t5]: This mode starts at time t4 when the diode
current iD2=0 and the anti-parallel diode of S3 is on. The
inductor voltages vL1=vlow-vC2<0 and vL2=vC2-vhigh<0. Thus the
inductor currents iL1 and iL2 decrease. The resonant inductor
voltage vLr=vhigh-vCc<0 so that the inductor current iLr decreases
from positive value to negative value in this mode. Before the
inductor current iLr is negative value, the auxiliary switch Sa
should be turned on to achieve ZVS. This mode ends at time t5
when auxiliary switch Sa is turned off.
Mode 6 [t5≤t<t6]: This mode starts at time t5 when auxiliary
switch Sa is turned off and ends at time t6 when capacitor voltage
vCr=0. The anti-parallel diode of S3 is still on in this mode.
Since the inductor current iLr is negative, the capacitor Cr is
discharged by iLr. The capacitor voltage vCr decreases from vCc
to zero voltage. The inductor currents iL1 and iL2 decrease. The
capacitor voltage vCr should reach zero before the end of this
mode to ensure ZVS operation of switch S2. To achieve this
condition, the energy stored in the resonant inductor Lr must be
greater than the energy stored in the resonant capacitor Cr. This
mode ends at time t6 when capacitor voltage vCr=0. The
anti-parallel diode of switch S2 is turned on.
Mode 7 [t6≤t<t7]: This mode starts at time t6 when capacitor
voltage vCr=0 and the anti-parallel diode of switch S2 is turned
on. In this mode the anti-parallel diodes of S1 and S3 are still
on. The inductor currents iL1 and iL2 decrease. The inductor
current iLr increases from negative value to positive value.
Before the switch current iS2 is positive, switch S2 should be
turned on to achieve ZVS. This mode ends at time t7 when the
switch current iS3 is zero and diode D2 is on.
Mode 8 [t7≤t<T+t0]: This mode starts at time t7 when the switch
current iS3 is zero and diode D2 and the anti-parallel diode of S1
are in the commutation interval. The inductor voltage vL2
equals zero. The inductor voltage vLr=vC2 so that the inductor
current iLr increases. The current iS1 increases to zero and the
diode current iD2 increases. This mode ends at time t0 when the
current iS1 equals zero. Then the operation behavior in one
switching period is completed.
 Based on the key waveforms of the proposed converter
shown in Fig. 8, the delay time at modes 2, 3, 6 and 7 during the
transition interval between switches S2 and Sa is neglected in

vhigh
vlow
steady state analysis. In modes 4 and 8, the anti-parallel diode
of S1 and diode D2 are in the commutation interval. The
inductor voltage vL1≈vlow in mode 1 and vL1=vlow-vC2 in modes
(a) (b) 4, 5 and 8. Based on the voltage-second balance on inductor L1,
one can obtain the equation.
vlow(D-DM8)+(vlow-vC2)(1-D+DM8)=0 (4)
where D is the duty cycle of switch S2 and DM8=(T+t0-t7)/T is
the duty cycle loss of the converter in mode 8. Based on (4), the
capacitor voltage vC2 can be expressed as:
vC2=vlow/(1-D+DM8) (5)
(c) (d) The inductor voltage vL2≈vC2 in mode 1 and vL2=vC2-vhigh in
mode 5. Applying the voltage-second balance to inductor L2,
one can obtain the equation.
vC2(D-DM8)+(vC2-vhigh)(1-D-DM4)=0 (6)
vhigh
vlow

where DM4=(t4-t3)/T is the duty cycle loss of the converter in

mode 4. Based on (6), one can derive the high side voltage vhigh
as:
(e) (f) vhigh=vC2(1-DM4-DM8)/(1-D-DM4)
=vlow(1-DM4-DM8)/[(1-D+DM8)(1-D-DM4)] (7)
If DM4=DM8<<D, we can obtain vhigh≈vlow/(1-D)2 and
vC2≈vlow/(1-D). This equation meets voltage equation in the
proposed hard switching bidirectional converter in (1). The
voltage on the inductors L2 and Lr is vL2+vLr=vC2 in modes 1
and 8 and vL2+vLr=vC2-vCc in modes 4 and 5. Based on the
(g) (h) voltage-second balance on the inductors L2 and Lr, one can
Fig. 7 Operation modes of proposed ZVS converter in boost mode operation (a)
mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7 (h)
obtain the following equation.
mode 8. DvC2+(vC2-vCc)(1-D)=0 (8)
T The clamp capacitor voltage can be expressed as:
DT
vS2,gs vCc=vC2/(1-D)=vlow/[(1-D)(1-D+DM8)]≈vlow/(1-D)2 (9)
vSa,gs Therefore, the active snubber circuit shown in Fig. 6(a) is a
vCr=vS2,ds vCc boost type topology.
vSa,ds vCc
B. Design consideration
vCc The average current on input inductor L1 is given as:
iL1 Phigh
i L1, av = (10)
iL2 ηv low
iLr where η is the circuit efficiency and Phigh is the output power at
the high voltage side. Since DM4, DM8<<D, we neglect the duty
iS2 cycle losses in modes 4 and 8 to simplify the circuit design. The
duty cycle of the switch S2 is
iSa v low
D ≈ 1− (11)
v high
-iS1 One can obtain the peak current on input inductor L1.
iD2 Phigh v
i L1,peak = i L1 (t 2 ) ≈ + low DT (12)
-iS3 ηv low 2L1
t
If the ripple currents ΔiL1 and ΔiL2 on inductors L1 and L2 are
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8
t0 t1 t2 t3 t4 t5 t6 t7 T+t0 given, the inductances of L1 and L2 can be expressed as:
Fig. 8 Key waveforms of proposed ZVS converter in boost mode operation. DTv low DTv low
L1 ≥ , L2 ≥ (13)
Δi L1 Δi L 2 (1 - D)
IV. STEADY STATE ANALYSIS AND DESIGN CONSIDERATION
The voltage stresses of power switches S2 and Sa are expressed
OF ZVS BIDIRECTIONAL CONVERTER
as:
A. Steady state analysis v Low
v S2 ,stress = vSa ,stress ≈ (14)
(1 − D) 2

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If we assume! η = 1 ,!the peak current stresses of switches S2 voltage and current waveforms in boost mode operation at rated
and Sa are approximately equal to power. From the measured results, we can see that iL1=iD2-iS1
Phigh and iD2+iL2+iS3=iLr. When switch S2 is turned on, iD2=iL1,
v
i S2, peak ≈ i L1, peak + i L2, peak ≈ [ + low DT] iLr=iS2=iL1+iL2, iS1=0, iS3=0 and iSa=0. The inductor currents iL1
v high (1 − D) 2
2L1 and iL2 increase. When switch S2 is off and auxiliary switch Sa
,
Phigh vlow is on, then -iS1=iL1, iD2=0, iS2=0 and iLr=-iSa=iL2+iS3. The
+[ + DT] inductor currents iL1 and iL2 decrease. The drain voltage
v high (1 − D) 2(1 − D)L 2 vS2,ds=vCc. Fig. 11 gives the measured key current and voltage
Phigh v low waveforms in the buck mode operation at rated power. It can be
i Sa , peak ≈ i L 2, peak ≈ + DT (15) found in Fig. 11 that iL2=-iS3 and i1=-iS1 if switches S1 and S3
v high (1 − D) 2(1 − D)L2
are turned on. When S1 and S3 are turned off, i1=-iD1 and
The average diode and switch currents are expressed as: iL2=iS2.
Phigh DPhigh
i S1, av ≈ , i D 2, av ≈ ,
v high (1 − D) v high (1 − D) 2
vS2,gs
Phigh
i S3,av = (16)
v high
The voltage stresses of diode D2 and switches S1 and S3 are
approximately given as: vS2,ds ZVS
v Dv low
vS1,stress ≈ v C2 ≈ low , v D 2,stress = v high − v C 2 ≈ ,
1- D (1 - D) 2
v low iS2
vS3, stress ≈ v high ≈ (17)
(1 - D) 2
In mode 6, the energy stored in the resonant inductor Lr must be
greater than the energy stored in the resonant capacitor Cr to 1 s
create the ZVS condition for main switch S2, i.e.
(a)
L r ≥ C r v 2Cc /[i Lr ( t 5 )]2 . The delay time td at t1-t3, and t5-t7
respectively is approximately equal to π L r C r / 2 . If the
capacitance of Cr is given, the inductance of Lr is about
4t 2d /(C r π 2 ) . In the design of clamp capacitance, half of the
resonant period in mode 5 is larger than the off time of main
switch S2. Therefore the clamp capacitance Cc can be given as
C c >> (1 − D) 2 T 2 /( π 2 L r ) .

V. EXPERIMENTAL RESULTS
The performance and effectiveness of the proposed ZVS
bidirectional converter shown in Fig. 6(a) are verified by the
experimental results based on a laboratory prototype. The
system parameters of the design circuit are: (1) low side voltage
vlow=36V, (2) high side voltage vhigh=200V, (3) rated power (b)
Fig. 9 Measured results of the gate voltage, drain voltage and switch current at
P=240W, and (4) switching frequency:110kHz. The input and rated output power (a) switch S2 (b) auxiliary switch Sa.
output inductances L1=150μH and L2=210μH. The selected
clamp capacitance Cc is 0.47μF with voltage stress of 400V. VI. CONCLUSION
The capacitances of C1, C2 and C3 are 680μF, 220μF and
The ZVS bidirectional dc converter is presented to have the
470μF, respectively. The IGBT IRG4PC40W with anti-parallel
following features: wide voltage conversion ratio and low
diode MUR860 are used for switching devices S1-S3 and Sa in
switching losses on switches. When power is transferred from
the proposed converter. The adopted diodes are MUR860. The
the high voltage side to the low voltage side, the converter is
adopted resonant capacitor Cr is about 470pF. The selected
operated in buck mode to charge the low voltage side. On the
resonant inductor Lr is 22μH. other hand, the converter is operated in boost mode when power
In the boost mode operation, Fig. 9 shows the measured is delivered from low voltage side to high voltage side. The
waveforms of gate voltage, drain voltage and switch current of boost type and buck-boost type of active snubber are presented
power switches S2 and Sa at rated output power. Before the in the circuit to achieve ZVS turn-on in boost mode operation.
switches are turned on, the switch currents are negative and the The circuit configuration, operation principle and design
drain voltages have been decreased to zero. Therefore, both consideration are demonstrated in detail. Finally the
switches are turned on at ZVS. Fig. 10 gives the measured key

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Fig. 10 Measured key waveforms of the proposed ZVS converter in boost mode
operation.

VII. ACKNOWLEDGEMENT
The authors would like to acknowledge the partial financial
support of the National Science Council in Taiwan, Republic of
China, through its grant NSC96-2622-E-224-030-CC3.

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