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Analysis and Implementation of a Bidirectional

Converter with High Conversion Ratio


1
Lin, B.-R., Senior Member, IEEE, 2Chen, J.-J., and 1Hsieh, F.-Y.
1
Department of Electrical Engineering
2
Graduate School of Engineering Science and Technology
National Yunlin University of Science and Technology, Yunlin 640, Taiwan, ROC

ABSTRACT—A bidirectional dc converter with high conversion configuration, operational principle, steady state analysis and
ratio is presented in this paper to have the capability of design consideration of the proposed converter are presented in
bidirectional power flow. Two boost conversion stages are adopted detail. Finally, experimental results, taken from a laboratory
in the converter to achieve high voltage step-up conversion. The prototype are presented to demonstrate the circuit performance
other power flow direction can also be achieved in the proposed
converter with low voltage step-down conversion. Comparison
and to verify the feasibility of the proposed converter.
with the conventional boost converter with narrow turn-off period,
the proposed converter has wide conversion ratio so that the iL1 L1 D2 iS3 S3
higher or lower output voltage can be achieved. To reduce the
switching losses and limit the voltage stress on the power switch, iD2
S1
the boost type of active snubber is used in the converter. The iS1 L2
resonance based on the output capacitance of power switch and C1 D1 C3
iL2
resonant inductance at the transition interval will make the power iD1 vC2 C2
switches to turn on at zero voltage switching (ZVS). The circuit S2
configuration, principle operation, system analysis, and design iS2
consideration of the proposed converter are presented. Finally,
Fig. 1. Circuit configuration of the proposed bidirectional converter.
experiments conducted on a laboratory prototype are presented to
verify the effectiveness of the proposed converter.
II. PROPOSED BIDIRECTIONAL DC CONVERTER
Index Terms—active snubber, dc converters, soft switching. A. Circuit configuration
Fig. 1 gives the circuit configuration of the proposed
I. INTRODUCTION converter with high conversion ratio. The proposed converter
can be operated in the boost mode to deliver dc power from low
T he high performance bidirectional dc converters have been
widely studied for many industrial applications, such as car
auxiliary power supplies [1], hybrid electric vehicle [2-3],
voltage side to high voltage side by controlling the switch S2.
The circuit components vlow, L1, D2, S1, C2 and S2 are
battery-charged/discharged dc converter in UPS system [4] and operated as a boost converter with vC2/vlow=1/(1-D) where D is
fuel-cell based dc converter [5-7]. Conventional converter with the duty cycle of switch S2. The circuit components of the other
high voltage step-up can be easily implemented with the boost converter include C2, L2, S2, S3 and C3. The voltage
isolation transformer. However, a converter without conversion of this boost converter is vhigh/vC2=1/(1-D) where D
transformer is not easily realized by conventional boost is the duty cycle of switch S2. Therefore, the total voltage
converter due to the narrow allowed duty cycle. The switching conversion ratio between high voltage side and low voltage side
losses on the power devices are the other drawback. The high is vhigh/vlow=1/(1-D)2. On the other hand, the power flow from
step-down buck converters are presented in [8-9]. The cascade high voltage side to low voltage side can be achieved by
boost converters and coupled-inductor converters with high controlling the switches S1 and S3. In the buck mode, The
step-up have been proposed in [10-11] for non-isolated circuit components vhigh, S1, L2, S3 and C2 are operated as a
applications. However, the switching losses of switches are still buck converter with the conversion ratio vC2/vhigh=D where D is
high enough. The passive or active snubber [12-13] can be used the duty ratio of switch S3. The circuit components C2, S1, D1,
for reducing the voltage surge of switch to improve the L1 and vlow are operated as a buck conversion with vlow/vC2=D
converter efficiency. where D is the duty ratio of S1. Since the duty ratios of S1 and
A bidirectional dc converter with high conversion ratio is S3 equal D, the total conversion ratio of the proposed converter
presented in this paper to achieve bidirectional power flow in buck mode operation is vlow/vhigh=D2. The proposed
capability. In the proposed converter, two boost conversion bidirectional converter with high voltage gain can be used in
stages are used to achieve high conversion ratio. The power fuel cell based dc-dc converter or battery charged/discharged
flow is transferred from low voltage side to high voltage side if converter in UPS system.
the converter is operated in the boost mode. On the other hand,
the power flow is transferred from high voltage side to low B. Circuit operation
voltage side if the converter is operated in the buck mode. To To simplify the discussion of the circuit operation during one
further reduce the switching losses on the power switches, the switching cycle, some assumptions are made as follows.
active snubber circuit is adopted in the converter to achieve Capacitances of C1, C2 and C3 are large enough such that the
zero voltage switching (ZVS) of power switches. The circuit capacitor voltages vlow, vC2 and vhigh are constant. All diodes

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and switches are ideal. There are two operation modes in the equivalent circuits and key waveforms for buck mode operation
proposed converter for boost and buck modes respectively. are given in Figs. 4 and 5. When switches S1 and S3 are turned
When the proposed converter is operated in the boost mode, the on (Fig. 4(a)), the dc power is delivered from high voltage side
switches S1 and S3 are off. The power is delivered from low vhgih to capacitor C2 through the path C3-S3-L2-C2. The
voltage side to high voltage side by controlling the duty cycle D inductor voltage vL2=vC2-vhigh<0. Therefore the inductor current
of switch S2. The corresponding equivalent circuits and key iL2 decreases. In the mean time, the energy stored in capacitor
waveforms for boost mode operation are given in Figs. 2 and 3. C2 is delivered to low voltage side vlow through the path
C2-S1-L1-C1. The inductor voltage vL1=vlow-vC2<0 so that the
iL1 L1 D2 iS3 S3 inductor current iL1 decreases. The diodes D1 and D2 are
blocking and switch S2 is off. When switches S1 and S3 are
iD2
S1 turned off (Fig. 4(b)), the inductor current iL2 flows through the
iS1 L2
C1 D1
iL2
C3 anti-parallel diode of S2, L2 and C2. The inductor voltage
iD1 vC2 C2 vL2=vC2 so that the inductor current iL2 increases. The inductor
S2
iS2
current iL1 flows through D1, L1 and C1. The inductor voltage
vL1=vlow so that the inductor current iL1 increases. Based on the
(a) (b) voltage-second balance on inductors L1 and L2 respectively,
Fig. 2 Equivalent circuit of the proposed converter in boost mode operation (a)
S2 on (b) S2 off. one can obtain the voltage ratios of the proposed converter in
the buck mode.
vC2=Dvhig, vlow=DvC2, vlow=D2vhigh (2)
vS2,gs
iL1

vhigh
iL2
vlow

-iS1

(a) (b)
iS2 Fig. 4 Equivalent circuit of the proposed converter in buck mode operation (a)
S1 and S3 on (b) S1 and S3 off.

iD2

-iS3
t
T
DT
Fig. 3 Key waveforms of the proposed converter in boost mode operation.

When switch S2 is turned on (Fig. 2(a)), the low voltage


source vlow will charge inductor L1 through the path
C1-L1-D2-S2. The inductor current iL1 increases. In the mean
time, the capacitor C2 delivers the power to inductor L2
through the path C2-L2-S2. The inductor current iL2 increases.
The diode D1 is blocking and switches S1 and S3 are in the off
state. The inductor voltages vL1=vlow and vL2=vC2. When switch
S2 is turned off (Fig. 2(b)), the energy stored in inductor L1 is Fig. 5 Key waveforms of the proposed converter in buck mode operation.
delivered to capacitor C2 through the path C1, L1, anti-parallel
diode of S1 and C2. The inductor voltage vL1=vlow-vC2. The III. ZVS BIDIRECTIONAL DC CONVERTER
inductor current iL1 decreases. The energy stored in inductor L2 In order to reduce the switching losses on S2, an active
is delivered to high voltage side through the path C2, L2, snubber circuit including clamp capacitor Cc, auxiliary Sa and
anti-parallel diode of S3 and vhigh. The inductor voltage resonant inductor Lr can be added in the circuit to create a
vL2=vC2-vhigh. The inductor current iL2 decreases. The diodes D1 resonance. Fig. 6 shows the ZVS bidirectional dc converter
and D2 are blocking when S2 is turned off. Based on the with three kinds of active snubber. Switch S2 and Sa are
voltage-second balance on inductors L1 and L2 respectively, switched in a complementary way with a short delay time.
one can obtain the voltage ratios of the proposed converter in When dc power is transferred from high voltage side to low
the boost mode. voltage side (buck mode), the ZVS bidirectional converter is
vC2=vlow/(1-D), vhigh=vC2/(1-D), vhigh=vlow/(1-D)2 (1) the same operation behavior as shown in Fig. 4. When dc power
When the proposed converter is operated in the buck mode, is transferred from low voltage vlow to high voltage vhigh (boost
the switch S2 is off. The dc power is delivered from high mode), the switches S2 and Sa are turned on at ZVS. In Fig. 6(a),
voltage side to low voltage side by controlling the duty cycle D the clamp capacitor voltage vCc is greater than the low side
of switches S1 and S3 simultaneously. The corresponding voltage vlow. However, the clamp capacitor voltage

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vCc=Dvlow/(1-D) in Figs. 6(b) and 6(c). The operation behaviors currents iL1 and iL2 are almost constant in this mode. This mode
of three kinds of ZVS bidirectional converter shown in Fig. 6 ends at time t2 when the capacitor voltage vCr=vC2. At time t2, the
are almost the same. Therefore, only the operation principle of anti-parallel diode of switch S1 and diode D2 are both on to
circuit configuration shown in Fig. 6(a) is discussed. When commutate the inductor current iL1. The time interval in this
switch S2 is turned off, the positive inductor current iLr will mode is given as:
flow through the anti-parallel diode of the auxiliary switch Sa Cv
and clamp capacitor Cc. Therefore the drain voltage of auxiliary Δt12 = t 2 − t1 ≈ r C2 (3)
i Lr (t1 )
switch vDa,ds is zero. At this instant, the auxiliary switch Sa can
be turned on at ZVS. If the auxiliary switch Sa is turned on, the Mode 3 [t2≤t<t3]: This mode starts at time t2 when the
inductor current iLr decreases from positive to negative value. anti-parallel diode of S1 and diode D2 are both on. The current
When the auxiliary switch Sa is turned off, the negative iS1 decreases from zero and the diode current iD2 decreases. This
inductor current iLr will flow through resonant capacitor Cr. The mode ends at time t3 when the capacitor voltage vCr equals vCc
capacitor Cr is discharged from positive voltage to zero voltage. and the anti-parallel diode of Sa is on.
When the capacitor voltage vCr=0, the anti-parallel diode of the Mode 4 [t3≤t<t4]: This mode starts at time t3 when vCr=vCc and
switch S2 is turned on. Then switch S2 can be turned on at this the anti-parallel diode of Sa is on. Since the anti-parallel diode
instant to achieve ZVS. During one switching period, there are of S1 and diode D2 are on, the inductor voltage vL2 equals zero
eight operation modes of the proposed ZVS converter in boost and the inductor voltage vLr=vC2-vCc<0. Thus the inductor
mode operation. The corresponding equivalent circuits for each current iLr decreases. This mode ends at time t4 when the diode
operation mode are given in Fig. 7. Fig. 8 shows the time current iD2=0 and the anti-parallel diode of S3 is on.
sequence of key waveforms in the boost mode operation. The Mode 5 [t4≤t<t5]: This mode starts at time t4 when the diode
following description explains the detailed operation principle current iD2=0 and the anti-parallel diode of S3 is on. The
of the proposed topology. inductor voltages vL1=vlow-vC2<0 and vL2=vC2-vhigh<0. Thus the
inductor currents iL1 and iL2 decrease. The resonant inductor
voltage vLr=vhigh-vCc<0 so that the inductor current iLr decreases
from positive value to negative value in this mode. Before the
inductor current iLr is negative value, the auxiliary switch Sa
should be turned on to achieve ZVS. This mode ends at time t5
when auxiliary switch Sa is turned off.
Mode 6 [t5≤t<t6]: This mode starts at time t5 when auxiliary
switch Sa is turned off and ends at time t6 when capacitor voltage
vCr=0. The anti-parallel diode of S3 is still on in this mode.
(a)
Since the inductor current iLr is negative, the capacitor Cr is
discharged by iLr. The capacitor voltage vCr decreases from vCc
to zero voltage. The inductor currents iL1 and iL2 decrease. The
capacitor voltage vCr should reach zero before the end of this
mode to ensure ZVS operation of switch S2. To achieve this
condition, the energy stored in the resonant inductor Lr must be
greater than the energy stored in the resonant capacitor Cr. This
mode ends at time t6 when capacitor voltage vCr=0. The
(b) anti-parallel diode of switch S2 is turned on.
Mode 7 [t6≤t<t7]: This mode starts at time t6 when capacitor
voltage vCr=0 and the anti-parallel diode of switch S2 is turned
on. In this mode the anti-parallel diodes of S1 and S3 are still
on. The inductor currents iL1 and iL2 decrease. The inductor
current iLr increases from negative value to positive value.
Before the switch current iS2 is positive, switch S2 should be
turned on to achieve ZVS. This mode ends at time t7 when the
(c) switch current iS3 is zero and diode D2 is on.
Fig. 6 ZVS bidirectional converter (a) with boost type of active snubber (b) and
(c) with buck-boost type of active snubber.
Mode 8 [t7≤t<T+t0]: This mode starts at time t7 when the switch
current iS3 is zero and diode D2 and the anti-parallel diode of S1
Mode 1 [t0≤t<t1]: In this mode, switch S2 is on, auxiliary switch are in the commutation interval. The inductor voltage vL2
Sa is off, and diode D2 is on. The inductor voltages vL1+vLr=vin equals zero. The inductor voltage vLr=vC2 so that the inductor
and vL2+vLr=vC2. Since, Lr<<L1 and L2, the inductor currents current iLr increases. The current iS1 increases to zero and the
iL1 and iL2 increase. The switch currents iS2=iL1+iL2 and iSa=0. diode current iD2 increases. This mode ends at time t0 when the
This mode ends at time t1 when switch S2 is turned off. current iS1 equals zero. Then the operation behavior in one
Mode 2 [t1≤t<t2]: Main switch S2 is turned off at time t1. The switching period is completed.
positive inductor current iLr will charge capacitor Cr from zero
voltage to vC2+vLr≈vC2. The capacitance of Cr is small enough
such that the capacitor Cr is linearly charged. The inductor

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Based on the key waveforms of the proposed converter
shown in Fig. 8, the delay time at modes 2, 3, 6 and 7 during the
transition interval between switches S2 and Sa is neglected in

vhigh
vlow
steady state analysis. In modes 4 and 8, the anti-parallel diode
of S1 and diode D2 are in the commutation interval. The
inductor voltage vL1≈vlow in mode 1 and vL1=vlow-vC2 in modes
(a) (b) 4, 5 and 8. Based on the voltage-second balance on inductor L1,
one can obtain the equation.
vlow(D-DM8)+(vlow-vC2)(1-D+DM8)=0 (4)
where D is the duty cycle of switch S2 and DM8=(T+t0-t7)/T is
the duty cycle loss of the converter in mode 8. Based on (4), the
capacitor voltage vC2 can be expressed as:
vC2=vlow/(1-D+DM8) (5)
(c) (d) The inductor voltage vL2≈vC2 in mode 1 and vL2=vC2-vhigh in
mode 5. Applying the voltage-second balance to inductor L2,
one can obtain the equation.
vC2(D-DM8)+(vC2-vhigh)(1-D-DM4)=0 (6)
vhigh
vlow

where DM4=(t4-t3)/T is the duty cycle loss of the converter in


mode 4. Based on (6), one can derive the high side voltage vhigh
as:
(e) (f) vhigh=vC2(1-DM4-DM8)/(1-D-DM4)
=vlow(1-DM4-DM8)/[(1-D+DM8)(1-D-DM4)] (7)
If DM4=DM8<<D, we can obtain vhigh≈vlow/(1-D)2 and
vC2≈vlow/(1-D). This equation meets voltage equation in the
proposed hard switching bidirectional converter in (1). The
voltage on the inductors L2 and Lr is vL2+vLr=vC2 in modes 1
and 8 and vL2+vLr=vC2-vCc in modes 4 and 5. Based on the
(g) (h) voltage-second balance on the inductors L2 and Lr, one can
Fig. 7 Operation modes of proposed ZVS converter in boost mode operation (a)
mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7 (h)
obtain the following equation.
mode 8. DvC2+(vC2-vCc)(1-D)=0 (8)
T The clamp capacitor voltage can be expressed as:
DT
vS2,gs vCc=vC2/(1-D)=vlow/[(1-D)(1-D+DM8)]≈vlow/(1-D)2 (9)
vSa,gs Therefore, the active snubber circuit shown in Fig. 6(a) is a
vCr=vS2,ds vCc boost type topology.
vSa,ds vCc
B. Design consideration
vCc The average current on input inductor L1 is given as:
iL1 Phigh
i L1, av = (10)
iL2 ηv low
iLr where η is the circuit efficiency and Phigh is the output power at
the high voltage side. Since DM4, DM8<<D, we neglect the duty
iS2 cycle losses in modes 4 and 8 to simplify the circuit design. The
duty cycle of the switch S2 is
iSa v low
D ≈ 1− (11)
v high
-iS1 One can obtain the peak current on input inductor L1.
iD2 Phigh v
i L1,peak = i L1 (t 2 ) ≈ + low DT (12)
-iS3 ηv low 2L1
t
If the ripple currents ΔiL1 and ΔiL2 on inductors L1 and L2 are
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8
t0 t1 t2 t3 t4 t5 t6 t7 T+t0 given, the inductances of L1 and L2 can be expressed as:
Fig. 8 Key waveforms of proposed ZVS converter in boost mode operation. DTv low DTv low
L1 ≥ , L2 ≥ (13)
Δi L1 Δi L 2 (1 - D)
IV. STEADY STATE ANALYSIS AND DESIGN CONSIDERATION
The voltage stresses of power switches S2 and Sa are expressed
OF ZVS BIDIRECTIONAL CONVERTER
as:
A. Steady state analysis v Low
v S2 ,stress = vSa ,stress ≈ (14)
(1 − D) 2

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If we assume! η = 1 ,!the peak current stresses of switches S2 voltage and current waveforms in boost mode operation at rated
and Sa are approximately equal to power. From the measured results, we can see that iL1=iD2-iS1
Phigh and iD2+iL2+iS3=iLr. When switch S2 is turned on, iD2=iL1,
v
i S2, peak ≈ i L1, peak + i L2, peak ≈ [ + low DT] iLr=iS2=iL1+iL2, iS1=0, iS3=0 and iSa=0. The inductor currents iL1
v high (1 − D) 2
2L1 and iL2 increase. When switch S2 is off and auxiliary switch Sa
,
Phigh vlow is on, then -iS1=iL1, iD2=0, iS2=0 and iLr=-iSa=iL2+iS3. The
+[ + DT] inductor currents iL1 and iL2 decrease. The drain voltage
v high (1 − D) 2(1 − D)L 2 vS2,ds=vCc. Fig. 11 gives the measured key current and voltage
Phigh v low waveforms in the buck mode operation at rated power. It can be
i Sa , peak ≈ i L 2, peak ≈ + DT (15) found in Fig. 11 that iL2=-iS3 and i1=-iS1 if switches S1 and S3
v high (1 − D) 2(1 − D)L2
are turned on. When S1 and S3 are turned off, i1=-iD1 and
The average diode and switch currents are expressed as: iL2=iS2.
Phigh DPhigh
i S1, av ≈ , i D 2, av ≈ ,
v high (1 − D) v high (1 − D) 2
vS2,gs
Phigh
i S3,av = (16)
v high
The voltage stresses of diode D2 and switches S1 and S3 are
approximately given as: vS2,ds ZVS
v Dv low
vS1,stress ≈ v C2 ≈ low , v D 2,stress = v high − v C 2 ≈ ,
1- D (1 - D) 2
v low iS2
vS3, stress ≈ v high ≈ (17)
(1 - D) 2
In mode 6, the energy stored in the resonant inductor Lr must be
greater than the energy stored in the resonant capacitor Cr to 1 s
create the ZVS condition for main switch S2, i.e.
(a)
L r ≥ C r v 2Cc /[i Lr ( t 5 )]2 . The delay time td at t1-t3, and t5-t7
respectively is approximately equal to π L r C r / 2 . If the
capacitance of Cr is given, the inductance of Lr is about
4t 2d /(C r π 2 ) . In the design of clamp capacitance, half of the
resonant period in mode 5 is larger than the off time of main
switch S2. Therefore the clamp capacitance Cc can be given as
C c >> (1 − D) 2 T 2 /( π 2 L r ) .

V. EXPERIMENTAL RESULTS
The performance and effectiveness of the proposed ZVS
bidirectional converter shown in Fig. 6(a) are verified by the
experimental results based on a laboratory prototype. The
system parameters of the design circuit are: (1) low side voltage
vlow=36V, (2) high side voltage vhigh=200V, (3) rated power (b)
Fig. 9 Measured results of the gate voltage, drain voltage and switch current at
P=240W, and (4) switching frequency:110kHz. The input and rated output power (a) switch S2 (b) auxiliary switch Sa.
output inductances L1=150μH and L2=210μH. The selected
clamp capacitance Cc is 0.47μF with voltage stress of 400V. VI. CONCLUSION
The capacitances of C1, C2 and C3 are 680μF, 220μF and
The ZVS bidirectional dc converter is presented to have the
470μF, respectively. The IGBT IRG4PC40W with anti-parallel
following features: wide voltage conversion ratio and low
diode MUR860 are used for switching devices S1-S3 and Sa in
switching losses on switches. When power is transferred from
the proposed converter. The adopted diodes are MUR860. The
the high voltage side to the low voltage side, the converter is
adopted resonant capacitor Cr is about 470pF. The selected
operated in buck mode to charge the low voltage side. On the
resonant inductor Lr is 22μH. other hand, the converter is operated in boost mode when power
In the boost mode operation, Fig. 9 shows the measured is delivered from low voltage side to high voltage side. The
waveforms of gate voltage, drain voltage and switch current of boost type and buck-boost type of active snubber are presented
power switches S2 and Sa at rated output power. Before the in the circuit to achieve ZVS turn-on in boost mode operation.
switches are turned on, the switch currents are negative and the The circuit configuration, operation principle and design
drain voltages have been decreased to zero. Therefore, both consideration are demonstrated in detail. Finally the
switches are turned on at ZVS. Fig. 10 gives the measured key

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performance and effectiveness of the proposed converter are for a hybrid electric vehicle, using ultracapacitors and neural networks,”
verified from the experiments based on a laboratory prototype. IEEE Trans. Ind. Electron., vol. 53, no. 2, pp. 614-623, April 2006.
[6]M. E. Ortuzar, J. Moreno, and J. W. Dixon, “Ultracapacitor-Based Auxiliary
Energy System for an Electric Vehicle: Implementation and Evaluation,”
IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 2147-2156, Aug. 2007.
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no. 4, pp. 1094-1104, June 2006.
[8]Y. Kaiwei, Q. Yang, M. Xu, and F. C. Lee, “A novel winding-coupled buck
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[9]J.-H. Park, and B.-H. Cho, “Non-Isolation Soft-Switching Buck Converter
with Tapped-Inductor for Wide-Input Extreme Step-Down Applications”,
IEEE Trans. Circuits Syst. I, Fundamental Theory and Applic., vol.
54, 2007.
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Fig. 10 Measured key waveforms of the proposed ZVS converter in boost mode
operation.

VII. ACKNOWLEDGEMENT
The authors would like to acknowledge the partial financial
support of the National Science Council in Taiwan, Republic of
China, through its grant NSC96-2622-E-224-030-CC3.

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