A B C D E

1 1

QMLE4/5
2
Eureka Discrete 2

LA-8863P REV 0.3 Schematic

3
AMD Trinity APU / Hudson M3 FCH 3

Thames XT & Chelsea PRO

2012-03-13 Rev 0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 1 of 51
A B C D E
 A B C D E

Fan Control GCLK

VGA Thermal Sensor page 5 SLG3NB270VTR page 31
ADM1032ARMZ-2
DP2 X4 AMD APU
HDMI Conn.
page 13 FS1 Processor
page 24
Memory BUS(DDRIII)
1 200pin DDRIII-SO-DIMM X2 1
PCI-Express X16 5GHz Trinity uPGA-722 Dual Channel page 10,11
35mm*35mm
BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333/1600 MT/s
page 5,6,7,8,9

DP0 DP1
LVDS Translator (X2) (X4) PCIe X1 X1 USB/B Right Cardreader
UMI X4 1.1V 5GT/s
AMD GPU RTD2136S 2.5GT/s USB port 0,1 USB port 9
page 31 page 33
page 21
AMD Thames XT, 128bit with 1GB/2GB DDR3 PCIe X1
AMD Chelsea PRO, 128bit with 1GB/2GB DDR3 1.1V 5GT/s
USB3.0 USB 3.0 Int. Camera
5V 5GT/s USB3.0 port 0,1
USB2.0 port 10,11 USB port 5
page 12,13,14,15,16,17,18,19,20 USB page 34 page 22
LVDS Conn.
5V 480MHz
page 22

2 2
USB
5V 480MHz PCIeMini Card
CRT WLAN/BT
page 23

AMD FCH USB port 8

APU PCIe port 1
RTL8105E-VD 10/100M Hudson M3 page 31
RJ45 RTL8111F-VB 1G
page 34
APU PCIe port 0
page 32
SATA port 0 SATA HDD
FCBGA-656 5V 6GHz(600MB/s) SATA port 0
24.5mm*24.5mm page 30

ODD/B
page 30 SATA port 1 SATA ODD
page 25,26,27,28,29 5V 6GHz(600MB/s) SATA port 1
page 30
3 Audio + CR/B SPI Bus 3

page 33 3.3V 33 MHz

LPC Bus HD Audio 3.3V 24MHz

TP/B 3.3V 33 MHz
page 38

HDA Codec
RUSB + Power/B ALC259
page 30 SPI ROM Debug Port ENE KB9012 page 35
page 37 page 36
(4MB)
page 27
RTC CKT.
page 25
Touch Pad Int.KBD SPK Conn JPIO
page 35
page 38 page 37 (HP &page
MIC)35
DC/DC Interface CKT.
page 39

4 4

Power Circuit DC/DC

page 40,41,42,43,44,45
,46,47,48,49
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

Power On/Off CKT. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
page 30 A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 2 of 51
A B C D E
 5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9A DESIGN CURRENT 5A +5VALW
SUSP

N-CHANNEL DESIGN CURRENT 4A +5VS

SI4800

D D

+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191
ODD_PWR
TPS51125A DESIGN CURRENT 1.6A
P-CHANNEL
+5VS_ODD
AO-3413

Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 5A +3VALW

WOL_EN#

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

AO-3413

SYSON
DESIGN CURRENT 0.2A +3V
P-CHANNEL
AO-3413
GPU_PWREN
DESIGN CURRENT 1.65A +1.8VSG
SY8033BDBC
SUSP
C C
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800 LCD_ENVDD

P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

AO-3413

PXS_PWREN
DESIGN CURRENT 0.3A +3VGS
P-CHANNEL
POK AO-3413

Ipeak=5.3A, Imax=3.71A, Iocp min=6.814A DESIGN CURRENT 5.3A +1.1VALW

G5603RU1U
SUSP

N-CHANNEL DESIGN CURRENT 4A +1.1VS

FDS6676AS
VR_ON

Ipeak=54A, Imax=36A, Iocp min=65A DESIGN CURRENT 50A +CPU_CORE

ISL6267HRZ-T Ipeak=27.5A, Imax=22A, Iocp min=35A DESIGN CURRENT 23A
B +CPU_CORE_NB B

VR_ON

Ipeak=6.5A, Imax=4.55A, Iocp min=8.553A DESIGN CURRENT 6.5A +1.2VS

G5603RU1U

SYSON
Ipeak=20A, Imax=11.2A, Iocp min=24.136A DESIGN CURRENT 20A +1.5V
G5603RU1U SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5VS

FDS6676AS
+3V

LDO DESIGN CURRENT 1A +1.05V

APL5930KAI-TRG

SUSP

DESIGN CURRENT 1.5A +0.75VS

G2992F1U

VGA_PWRGD

A N-CHANNEL DESIGN CURRENT 11A +1.5VSG A

FDS6676AS

GPU_PWREN

LDO DESIGN CURRENT 3A +1.0VSG

APL5930KAI
VGACORE_EN Security Classification Compal Secret Data Compal Electronics, Inc.
Ipeak=32.6A, Imax=20.3A, Iocp min=36A DESIGN CURRENT 32.6A +VGA_CORE Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

RT8237CZQW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 3 of 51
5 4 3 2 1
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails
+5VS BTO Option Table
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW +3V Function HDMI SKU
+2.5VS
+1.1VALW +1.05V
power +1.5VS description HDMI SKU
1 plane +VSB 1
+1.2VS UMA
explain PowerXpress COMMON UMA PowerXpress Discrete
+1.1VS
+0.75VS BTO IHDMI@ HDMI@ UMA@ UMA@+VGA@+PXS@ VGA@+DIS@
+CPU_CORE
+CPU_CORE_NB
Function MINI PCI-E SLOT LAN
+VGA_CORE
State
+3VGS description LAN
+1.8VSG
explain 10/100M GIGA
+1.5VSG
+1.0VSG BTO 8105ELDO@ 8105ESWR@ 8111E@

S0 Function Cam & Mic Panel

O O O O O O
description Cam & Mic Panel (DIS@)
S1
O O O O O O
explain Cam & Mic
2 2
S3
O O O O O X BTO CAM@

S5 S4/AC
O O O O X X
Function GPIO for PowerXpress Chipset
S5 S4/ Battery only
O O O X X X description PowerXpress (PXS@) FCH GPU

S5 S4/AC & Battery explain PowerXpress Enable Crossfire Enable Hudson-M3 Whistler Pro
don't exist
O X X X X X
BTO PXSEN@ CROSSEN@ HUDM3R1@ HUDM3R3@ WHPROR1@ WHPROR3@

Function PowerXpress FCH

description PowerXpress FCH

FCH SM Bus Address (SCL0/SDA0)
explain BACO mode Non-BACO Hudson-M2 Hudson-M3
Power Device HEX Address BACO@ NOBACO@ M2@ M3@
BTO
3 3
+3VS DDR SO-DIMM 0 90 H 1001 000xb
+3VS DDR SO-DIMM 1 92 H 1001 001xb
+3VS WLAN

SIGNAL
STATE SLP_S3# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH
Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH
+3VL Smart Battery 16 H 0001 011x b +3VS APU Thermal Sensor 98 H 1001 100x b
S3 (Suspend to RAM) LOW HIGH
+3VL Charger IC 12 H 0001 001x b +3VS GPU Internal Thermal 82 H 1000 001x b
+3VS GPU External Thermal 9A H 1001 101x b S4 (Suspend to Disk) LOW HIGH
EC SM Bus3 Address +3VS GPU External Thermal 9A H 1001 101x b
S5 (Soft OFF) LOW LOW
+3VS LVDS EEPROM A8 H 1010 1000 b
4 4
G3 LOW LOW

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 4 of 51
A B C D E
 A B C D E

<12> PCIE_GTX_C_CRX_P[0..15] PCIE_CTX_C_GRX_P[0..15] <12>

<12> PCIE_GTX_C_CRX_N[0..15] PCIE_CTX_C_GRX_N[0..15] <12>

JAPUA @
1 PCI EXPRESS
1
PCIE_GTX_C_CRX_P0 AB8 AB2 PCIE_CTX_GRX_P0 C1 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P0
PCIE_GTX_C_CRX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_GRX_N0 C2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N0
AB7 P_GFX_RXN0 P_GFX_TXN0 AB1 1 2
PCIE_GTX_C_CRX_P1 AA9 AA3 PCIE_CTX_GRX_P1 C3 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P1
PCIE_GTX_C_CRX_N1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_GRX_N1 C4 0.1U_0402_16V7K PCIE_CTX_C_GRX_N1
AA8 P_GFX_RXN1 P_GFX_TXN1 AA2 1 2
PCIE_GTX_C_CRX_P2 AA5 Y5 PCIE_CTX_GRX_P2 C5 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P2
PCIE_GTX_C_CRX_N2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_GRX_N2 C6 0.1U_0402_16V7K PCIE_CTX_C_GRX_N2
AA6 P_GFX_RXN2 P_GFX_TXN2 Y4 1 2
PCIE_GTX_C_CRX_P3 Y8 Y2 PCIE_CTX_GRX_P3 C7 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P3
PCIE_GTX_C_CRX_N3 P_GFX_RXP3 P_GFX_TXP3 PCIE_CTX_GRX_N3 C8 0.1U_0402_16V7K PCIE_CTX_C_GRX_N3
Y7 P_GFX_RXN3 P_GFX_TXN3 Y1 1 2
PCIE_GTX_C_CRX_P4 W9 W3 PCIE_CTX_GRX_P4 C9 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P4
PCIE_GTX_C_CRX_N4 P_GFX_RXP4 P_GFX_TXP4 PCIE_CTX_GRX_N4 C10 0.1U_0402_16V7K PCIE_CTX_C_GRX_N4
W8 P_GFX_RXN4 P_GFX_TXN4 W2 1 2
PCIE_GTX_C_CRX_P5 W5 V5 PCIE_CTX_GRX_P5 C11 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P5
PCIE_GTX_C_CRX_N5 P_GFX_RXP5 P_GFX_TXP5 PCIE_CTX_GRX_N5 C37 0.1U_0402_16V7K PCIE_CTX_C_GRX_N5
W6 P_GFX_RXN5 P_GFX_TXN5 V4 1 2
PCIE_GTX_C_CRX_P6 V8 V2 PCIE_CTX_GRX_P6 C29 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P6
PCIE_GTX_C_CRX_N6 P_GFX_RXP6 P_GFX_TXP6

GRAPHICS
V7 V1 PCIE_CTX_GRX_N6 C35 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N6
PCIE_GTX_C_CRX_P7 P_GFX_RXN6 P_GFX_TXN6 PCIE_CTX_GRX_P7 C18 0.1U_0402_16V7K PCIE_CTX_C_GRX_P7
U9 P_GFX_RXP7 P_GFX_TXP7 U3 1 2
PCIE_GTX_C_CRX_N7 U8 U2 PCIE_CTX_GRX_N7 C16 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N7
PCIE_GTX_C_CRX_P8 P_GFX_RXN7 P_GFX_TXN7 PCIE_CTX_GRX_P8 C22 0.1U_0402_16V7K PCIE_CTX_C_GRX_P8
U5 P_GFX_RXP8 P_GFX_TXP8 T5 1 2
PCIE_GTX_C_CRX_N8 U6 T4 PCIE_CTX_GRX_N8 C38 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N8
PCIE_GTX_C_CRX_P9 P_GFX_RXN8 P_GFX_TXN8 PCIE_CTX_GRX_P9 C34 0.1U_0402_16V7K PCIE_CTX_C_GRX_P9
T8 P_GFX_RXP9 P_GFX_TXP9 T2 1 2
PCIE_GTX_C_CRX_N9 T7 T1 PCIE_CTX_GRX_N9 C20 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N9
PCIE_GTX_C_CRX_P10 P_GFX_RXN9 P_GFX_TXN9 PCIE_CTX_GRX_P10 C21 0.1U_0402_16V7K PCIE_CTX_C_GRX_P10
R9 P_GFX_RXP10 P_GFX_TXP10 R3 1 2
PCIE_GTX_C_CRX_N10 R8 R2 PCIE_CTX_GRX_N10 C23 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N10
PCIE_GTX_C_CRX_P11 P_GFX_RXN10 P_GFX_TXN10 PCIE_CTX_GRX_P11 C33 0.1U_0402_16V7K PCIE_CTX_C_GRX_P11
R5 P_GFX_RXP11 P_GFX_TXP11 P5 1 2
PCIE_GTX_C_CRX_N11 R6 P4 PCIE_CTX_GRX_N11 C24 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N11
PCIE_GTX_C_CRX_P12 P_GFX_RXN11 P_GFX_TXN11 PCIE_CTX_GRX_P12 C25 0.1U_0402_16V7K PCIE_CTX_C_GRX_P12
P8 P_GFX_RXP12 P_GFX_TXP12 P2 1 2
PCIE_GTX_C_CRX_N12 P7 P1 PCIE_CTX_GRX_N12 C26 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N12
PCIE_GTX_C_CRX_P13 P_GFX_RXN12 P_GFX_TXN12 PCIE_CTX_GRX_P13 C27 0.1U_0402_16V7K PCIE_CTX_C_GRX_P13
N9 P_GFX_RXP13 P_GFX_TXP13 N3 1 2
PCIE_GTX_C_CRX_N13 N8 N2 PCIE_CTX_GRX_N13 C28 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N13
PCIE_GTX_C_CRX_P14 P_GFX_RXN13 P_GFX_TXN13 PCIE_CTX_GRX_P14 C31 0.1U_0402_16V7K PCIE_CTX_C_GRX_P14
N5 P_GFX_RXP14 P_GFX_TXP14 M5 1 2
PCIE_GTX_C_CRX_N14 N6 M4 PCIE_CTX_GRX_N14 C30 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N14
PCIE_GTX_C_CRX_P15 P_GFX_RXN14 P_GFX_TXN14 PCIE_CTX_GRX_P15 C36 0.1U_0402_16V7K PCIE_CTX_C_GRX_P15
M8 P_GFX_RXP15 P_GFX_TXP15 M2 1 2
2 PCIE_GTX_C_CRX_N15 PCIE_CTX_GRX_N15 C32 0.1U_0402_16V7K PCIE_CTX_C_GRX_N15 2
M7 P_GFX_RXN15 P_GFX_TXN15 M1 1 2

PCIE_FRX_C_LANTX_P0 AE5 AD5 PCIE_FTX_LANRX_P0 C50 1 2 0.1U_0402_16V7K

<32> PCIE_FRX_C_LANTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_FTX_C_LANRX_P0 <32>
LAN PCIE_FRX_C_LANTX_N0 AE6 AD4 PCIE_FTX_LANRX_N0 C55 1 2 0.1U_0402_16V7K LAN
<32> PCIE_FRX_C_LANTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_FTX_C_LANRX_N0 <32>
PCIE_FRX_WLANTX_P1 AD8 AD2 PCIE_FTX_WLANRX_P1 C51 1 2 0.1U_0402_16V7K
<31> PCIE_FRX_WLANTX_P1 P_GPP_RXP1 P_GPP_TXP1 PCIE_FTX_C_WLANRX_P1 <31>
WLAN PCIE_FRX_WLANTX_N1 AD7 AD1 PCIE_FTX_WLANRX_N1 C54 1 2 0.1U_0402_16V7K WLAN
<31> PCIE_FRX_WLANTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_FTX_C_WLANRX_N1 <31>
AC9 P_GPP_RXP2 P_GPP_TXP2 AC3

GPP
AC8 P_GPP_RXN2 P_GPP_TXN2 AC2
AC5 P_GPP_RXP3 P_GPP_TXP3 AB5
AC6 P_GPP_RXN3 P_GPP_TXN3 AB4

UMI_MTX_C_FRX_P0 AG8 AG2 UMI_FTX_MRX_P0 C59 1 2 0.1U_0402_16V7K

<25> UMI_MTX_C_FRX_P0 P_UMI_RXP0 P_UMI_TXP0 UMI_FTX_C_MRX_P0 <25>
UMI_MTX_C_FRX_N0 AG9 AG3 UMI_FTX_MRX_N0 C60 1 2 0.1U_0402_16V7K
<25> UMI_MTX_C_FRX_N0 P_UMI_RXN0 P_UMI_TXN0 UMI_FTX_C_MRX_N0 <25>
UMI_MTX_C_FRX_P1 AG6 AF4 UMI_FTX_MRX_P1 C61 1 2 0.1U_0402_16V7K
<25> UMI_MTX_C_FRX_P1 P_UMI_RXP1 P_UMI_TXP1 UMI_FTX_C_MRX_P1 <25>
UMI_MTX_C_FRX_N1 AG5 AF5 UMI_FTX_MRX_N1 C62 1 2 0.1U_0402_16V7K
<25> UMI_MTX_C_FRX_N1 P_UMI_RXN1 P_UMI_TXN1 UMI_FTX_C_MRX_N1 <25>
UMI_MTX_C_FRX_P2 AF7 AF1 UMI_FTX_MRX_P2 C122 1 2 0.1U_0402_16V7K
<25> UMI_MTX_C_FRX_P2 P_UMI_RXP2 P_UMI_TXP2 UMI_FTX_C_MRX_P2 <25>
UMI_MTX_C_FRX_N2 AF8 AF2 UMI_FTX_MRX_N2 C123 1 2 0.1U_0402_16V7K
<25> UMI_MTX_C_FRX_N2 P_UMI_RXN2 P_UMI_TXN2 UMI_FTX_C_MRX_N2 <25>
UMI_MTX_C_FRX_P3 AE8 AE2 UMI_FTX_MRX_P3 C120 1 2 0.1U_0402_16V7K
<25> UMI_MTX_C_FRX_P3 UMI_FTX_C_MRX_P3 <25>
UMI

UMI_MTX_C_FRX_N3 P_UMI_RXP3 P_UMI_TXP3 UMI_FTX_MRX_N3 C121 0.1U_0402_16V7K

<25> UMI_MTX_C_FRX_N3 AE9 P_UMI_RXN3 P_UMI_TXN3 AE3 1 2 UMI_FTX_C_MRX_N3 <25>

+1.2VS 1 2 P_ZVDDP AG11 P_ZVDDP P_ZVSS AH11 P_ZVSS 1 2

R1 196_0402_1% R2 196_0402_1%

LOTES_ACA-ZIF-109-P12-A_FS1R2

3 3

FAN Control Circuit

+5VS JFAN @
1A +FAN 1 1
2 2
2 2 3 3
C13 C15
10U_0603_6.3V6M 1000P_0402_50V7K 4
@ GND
5 GND
U2 1 1
1 8 ACES_85204-0300N
EN GND
2 VIN GND 7
+FAN 3 6 R59 10K_0402_5%
VOUT GND
<36> EN_DFAN1 4 VSET GND 5 2 1 +3VS
10mil 1
C17 APL5607KI-TRG_SO8
FAN_SPEED1 <36>
1
10U_0603_6.3V6M C14
2 0.01U_0402_25V7K
4 @ 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019IT A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 23, 2012 Sheet 5 of 51
A B C D E
 A B C D E

<10> DDR_A_DQS[0..7] <11> DDR_B_DQS[0..7]

<10> DDR_A_DQS#[0..7] <11> DDR_B_DQS#[0..7]

1 1

JAPUB JAPUC
MEMORY CHANNEL A MEMORY CHANNEL B
<10> DDR_A_MA[0..15] DDR_A_D[0..63] <10> <11> DDR_B_MA[0..15] DDR_B_D[0..63] <11>
DDR_A_MA0 U20 E13 DDR_A_D0 DDR_B_MA0 T27 A14 DDR_B_D0
DDR_A_MA1 MA_ADD0 MA_DATA0 DDR_A_D1 DDR_B_MA1 MB_ADD0 MB_DATA0 DDR_B_D1
R20 MA_ADD1 MA_DATA1 J13 P24 MB_ADD1 MB_DATA1 B14
DDR_A_MA2 R21 H15 DDR_A_D2 DDR_B_MA2 P25 D16 DDR_B_D2
DDR_A_MA3 MA_ADD2 MA_DATA2 DDR_A_D3 DDR_B_MA3 MB_ADD2 MB_DATA2 DDR_B_D3
P22 MA_ADD3 MA_DATA3 J15 N27 MB_ADD3 MB_DATA3 E16
DDR_A_MA4 P21 H13 DDR_A_D4 DDR_B_MA4 N26 B13 DDR_B_D4
DDR_A_MA5 MA_ADD4 MA_DATA4 DDR_A_D5 DDR_B_MA5 MB_ADD4 MB_DATA4 DDR_B_D5
N24 MA_ADD5 MA_DATA5 F13 M28 MB_ADD5 MB_DATA5 C13
DDR_A_MA6 N23 F15 DDR_A_D6 DDR_B_MA6 M27 B16 DDR_B_D6
DDR_A_MA7 MA_ADD6 MA_DATA6 DDR_A_D7 DDR_B_MA7 MB_ADD6 MB_DATA6 DDR_B_D7
N20 MA_ADD7 MA_DATA7 E15 M24 MB_ADD7 MB_DATA7 A16
DDR_A_MA8 N21 DDR_B_MA8 M25
DDR_A_MA9 MA_ADD8 DDR_A_D8 DDR_B_MA9 MB_ADD8 DDR_B_D8
M21 MA_ADD9 MA_DATA8 H17 L26 MB_ADD9 MB_DATA8 C17
DDR_A_MA10 U23 F17 DDR_A_D9 DDR_B_MA10 U26 B18 DDR_B_D9
DDR_A_MA11 MA_ADD10 MA_DATA9 DDR_A_D10 DDR_B_MA11 MB_ADD10 MB_DATA9 DDR_B_D10
M22 MA_ADD11 MA_DATA10 E19 L27 MB_ADD11 MB_DATA10 B20
DDR_A_MA12 L24 J19 DDR_A_D11 DDR_B_MA12 K27 A20 DDR_B_D11
DDR_A_MA13 MA_ADD12 MA_DATA11 DDR_A_D12 DDR_B_MA13 MB_ADD12 MB_DATA11 DDR_B_D12
AA25 MA_ADD13 MA_DATA12 G16 W26 MB_ADD13 MB_DATA12 E17
DDR_A_MA14 L21 H16 DDR_A_D13 DDR_B_MA14 K25 B17 DDR_B_D13
DDR_A_MA15 MA_ADD14 MA_DATA13 DDR_A_D14 DDR_B_MA15 MB_ADD14 MB_DATA13 DDR_B_D14
L20 MA_ADD15 MA_DATA14 H19 K24 MB_ADD15 MB_DATA14 B19
F19 DDR_A_D15 C19 DDR_B_D15
DDR_A_BS0 MA_DATA15 DDR_B_BS0 MB_DATA15
<10> DDR_A_BS0 U24 MA_BANK0 <11> DDR_B_BS0 U27 MB_BANK0
DDR_A_BS1 U21 H20 DDR_A_D16 DDR_B_BS1 T28 C21 DDR_B_D16
<10> DDR_A_BS1 MA_BANK1 MA_DATA16 <11> DDR_B_BS1 MB_BANK1 MB_DATA16
DDR_A_BS2 L23 F21 DDR_A_D17 DDR_B_BS2 K28 B22 DDR_B_D17
<10> DDR_A_BS2 MA_BANK2 MA_DATA17 <11> DDR_B_BS2 MB_BANK2 MB_DATA17
J23 DDR_A_D18 C23 DDR_B_D18
<10> DDR_A_DM[0..7] MA_DATA18 <11> DDR_B_DM[0..7] MB_DATA18
DDR_A_DM0 E14 H23 DDR_A_D19 DDR_B_DM0 D14 A24 DDR_B_D19
DDR_A_DM1 MA_DM0 MA_DATA19 DDR_A_D20 DDR_B_DM1 MB_DM0 MB_DATA19 DDR_B_D20
J17 MA_DM1 MA_DATA20 G20 A18 MB_DM1 MB_DATA20 D20
DDR_A_DM2 E21 E20 DDR_A_D21 DDR_B_DM2 A22 B21 DDR_B_D21
DDR_A_DM3 MA_DM2 MA_DATA21 DDR_A_D22 DDR_B_DM3 MB_DM2 MB_DATA21 DDR_B_D22
F25 MA_DM3 MA_DATA22 G22 C25 MB_DM3 MB_DATA22 E23
DDR_A_DM4 AD27 H22 DDR_A_D23 DDR_B_DM4 AF25 B23 DDR_B_D23
DDR_A_DM5 MA_DM4 MA_DATA23 DDR_B_DM5 MB_DM4 MB_DATA23
AC23 MA_DM5 AG22 MB_DM5
2 DDR_A_DM6 DDR_A_D24 DDR_B_DM6 DDR_B_D24 2
AD19 MA_DM6 MA_DATA24 G24 AH18 MB_DM6 MB_DATA24 E24
DDR_A_DM7 AC15 E25 DDR_A_D25 DDR_B_DM7 AD14 B25 DDR_B_D25
MA_DM7 MA_DATA25 DDR_A_D26 MB_DM7 MB_DATA25 DDR_B_D26
MA_DATA26 G27 MB_DATA26 B27
DDR_A_DQS0 G14 G26 DDR_A_D27 DDR_B_DQS0 C15 D28 DDR_B_D27
DDR_A_DQS#0 MA_DQS_H0 MA_DATA27 DDR_A_D28 DDR_B_DQS#0 MB_DQS_H0 MB_DATA27 DDR_B_D28
H14 MA_DQS_L0 MA_DATA28 F23 B15 MB_DQS_L0 MB_DATA28 B24
DDR_A_DQS1 G18 H24 DDR_A_D29 DDR_B_DQS1 E18 D24 DDR_B_D29
DDR_A_DQS#1 MA_DQS_H1 MA_DATA29 DDR_A_D30 DDR_B_DQS#1 MB_DQS_H1 MB_DATA29 DDR_B_D30
H18 MA_DQS_L1 MA_DATA30 E28 D18 MB_DQS_L1 MB_DATA30 D26
DDR_A_DQS2 J21 F27 DDR_A_D31 DDR_B_DQS2 E22 C27 DDR_B_D31
DDR_A_DQS#2 MA_DQS_H2 MA_DATA31 DDR_B_DQS#2 MB_DQS_H2 MB_DATA31
H21 MA_DQS_L2 D22 MB_DQS_L2
DDR_A_DQS3 E27 AB28 DDR_A_D32 DDR_B_DQS3 B26 AG26 DDR_B_D32
DDR_A_DQS#3 MA_DQS_H3 MA_DATA32 MB_DQS_H3 MB_DATA32
E26 MA_DQS_L3 MA_DATA33 AC27 DDR_A_D33 DDR_B_DQS#3 A26 MB_DQS_L3 MB_DATA33 AH26 DDR_B_D33
DDR_A_DQS4 AE26 AD25 DDR_A_D34 DDR_B_DQS4 AG24 AF23 DDR_B_D34
DDR_A_DQS#4 MA_DQS_H4 MA_DATA34 MB_DQS_H4 MB_DATA34
AD26 MA_DQS_L4 MA_DATA35 AA24 DDR_A_D35 DDR_B_DQS#4 AG25 MB_DQS_L4 MB_DATA35 AG23 DDR_B_D35
DDR_A_DQS5 AB22 AE28 DDR_A_D36 DDR_B_DQS5 AG21 AG27 DDR_B_D36
DDR_A_DQS#5 MA_DQS_H5 MA_DATA36 MB_DQS_H5 MB_DATA36
AA22 MA_DQS_L5 MA_DATA37 AD28 DDR_A_D37 DDR_B_DQS#5 AF21 MB_DQS_L5 MB_DATA37 AF27 DDR_B_D37
DDR_A_DQS6 AB18 AB26 DDR_A_D38 DDR_B_DQS6 AG17 AH24 DDR_B_D38
DDR_A_DQS#6 MA_DQS_H6 MA_DATA38 MB_DQS_H6 MB_DATA38
AA18 MA_DQS_L6 MA_DATA39 AC25 DDR_A_D39 DDR_B_DQS#6 AG18 MB_DQS_L6 MB_DATA39 AE24 DDR_B_D39
DDR_A_DQS7 AA14 DDR_B_DQS7 AH14
DDR_A_DQS#7 MA_DQS_H7 MB_DQS_H7
AA15 MA_DQS_L7 MA_DATA40 Y23 DDR_A_D40 DDR_B_DQS#7 AG14 MB_DQS_L7 MB_DATA40 AE22 DDR_B_D40
MA_DATA41 AA23 DDR_A_D41 MB_DATA41 AH22 DDR_B_D41
DDR_A_CLK0 T21 Y21 DDR_A_D42 DDR_B_CLK0 R26 AE20 DDR_B_D42
<10> DDR_A_CLK0 MA_CLK_H0 MA_DATA42 <11> DDR_B_CLK0 MB_CLK_H0 MB_DATA42
DDR_A_CLK0# T22 AA20 DDR_A_D43 DDR_B_CLK0# R27 AH20 DDR_B_D43
<10> DDR_A_CLK0# MA_CLK_L0 MA_DATA43 <11> DDR_B_CLK0# MB_CLK_L0 MB_DATA43
DDR_A_CLK1 R23 AB24 DDR_A_D44 DDR_B_CLK1 P27 AD23 DDR_B_D44
<10> DDR_A_CLK1 MA_CLK_H1 MA_DATA44 <11> DDR_B_CLK1 MB_CLK_H1 MB_DATA44
DDR_A_CLK1# R24 AD24 DDR_A_D45 DDR_B_CLK1# P28 AD22 DDR_B_D45
<10> DDR_A_CLK1# MA_CLK_L1 MA_DATA45 <11> DDR_B_CLK1# MB_CLK_L1 MB_DATA45
MA_DATA46 AA21 DDR_A_D46 MB_DATA46 AD21 DDR_B_D46
DDR_A_CKE0 H28 AC21 DDR_A_D47 DDR_B_CKE0 J26 AD20 DDR_B_D47
<10> DDR_A_CKE0 MA_CKE0 MA_DATA47 <11> DDR_B_CKE0 MB_CKE0 MB_DATA47
DDR_A_CKE1 H27 DDR_B_CKE1 J27
<10> DDR_A_CKE1 MA_CKE1 <11> DDR_B_CKE1 MB_CKE1
MA_DATA48 AA19 DDR_A_D48 MB_DATA48 AF19 DDR_B_D48
DDR_A_ODT0 Y25 AC19 DDR_A_D49 DDR_B_ODT0 W27 AE18 DDR_B_D49
<10> DDR_A_ODT0 MA_ODT0 MA_DATA49 <11> DDR_B_ODT0 MB_ODT0 MB_DATA49
DDR_A_ODT1 AA27 AC17 DDR_A_D50 DDR_B_ODT1 Y28 AE16 DDR_B_D50
<10> DDR_A_ODT1 MA_ODT1 MA_DATA50 <11> DDR_B_ODT1 MB_ODT1 MB_DATA50
MA_DATA51 AA17 DDR_A_D51 MB_DATA51 AH16 DDR_B_D51
DDR_A_SCS0# V22 AB20 DDR_A_D52 DDR_B_SCS0# V25 AG20 DDR_B_D52
3 <10> DDR_A_SCS0# MA_CS_L0 MA_DATA52 <11> DDR_B_SCS0# MB_CS_L0 MB_DATA52 3
DDR_A_SCS1# AA26 Y19 DDR_A_D53 DDR_B_SCS1# Y27 AG19 DDR_B_D53
<10> DDR_A_SCS1# MA_CS_L1 MA_DATA53 <11> DDR_B_SCS1# MB_CS_L1 MB_DATA53
MA_DATA54 AD18 DDR_A_D54 MB_DATA54 AF17 DDR_B_D54
DDR_A_RAS# V21 AD17 DDR_A_D55 DDR_B_RAS# V24 AD16 DDR_B_D55
<10> DDR_A_RAS# MA_RAS_L MA_DATA55 <11> DDR_B_RAS# MB_RAS_L MB_DATA55
DDR_A_CAS# W24 DDR_B_CAS# V27
<10> DDR_A_CAS# MA_CAS_L <11> DDR_B_CAS# MB_CAS_L
DDR_A_WE# W23 AA16 DDR_A_D56 DDR_B_WE# V28 AG15 DDR_B_D56
<10> DDR_A_WE# MA_WE_L MA_DATA56 <11> DDR_B_WE# MB_WE_L MB_DATA56
MA_DATA57 Y15 DDR_A_D57 MB_DATA57 AD15 DDR_B_D57
MEM_MA_RST# H25 AA13 DDR_A_D58 MEM_MB_RST# J25 AG13 DDR_B_D58
<10> MEM_MA_RST# MA_RESET_L MA_DATA58 <11> MEM_MB_RST# MB_RESET_L MB_DATA58
MEM_MA_EVENT#T24 AC13 DDR_A_D59 MEM_MB_EVENT#T25 AD13 DDR_B_D59
<10> MEM_MA_EVENT# MA_EVENT_L MA_DATA59 <11> MEM_MB_EVENT# MB_EVENT_L MB_DATA59
15mil MA_DATA60 Y17 DDR_A_D60 MB_DATA60 AG16 DDR_B_D60
+MEM_VREF W20 AB16 DDR_A_D61 AF15 DDR_B_D61
M_VREF MA_DATA61 MB_DATA61
MA_DATA62 AB14 DDR_A_D62 MB_DATA62 AE14 DDR_B_D62
+1.5V 1 2 M_ZVDDIO W21 M_ZVDDIO MA_DATA63 Y13 DDR_A_D63 MB_DATA63 AF13 DDR_B_D63
R60 39.2_0402_1%

LOTES_ACA-ZIF-109-P12-A_FS1R2 @
LOTES_ACA-ZIF-109-P12-A_FS1R2 @

EVENT# pull high 0.75V Reference Voltage +1.5V

2

+1.5V
4 R64 4
1K_0402_1%

R15
15mil
1 2 1K_0402_5% MEM_MA_EVENT#
1

+MEM_VREF
R61 1 2 1K_0402_5% MEM_MB_EVENT#
2

1 2
R65 C124 C125
1K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
1000P_0402_50V7K 0.1U_0402_16V7K 2011/11/28 2013/12/31 Title
2 1 Issued Date Deciphered Date
SCHEMATIC,MB LA-8863
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 6 of 51
A B C D E
 A B C D E

Close to APU JAPUD

ANALOG/DISPLAY/MISC
C56 1 2 0.1U_0402_16V7K DP0_TXP0 L3 D1 DP0_AUXP C47 1 2 0.1U_0402_16V7K
<21> DP0_TXP0_C DP0_TXP0 DP0_AUXP DP0_AUXP_C <21>
C48 1 2 0.1U_0402_16V7K DP0_TXN0 L2 D2 DP0_AUXN C49 1 2 0.1U_0402_16V7K LVDS DP0_AUXP R25 2 1 1.8K_0402_5%
<21> DP0_TXN0_C DP0_TXN0 DP0_AUXN DP0_AUXN_C <21>
LVDS C58 DP0_TXP1 DP1_AUXP DP0_AUXN
<21> DP0_TXP1_C 1 2 0.1U_0402_16V7K K5 DP0_TXP1 DP1_AUXP E1 C57 1 2 0.1U_0402_16V7K ML_VGA_AUXP <27>
R58 2 1 1.8K_0402_5%
C53 1 2 0.1U_0402_16V7K DP0_TXN1 K4 E2 DP1_AUXN C52 1 2 0.1U_0402_16V7K CRT (To FCH)
<21> DP0_TXN1_C DP0_TXN1 DP1_AUXN ML_VGA_AUXN <27>
DP1_AUXP R10 2 1 1.8K_0402_5%
K2 D5 UMA_HDMI_CLK
DP0_TXP2 DP2_AUXP UMA_HDMI_CLK <24>
K1 D6 UMA_HDMI_DATA HDMI DP1_AUXN R11 2 1 1.8K_0402_5%
DP0_TXN2 DP2_AUXN UMA_HDMI_DATA <24>

DISPLAY PORT 0
J3 E5 LVDS_HPD R74 2 1 100K_0402_5%
DP0_TXP3 DP3_AUXP
J2 DP0_TXN3 DP3_AUXN E6
FCH_CRT_HPD R75 2 1 100K_0402_5%
C63 1 2 0.1U_0402_16V7K DP1_TXP0 H5 F5
1 <27> ML_VGA_TXP0 DP1_TXP0 DP4_AUXP 1
C64 1 2 0.1U_0402_16V7K DP1_TXN0 H4 F6 HDMI_HPD R95 2 1 100K_0402_5%
<27> ML_VGA_TXN0 DP1_TXN0 DP4_AUXN

DISPLAY PORT MISC.

C65 1 2 0.1U_0402_16V7K DP1_TXP1 H2 G5
<27> ML_VGA_TXP1 DP1_TXP1 DP5_AUXP
C66 1 2 0.1U_0402_16V7K DP1_TXN1 H1 G6
<27> ML_VGA_TXN1 DP1_TXN1 DP5_AUXN
CRT C67 DP1_TXP2 LVDS_HPD
<27> ML_VGA_TXP2 1 2 0.1U_0402_16V7K G3 DP1_TXP2 DP0_HPD D3 LVDS_HPD <21>
(To FCH) <27> ML_VGA_TXN2
C68 1 2 0.1U_0402_16V7K DP1_TXN2 G2 E3 FCH_CRT_HPD
FCH_CRT_HPD <27>
DP1_TXN2 DP1_HPD HDMI_HPD +1.5V

DISPLAY PORT 1
DP2_HPD D7 HDMI_HPD <24> 3.3V Tolerance
C69 1 2 0.1U_0402_16V7K DP1_TXP3 F2 E7
<27> ML_VGA_TXP3 DP1_TXP3 DP3_HPD
C70 1 2 0.1U_0402_16V7K DP1_TXN3 F1 F7
<27> ML_VGA_TXN3 DP1_TXN3 DP4_HPD
G7 APU_SVT_R R36 2 @ 1 1K_0402_5%
UMA_HDMI_TX2+ DP5_HPD
<24> UMA_HDMI_TX2+ L9 DP2_TXP0
<24> UMA_HDMI_TX2- UMA_HDMI_TX2- L8 C6 APU_SVC_R R39 2 @ 1 1K_0402_5%
DP2_TXN0 DP_BLON
DP_DIGON B6
<24> UMA_HDMI_TX1+ UMA_HDMI_TX1+ L5 A6 DP_INT_PWM APU_SVD_R R41 2 @ 1 1K_0402_5%
DP2_TXP1 DP_VARY_BL DP_INT_PWM <9>
<24> UMA_HDMI_TX1- UMA_HDMI_TX1- L6 DP2_TXN1 DP_AUX_ZVSS APU_SIC R42
HDMI DP_AUX_ZVSS C1 1 2 2 1 1K_0402_5%
<24> UMA_HDMI_TX0+ UMA_HDMI_TX0+ K8 R16 150_0402_1%
UMA_HDMI_TX0- DP2_TXP2 APU_SID R44
<24> UMA_HDMI_TX0- K7 DP2_TXN2 TEST6 AD12 2 1 1K_0402_5%

DISPLAY PORT 2
TEST9 M18 T5
<24> UMA_HDMI_TXC+ UMA_HDMI_TXC+ J6 N18 T6 APU_ALERT# R46 2 1 1K_0402_5%
UMA_HDMI_TXC- DP2_TXP3 TEST10
<24> UMA_HDMI_TXC- J5 DP2_TXN3 TEST14 F11 T1
G11 T2 DMA_ACTIVE# R48 2 1 1K_0402_5%
APU_CLKP TEST15
<25> APU_CLKP AE11 CLKIN_H TEST16 H11 T3
100MHz (SS) APU_CLKN AD11 J11 T4
<25> APU_CLKN CLKIN_L TEST17 +1.5VS
F12 APU_TEST18 R18 1 2 1K_0402_5%

CLK
APU_DISP_CLKP AB11 TEST18
<25> APU_DISP_CLKP DISP_CLKIN_H TEST19 G12 APU_TEST19 R19 1 2 1K_0402_5%
100MHz (NSS) APU_DISP_CLKN AA11 J12 APU_TEST20 R21 1 2 1K_0402_5%
<25> APU_DISP_CLKN DISP_CLKIN_L TEST20

TEST
TEST24 H12 APU_TEST24 R22 1 2 1K_0402_5% DMA_ACTIVE# R57 2 @ 1 1K_0402_5%
R31 1 @ 2 0_0402_5% APU_SVC_R B3 AE10 TEST25_H R23 1 2 510_0402_1%
<47> APU_SVC SVC TEST25_H
R32 1 @ 2 0_0402_5% APU_SVD_R A3 AD10 TEST25_L R24 1 2 510_0402_1% +1.2VS APU_RST# R52 2 1 300_0402_5%
<47> APU_SVD SVD TEST25_L
TEST28_H L10 T7
2 R33 @ APU_SVT_R APU_PWRGD 2
1 2 0_0402_5% C3 M10 R54 2 1 300_0402_5%

SER.
<47> APU_SVT SVT TEST28_L T8
TEST30_H P19
APU_SIC AG12 R19
<9> APU_SIC SIC TEST30_L
APU_SID AH12 K22 APU_TEST31 R27 1 2 39.2_0402_1% @
<9> APU_SID SID TEST31
T19 APU_RST# 1 2
APU_RST# TEST32_H C126 1000P_0402_50V7K
<25> APU_RST# AF10 RESET_L TEST32_L N19 Change TEST35 to pull-high
APU_PWRGD AB12 AA12 APU_TEST35 R28 1 2 300_0402_5% +1.5V @
<25,47> APU_PWRGD PWROK TEST35 R29 @ 300_0402_5% for HDMI issue APU_PWRGD
1 2 1 2

CTRL
APU_PROCHOT# AC10 W10 FS1R2 R30 1 2 10K_0402_5% +3VALW C127 1000P_0402_50V7K
APU_THERMTRIP# AE12 PROCHOT_L FS1R2
THERMTRIP_L DMAACTIVE_L AC12 DMA_ACTIVE# DMA_ACTIVE# <25>
APU_ALERT# AF12
<27> APU_ALERT# ALERT_L
TEST4 P18 T11
APU_TDI H10 R18 T12
APU_TDO TDI TEST5
J10 TDO
APU_TCK F10 +3VS
APU_TMS TCK JTAG
G10 TMS
APU_TRST# F9 Y10
APU_DBRDY TRST_L RSVD1 UMA_HDMI_CLK R66
G9 DBRDY RSVD2 AA10 2 1 4.7K_0402_5%
RSVD
APU_DBREQ# H9 Y12
DBREQ_L RSVD3 UMA_HDMI_DATA R67
RSVD4 K21 2 1 4.7K_0402_5%
R212 1 2 0_0402_5% VSS_SENSE B4
<47> APU_VDD_RUN_FB_L VSS_SENSE
T9 C5 VDDP_SENSE Aux signal are re-configured as I2C signals for DDC
R214 1 2 0_0402_5% VDDNB_SENSE A4
<47> APU_VDDNB_SEN VDDNB_SENSE APU AUX pin are 3.3V tolerant
SENSE

T10 A5 VDDIO_SENSE
R215 1 2 0_0402_5% VDD_SENSE C4
<47> APU_VDD_SEN VDD_SENSE
T13 B5 VDDR_SENSE
LOTES_ACA-ZIF-109-P12-A_FS1R2 @

+1.5V

3 3

2
R55
1K_0402_5%
HDT Debug conn Asserted as an input to force the
processor into the HTC-active state

1
+1.5V
Close to JHDT
APU_PROCHOT# 1 @ 2
<25> APU_PROCHOT# H_PROCHOT# <36,47>
R97 1 2 1K_0402_5% APU_TDI R136 0_0402_5%

R100 1 2 1K_0402_5% APU_TCK +1.5V

JHDT @
R110 1 2 1K_0402_5% APU_TMS 1 2 APU_TCK
1 2
R116 1 2 1K_0402_5% APU_TRST# 3 4 APU_TMS
3 4 +1.5V
R117 1 2 1K_0402_5% APU_DBREQ# 5 6 APU_TDI
5 6
Close to APU side, Debug Stuff
7 8 APU_TDO
7 8

1
APU_TRST# 1 @ 2 9 10 APU_PWRGD_RR 1 @ 2 APU_PWRGD R68 R69
R121 0_0402_5% 9 10 R125 0_0402_5% 1K_0402_5% 10K_0402_5%
1 @ 2 11 12 APU_RST#_R 1 @ 2 APU_RST#
R122 10K_0402_5% 11 12 R127 0_0402_5% Thermal Shutdown Temperature:

2 2
1 @ 2 13 14 APU_DBRDY
13 14 115 degree

B
R123 10K_0402_5%
1 @ 2 15 16 APU_DBREQ# Q5
15 16

E
R124 10K_0402_5% APU_THERMTRIP# 3 1 H_THERMTRIP# <26>

C
4 @ APU_TEST19 4
17 17 18 18 1 2
R118 0_0402_5% MMBT3904_NL_SOT23-3
19 20 1 @ 2 APU_TEST18
19 20 R119 0_0402_5%

SAMTE_ASP-136446-07-B
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019IT A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 23, 2012 Sheet 7 of 51
A B C D E
 A B C D E

JAPUF
J20 VSS_1 VSS_73 A19
L4 VSS_2 VSS_74 A21
R7 VSS_3 VSS_75 A23
W18 VSS_4 VSS_76 A25
A15 VSS_5 VSS_77 A7
AB17 VSS_6 VSS_78 AA4
AC22 VSS_7 VSS_79 AA7
+APU_CORE JAPUE +APU_CORE AE21 AB13
VSS_8 VSS_80
AF24 VSS_9 VSS_81 AB15
F8 VDD_1 VDD_32 R11 AH23 VSS_10 VSS_82 AB19
1 1
H6 VDD_2 VDD_33 T10 AH25 VSS_11 VSS_83 AB21
J1 VDD_3 VDD_34 H8 B7 VSS_12 VSS_84 AB23
J14 VDD_4 VDD_35 G1 C14 VSS_13 VSS_85 AB25
P6 VDD_5 VDD_36 U11 C16 VSS_14 VSS_86 AB27
P10 VDD_6 VDD_37 W11 C2 VSS_15 VSS_87 AB9
J16 VDD_7 VDD_38 W13 Co-layout with C100 on PVT C20 VSS_16 VSS_88 AC14
J18 VDD_8 VDD_39 W15 C22 VSS_17 VSS_89 AC16
J9 VDD_9 VDD_40 W17 C24 VSS_18 VSS_90 AC18
K19 W19 +1.5V C26 AC20
VDD_10 VDD_41 VSS_19 VSS_91
K3 VDD_11 VDD_42 AB3 C28 VSS_20 VSS_92 AC24
K17 VDD_12 VDD_43 AD3 D13 VSS_21 VSS_93 AC26
M3 VDD_13 VDD_44 AD6 1 D15 VSS_22 VSS_94 AC28
K6 VDD_14 VDD_45 AE1 D17 VSS_23 VSS_95 AC4
V10 L1 + C147 D19 AC7
VDD_15 VDD_46 330U_D2_2V_Y VSS_24 VSS_96
V18 VDD_16 VDD_47 Y6 D23 VSS_25 VSS_97 AD9
V3 M6 D25 AE13
F3
VDD_17 50A VDD_48
N11
2
D27
VSS_26 VSS_98
AE15
VDD_18 VDD_49 VSS_27 VSS_99
L18 VDD_19 VDD_50 N1 E4 VSS_28 VSS_100 AE17
V6 VDD_20 VDD_51 T3 E9 VSS_29 VSS_101 M9
W1 VDD_21 VDD_52 T6 F14 VSS_30 VSS_102 N10
T18 VDD_22 VDD_53 U19 F16 VSS_31 VSS_103 N4
Y14 U1 +1.5V F18 N7
VDD_23 VDD_54 VSS_32 VSS_104
AA1 VDD_24 VDD_55 Y16 F20 VSS_33 VSS_105 R10
AB6 Y18 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C130 F22 R4
VDD_25 VDD_56 VSS_34 VSS_106
AC1 VDD_26 VDD_57 Y3 F26 VSS_35 VSS_107 T11

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J
R1 VDD_27 VDD_58 D4 1 F28 VSS_36 VSS_108 T9
P3 F4 C85 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G13 U10
VDD_28 VDD_59 + C100 VSS_37 VSS_109
K10 VDD_29 VDD_60 AF6 G15 VSS_38 VSS_110 U18
H3 AF3 330U_2.5V_M_R17 G17 U4
VDD_30 VDD_61 @ VSS_39 VSS_111
M19 VDD_31 VDD_62 L11 G19 VSS_40 VSS_112 U7
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
G21 VSS_41 VSS_113 V11
2
H=4.2mm G23 VSS_42 VSS_114 AE19
2
+APU_CORE_NB C8 VDDNB_1 VDDNB_13 C11 +APU_CORE_NB G25 VSS_43 VSS_115 AE23
D10 VDDNB_2 VDDNB_14 C12 G4 VSS_44 VSS_116 AE25
B8 VDDNB_3 VDDNB_15 D9 J22 VSS_45 VSS_117 AE27
B12 VDDNB_4 VDDNB_16 D8 J24 VSS_46 VSS_118 AE4
C9 VDDNB_5 VDDNB_17 D12 J4 VSS_47 VSS_119 AE7
A9 D11 J7 AF14
A10
VDDNB_6 33A VDDNB_18
B11 K11
VSS_48 VSS_120
AF16
VDDNB_7 VDDNB_19 VSS_49 VSS_121
A8 VDDNB_8 VDDNB_20 A12 K14 VSS_50 VSS_122 AF18
A11 VDDNB_9 VDDNB_21 B10 K9 VSS_51 VSS_123 AF20
E10 VDDNB_10 VDDNB_22 E12 AC11 VSS_52 VSS_124 AF22
E11 VDDNB_11 VDDNB_23 B9 L19 VSS_53 VSS_125 AF26
C10 +1.5V L7 AF28
VDDNB_12 +VDDNB_CAP C119 C141 VSS_54 VSS_126
VDDNB_CAP_1 K13 M11 VSS_55 VSS_127 AF9
K12 C103 C104 C131 AF11 AG4
VDDNB_CAP_2 VSS_56 VSS_128

22U_0805_6.3V6M

22U_0805_6.3V6M

180P_0402_50V8J
V19 VSS_57 VSS_129 AG7

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J
1 1 1 If the VSS plane is cut to V9 VSS_58 VSS_130 AH13
C117 1 1 1 1 W16 AH15
+1.5V H26 T23 +1.5V C102 create a VDDIO plane, W4
VSS_59 VSS_131
AH17
VDDIO_1 VDDIO_19 VSS_60 VSS_132
K20 VDDIO_2 VDDIO_20 T26
2 2 2
place across the VDDIO W7 VSS_61 VSS_133 AH19
J28 U22 Y11 AH21
K23
VDDIO_3 VDDIO_21
U25
2 2 2 2 and VSS plane split Y20
VSS_62 VSS_134
P9
VDDIO_4 VDDIO_22 VSS_63 VSS_135
K26 VDDIO_5 VDDIO_23 U28 Y22 VSS_64 VSS_136 C18
L22 VDDIO_6 VDDIO_24 Y26 Y9 VSS_65 VSS_137 D21
L25 VDDIO_7 VDDIO_25 T20 A17 VSS_66 VSS_138 W14
L28 VDDIO_8 VDDIO_26 R28 A13 VSS_67 VSS_139 P11
M20 VDDIO_9 VDDIO_27 R25 K16 VSS_68 VSS_140 C7
M23 VDDIO_10 VDDIO_28 R22 F24 VSS_69 VSS_141 E8
M26
N22
VDDIO_11 3.2A VDDIO_29 V20
V23
G8
H7
VSS_70 VSS_142 K18
W12
VDDIO_12 VDDIO_30 VSS_71 VSS_143
N25 VDDIO_13 VDDIO_31 V26 J8 VSS_72
N28 VDDIO_14 VDDIO_32 W22
P20 W25 LOTES_ACA-ZIF-109-P12-A_FS1R2
3 VDDIO_15 VDDIO_33 @ 3
P23 VDDIO_16 VDDIO_34 W28
P26 Y24 +1.2VS
VDDIO_17 VDDIO_35
AA28 VDDIO_18 VDDIO_36 G28 VDDR Decoupling

+1.2VS AH6 AG10 C110 C111 C115 C116 C77 C78 C79
VDDP_1 VDDR_1
AH5 VDDP_2 VDDR_2 AH8
180P_0402_50V8J

180P_0402_50V8J

1000P_0402_50V7K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AH4
AH3
VDDP_3 5A 3.5AVDDR_3 AH9
AH10 C109 1 1 1 1 1 1 1 1
VDDP_4 VDDR_4
AH7 VDDP_5
AB10 VDDA 0.75A 2 2 2 2 2 2 2 2

LOTES_ACA-ZIF-109-P12-A_FS1R2
@
Demo Board Capacitor
+1.2VS APU_CORE CORE_NB CORE_NB_CAP VDDIO_SUS
VDDP Decoupling 22uF x 10 22uF x 2 22uF x 2 (CPU side)
C72 C73 C74 C146 C145 C143 C144 C75
0.22uF x 2 10uF x 1 180pF x 1 22uF x 4
+2.5VS 0.01uF x 3 0.22uF x 2 4.7uF x 4
22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

180P_0402_50V8J

180P_0402_50V8J

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

1000P_0402_50V7K

L1
40mil 180pF x 2 180pF x 3 0.22uF x 6 +2(split)
1 2 C170 C164 +VDDA C76 1 1 1 1 1 1 1 1 1 180pF x 1 + 2(split)
FBMA-L11-201209-300LMA30T @
4.7U_0603_6.3V6K

0.22U_0402_6.3V6K

3300P_0402_50V7K

1 1
1

C165 2 2 2 2 2 2 2 2 2
4
VDDP VDDR VDDA VDDIO_SUS 4
0.22uF x 2 0.22uF x 2 4.7uF x 1 (DIMM x2)
2

2 2
180pF x 2 1nF x 1 0.22uF x 1 100uF x 2
180pF x 2 3.3nF x 1 0.1uF x 12

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019IT A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 23, 2012 Sheet 8 of 51
A B C D E
 5 4 3 2 1

SB-TSI

CPU TSI interface level shift

D BSH111, the Vgs is: D
min = 0.4V
@
C935 1 Max = 1.3V
2 0.1U_0402_16V4Z

+3VS 1 R535 2 1 R536 2 When APU High -> MOS OFF (Vgs < 0.4V )
APU Low -> MOS ON (Vgs > 1.3V)
31.6K_0402_1% 30K_0402_1%

Vg = 1.607 V
2
G Q14

APU_SID 3 1 EC_SMB_DA2
<7> APU_SID EC_SMB_DA2 <13,36>
S

D
BSH111_SOT23-3
2
G

Q15

APU_SIC 3 1 EC_SMB_CK2
<7> APU_SIC EC_SMB_CK2 <13,36>
S

BSH111_SOT23-3

C C

Panel PWM +3VS

1

R92 R93
47K_0402_5% 4.7K_0402_5%
2

B B
APU_INVT_PWM <21>

D
1

Q26
2
G 2N7002_SOT23-3
S
3
1

C
1 2 2 Q21
<7> DP_INT_PWM
R89 2.2K_0402_5% B MMBT3904_NL_SOT23-3
E
3
1

R76
4.7K_0402_5%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title
SCHEMATIC,MB LA-8863
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 9 of 51
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

1
JDDR3H
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4 4
6
DDR_A_D4
DDR_A_D5
Standard Type DDR_A_DQS[0..7] <6>

DQ0 DQ5 DDR_A_DQS#[0..7] <6>

DDR_A_D1 7 8
DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10 DDR_A_D[0..63] <6>
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS5 VSS6 14 DDR_A_MA[0..15] <6>
DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18 DDR_A_DM[0..7] <6>
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
D
23 DQ9 DQ13 24 D
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 MEM_MA_RST#
29 DQS1 RESET# 30 MEM_MA_RST# <6>
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 DDR_A_D20 +1.5V
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21
43 VSS15 VSS16 44

1
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2 R79
47 DQS2 VSS17 48
49 50 DDR_A_D22 1K_0402_1%
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54

2
DQ19 VSS19 DDR_A_D28 +VREF_DQA
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DQ24 DQ29

1
DDR_A_D25 59 60
DQ25 VSS21 DDR_A_DQS#3 @ 1 R81
61 VSS22 DQS#3 62 1 1
DDR_A_DM3 63 64 DDR_A_DQS3 C71 C156 C157 1K_0402_1%
DM3 DQS3
65 VSS23 VSS24 66

1000P_0402_50V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K
DDR_A_D26 67 68 DDR_A_D30

2
DDR_A_D27 DQ26 DQ30 DDR_A_D31 2 2 2
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDR_A_CKE0 73 74 DDR_A_CKE1
<6> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <6>
75 VDD1 VDD2 76
C 77 78 DDR_A_MA15 C
DDR_A_BS2 NC1 A15 DDR_A_MA14
<6> DDR_A_BS2 79 BA2 A14 80 Close to JDDR3H.1
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100 Co-layout with C218 on PVT
DDR_A_CLK0 101 102 DDR_A_CLK1
<6> DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 <6>
DDR_A_CLK0# 103 104 DDR_A_CLK1#
<6> DDR_A_CLK0# CK0# CK1# DDR_A_CLK1# <6> +1.5V
105 VDD11 VDD12 106
DDR_A_MA10 DDR_A_BS1 +1.5V
107 A10/AP BA1 108 DDR_A_BS1 <6>
DDR_A_BS0 109 110 DDR_A_RAS#
<6> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <6>
111 VDD13 VDD14 112 1

1
DDR_A_WE# 113 114 DDR_A_SCS0#
<6> DDR_A_WE# WE# S0# DDR_A_SCS0# <6> + C148
DDR_A_CAS# 115 116 DDR_A_ODT0 R80
<6> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <6>
117 118 1K_0402_1% 330U_D2_2V_Y
DDR_A_MA13 VDD15 VDD16 DDR_A_ODT1
119 A13 ODT1 120 DDR_A_ODT1 <6>
DDR_A_SCS1# 2
121 122

2
<6> DDR_A_SCS1# S1# NC2
123 VDD17 VDD18 124
125 126 +VREF_CAA
NCTEST VREF_CA
127 VSS27 VSS28 128
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37 1 1 @ 1
DQ33 DQ37 C101 C162 C161 R82
133 VSS29 VSS30 134
DDR_A_DQS#4 135 136 DDR_A_DM4 1K_0402_1%
B DQS#4 DM4 B
1000P_0402_50V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K

DDR_A_DQS4 137 138 Layout Note:

DQS4 VSS31 DDR_A_D38 2 2 2
139 140
2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 Place near JDDR3H
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44
145 VSS34 DQ44 146
DDR_A_D40 147 148 DDR_A_D45 +1.5V
DDR_A_D41 DQ40 DQ45 @
149 DQ41 VSS35 150
DDR_A_DQS#5 C218 1
Layout Note:
2 330U_6.3V_M_R15

+
151 VSS36 DQS#5 152
DDR_A_DM5 153 DM5 DQS5 154 DDR_A_DQS5 Place near JDDR3H.203 and 204
DDR_A_D42
155 VSS37 VSS38 156
DDR_A_D46
Close to JDDR3H.126 C166 1
157 DQ42 DQ46 158 2 0.1U_0402_16V4Z
DDR_A_D43 159 160 DDR_A_D47
DQ43 DQ47 C168 1
161 VSS39 VSS40 162 2 0.1U_0402_16V4Z
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53 C171 1 +0.75VS +1.5V
165 DQ49 DQ53 166 2 0.1U_0402_16V4Z
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6 C174 1 2 0.1U_0402_16V4Z @
DDR_A_DQS6 DQS#6 DM6 C114 1
171 DQS6 VSS43 172 2 0.1U_0402_16V4Z
173 174 DDR_A_D54 C173 1 2 0.1U_0402_16V4Z
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 C176 1 2 0.1U_0402_16V4Z
DQ51 VSS45 DDR_A_D60 C84
179 VSS46 DQ60 180 1 2 4.7U_0603_6.3V6K
DDR_A_D56 181 182 DDR_A_D61 C179 1 2 0.1U_0402_16V4Z
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 C178 1 2 0.1U_0402_16V4Z C186 1 2 0.1U_0402_16V4Z
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 190 C185 1 2 0.1U_0402_16V4Z C205 1 2 0.1U_0402_16V4Z
DDR_A_D58 VSS49 VSS50 DDR_A_D62
191 DQ58 DQ62 192
DDR_A_D59 193 194 DDR_A_D63 C180 1 2 0.1U_0402_16V4Z
R90 1 DQ59 DQ63
A 2 195 VSS51 VSS52 196 A
10K_0402_5% 197 198 MEM_MA_EVENT#
SA0 EVENT# MEM_MA_EVENT# <6>
199 200 FCH_SDATA0
+3VS VDDSPD SDA FCH_SDATA0 <11,26,31>
FCH_SCLK0
2.2U_0603_6.3V6K

0.1U_0402_16V4Z

201 SA1 SCL 202 FCH_SCLK0 <11,26,31>

1 1 +0.75VS 203 VTT1 VTT2 204 +0.75VS
1

C182
C181 @ 205 206
@ R91 G1 G2 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 10K_0402_5% LCN_DAN06-K4806-0102
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title
@
SCHEMATIC,MB LA-8863
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 10 of 51
5 4 3 2 1
 A B C D E

+1.5V +1.5V

1
JDDR3L
2
DDR3 SO-DIMM B DDR_B_DQS#[0..7] <6>
+VREF_DQB VREF_DQ VSS1
3 4 DDR_B_D4
DDR_B_D0
DDR_B_D1
5
7
VSS2
DQ0
DQ4
DQ5 6
8
DDR_B_D5 Standard Type DDR_B_DQS[0..7] <6>

DQ1 VSS3 DDR_B_D[0..63] <6>

9 10 DDR_B_DQS#0
DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0
11 DM0 DQS0 12 DDR_B_MA[0..15] <6>
13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6 DDR_B_DM[0..7] <6>
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
1
23 DQ9 DQ13 24 1
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 MEM_MB_RST#
29 DQS1 RESET# 30 MEM_MB_RST# <6>
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
+1.5V
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48

1
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23 R83
51 DQ18 DQ23 52
DDR_B_D19 53 54 1K_0402_1%
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29

2
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3 +VREF_DQB
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66

1
DDR_B_D26 67 68 DDR_B_D30 1 1 @ 1
DDR_B_D27 DQ26 DQ30 DDR_B_D31 C112 C184 C183 R84
69 DQ27 DQ31 70
71 72 1K_0402_1%
VSS25 VSS26

1000P_0402_50V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K
2 2 2

2
DDR_B_CKE0 73 74 DDR_B_CKE1
<6> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <6>
75 VDD1 VDD2 76
2 77 78 DDR_B_MA15 2
DDR_B_BS2 NC1 A15 DDR_B_MA14
<6> DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86 Close to JDDR3L.1
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_B_CLK0 101 102 DDR_B_CLK1
<6> DDR_B_CLK0 CK0 CK1 DDR_B_CLK1 <6>
DDR_B_CLK0# 103 104 DDR_B_CLK1#
<6> DDR_B_CLK0# CK0# CK1# DDR_B_CLK1# <6>
105 VDD11 VDD12 106
DDR_B_MA10 DDR_B_BS1 +1.5V
107 A10/AP BA1 108 DDR_B_BS1 <6>
DDR_B_BS0 109 110 DDR_B_RAS#
<6> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <6>
111 VDD13 VDD14 112

1
DDR_B_WE# 113 114 DDR_B_SCS0#
<6> DDR_B_WE# WE# S0# DDR_B_SCS0# <6>
DDR_B_CAS# 115 116 DDR_B_ODT0 R86
<6> DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 <6>
117 118 1K_0402_1%
DDR_B_MA13 VDD15 VDD16 DDR_B_ODT1
119 A13 ODT1 120 DDR_B_ODT1 <6>
DDR_B_SCS1# 121 122

2
<6> DDR_B_SCS1# S1# NC2
123 VDD17 VDD18 124
125 126 +VREF_CAB
NCTEST VREF_CA
127 VSS27 VSS28 128
DDR_B_D37 129 130 DDR_B_D32
DQ32 DQ36

1
DDR_B_D36 131 132 DDR_B_D33 1 1 @ 1
DQ33 DQ37 C113 C188 C187 R94
133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 DDR_B_DM4 1K_0402_1%
3 DQS#4 DM4 3
1000P_0402_50V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K

DDR_B_DQS4 137 138 Layout Note:

DQS4 VSS31 DDR_B_D38 2 2 2
139 140

2
DDR_B_D34 VSS32 DQ38 DDR_B_D39 Place near JDDR3L
141 DQ34 DQ39 142
DDR_B_D35 143 144
DQ35 VSS33 DDR_B_D44
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45 +1.5V
DDR_B_D41 DQ40 DQ45 @
149 DQ41 VSS35 150
DDR_B_DQS#5 C189 1
Layout Note:
2 330U_B2_2.5VM_R15M

+
151 VSS36 DQS#5 152
DDR_B_DM5 153 DM5 DQS5 154 DDR_B_DQS5 Place near JDDRL.203 and 204
DDR_B_D42
155 VSS37 VSS38 156
DDR_B_D46
Close to JDDR3L.126 C167 1
157 DQ42 DQ46 158 2 0.1U_0402_16V4Z
DDR_B_D43 159 160 DDR_B_D47
DQ43 DQ47 C169 1
161 VSS39 VSS40 162 2 0.1U_0402_16V4Z
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53 C172 1 +0.75VS +1.5V
165 DQ49 DQ53 166 2 0.1U_0402_16V4Z
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6 C175 1 2 0.1U_0402_16V4Z @
DDR_B_DQS6 DQS#6 DM6 C118 1
171 DQS6 VSS43 172 2 0.1U_0402_16V4Z
173 174 DDR_B_D50 C195 1 2 0.1U_0402_16V4Z
DDR_B_D54 VSS44 DQ54 DDR_B_D51
175 DQ50 DQ55 176
DDR_B_D55 177 178 C177 1 2 0.1U_0402_16V4Z
DQ51 VSS45 DDR_B_D60 C142 1
179 VSS46 DQ60 180 2 4.7U_0603_6.3V6K
DDR_B_D56 181 182 DDR_B_D61 C190 1 2 0.1U_0402_16V4Z
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_B_DQS#7 C191 1 2 0.1U_0402_16V4Z C194 1 2 0.1U_0402_16V4Z
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
189 190 C192 1 2 0.1U_0402_16V4Z C206 1 2 0.1U_0402_16V4Z
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 DQ58 DQ62 192
DDR_B_D59 193 194 DDR_B_D63 C193 1 2 0.1U_0402_16V4Z
R98 1 DQ59 DQ63
4 2 195 VSS51 VSS52 196 4
10K_0402_5% 197 198 MEM_MB_EVENT#
SA0 EVENT# MEM_MB_EVENT# <6>
199 200 FCH_SDATA0
+3VS VDDSPD SDA FCH_SDATA0 <10,26,31>
201 202 FCH_SCLK0
SA1 SCL FCH_SCLK0 <10,26,31>
2.2U_0603_6.3V6K
1 1 +0.75VS 203 204 +0.75VS
VTT1 VTT2
2

R99 205 206

C207 C208 10K_0402_5% G1 G2 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 LCN_DAN06-K4406-0102
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title
0.1U_0402_16V4Z @
SCHEMATIC,MB LA-8863
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Change SODIMM1 SMbus address Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
to A2(SA0=1, SA1=0) on DVT Date: Friday, March 23, 2012 Sheet 11 of 51
A B C D E
 A B C D E

PCIE_CTX_C_GRX_P[0..15] PCIE_GTX_C_CRX_P[0..15]
<5> PCIE_CTX_C_GRX_P[0..15] PCIE_GTX_C_CRX_P[0..15] <5>
UV1A
PCIE_CTX_C_GRX_N[0..15] PCIE_GTX_C_CRX_N[0..15]
<5> PCIE_CTX_C_GRX_N[0..15] PCIE_GTX_C_CRX_N[0..15] <5>

Close to UV1
LVDS Interface
1 PCIE_CTX_C_GRX_P0 1
AA38 PCIE_RX0P PCIE_TX0P Y33 PCIE_GTX_CRX_P0 0.1U_0402_16V7K 2 1 CV73 PCIE_GTX_C_CRX_P0 UV1G
PCIE_CTX_C_GRX_N0 Y37 Y32 PCIE_GTX_CRX_N0 0.1U_0402_16V7K 2 1 CV74 PCIE_GTX_C_CRX_N0
PCIE_RX0N PCIE_TX0N

PCIE_CTX_C_GRX_P1 Y35 W33 PCIE_GTX_CRX_P1 0.1U_0402_16V7K 2 1 CV71 PCIE_GTX_C_CRX_P1 LVDS CONTROL AK27
PCIE_CTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P VARY_BL
W36 PCIE_RX1N PCIE_TX1N W32 PCIE_GTX_CRX_N1 0.1U_0402_16V7K 2 1 CV72 PCIE_GTX_C_CRX_N1
DIGON AJ27

PCIE_CTX_C_GRX_P2 W38 U33 PCIE_GTX_CRX_P2 0.1U_0402_16V7K 2 1 CV69 PCIE_GTX_C_CRX_P2

PCIE_CTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P
V37 PCIE_RX2N PCIE_TX2N U32 PCIE_GTX_CRX_N2 0.1U_0402_16V7K 2 1 CV70 PCIE_GTX_C_CRX_N2
TXCLK_UP_DPF3P AK35
TXCLK_UN_DPF3N AL36
PCIE_CTX_C_GRX_P3 V35 U30 PCIE_GTX_CRX_P3 0.1U_0402_16V7K 2 1 CV67 PCIE_GTX_C_CRX_P3
PCIE_CTX_C_GRX_N3 PCIE_RX3P PCIE_TX3P
U36 PCIE_RX3N PCIE_TX3N U29 PCIE_GTX_CRX_N3 0.1U_0402_16V7K 2 1 CV68 PCIE_GTX_C_CRX_N3
TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37

PCIE_CTX_C_GRX_P4 U38 T33 PCIE_GTX_CRX_P4 0.1U_0402_16V7K 2 1 CV65 PCIE_GTX_C_CRX_P4 AH35

PCIE_CTX_C_GRX_N4 PCIE_RX4P PCIE_TX4P PCIE_GTX_CRX_N4 0.1U_0402_16V7K PCIE_GTX_C_CRX_N4 TXOUT_U1P_DPF1P
T37 PCIE_RX4N PCIE_TX4N T32 2 1 CV66 TXOUT_U1N_DPF1N AJ36

PCI EXPRESS INTERFACE

TXOUT_U2P_DPF0P AG38
PCIE_CTX_C_GRX_P5 T35 T30 PCIE_GTX_CRX_P5 0.1U_0402_16V7K 2 1 CV63 PCIE_GTX_C_CRX_P5 AH37
PCIE_CTX_C_GRX_N5 PCIE_RX5P PCIE_TX5P PCIE_GTX_CRX_N5 0.1U_0402_16V7K TXOUT_U2N_DPF0N
R36 PCIE_RX5N PCIE_TX5N T29 2 1 CV64 PCIE_GTX_C_CRX_N5
TXOUT_U3P AF35
TXOUT_U3N AG36
PCIE_CTX_C_GRX_P6 R38 P33 PCIE_GTX_CRX_P6 0.1U_0402_16V7K 2 1 CV61 PCIE_GTX_C_CRX_P6
PCIE_CTX_C_GRX_N6 PCIE_RX6P PCIE_TX6P
P37 PCIE_RX6N PCIE_TX6N P32 PCIE_GTX_CRX_N6 0.1U_0402_16V7K 2 1 CV62 PCIE_GTX_C_CRX_N6
LVTMDP

PCIE_CTX_C_GRX_P7 P35 P30 PCIE_GTX_CRX_P7 0.1U_0402_16V7K 2 1 CV59 PCIE_GTX_C_CRX_P7 AP34

PCIE_CTX_C_GRX_N7 PCIE_RX7P PCIE_TX7P TXCLK_LP_DPE3P
N36 PCIE_RX7N PCIE_TX7N P29 PCIE_GTX_CRX_N7 0.1U_0402_16V7K 2 1 CV60 PCIE_GTX_C_CRX_N7
TXCLK_LN_DPE3N AR34

TXOUT_L0P_DPE2P AW37
2 PCIE_CTX_C_GRX_P8 2
N38 PCIE_RX8P PCIE_TX8P N33 PCIE_GTX_CRX_P8 0.1U_0402_16V7K 2 1 CV57 PCIE_GTX_C_CRX_P8
TXOUT_L0N_DPE2N AU35
PCIE_CTX_C_GRX_N8 M37 N32 PCIE_GTX_CRX_N8 0.1U_0402_16V7K 2 1 CV58 PCIE_GTX_C_CRX_N8
PCIE_RX8N PCIE_TX8N
TXOUT_L1P_DPE1P AR37
TXOUT_L1N_DPE1N AU39
PCIE_CTX_C_GRX_P9 M35 N30 PCIE_GTX_CRX_P9 0.1U_0402_16V7K 2 1 CV55 PCIE_GTX_C_CRX_P9
PCIE_CTX_C_GRX_N9 PCIE_RX9P PCIE_TX9P
L36 PCIE_RX9N PCIE_TX9N N29 PCIE_GTX_CRX_N9 0.1U_0402_16V7K 2 1 CV56 PCIE_GTX_C_CRX_N9
TXOUT_L2P_DPE0P AP35
TXOUT_L2N_DPE0N AR35

PCIE_CTX_C_GRX_P10 L38 L33 PCIE_GTX_CRX_P10 0.1U_0402_16V7K 2 1 CV53 PCIE_GTX_C_CRX_P10 AN36

PCIE_CTX_C_GRX_N10 PCIE_RX10P PCIE_TX10P PCIE_GTX_CRX_N10 0.1U_0402_16V7K TXOUT_L3P
K37 PCIE_RX10N PCIE_TX10N L32 2 1 CV54 PCIE_GTX_C_CRX_N10
TXOUT_L3N AP37

PCIE_CTX_C_GRX_P11 K35 L30 PCIE_GTX_CRX_P11 0.1U_0402_16V7K 2 1 CV51 PCIE_GTX_C_CRX_P11

PCIE_CTX_C_GRX_N11 PCIE_RX11P PCIE_TX11P PCIE_GTX_CRX_N11 0.1U_0402_16V7K PCIE_GTX_C_CRX_N11
J36 PCIE_RX11N PCIE_TX11N L29 2 1 CV52

THAMES XT M2 TH@
PCIE_CTX_C_GRX_P12 J38 K33 PCIE_GTX_CRX_P12 0.1U_0402_16V7K 2 1 CV49 PCIE_GTX_C_CRX_P12
PCIE_CTX_C_GRX_N12 PCIE_RX12P PCIE_TX12P
H37 PCIE_RX12N PCIE_TX12N K32 PCIE_GTX_CRX_N12 0.1U_0402_16V7K 2 1 CV50 PCIE_GTX_C_CRX_N12

PCIE_CTX_C_GRX_P13 H35 J33 PCIE_GTX_CRX_P13 0.1U_0402_16V7K 2 1 CV47 PCIE_GTX_C_CRX_P13

PCIE_CTX_C_GRX_N13 PCIE_RX13P PCIE_TX13P PCIE_GTX_CRX_N13 0.1U_0402_16V7K
G36 PCIE_RX13N PCIE_TX13N J32 2 1 CV48 PCIE_GTX_C_CRX_N13

PCIE_CTX_C_GRX_P14 G38 K30 PCIE_GTX_CRX_P14 0.1U_0402_16V7K 2 1 CV45 PCIE_GTX_C_CRX_P14

PCIE_CTX_C_GRX_N14 PCIE_RX14P PCIE_TX14P
F37 PCIE_RX14N PCIE_TX14N K29 PCIE_GTX_CRX_N14 0.1U_0402_16V7K 2 1 CV46 PCIE_GTX_C_CRX_N14

PCIE_CTX_C_GRX_P15 F35 H33 PCIE_GTX_CRX_P15 0.1U_0402_16V7K 2 1 CV43 PCIE_GTX_C_CRX_P15

PCIE_CTX_C_GRX_N15 PCIE_RX15P PCIE_TX15P
E37 PCIE_RX15N PCIE_TX15N H32 PCIE_GTX_CRX_N15 0.1U_0402_16V7K 2 1 CV44 PCIE_GTX_C_CRX_N15

3
CLOCK Chelsea Only 3

CLK_PCIE_VGA AB35 1 CH@ 2 +1.0VGS

<25> CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AA36 RV198 1.69K_0402_1%
<25> CLK_PCIE_VGA# PCIE_REFCLKN

CALIBRATION Thames Only

Y30 1.27K_0402_1% 1 TH@ 2 RV63
PCIE_CALRP
1 2 AH16 Y29 2K_0402_1% 1 TH@ 2 RV65 +1.0VGS
RV64 1K_0402_5% PWRGOOD PCIE_CALRN
Install 2K for Thames/Seymour
GPU_RST# AA30
<25> GPU_RST# PERSTB
2

RV65
RV436 1K_0402_1%
100K_0402_5% THAMES XT M2 THR3@ CH@
Need to modify P/N
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 12 of 51
A B C D E
 A B C D E

UV1B

TXCAP_DPA3P AU24
TXCAM_DPA3N AV23

TX0P_DPA2P AT25
MUTI GFX AR24
DPA TX0M_DPA2N

TX1P_DPA1P AU26
TX1M_DPA1N AV25

AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27

AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26
AP8 DVPCNTL_0
AW8 DVPCNTL_1 TXCBP_DPB3P AR30
AR3 DVPCNTL_2 TXCBM_DPB3N AT29
1 1
AR1 DVPCLK
VRAM_ID0 AU1 AV31
<20> VRAM_ID0 DVPDATA_0 TX3P_DPB2P
VRAM_ID1 AU3 AU30
<20> VRAM_ID1 DVPDATA_1 DPB TX3M_DPB2N
VRAM_ID2 AW3
<20> VRAM_ID2 DVPDATA_2
AP6 DVPDATA_3 TX4P_DPB1P AR32
AW5 DVPDATA_4 TX4M_DPB1N AT31
AU5 DVPDATA_5
AR6 DVPDATA_6 TX5P_DPB0P AT33
AW6 DVPDATA_7 TX5M_DPB0N AU32
AU6 DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13
AN7 DVPDATA_11
AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 DVPDATA_13 TX0M_DPC2N AR14
AR10 DVPDATA_14
AW10 DPC AU16
DVPDATA_15 TX1P_DPC1P
AU10 DVPDATA_16 TX1M_DPC1N AV15
AP10 DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16
AR12 DVPDATA_20
AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 DVPDATA_22 TXCDM_DPD3N AT19
AP12 DVPDATA_23
TX3P_DPD2P AT21
AJ21 SWAPLOCKA TX3M_DPD2N AR20
AK21 SWAPLOCKB DPD AU22
TX4P_DPD1P
TX4M_DPD1N AV21
I2C AT23
TX5P_DPD0P
TX5M_DPD0N AR22
AK26 SCL
AJ26 SDA

R AD39 VGA_CRT_R <23>

GENERAL PURPOSE I/O AD37
GPU_GPIO0 RB
AH20 GPIO_0
AH18GPU_GPIO1 AE36 VGA_CRT_G <23>
GPU_GPIO2 GPIO_1 G
AN16 GPIO_2 GB AD35 Not Share via for other GND
@ DV1 VGA_SMB_DA2_R
AH23
2 STRAPS RB751V40_SC76-2 VGA_SMB_CK2_R
AJ23
GPIO_3_SMBDATA
GPIO_4_SMBCLK B AF37 VGA_CRT_B <23>
2
1 2 AH17AC_BATT AE38 Reserved test pad of CRT Signals for debug
<36,41> ACIN GPIO_5_AC_BATT DAC1 BB
AJ17VDDCI_VID Transmitter Power Saving Enable
<45> VDDCI_VID R02 GPIO_6
+3VGS AK17 AC36 VGA_CRT_HSYNC <23> TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode
GPU_GPIO8 GPIO_7_BLON HSYNC
AJ13 GPIO_8_ROMSO VSYNC AC38 VGA_CRT_VSYNC <23> 1: full Tx output swing (Default setting for Desktop)
AH15GPU_GPIO9
10K_0402_5% 1 RV75 GPU_GPIO0 GPU_GPIO10 GPIO_9_ROMSI +1.8VGS
2 AJ16 GPIO_10_ROMSCK PCI Express Transmitter De-emphasis Enable
10K_0402_5% 1 2 RV76 GPU_GPIO1 T772AK16GPU_GPIO11 AB34 RV84 1 2 499_0402_1% TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode
10K_0402_5% 1 @ RV77 GPU_GPIO2 GPU_GPIO12 GPIO_11 RSET
2 <49> GPU_VID1 1 CH@ 2 AL16 GPIO_12 10mil 65mA 1: Tx de-emphasis enabled (Defailt setting for desktop)
RV13 0_0402_5% GPU_GPIO13
AM16 AD34 +AVDDGPU (1.8V@65mA AVDD) 1 2
GPIO_13 AVDD LV12
AM14 GPIO_14_HPD2 AVSSQ AE34

10U_0603_6.3V6M
CV75

CV76

CV77
0.1U_0402_16V7K

1U_0402_6.3V6K
100K_0402_5% 1 @ RV78 AC_BATT GPU_VID3 100mA BLM15BD121SN1D_0402
2 <49> GPU_VID3
1 CH@ 2 GPIO_16
AM13
AK14
GPIO_15_PWRCNTL_0
AC33 +VDD1DI
10mil
(1.8V@100mA VDD1DI)1 2 1 1 1
<49> GPU_VID2 GPIO_16 VDD1DI +1.8VGS
RV14 0_0402_5% THM_ALERT# AG30 AC34 LV13
GPIO_17_THERMAL_INT VSS1DI

10U_0603_6.3V6M
CV78

CV79

CV80
0.1U_0402_16V7K

1U_0402_6.3V6K
10K_0402_5% 1 @ 2 RV79 GPU_GPIO8 AN14 BLM15BD121SN1D_0402
10K_0402_5% 1 @ RV80 GPU_GPIO9 RV89 CH@ 10K_0402_5% GPIO_18_HPD3
2 1 2 AM17 GPIO_19_CTF 1 1 1
GPU_VID4 AL13 AC30 2 2 2
<49> GPU_VID4 GPIO_20_PWRCNTL_1 R2/NC
10K_0402_5% 1 2 RV81GPU_GPIO11 GPIO21_BBEN AJ14 AC31
10K_0402_5% 1 @ RV82GPU_GPIO12 T781 GPIO22_ROMCSB AK13 GPIO_21_BB_EN R2B/NC
2
10K_0402_5% 1 @ 2 RV83GPU_GPIO13
<26> PEG_CLKREQ#
T782 PEG_CLKREQ# AN13
GPIO24_TRSTB AM23
GPIO_22_ROMCSB
GPIO_23_CLKREQB G2/NC AD30
AD31 PS_1 <20>
2 2 2 +3VGS
Internal VGA Thermal Sensor
10K_0402_5% 1 @ RV96PEG_CLKREQ# GPIO25_TDI JTAG_TRSTB G2B/NC
2 AN23 JTAG_TDI
GPIO26_TCK AK23 AF30 RV9 1 @ 2+DPLL_PVDD
GPIO27_TMS JTAG_TCK B2/NC @ 0_0402_5% +3VGS
AL24 JTAG_TMS B2B/NC AF31 1 2

1
T791 GPIO28_TDO AM24 RV10 0_0402_5%
JTAG_TDO RV90 RV91
AJ19 GENERICA
AK19 AC32 10K_0402_5% 10K_0402_5%
GENERICB C/NC
AJ20 GENERICC Y/NC AD32

2
+3VGS AK20 AF32

2
GENERICD COMP/NC
AJ24 GENERICE_HPD4
10K_0402_5% 1 @ 2 RV85 GPIO24_TRSTB AH26 DAC2 VGA_SMB_CK2_R 1 TH@ 2VGA_SMB_CK2 1 6
GENERICF_HPD5 EC_SMB_CK2 <9,36>
10K_0402_5% 1 @ 2 RV86 GPIO25_TDI AH24 AD29 GENLK_CLK RV15 0_0402_5%
GENERICG_HPD6 H2SYNC/GENLK_CLK GENLK_CLK <20>

5
10K_0402_5% 1 @ 2 RV87 GPIO27_TMS AC29 GENLK_VSYNC
V2SYNC/GENLK_VSYNC GENLK_VSYNC <20> QV15A
10K_0402_5% 1 @ 2 RV88 GPIO26_TCK AK24 VGA_SMB_DA2_R 1 TH@ 2VGA_SMB_DA2 2N7002KDWH_SOT363-6 4 3
HPD1 EC_SMB_DA2 <9,36>
AG31 PS_2 <20> RV16 0_0402_5%
VDD2DI/NC
VSS2DI/NC AG32 QV15B
0.60 V level, Please 2N7002KDWH_SOT363-6
VREFG Divider ans A2VDD/NC AG33
+1.8VGS
cap close to ASIC 15mil AD33 PS_3 <20>
3 +1.8VGS +VREFG_GPU AH13 A2VDDQ/NC 3
2 RV93 1 499_0402_1% VREFG
(Thames 75mA) A2VSSQ/TSVSSQ AF33 1 TH@ 2
LV14
TH@ 2 RV95 1 249_0402_1% RV200 0_0402_5%
2 1 +DPLL_PVDD
BLM15BD121SN1D_0402 2 1
10mil AA29 NC_TSVSSQ should be tied to GND on Thames
R2SET/NC
10U_0603_6.3V6M
CV82

CV83

CV84
1U_0402_6.3V6K

0.1U_0402_16V7K

CV81 0.1U_0402_16V7K +DPLL_PVDDAM32

DPLL_PVDD
1 1 1 AN32 DPLL_PVSS
LV14
10mil DDC/AUX AM26
0_0402_5% +DPLL_VDDCAN31 PLL/CLOCK DDC1CLK
DPLL_VDDC DDC1DATA AN26
CH@ 2 2 2

AUX1P AM27
XTALIN XTALIN AV33 AL27
XTALOUT AU34 XTALIN AUX1N
Voltage Swing: 1.8 V XTALOUT
DDC2CLK AM19
+1.0VGS AL19
LV15 TH@ (Thames RV11 1 @ DDC2DATA
125mA) +DPLL_VDDC
2
0_0402_5%
AW34 XO_IN
2 1 AUX2P AN20
BLM15BD121SN1D_0402 1 @ 2 AW35 AM20
XO_IN2 AUX2N
VGA Thermal Sensor ADM1032ARMZ
10U_0603_6.3V6M
CV86

CV87

CV88
1U_0402_6.3V6K

0.1U_0402_16V7K

RV12 0_0402_5%
1 1 1 DDCCLK_AUX3P AL30
LV15 AM30
0_0402_5% DDCDATA_AUX3N Closed to GPU +3VGS +3VGS
CH@ AL29 Reserved test pad of CRT Signals for debug
2 2 2 GPU_THERMAL_D+ DDCCLK_AUX4P
AF29 DPLUS DDCDATA_AUX4N AM29
GPU_THERMAL_D- AG29 THERMAL 2
DMINUS

2
AN21 VGA_CRT_CLK
DDCCLK_AUX5P VGA_CRT_CLK <23>
VGA_CRT_DATA CV85 RV98 CH@
TS_FDO AK32
DDCDATA_AUX5N AM21 VGA_CRT_DATA <23> CRT 0.1U_0402_16V7K 4.7K_0402_5%
<20> TS_FDO TS_FDO 1
AJ30 T792 CH@
RV97 DDC6CLK
NOGCLK@ (Thames 5mA) AL31 AJ31 T793 UV14

1
XTALOUT XTALIN TS_A/NC DDC6DATA VGA_SMB_CK2
(1.8V@20mA TSVDD) 1 VDD SCLK 8
LV16
1M_0402_5% 1 2 +TSVDD
10mil
AJ32
DDCCLK_AUX7P AK30
AK29 GPU_THERMAL_D+ 2 7 VGA_SMB_DA2
+1.8VGS TSVDD DDCDATA_AUX7N D+ SDATA
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z

YV1 NOGCLK@ BLM15BD121SN1D_0402 AJ33 CV89 CH@

TSVSS
CV91

CV92

CV93

2 1 SM010009U00 1 1 1 1 2 3 6 THM_ALERT#
D- ALERT#
27MHZ_16PF_X5H027000FG1H 300mA 120ohm@100mhz DCR 0.3 GPU_THERMAL_D- 2200P_0402_50V7K 4 5
THAMES XT M2 THR3@ THERM# GND
2 2 2
for debug CRT +3VGS
NOGCLK@ CV94 CV95 NOGCLK@
18P_0402_50V8J 18P_0402_50V8J ADM1032ARMZ-2REEL_MSOP8
VGA_CRT_VSYNC RV216 1 @ 210K_0402_5% +3VGS CH@
4 VGA_CRT_HSYNC RV217 1 @ 4
210K_0402_5% Address:100_1101
VGA_CRT_CLK RV218 1 @ 210K_0402_5% 1 CH@ 2
VGA_CRT_DATA RV219 1 @ 210K_0402_5% RV106 4.7K_0402_5%

VGA_CRT_R RV220 1 @ 2150_0402_1%

VGA_CRT_G
VGA_CRT_B
RV221 1
RV222 1
@
@
2150_0402_1%
2150_0402_1%
Reserve External
CLOSE TO YV1 Thermal Sensor for
<31> VGA_X1 1
R802
2 XTALIN AMD FAE strong suggest
0_0402_5%
GCLK@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
R802 place near YV1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
4019IT
Rev
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 23, 2012 Sheet 13 of 51
A B C D E
 A B C D E

1 1

PXS_PWREN 1 @ 2 PX_MODE
<25,26,44,49> PXS_PWREN PX_MODE <45,49>
RV102 0_0402_5%
PX_MODE=1 for Normal Operation
for PX5.0
PX_MODE=0 to shut down VDDR3, PCIE_VDDC, 1.5VGS and 1.8VGS power rails

+5VALW

2
R424
100K_0402_5%

+1.5V to +1.5VGS

1
2 PX_MODE# 2
+1.5V +1.5VGS

6
Vgs=10V,Id=14.5A,Rds=6mohm
Q188A
1 1 PX_MODE 2
Q43 C478 C475

470_0805_5%
8 1 4.7U_0805_10V4Z 2N7002DW-T/R7_SOT363-6

1
D S

2
7 D S 2
2 2 R429
6 D S 3
5 D G 4
1U_0402_6.3V6K
FDS6676AS_SO8 1 R431 2 +VSB

3 1
4.7U_0805_10V4Z
1 1 220K_0402_5%

6
+BIF_VDDC +VGA_CORE +1.0VGS

0.1U_0402_25V6
C473 C481 R430 Q13A +1.0VGS
820K_0402_5% Q13B
2 2 PX_MODE# 2N7002DW-T/R7_SOT363-6
2 5

2
1 2 2N7002DW-T/R7_SOT363-6

2
RV204 0_0805_5% R475

4
TH@ 470_0805_5%
1 2
RV205 0_0805_5%

1
CH@
1

3
CV97 Q188B

PX4@ 22U_0805_6.3V6M
2 PXS_PWREN#
5

2N7002DW-T/R7_SOT363-6
Only stuff at PX5.0 and Thames XT,

4
3 3
un-stuff on PX4.0

+3VS to +3VGS
+3VGS
+3VS
+3VALW

2
R458
470_0805_5%

2
2
R433 C491 Vgs=-4.5V,Id=3A,Rds<97mohm

3 1
100K_0402_5% 0.1U_0402_16V7K

1
1

1
S

3
Q206B R426 Q54
G R104
2N7002DW-T/R7_SOT363-6 5PXS_PWREN# 1 2 2 0_0805_5%
@
47K_0402_5% AO3413_SOT23 D +3VGS
2

2
C492

6
0.01U_0402_25V7K
Q206A 1
1
1 C684
PXS_PWREN 2 C683 1U_0402_6.3V6K
2N7002DW-T/R7_SOT363-6 4.7U_0805_10V4Z
@ 2

1
4 2 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 14 of 51
A B C D E
 A B C D E

(Thames 440mA) +1.8VGS

(1.8V@504mA PCIE_VDDR) LV17
+PCIE_VDDR 2 1

CV126

CV127

CV128

CV129

CV130

CV131
FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_16V7K

0.1U_0402_16V7K
1 1 1 1 1 1

2 2 2 2 2 2
UV1E
40mA +1.8VGS
(1.8V@40mA PCIE_PVDD) LV18
+1.5VGS MEM I/O
For DDR3, MVDDQ = 1.5V PCIE 40mil 2 1

CV132

CV133

CV134
MBK1608121YZF_0603

10U_0603_6.3V6M
0.1U_0402_16V7K

1U_0402_6.3V6K
(Thames 1.7)A AC7 AA31 1 1 1
VDDR1#1 PCIE_VDDR#1
1 AD11 VDDR1#2 PCIE_VDDR#2 AA32

1U_0402_6.3V6K
CV406

1U_0402_6.3V6K
CV420

1U_0402_6.3V6K
CV367

1U_0402_6.3V6K
CV413

1U_0402_6.3V6K
CV409

1U_0402_6.3V6K
CV412

1U_0402_6.3V6K
CV410

1U_0402_6.3V6K
CV369
1 1 1 1 1 1 1 1 1 AF7 VDDR1#3 PCIE_VDDR#3 AA33 1
CV401 + AG10 AA34
330U_D2_2V_Y VDDR1#4 PCIE_VDDR#4 2 2 2
AJ7 VDDR1#5 PCIE_VDDR#5 V28
AK8 VDDR1#6 PCIE_VDDR#6 W29
2 2 2 2 2 2 2 2 2
AL9 VDDR1#7 PCIE_VDDR#7 W30
G11
G14
VDDR1#8 PCIE_VDDR#8 Y31
AB37 +PCIE_PVDD
(Thames 1.1A) +1.0VGS
VDDR1#9 PCIE_VDDR/PCIE_PVDD
G17 VDDR1#10 (1.0V@1920mA PCIE_VDDC)
G20 VDDR1#11 PCIE_VDDC#1 G30
1U_0402_6.3V6K
CV417

1U_0402_6.3V6K
CV368
1 1 1 1 1 1 1 1 G23 VDDR1#12 PCIE_VDDC#2 G31

10U_0603_6.3V6M
CV421

10U_0603_6.3V6M
CV418

10U_0603_6.3V6M
CV377

10U_0603_6.3V6M
CV376

10U_0603_6.3V6M
CV375

10U_0603_6.3V6M
CV419

CV146

CV147

CV148

CV149

CV150

CV151
10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
G26 VDDR1#13 PCIE_VDDC#3 H29
G29 VDDR1#14 PCIE_VDDC#4 H30 1 1 1 1 1 1
H10 VDDR1#15 PCIE_VDDC#5 J29
+1.5VGS 2 2 2 2 2 2 2 2
J7 VDDR1#16 PCIE_VDDC#6 J30
J9 VDDR1#17 PCIE_VDDC#7 L28
2 2 2 2 2 2
K11 VDDR1#18 PCIE_VDDC#8 M28
1 K13 VDDR1#19 PCIE_VDDC#9 N28
@ K8 R28
CV402 + VDDR1#20 PCIE_VDDC#10
L12 VDDR1#21 PCIE_VDDC#11 T28
330U_D2_2V_Y L16 U28
VDDR1#22 PCIE_VDDC#12 +VGA_CORE
L21 VDDR1#23
2
L23
L26
VDDR1#24
AA15
(Thames 20.5A)
VDDR1#25 CORE VDDC#1
L7 VDDR1#26 VDDC#2 AA17

CV191
10U_0603_6.3V6M
M11 VDDR1#27 VDDC#3 AA20
N11 VDDR1#28 VDDC#4 AA22 1 1
P7 AA24 CV192
VDDR1#29 VDDC#5
R11 VDDR1#30 VDDC#6 AA27

22U_0805_6.3V6M
U11 VDDR1#31 VDDC#7 AB16
+1.8VGS 2 2
(Thames 250mA) U7
Y11
VDDR1#32 VDDC#8 AB18
AB21
LV19 VDDR1#33 VDDC#9
(1.8V@110mA VDD_CT) Y7 VDDR1#34 VDDC#10 AB23
1 2 +VDDC_CT AB26
BLM18AG121SN1D_2P VDDC#11
VDDC#12 AB28
CV170

CV171

CV172

CV173

CV174
10U_0603_6.3V6M

SM010009U00
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

VDDC#13 AC17
2 1 1 1 1 1 VDDC#14 AC20 2
300mA 120ohm@100mhz DCR 0.3 LEVEL AC22
+3VGS TRANSLATION VDDC#15
20mil VDDC#16 AC24

POWER
(Thames 60mA) 2 2 2 2 2
AF26
AF27
VDD_CT#1 VDDC#17 AC27
AD18
VDD_CT#2 VDDC#18
AG26 VDD_CT#3 VDDC#19 AD21
CV187

CV188

CV189

CV190
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

AG27 VDD_CT#4 VDDC#20 AD23

1 1 1 1 VDDC#21 AD26
VDDC#22 AF17
I/O
10mil AF23
VDDC#23 AF20
AF22
2 2 2 2 VDDR3#1 VDDC#24
AF24 VDDR3#2 VDDC#25 AG16
AG23 VDDR3#3 VDDC#26 AG18
+1.8VGS 20mil AG24 VDDR3#4 VDDC#27 AG21
AH22
LV20 VDDC#28
(1.8V@300mA VDDR4) VDDC#29 AH27
1 2 +VDDR4 AF13 AH28
BLM18AG121SN1D_2P VDDR4#4 VDDC#30
AF15 VDDR4#5 VDDC#31 M26
CV193

CV194
1U_0402_6.3V6K

0.1U_0402_16V7K

AG13 VDDR4#7 VDDC#32 N24

SM010009U00 1 1 AG15 VDDR4#8 VDDC/BIF_VDDC#33 N27
VDDC#34 R18
300mA 120ohm@100mhz DCR 0.3 R21
VDDC#35
AD12 VDDR4#1 VDDC#36 R23
2 2
AF11 VDDR4#2 VDDC#37 R26
SM01000BL00 AF12 VDDR4#3 VDDC#38 T17
+BIF_VDDC
AG11 T20
1000mA 470ohm@100mhz DCR 0.2 VDDR4#6 VDDC#39
T22
VDDC#40
+1.8VGS (Thames 150mA) VDDC#41 T24
T27
55mA
VDDC/BIF_VDDC#42
(M97, Broadway and Madison: 1.8V@150mA MPV18) VDDC#43 U16

CV195

CV196
LV21 For non-BACO designs, connect BIF_VDDC to VDDC.

1U_0402_6.3V6K

1U_0402_6.3V6K
M20 NC_VDDRHA VDDC#44 U18
1 2 +MPV18 M21 U21 1 1
MCK1608471YZF 0603 NC_VSSRHA VDDC#45 For BACO designs - see BACO reference schematics
+1.8VGS (Thames 50mA) VDDC#46 U23
U26
VDDC#47
CV197

CV198

CV199

LV22
10U_0603_6.3V6M

(1.8V@75mA SPV18)
1U_0402_6.3V6K

0.1U_0402_16V7K

V12 NC_VDDRHB VDDC#48 V17

2 2
3 1 2 1 1 1 U12 NC_VSSRHB VDDC#49 V20 3
BLM18AG121SN1D_2P V22
VDDC#50
CV200

CV201

CV202
10U_0603_6.3V6M

SM010009U00
1U_0402_6.3V6K

0.1U_0402_16V7K

VDDC#51 V24
1 1 1 VDDC#52 V27
300mA 120ohm@100mhz DCR 0.3 2 2 2
Y16
PLL VDDC#53
VDDC#54 Y18
2 2 2 20mil VDDC#55 Y21
Y23
VDDC#56
H7 MPV18#1 VDDC#57 Y26
H8 MPV18#2 VDDC#58 Y28
+1.0VGS
(Thames 100mA) 10mil +SPV18 AM10 (GDDR3/DDR3 1.12V@4A VDDCI)
LV23 SPV18
(120mA SPV10) 20mil +SPV10 AN9 VDDCI#1 AA13 +VDDCI
1 2 SPV10 VDDCI#2 AB13
MCK1608471YZF 0603
+VDDCI +VGA_CORE VDDCI#3 AC12 4A
CV215

CV216

CV217
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

AN10 SPVSS VDDCI#4 AC15

SM01000BL00 1 1 1 VDDCI#5 AD13
1

AD16
1000mA 470ohm@100mhz DCR 0.2 VDDCI#6
1

RV215 M15
10_0402_5% RV22 VDDCI#7
VDDCI#8 M16
2 2 2 10_0402_5% VOLTAGE
VDDCI#9 M18
SENESE M23
2

VDDCI#10
10mil N13
2

VDDCI#11
<49> VCCSENSE_VGA AF28 FB_VDDC VDDCI#12 N15
VDDCI#13 N17
10mil VDDCI#14 N20
VDDCI_SEN AG28 N22
<45> VDDCI_SEN FB_VDDCI ISOLATED VDDCI#15 R12
CORE I/O VDDCI#16 R13
VDDCI#17
<49> VSSSENSE_VGA AH29 FB_GND VDDCI#18 R16
VDDCI#19 T12
1

VDDCI#20 T15
RV23 V15
10_0402_5% VDDCI#21
VDDCI#22 Y13
4 4
VDDCI and VDDC should have seperate regulators with a merge option on PCB
2

THAMES XT M2
THR3@
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC
can share one common regulator
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 15 of 51
A B C D E
 A B C D E

UV1F

AB39 PCIE_VSS#1 GND#1 A3

E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 PCIE_VSS#8 GND#8 AA26
H39 AA28 UV1H
J31
PCIE_VSS#9 GND#9
AA6
(Thames 330mA) 20mil 20mil
(Thames 330mA)
PCIE_VSS#10 GND#10 DP C/D POWER DP A/B POWER
J34 PCIE_VSS#11 GND#11 AB12 1.8V@300mA DPCD_VDD18) 1.8V@300mA DPAB_VDD18)
1 130mA 1
K31 PCIE_VSS#12 GND#12 AB15
K34 PCIE_VSS#13 GND#13 AB17 +1.8VGS 1 2 +DPCD_VDD18 AP20 DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1 AN24 +DPAB_VDD18 1 2 +1.8VGS
K39 AB20 RV119 0_0402_5% AP21 AP24 RV118 0_0402_5%
PCIE_VSS#14 GND#14 DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2
L31 PCIE_VSS#15 GND#15 AB22 20mil
L34 PCIE_VSS#16 GND#16 AB24 (1.0V@220mA DPAB_VDD10)
M34 PCIE_VSS#17 GND#17 AB27 (Thames 220mA) 20mil 110mA
M39 PCIE_VSS#18 GND#18 AC11 +1.0VGS 1 2 +DPCD_VDD10 AP13 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 AP31 +DPAB_VDD10 1 2 +1.0VGS
N31 AC13 1.0V@220mA DPCD_VDD10) RV121 0_0402_5% AT13 AP32 RV120 0_0402_5%
PCIE_VSS#19 GND#19 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2
N34 PCIE_VSS#20 GND#20 AC16
P31 PCIE_VSS#21 GND#21 AC18
P34 PCIE_VSS#22 GND#22 AC2 AN17 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AN27
P39 PCIE_VSS#23 GND#23 AC21 AP16 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP27
R34 PCIE_VSS#24 GND#24 AC23 AP17 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AP28
T31 PCIE_VSS#25 GND#25 AC26 AW14 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW24
T34 PCIE_VSS#26 GND#26 AC28 AW16 DP/DPC_VSSR#5 DP/DPA_VSSR#5 AW26
T39 PCIE_VSS#27 GND#27 AC6
U31 PCIE_VSS#28 GND#28 AD15
U34 PCIE_VSS#29 GND#29 AD17 20mil 20mil
V34 PCIE_VSS#30 GND#30 AD20 +DPCD_VDD18 AP22 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 AP25 130mA +DPAB_VDD18
V39 PCIE_VSS#31 GND#31 AD22 AP23 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 AP26
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 PCIE_VSS#34 GND#34 AD9 20mil 20mil
Y39 PCIE_VSS#35 GND#35 AE2 +DPCD_VDD10 AP14 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AN33 110mA +DPAB_VDD10
GND#36 AE6 AP15 DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 AP33
GND#37 AF10
GND#38 AF16
GND#39 AF18

F15 GND#100
GND GND#40
GND#41
GND#42
AF21
AG17
AG2
AN19
AP18
AP19
DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
AN29
AP29
AP30
F17 GND#101 GND#43 AG20 AW20 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW30
2 2
F19 GND#102 GND#44 AG22 AW22 DP/DPD_VSSR#5 DP/DPB_VSSR#5 AW32
F21 GND#103 GND#45 AG6
F23 GND#104 GND#46 AG9
F25 GND#105 GND#47 AH21
F27 AJ10 150_0402_1%2 1 RV122 AW18 AW28 RV123 1 2 150_0402_1%
GND#106 GND#48 DPCD_CALR DPAB_CALR
F29 GND#107 GND#49 AJ11
F31 GND#108 GND#50 AJ2
F33 GND#109 GND#51 AJ28 1.8V@300mA DPEF_VDD18) 20mil DP E/F POWER DP PLL POWER 20mA 10mil
F7 AJ6 1 2 +DPEF_VDD18 AH34 AU28
F9
GND#110 GND#52
AK11
(Thames 330mA) +1.8VGS
RV124 0_0402_5% AJ34
DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD
AV27
+DPAB_VDD18
GND#111 GND#53 DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS
G2 GND#112 GND#54 AK31
G6 GND#113 GND#55 AK7
H9 GND#114 GND#56 AL11 1.0V@240mA DPEF_VDD10) 20mil 20mA 10mil
J2 AL14 +1.0VGS 1 2 +DPEF_VDD10 AL33 AV29 +DPAB_VDD18
GND#115 GND#57 RV126 0_0402_5% DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD
J27
J6
GND#116 GND#58 AL17
AL2
(Thames 220mA) AM33 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS AR28
GND#117 GND#59
J8 GND#118 GND#60 AL20
K14 GND#119 GND/PX_EN#61 AL21 10mil
K7 GND#120 GND#62 AL23 AN34 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AU18 +DPCD_VDD18
L11 GND#121 GND#63 AL26 AP39 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS AV17
L17 GND#122 GND#64 AL32 AR39 DP/DPE_VSSR#3
1

L2 GND#123 GND#65 AL6 AU37 DP/DPE_VSSR#4

L22 GND#124 GND#66 AL8 10mil
L24 AM11 RV125 AV19 +DPCD_VDD18
GND#125 GND#67 4.7K_0402_5% DPCD_VDD18/DPD_PVDD
L6 GND#126 GND#68 AM31 DP_VSSR/DPD_PVSS AR18
M17 AM9 20mil 20mA
2

GND#127 GND#69
M22 GND#128 GND#70 AN11 +DPEF_VDD18 AF34 DPEF/DPF_VDD18#1
M24 GND#129 GND#71 AN2 AG34 DPEF/DPF_VDD18#2 10mil
N16 GND#130 GND#72 AN30 DPEF_VDD18/DPE_PVDD AM37 +DPEF_VDD18
N18 GND#131 GND#73 AN6 DP_VSSR/DPE_PVSS AN38
N2 GND#132 GND#74 AN8 20mil 20mA
N21 GND#133 GND#75 AP11 +DPEF_VDD10 AK33 DPEF/DPF_VDD10#1
3 3
N23 GND#134 GND#76 AP7 AK34 DPEF/DPF_VDD10#2 10mil
N26 GND#135 GND#77 AP9 DPEF_VDD18/DPF_PVDD AL38 +DPEF_VDD18
N6 GND#136 GND#78 AR5 DP_VSSR/DPF_PVSS AM35
R15 GND#137 GND#79 B11
R17 GND#138 GND#80 B13 AF39 DP/DPF_VSSR#1
R2 GND#139 GND#81 B15 AH39 DP/DPF_VSSR#2
R20 GND#140 GND#82 B17 AK39 DP/DPF_VSSR#3
R22 GND#141 GND#83 B19 AL34 DP/DPF_VSSR#4
R24 B21 PS_0 AM34
GND#142 GND#84 <20> PS_0 DP/DPF_VSSR#5
R27 GND#143 GND#85 B23 Thames/Seymour Only

2
R6 GND#144 GND#86 B25
T11 B27 Do not install for Heathrow/Chelsea RV199
GND#145 GND#87
T13 GND#146 GND#88 B29 0_0402_5% AM39 DPEF_CALR
T16 GND#147 GND#89 B31 PS_0 Should be tied to GND on Thames/Seymour TH@

1
T18 B33
1
GND#148 GND#90 RV127 THAMES XT M2 THR3@
T21 GND#149 GND#91 B7
T23 B9 150_0402_1%
GND#150 GND#92
T26 GND#151 GND#93 C1
U15 C39

2
GND#153 GND#94
U17 GND#154 GND#95 E35
U2 GND#155 GND#96 E5
U20 GND#156 GND#97 F11
U22 GND#157 GND#98 F13
U24 GND#158
U27 GND#159
U6 GND#160
V11 GND#161
V16 GND#163
V18 GND#164
V21 GND#165
V23 GND#166
V26 GND#167
4 4
W2 GND#168
W6 GND#169
Y15 GND#170
Y17 GND#171
Y20 GND#172
Y22 GND#173 VSS_MECH#1 A39 MECH#1
Y24 AW1 MECH#2 T821PAD
GND#174 VSS_MECH#2 T831PAD
AW39 MECH#3
Y27
U13
GND#175
GND#152
VSS_MECH#3 T841PAD Security Classification Compal Secret Data Compal Electronics, Inc.
V13 GND#162 Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THAMES XT M2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
THR3@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 16 of 51
A B C D E
 A B C D E

UV1C MDA[0..63] UV1D MDB[0..63]

<18> MDA[0..63] <19> MDB[0..63]
DDR2 DDR2 DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 MAA[12..0] DDR3 DDR3 MAB[12..0]
MAA[12..0] <18> MAB[12..0] <19>
MDA0 C37 G24 MAA0 MDB0 C5 P8 MAB0
MDA1 DQA0_0/DQA_0 MAA0_0/MAA_0 MAA1 A_BA[2..0] MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB1 B_BA[2..0]
C35 DQA0_1/DQA_1 MAA0_1/MAA_1 J23 A_BA[2..0] <18> C3 DQB0_1/DQB_1 MAB0_1/MAB_1 T9 B_BA[2..0] <19>
MDA2 A35 H24 MAA2 MDB2 E3 P9 MAB2
MDA3 DQA0_2/DQA_2 MAA0_2/MAA_2 MAA3 MDB3 DQB0_2/DQB_2 MAB0_2/MAB_2 MAB3
E34 DQA0_3/DQA_3 MAA0_3/MAA_3 J24 E1 DQB0_3/DQB_3 MAB0_3/MAB_3 N7

MEMORY INTERFACE A
MDA4 G32 H26 MAA4 MDB4 F1 N8 MAB4
DQA0_4/DQA_4 MAA0_4/MAA_4 DQB0_4/DQB_4 MAB0_4/MAB_4

MEMORY INTERFACE B
MDA5 D33 J26 MAA5 MDB5 F3 N9 MAB5
MDA6 DQA0_5/DQA_5 MAA0_5/MAA_5 MAA6 MDB6 DQB0_5/DQB_5 MAB0_5/MAB_5 MAB6
F32 DQA0_6/DQA_6 MAA0_6/MAA_6 H21 F5 DQB0_6/DQB_6 MAB0_6/MAB_6 U9
MDA7 E32 G21 MAA7 MDB7 G4 U8 MAB7
MDA8 DQA0_7/DQA_7 MAA0_7/MAA_7 MAA8 MDB8 DQB0_7/DQB_7 MAB0_7/MAB_7 MAB8
D31 DQA0_8/DQA_8 MAA1_0/MAA_8 H19 H5 DQB0_8/DQB_8 MAB1_0/MAB_8 Y9
MDA9 F30 H20 MAA9 MDB9 H6 W9 MAB9
MDA10 DQA0_9/DQA_9 MAA1_1/MAA_9 MAA10 MDB10 DQB0_9/DQB_9 MAB1_1/MAB_9 MAB10
C30 DQA0_10/DQA_10 MAA1_2/MAA_10 L13 J4 DQB0_10/DQB_10 MAB1_2/MAB_10 AC8
1 MDA11 A30 G16 MAA11 MDB11 K6 AC9 MAB11 1
MDA12 DQA0_11/DQA_11 MAA1_3/MAA_11 MAA12 MDB12 DQB0_11/DQB_11 MAB1_3/MAB_11 MAB12
F28 DQA0_12/DQA_12 MAA1_4/MAA_12 J16 K5 DQB0_12/DQB_12 MAB1_4/MAB_12 AA7
MDA13 C28 H16 A_BA2 MDB13 L4 AA8 B_BA2
MDA14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 A_BA0 MDB14 DQB0_13/DQB_13 MAB1_5/BA2 B_BA0
A28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 J17 M6 DQB0_14/DQB_14 MAB1_6/BA0 Y8
MDA15 E28 H17 A_BA1 MDB15 M1 AA9 B_BA1
MDA16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 MDB16 DQB0_15/DQB_15 MAB1_7/BA1
D27 DQA0_16/DQA_16 DQMA#[7..0] <18> M3 DQB0_16/DQB_16 DQMB#[7..0] <19>
MDA17 F26 A32 DQMA#0 MDB17 M5 H3 DQMB#0
MDA18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 DQMA#1 MDB18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 DQMB#1
C26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 C32 N4 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 H1
MDA19 A26 D23 DQMA#2 MDB19 P6 T3 DQMB#2
MDA20 DQA0_19/DQA_19 WCKA0_1/DQMA_2 DQMA#3 MDB20 DQB0_19/DQB_19 WCKB0_1/DQMB_2 DQMB#3
F24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 E22 P5 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 T5
MDA21 C24 C14 DQMA#4 MDB21 R4 AE4 DQMB#4
MDA22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 DQMA#5 MDB22 DQB0_21/DQB_21 WCKB1_0/DQMB_4 DQMB#5
A24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 A14 T6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AF5
MDA23 E24 E10 DQMA#6 MDB23 T1 AK6 DQMB#6
MDA24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 DQMA#7 MDB24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 DQMB#7
C22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 D9 U4 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 AK5
MDA25 A22 MDB25 V6
DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 QSA[7..0] <18> DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 QSB[7..0] <19>
MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0
MDA27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 QSA1 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 QSB1
D21 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D29 V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 K3
MDA28 A20 D25 QSA2 MDB28 Y6 P3 QSB2
MDA29 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 QSA3 MDB29 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 QSB3
F20 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E20 Y1 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 V5
MDA30 D19 E16 QSA4 MDB30 Y3 AB5 QSB4
MDA31 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 QSA5 MDB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 QSB5
E18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 E12 Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AH1
MDA32 C18 J10 QSA6 MDB32 AA4 AJ9 QSB6
MDA33 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 QSA7 MDB33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 QSB7
A18 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 D7 QSA#[7..0] <18> AB6 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 AM5 QSB#[7..0] <19>
MDA34 F18 MDB34 AB1
MDA35 DQA1_2/DQA_34 QSA#0 MDB35 DQB1_2/DQB_34 QSB#0
D17 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 A34 AB3 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 G7
MDA36 A16 E30 QSA#1 MDB36 AD6 K1 QSB#1
MDA37 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 QSA#2 MDB37 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 QSB#2
F16 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 E26 AD1 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 P1
MDA38 D15 C20 QSA#3 MDB38 AD3 W4 QSB#3
MDA39 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 QSA#4 MDB39 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 QSB#4
E14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C16 AD5 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AC4
MDA40 F14 C12 QSA#5 MDB40 AF1 AH3 QSB#5
MDA41 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 QSA#6 MDB41 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 QSB#6
D13 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 J11 AF3 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AJ8
MDA42 F12 F8 QSA#7 MDB42 AF6 AM3 QSB#7
MDA43 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 MDB43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 DQA1_11/DQA_43 AG4 DQB1_11/DQB_43
MDA44 D11 J21 ODTA0 MDB44 AH5 T7 ODTB0
DQA1_12/DQA_44 ADBIA0/ODTA0 ODTA0 <18> DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB0 <19>
MDA45 F10 G19 ODTA1 MDB45 AH6 W7 ODTB1
DQA1_13/DQA_45 ADBIA1/ODTA1 ODTA1 <18> DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1 <19>
2 MDA46 A10 MDB46 AJ4 2
MDA47 DQA1_14/DQA_46 CLKA0 MDB47 DQB1_14/DQB_46 CLKB0
C10 DQA1_15/DQA_47 CLKA0 H27 CLKA0 <18> AK3 DQB1_15/DQB_47 CLKB0 L9 CLKB0 <19>
MDA48 G13 G27 CLKA0# MDB48 AF8 L8 CLKB0#
DQA1_16/DQA_48 CLKA0B CLKA0# <18> DQB1_16/DQB_48 CLKB0B CLKB0# <19>
MDA49 H13 MDB49 AF9
MDA50 DQA1_17/DQA_49 CLKA1 MDB50 DQB1_17/DQB_49 CLKB1
J13 DQA1_18/DQA_50 CLKA1 J14 CLKA1 <18> AG8 DQB1_18/DQB_50 CLKB1 AD8 CLKB1 <19>
MDA51 H11 H14 CLKA1# MDB51 AG7 AD7 CLKB1#
DQA1_19/DQA_51 CLKA1B CLKA1# <18> DQB1_19/DQB_51 CLKB1B CLKB1# <19>
MDA52 G10 MDB52 AK9
MDA53 DQA1_20/DQA_52 RASA0# MDB53 DQB1_20/DQB_52 RASB0#
G8 DQA1_21/DQA_53 RASA0B K23 RASA0# <18> AL7 DQB1_21/DQB_53 RASB0B T10 RASB0# <19>
MDA54 K9 K19 RASA1# MDB54 AM8 Y10 RASB1#
DQA1_22/DQA_54 RASA1B RASA1# <18> DQB1_22/DQB_54 RASB1B RASB1# <19>
MDA55 K10 MDB55 AM7
MDA56 DQA1_23/DQA_55 CASA0# MDB56 DQB1_23/DQB_55 CASB0#
G9 DQA1_24/DQA_56 CASA0B K20 CASA0# <18> AK1 DQB1_24/DQB_56 CASB0B W10 CASB0# <19>
MDA57 A8 K17 CASA1# MDB57 AL4 AA10 CASB1#
DQA1_25/DQA_57 CASA1B CASA1# <18> DQB1_25/DQB_57 CASB1B CASB1# <19>
MDA58 C8 MDB58 AM6
MDA59 DQA1_26/DQA_58 CSA0#_0 MDB59 DQB1_26/DQB_58 CSB0#_0
E8 DQA1_27/DQA_59 CSA0B_0 K24 CSA0#_0 <18> AM1 DQB1_27/DQB_59 CSB0B_0 P10 CSB0#_0 <19>
MDA60 A6 K27 MDB60 AN4 L10
MDA61 DQA1_28/DQA_60 CSA0B_1 MDB61 DQB1_28/DQB_60 CSB0B_1
C6 DQA1_29/DQA_61 AP3 DQB1_29/DQB_61
MDA62 E6 M13 CSA1#_0 MDB62 AP1 AD10 CSB1#_0
DQA1_30/DQA_62 CSA1B_0 CSA1#_0 <18> DQB1_30/DQB_62 CSB1B_0 CSB1#_0 <19>
MDA63 A5 K16 MDB63 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 DQB1_31/DQB_63 CSB1B_1
+VDD_MEM15_REFDA L18 K21 CKEA0 U10 CKEB0
+1.5VGS MVREFDA CKEA0 CKEA0 <18> CKEB0 CKEB0 <19>
+VDD_MEM15_REFSA L20 J20 CKEA1 +VDD_MEM15_REFDB Y12 AA11 CKEB1
MVREFSA CKEA1 CKEA1 <18> MVREFDB CKEB1 CKEB1 <19>
+VDD_MEM15_REFSB AA12
RV129 1 TH@ +3VGS MVREFSB
2 240_0402_1% L27 MEM_CALRN0 WEA0B K26 WEA0#
WEA0# <18> WEB0B N10 WEB0#
WEB0# <19>
RV130 1 @ 2 240_0402_1% N12 L15 WEA1# AB11 WEB1#
MEM_CALRN1 WEA1B WEA1# <18> WEB1B WEB1# <19>
RV131 1 TH@ 2 240_0402_1% AG12 1 @ 2
MEM_CALRN2 5.11K_0402_1% RV133
RV132 1 @ 2 240_0402_1% M12 H23 MAA13 1 2 TESTEN AD28 T8 MAB13
MEM_CALRP1 MAA0_8 MAA13 <18> TESTEN MAB0_8 MAB13 <19>
RV134 1 TH@ 2 240_0402_1% M27 J19 MAA14 1K_0402_1% RV206 W8 MAB14
MEM_CALRP0 MAA1_8 MAA14 <18> MAB1_8 MAB14 <19>
RV135 1 TH@ 2 240_0402_1% AH12 AK10

GDDR5
MEM_CALRP2 CLKTESTA DRAM_RST#_R
GDDR5

AL10 CLKTESTB DRAM_RST AH11

RV135 RV134
120_0402_1% 120_0402_1%
CH@ CH@

3 3
THAMES XT M2 THAMES XT M2
THR3@ THR3@
This basic topology should be used for DRAM_RST for DDR3/GDDR5.These

1
Capacitors and Resistor values are an example only. The Series R and @ @
|| Cap values will depend on the DRAM load and will have to be CV218 CV219
0.1U_0402_16V7K 0.1U_0402_16V7K
calculated for different Memory ,DRAM Load and board to pass Reset

2
Signal Spec. route 50ohms single-ended/100ohms diff
Place all these components very close to GPU (Within and keep short

1
25mm) and keep all component close to each Other (within Debug only, for clock observation, if not needed, DNI
5mm) except Rser2 @ @
5mil 5mil
RV136 RV137
51.1_0402_1% 51.1_0402_1%

2
+1.5VGS
1

RV138
4.7K_0402_5%
@
+1.5VGS +1.5VGS
2

+1.5VGS +1.5VGS
1

1
1 RV143 2 1 RV144 2 DRAM_RST#_R RV141 RV142
1

<18,19> DRAM_RST# 51.1_0402_1% 10_0402_5% 40.2_0402_1% 40.2_0402_1%

RV139 RV140
40.2_0402_1% 40.2_0402_1%
2

2
2
1

+VDD_MEM15_REFDB +VDD_MEM15_REFSB
2

CV222 RV145
+VDD_MEM15_REFDA +VDD_MEM15_REFSA 120P_0402_50V9 4.99K_0402_1%
2

1
CV223 CV224
1

4 RV148 0.1U_0402_16V7K RV149 0.1U_0402_16V7K 4

1

CV220 CV221 100_0402_1% 100_0402_1%

2

2
RV146 0.1U_0402_16V7K RV147 0.1U_0402_16V7K
100_0402_1% 100_0402_1%
2

2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 17 of 51
A B C D E
 A B C D E

CHANNEL A: 512MB/1024MB DDR3

UV18 UV19 UV20 UV21

+VREFC_A1 M8 E3 MDA29 +VREFC_A2 M8 E3 MDA18 +VREFC_A3 M8 E3 MDA35 +VREFC_A4 M8 E3 MDA50

+VREFD_Q1 H1 VREFCA DQL0 MDA25 +VREFD_Q2 VREFCA DQL0 MDA20 +VREFD_Q3 VREFCA DQL0 MDA36 +VREFD_Q4 VREFCA DQL0 MDA51
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA30 F2 MDA16 F2 MDA38 F2 MDA55
MAA0 DQL2 MDA24 MAA0 DQL2 MDA23 MAA0 DQL2 MDA34 MAA0 DQL2 MDA52
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAA1 P7 H3 MDA31 MAA1 P7 H3 MDA19 MAA1 P7 H3 MDA39 MAA1 P7 H3 MDA48
MAA2 A1 DQL4 MDA26 MAA2 A1 DQL4 MDA22 MAA2 A1 DQL4 MDA33 MAA2 A1 DQL4 MDA53
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA28 MAA3 N2 G2 MDA17 MAA3 N2 G2 MDA37 MAA3 N2 G2 MDA49
MAA4 A3 DQL6 MDA27 MAA4 A3 DQL6 MDA21 MAA4 A3 DQL6 MDA32 MAA4 A3 DQL6 MDA54
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAA5 P2 MAA5 P2 MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
1
R8 A6 R8 A6 R8 A6 R8 A6 1
MDA[0..63] MAA7 R2 D7 MDA0 MAA7 R2 D7 MDA15 MAA7 R2 D7 MDA42 MAA7 R2 D7 MDA60
<17> MDA[0..63] A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
MAA8 T8 C3 MDA5 MAA8 T8 C3 MDA10 MAA8 T8 C3 MDA44 MAA8 T8 C3 MDA58
MAA9 A8 DQU1 MDA1 MAA9 A8 DQU1 MDA14 MAA9 A8 DQU1 MDA40 MAA9 A8 DQU1 MDA63
R3 A9 DQU2 C8 R3 A9 DQU2 C8 R3 A9 DQU2 C8 R3 A9 DQU2 C8
MAA10 L7 C2 MDA6 MAA10 L7 C2 MDA11 MAA10 L7 C2 MDA46 MAA10 L7 C2 MDA59
MAA11 A10/AP DQU3 MDA3 MAA11 A10/AP DQU3 MDA13 MAA11 A10/AP DQU3 MDA43 MAA11 A10/AP DQU3 MDA61
R7 A11 DQU4 A7 R7 A11 DQU4 A7 R7 A11 DQU4 A7 R7 A11 DQU4 A7
MAA12 N7 A2 MDA4 MAA12 N7 A2 MDA9 MAA12 N7 A2 MDA45 MAA12 N7 A2 MDA56
MAA[14..0] MAA13 A12 DQU5 MDA2 MAA13 A12 DQU5 MDA12 MAA13 A12 DQU5 MDA41 MAA13 A12 DQU5 MDA62
<17> MAA[14..0] T3 A13 DQU6 B8 T3 A13 DQU6 B8 T3 A13 DQU6 B8 T3 A13 DQU6 B8
MAA14 T7 A3 MDA7 MAA14 T7 A3 MDA8 MAA14 T7 A3 MDA47 MAA14 T7 A3 MDA57
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+1.5VGS +1.5VGS +1.5VGS +1.5VGS

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

<17> A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
DQMA#[7..0] <17> A_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7
<17> DQMA#[7..0] <17> A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKA0 J7 N9 J7 N9 CLKA1 J7 N9
<17> CLKA0 CK VDD CK VDD <17> CLKA1 CK VDD CK VDD
K7 R1 CLKA0# K7 R1 K7 R1 CLKA1# K7 R1
QSA[7..0] <17> CLKA0# CK VDD CK VDD <17> CLKA1# CK VDD CK VDD
K9 R9 CKEA0 K9 R9 K9 R9 CKEA1 K9 R9
<17> QSA[7..0] <17> CKEA0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS <17> CKEA1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS

K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
<17> ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <17> ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
<17> CSA0#_0 CS/CS0 VDDQ CS/CS0 VDDQ <17> CSA1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
<17> RASA0# RAS VDDQ RAS VDDQ <17> RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
QSA#[7..0] <17> CASA0# CAS VDDQ CAS VDDQ <17> CASA1# CAS VDDQ CAS VDDQ
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
<17> QSA#[7..0] <17> WEA0# WE VDDQ WE VDDQ <17> WEA1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA3 F3 H2 QSA2 F3 H2 QSA4 F3 H2 QSA6 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

DQMA#3 E7 A9 DQMA#2 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9

DQMA#0 DML VSS DQMA#1 DML VSS DQMA#5 DML VSS DQMA#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
2 QSA#3 G3 J2 QSA#2 G3 J2 QSA#4 G3 J2 QSA#6 G3 J2 2
QSA#0 DQSL VSS QSA#1 DQSL VSS QSA#5 DQSL VSS QSA#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
<17,19> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV150 L1 B9 RV151 L1 B9 RV152 L1 B9 RV153 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9

96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96
CLKA0 1 2 @ @ @ @
RV154 40.2_0402_1%

CLKA0# 1 2
RV155 40.2_0402_1%
1

CV225
0.01U_0402_16V7K
+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
2

1
RV156 RV157 RV158 RV159 RV160 RV161 RV162 RV163
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
3 3

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

2

2
CLKA1 1 2
RV164 40.2_0402_1% +VREFD_Q1 +VREFC_A1 +VREFC_A2 +VREFD_Q2 +VREFC_A3 +VREFD_Q3 +VREFC_A4 +VREFD_Q4
1

1
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
CV226

CV227

CV228

CV229

CV230

CV231

CV232
1

1
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

CV233
CLKA1# 1 2 RV166 RV167 RV168 RV169 RV170 RV171 RV172 RV173
RV165 40.2_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
1

CV234
2

2
0.01U_0402_16V7K
2

2
2

+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
CV235

CV236

CV237

CV238

CV239

CV240

CV241

CV242

CV243

CV244

CV245

CV246

CV247
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

CV248

CV249

CV250

CV251

CV252

CV253

CV254

CV255

CV256

CV257

CV258

CV259

CV260

CV261

CV262

CV263

CV264

CV265

CV266

CV267

CV268

CV269

CV270

CV271
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 18 of 51
A B C D E
 5 4 3 2 1

CHANNEL B: 512MB/1024MB DDR3

UV22 UV23 UV24 UV25

+VREFC_A1_B M8 E3 MDB29 +VREFC_A2_B M8 E3 MDB17 +VREFC_A3_B M8 E3 MDB33 +VREFC_A4_B M8 E3 MDB53

+VREFD_Q1_B VREFCA DQL0 MDB26 +VREFD_Q2_B H1 VREFCA DQL0 MDB19 +VREFD_Q3_B H1 VREFCA DQL0 MDB37 +VREFD_Q4_B H1 VREFCA DQL0 MDB50
H1 VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7
F2 MDB30 F2 MDB16 F2 MDB35 F2 MDB52
MAB0 DQL2 MDB27 MAB0 DQL2 MDB22 MAB0 DQL2 MDB39 MAB0 DQL2 MDB51
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAB1 P7 H3 MDB31 MAB1 P7 H3 MDB20 MAB1 P7 H3 MDB32 MAB1 P7 H3 MDB55
MAB2 A1 DQL4 MDB25 MAB2 A1 DQL4 MDB21 MAB2 A1 DQL4 MDB36 MAB2 A1 DQL4 MDB49
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB28 MAB3 N2 G2 MDB18 MAB3 N2 G2 MDB34 MAB3 N2 G2 MDB54
MAB4 A3 DQL6 MDB24 MAB4 A3 DQL6 MDB23 MAB4 A3 DQL6 MDB38 MAB4 A3 DQL6 MDB48
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAB7 R2 D7 MDB3 MAB7 R2 D7 MDB15 MAB7 R2 D7 MDB45 MAB7 R2 D7 MDB57
D MDB[0..63] MAB8 A7 DQU0 MDB5 MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB43 MAB8 A7 DQU0 MDB59 D
<17> MDB[0..63] T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAB9 R3 C8 MDB1 MAB9 R3 C8 MDB12 MAB9 R3 C8 MDB47 MAB9 R3 C8 MDB63
MAB10 A9 DQU2 MDB6 MAB10 A9 DQU2 MDB8 MAB10 A9 DQU2 MDB42 MAB10 A9 DQU2 MDB62
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MAB11 R7 A7 MDB2 MAB11 R7 A7 MDB13 MAB11 R7 A7 MDB44 MAB11 R7 A7 MDB56
MAB12 A11 DQU4 MDB7 MAB12 A11 DQU4 MDB9 MAB12 A11 DQU4 MDB40 MAB12 A11 DQU4 MDB61
N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2
MAB13 T3 B8 MDB0 MAB13 T3 B8 MDB14 MAB13 T3 B8 MDB46 MAB13 T3 B8 MDB58
MAB[14..0] MAB14 A13 DQU6 MDB4 MAB14 A13 DQU6 MDB11 MAB14 A13 DQU6 MDB41 MAB14 A13 DQU6 MDB60
<17> MAB[14..0] T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+1.5VGS +1.5VGS +1.5VGS +1.5VGS

M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

<17> B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
<17> B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
DQMB#[7..0] <17> B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
<17> DQMB#[7..0] VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKB0 J7 N9 J7 N9 CLKB1 J7 N9
<17> CLKB0 CK VDD CK VDD <17> CLKB1 CK VDD CK VDD
K7 R1 CLKB0# K7 R1 K7 R1 CLKB1# K7 R1
<17> CLKB0# CK VDD CK VDD <17> CLKB1# CK VDD CK VDD
K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9
QSB[7..0] <17> CKEB0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS <17> CKEB1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
<17> QSB[7..0]
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
<17> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <17> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<17> CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ <17> CSB1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
<17> RASB0# RAS VDDQ RAS VDDQ <17> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<17> CASB0# CAS VDDQ CAS VDDQ <17> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
QSB#[7..0] <17> WEB0# WE VDDQ WE VDDQ <17> WEB1# WE VDDQ WE VDDQ
<17> QSB#[7..0] VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB0 DQSL VDDQ QSB1 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9

DQMB#0 DML VSS DQMB#1 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
QSB#0 DQSL VSS QSB#1 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
C B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 C
CLKB0 1 2 M1 M1 M1 M1
RV174 40.2_0402_1% VSS VSS VSS VSS
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
<17,18> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
CLKB0# 1 2 T1 T1 T1 T1
RV175 40.2_0402_1% VSS VSS VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

CV272
1

1
0.01U_0402_16V7K J1 B1 J1 B1 J1 B1 J1 B1
RV176 NC/ODT1 VSSQ RV177 NC/ODT1 VSSQ RV178 NC/ODT1 VSSQ RV179 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
2

NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ

240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
CLKB1 1 2
RV180 40.2_0402_1% 96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96
CLKB1# 1 2 @ @ @ @
RV181 40.2_0402_1%
1

CV273
0.01U_0402_16V7K
2

+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

B B
1

1
RV182 RV183 RV184 RV185 RV186 RV187 RV188 RV189
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

2

2
+VREFD_Q1_B +VREFC_A1_B +VREFC_A2_B +VREFD_Q2_B +VREFC_A3_B +VREFD_Q3_B +VREFC_A4_B +VREFD_Q4_B
CV274

CV275

CV276

CV277

CV278

CV279

CV280

CV281
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1

1
1 1 1 1 1 1 1 1
RV190 RV191 RV192 RV193 RV194 RV195 RV196 RV197
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2 2 2 2 2
2

2
+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
CV282

CV283

CV284

CV285

CV286

CV287

CV288

CV289

CV290

CV291

CV292

CV293

CV294
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

CV295

CV296

CV297

CV298

CV299

CV300

CV301

CV302

CV303

CV304

CV305

CV306

CV307

CV308

CV309

CV310

CV311

CV312

CV313

CV314

CV315

CV316

CV317

CV318
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2
A
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 19 of 51
5 4 3 2 1
 5 4 3 2 1

CONFIGURATION STRAPS RECOMMENDED SETTINGS

Bits[5:4] Bits[3:1] Capacitor R_pu R_pd ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
PS_0 11 001 NC 8.45k 2k GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
NA = NOT APPLICABLE
PS_1 11 000 NC NC 4.75k
PS_2 00 000 680 nF NC 4.75k Conventional Pin RECOMMENDED
MLPS Bit STRAPS Strap Equivalent DESCRIPTION OF DEFAULT SETTINGS SETTINGS
PS_3 11 000 NC NC 4.75k
PS_0[3:1] ROMIDCFG(2:0) GPIO[13:11] Memory aperture size select 256MB: 0 0 1 001
D
+1.8VGS D

PS_0[4] N/A GENLK_VSYNC Must be 1 at rest. (Chelsea PRO) 1

1
RV212 RV207 RV208 RV211 STRAP_BIF_ PCIE Gen3 capability 0: 2.5GT/s 0
8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% PS_1[1] GEN3_EN_A GPIO2 1: 5GT/s
@ @ @ CH@
STRAP_BIF_

2
<16> PS_0 PS_1[2] CLK_PM_EN GPIO8 PCIE clock power management capability. 0
<13> PS_1
<13> PS_2
<13> PS_3 PS_1[3] N/A GENLK_CLK Must be 0 at rest. (Chelsea PRO) 0

1
@ CH@ @ @ 0: Half swing
1

1
CV103 CV102 CV101 CV90 RV213 RV209 RV210 RV203 PS_1[4] TX_PWRS_ENB GPIO0 PCIE full TX output swing 1: Full swing 1
4.75K_0402_1% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%
0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

CH@ CH@ CH@ CH@ 0: Disable

2

PS_1[5] TX_DEEMPH_EN GPIO1 PCIE transmitter de-emphsis enable 1: Enable 1

2
PS_2[1]
PS_2[2] N/A N/A Reserved N/A

0: Disable
PS_2[3] BIOS_ROM_EN GPIO_22_ROMCSB Enable external BIOS ROM 1: Enable 0

0: Enable
PS_2[4] VGA DIS GPIO9 VGA disable 1: Disable 0
+3VGS
C PS_2[5] C
PS_3[3:1] N/A N/A Reserved N/A
2

AUD_PORT_CONN
RV92 Disable MLPS for Chelsea PRO PS_0[5] _PINSTRAP[0]
10K_0402_5% Audio-capable display outputs
@ AUD_PORT_CONN
PS_3[4] _PINSTRAP[1] N/A 0 0 0 All endpoints are usable 111
1

TS_FDO AUD_PORT_CONN
1 1 1 No usable endpoints.
<13> TS_FDO
PS_3[5] _PINSTRAP[2]
2

AUD[1] AUD[0]
RV94 AUD[1] HSYNC 0 0 No audio function
10K_0402_5% Enable MLPS for Chelsea PRO 0 1 Audio for DisplayPort and HDMI if dongle is detected
CH@ +3VGS AUD[0] VSYNC 1 0 Audio for DisplayPort only 00
1 1 Audio for both DisplayPort and HDMI
1

<13> GENLK_CLK GENLK_CLK 2 @ 1

GENLK_VSYNC RV107
2 CH@ 10K_0402_5%
1
<13> GENLK_VSYNC
RV108 10K_0402_5% AMD RESERVED CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET
GPIO21 H2SYNC GENERICC GPIO2 GPIO8
B B

+1.8VGS

VRAM Straps
1

RV67 RV69 RV71 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2

10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @
H5TQ1G63DFR-11C
2

VRAM_ID2 VRAM_ID2 <13> 64MX16 (1G) Hynix 1GB RV68 RV70 RV72
VRAM_ID1 VRAM_ID1 <13> SA000041S20 0 0 0
K4W1G1646G-BC11
VRAM_ID0 VRAM_ID0 <13> *64MX16 (1G) Samsung 1GB RV67 RV70 RV72
SA00004GS00 1 0 0
1

H5TQ2G63BFR-11C
RV72
RV68 RV70 128M16 (2G) Hynix 2GB RV68 RV69 RV72
10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ SA00003YO00 0 1 0
K4W2G1646C-HC11
2

*128M16 (2G) Samsung 2GB RV67 RV69 RV72

SA000047Q00 1 1 0
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 20 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_RT Power Consumption:

30mil 30mil
1 @ 2
Pin5 (DPV33) < 20mA
RV277 0_0805_5% Pin 11 (DPV12) < 100mA
Pin 15 (SWR_VCCK) < 100mA (layout trace > 60 mil)
Pin 17 (SWR_LX) < 600mA (layout trace > 60 mil) +DVCC33
EEROM
UV27
+AVCC33 Pin 18 (SWR_VDD) < 200mA (layout trace > 40 mil)
Pin 22 (PVCC) < 50 mA RTD2136S
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
UV26 @
D D
1 1 1 8 1
Pin 43 (VCCK) < 50mA TXOC+ 35 LCD_TXCLK+ <22> 7
VCC
WP
A0
A1 2
+3VS_RT
CV343

CV344

CV321
22 36 LCD_TXCLK- <22> MIIC_SCL 6 3
PVCC TXOC- MIIC_SDA SCL A2
5 SDA GND 4
2 2 2 LV25 2 +DVCC33 40 mils
1 18 SWR_VDD TXO0+ 41 LCD_TXOUT0+ <22>
FBMA-L11-201209-221LMA30T_0805 42 LCD_TXOUT0- <22> CAT24C64WI-GT3_SO8
TXO0-

PWR
LV24 2 1 +AVCC33 5 Addr: A8 (1010 100X)
FBMA-L11-201209-221LMA30T_0805 DP_V33
TXO1+ 39 LCD_TXOUT1+ <22>
Close to LV9 Close to 5 pin +SWR_V12 LV26 1 2 +SW_LX 60 mils 17 40 LCD_TXOUT1- <22>
4.7UH_PG031B-4R7MS_1.1A_20% SWR_LX TXO1-
60 mils 15 37 LCD_TXOUT2+ <22>
SWR_VCCK TXO2+
TXO2- 38 LCD_TXOUT2- <22>
43 +DVCC33
VCCK
TXO3+ 33
+DVCC33 11 34
DP_V12 TXO3-

2
LVDS
10U_0603_6.3V6M

0.1U_0402_16V4Z

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RV278 @
1 1 1 1 1 TXEC+ 25 LCD_TZCLK+ <22> 4.7K_0402_5% EEPROM
DP0_TXP0_C 7 26 LCD_TZCLK- <22>
<7> DP0_TXP0_C LANE0P TXEC-
CV322

CV323

CV324

CV325

CV326

DP0_TXN0_C 8
<7> DP0_TXN0_C

1
LANE0N MIIC_SCL
TXE0+ 31 LCD_TZOUT0+ <22>
2 2 2 2 2 DP0_TXP1_C
<7> DP0_TXP1_C 9 LANE1P TXE0- 32 LCD_TZOUT0- <22>
DP0_TXN1_C 10
<7> DP0_TXN1_C LANE1N

2
DP
TXE1+ 29 LCD_TZOUT1+ <22>
DP0_AUXP_C 4 30 LCD_TZOUT1- <22> RV279
<7> DP0_AUXP_C AUX-CH_P TXE1-
Close to LV10 Close to 18 pin Close to 22 pin <7> DP0_AUXN_C
DP0_AUXN_C 3 AUX-CH_N 4.7K_0402_5% ROMLESS
TXE2+ 27 LCD_TZOUT2+ <22>
<7> LVDS_HPD 1 RV327 2 1K_0402_5% LVDS_HPD_OUT 1 28 LCD_TZOUT2- <22>

1
DP_HPD TXE2-

TXE3+ 23
TXE3- 24
C
21 +DVCC33 C
<9> APU_INVT_PWM PWMIN
TP2 2 46 LCD_EDID_CLK LCD_EDID_CLK <22>
TESTMODE MIICSCL1 LCD_EDID_DATA LCD_EDID_DATA RV281 1
1 2 12 DP_REXT MIICSDA1 45 LCD_EDID_DATA <22> 2 4.7K_0402_5%

OTHERS
RV280 12K_0402_1%
20 LCD_ENVDD LCD_ENVDD <22> LCD_EDID_CLK RV282 1 2 4.7K_0402_5%
PANEL_VCC TL_INVT_PWM
PWMOUT 19 TL_INVT_PWM <22>
MIIC_SCL 48 44 EC_ENBKL EC_ENBKL <36>
MIIC_SDA 47 MIICSCL0 BL_EN
MIICSDA0 MIIC_SDA RV283 1 2 4.7K_0402_5%
60 mils CSCL @ CIICSCL CSCL RV285 1
1 2 13 CIICSCL1 DP_GND 6 2 4.7K_0402_5%
+SWR_V12 CSDA RV284 1 @ 2 0_0402_5% CIICSDA 14 CIICSDA1

GND
RV287 0_0402_5% 16 UTLGND1 2 CSDA RV289 1 2 4.7K_0402_5%
GND
22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RV288 0_0402_5%
1 1 1 1 PAD 49
CV327

CV328

CV329

CV330

RTD2136S-CG_QFN48_6X6
2 2 2 2

Close to LV11 Close to 11 pin Close to 43 pin

B B

P
u
l
l
-
L
o
w
1
0
0
K
+3VS_RT

EC_ENBKL

1
2

RV295
CSDA 1 6 EC_SMB_DA3 100K_0402_5%
EC_SMB_DA3 <36>

2
5

QV28A @
2N7002KDWH_SOT363-6
CSCL 4 3 EC_SMB_CK3
EC_SMB_CK3 <36>

QV28B @
2N7002KDWH_SOT363-6

1 2
RV290 0_0402_5%
A A
1 2
RV291 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019IT A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 23, 2012 Sheet 21 of 51
5 4 3 2 1
 A B C D E

+LCD_VDD +3VALW
<21> LCD_TXOUT0+ LCD_TXOUT0+ <21> LCD_TZOUT0+ LCD_TZOUT0+

1
<21> LCD_TXOUT0- LCD_TXOUT0- <21> LCD_TZOUT0- LCD_TZOUT0-

1
R109
<21> LCD_TXOUT1+ LCD_TXOUT1+ <21> LCD_TZOUT1+ LCD_TZOUT1+ 100_0805_5% R108
100K_0402_5% +3VS
<21> LCD_TXOUT1- LCD_TXOUT1- <21> LCD_TZOUT1- LCD_TZOUT1-

2
<21> LCD_TXOUT2+ LCD_TXOUT2+ <21> LCD_TZOUT2+ LCD_TZOUT2+

6
1 <21> LCD_TXOUT2- LCD_TXOUT2- <21> LCD_TZOUT2- LCD_TZOUT2- 2 W=80mils 1
Q1A C228
<21> LCD_TXCLK+ LCD_TXCLK+ <21> LCD_TZCLK+ LCD_TZCLK+ 2 0.047U_0402_25V7K

3
S
2N7002KDWH_SOT363-6
LCD_TXCLK- LCD_TZCLK- 1
R133 2LCDPWR_GATE
G
Q17
<21> LCD_TXCLK- <21> LCD_TZCLK- 1 2

1
68K_0402_5% 1 AO3413_SOT23

3
<21> LCD_EDID_CLK LCD_EDID_CLK D

1
C231 +LCD_VDD
<21> LCD_EDID_DATA LCD_EDID_DATA 4700P_0402_25V7K W=80mils
LCD_ENVDD 2
<21> LCD_ENVDD 5
Q1B 1
2N7002KDWH_SOT363-6 C233

4
0.1U_0402_10V7K

2
R112 2
100K_0402_5%

1
For RF @
C262 47P_0402_50V8J 1 2
1 2 R78 CAM@ 0_0402_5%
@ L55
CAM@ USB20_P4_R USB20_P4 <26>
W=20mils 0.1U_0402_10V7K
3 3 4 4
+3VS 1 CAM@ 2 +3VS_LVDS_CAM 1 2
R388 0_0603_5% C225 USB20_N4_R 2 1 USB20_N4 <26>
JLVDS 2 1
2
1 1 WCM-2012-900T_0805
1 USB20_N4_R
2 2 3
2 3 USB20_P4_R @ D84 AZ5125-02S.R7G_SOT23-3 1 2 2
3

1
4 R96 CAM@ 0_0402_5%
4 INT_MIC_CLK R70
5 5 INT_MIC_CLK <35>
6 INT_MIC_DATA Reserve for EMI request 300_0402_5%
6 INT_MIC_DATA <35>
7 +LCD_VDD @
7
JLVDS1 8 1 1 2A

2
8
9 9 1
12 10 +3VS C226 C227 For RF @ C287
GND 10 LCD_EDID_CLK C258 47P_0402_50V8J
GND 11 11 11 0.1U_0402_10V7K 4.7U_0805_10V4Z 10P_0402_50V8J
LCD_TZOUT0- LCD_EDID_DATA 2 2
10 12 +LCD_VDD 1 2
10 LCD_TZOUT0+ 12 2 @
9 9 13 13
8 LCD_TZOUT1- 14 LCD_TXOUT0-
8 LCD_TZOUT1+ 14 LCD_TXOUT0+
7 7 15 15
6 LCD_TZOUT2- 16 Reserved for EHCI CRC errors
6 LCD_TZOUT2+ 16 LCD_TXOUT1-
5 5 17 17
4 LCD_TZCLK- 18 LCD_TXOUT1+
4 LCD_TZCLK+ 18
3 3 19 19
2 20 LCD_TXOUT2-
2 20 LCD_TXOUT2+ +3VS
1 1 21 21
22 22
23 LCD_TXCLK- 1 LED_PWM 1 2 TL_INVT_PWM <21>
ACES_87036-1001-CP 23 LCD_TXCLK+ D19 RB751V40_SC76-2
24 24
@ 31 25 LED_PWM C232
GND1 25 DISPOFF# 0.1U_0402_10V7K
32 GND2 26 26

1
2
33 GND3 27 27
34 28 R135
GND4 28
35 GND5 29 29 +LCD_INV 47K_0402_5%
36 GND6 30 30 1.5A

2
3 3
1 2
STARC_107K30-000001-G2 @
C263 47P_0402_50V8J 1.5A
For RF +LCD_INV B+
L2
2 1
1 1 FBMA-L11-201209-221LMA30T_0805
C234 C235
68P_0402_50V8J 0.1U_0402_25V6
2 2 DISPOFF# 1 2 BKOFF# <36>
D20 RB751V40_SC76-2
B+
For EMI

1
R730
1 1 1 1 10K_0402_5%
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

2
C236 C268 C489 C490
@ @ @ @
2 2 2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 22 of 51
A B C D E
 A B C D E

CRT CONNECTOR
If=1A
+5VS +CRT_VCC_R +CRT_VCC
D6
2 F1 40 mils
1 1 2
1 3 1 1
0.5A_8V_KMC3S050RY
RB491D_SOT23-3 C237
0.1U_0402_16V4Z
CRT_R L3 2
1 2 NBQ100505T-800Y_0402 CRT_R_L @

CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L

CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L

JCRT
6
11
For PowerXpress T75 PAD

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
R138 R139 R140 CRT_R_L 1

150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 7

1
CRT_DDC_DAT 12
<27> UMA_CRT_R 1 2 CRT_R C238 C239 C240 C241 C242 C243 CRT_G_L 2
R200 0_0402_5% 8 G 16
CRT_G 2 2 2 2 2 2 HSYNC
<27> UMA_CRT_G 1 2 13 G 17
R204 0_0402_5% CRT_B_L 3

2
<27> UMA_CRT_B 1 2 CRT_B +CRT_VCC 9
R211 0_0402_5% VSYNC 14
1 2 CRT_HSYNC T76 PAD 4
<27> UMA_CRT_HSYNC
R213 0_0402_5% 10
1 2 CRT_VSYNC CRT_DDC_CLK 15
<27> UMA_CRT_VSYNC
R235 0_0402_5% 5
<27> UMA_CRT_CLK 1 2 CRT_CLK
R236 0_0402_5% SUYIN_070546FR015S251ZR
<27> UMA_CRT_DATA 1 2 CRT_DATA @
2 R261 0_0402_5% 2
+CRT_VCC

Close to CRT Connector

1 2
C244 0.1U_0402_16V4Z 2 1 D98 @
R141 10K_0402_5% CRT_R_L 6 3 CRT_B_L
For Debug I/O4 I/O2

5
1
P
OE#
CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC
@ CRT_R A Y L6 10_0402_5%
<13> VGA_CRT_R 1 2 +CRT_VCC +CRT_VCC 5 VDD GND 2

G
R178 0_0402_5% U6
1 @ 2 CRT_G SN74AHCT1G125GW_SOT353-5 1 2
<13> VGA_CRT_G

5
1
R181 0_0402_5% C247
1 @ 2 CRT_B 0.1U_0402_16V4Z CRT_G_L 4 1

P
OE#
<13> VGA_CRT_B I/O3 I/O1
R167 0_0402_5% CRT_VSYNC 2 4 D_CRT_VSYNC 1 2 VSYNC
A Y

10P_0402_50V8J

10P_0402_50V8J
1 @ 2 CRT_HSYNC L7 10_0402_5% 1 1 AZC099-04S.R7G_SOT23-6
<13> VGA_CRT_HSYNC

G
R177 0_0402_5% U7
1 @ 2 CRT_VSYNC SN74AHCT1G125GW_SOT353-5 C245 C246
<13> VGA_CRT_VSYNC

3
R179 0_0402_5% @ @ D97 @
@ CRT_CLK 2 2 CRT_DDC_CLK HSYNC
<13> VGA_CRT_CLK 1 2 6 I/O4 I/O2 3
R354 0_0402_5%
<13> VGA_CRT_DATA 1 @ 2 CRT_DATA
R353 0_0402_5%
+CRT_VCC 5 VDD GND 2

Close to CRT Connector +CRT_VCC

CRT_DDC_DAT 4 1 VSYNC
3 I/O3 I/O1 3
AZC099-04S.R7G_SOT23-6
+3VS

2
2/9: Add for ESD request
R153 R159
4.7K_0402_5% 4.7K_0402_5%

1
Q205A 2
CRT_CLK 1 6 CRT_DDC_CLK
5

2N7002DW-T/R7_SOT363-6
Q205B
CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002DW-T/R7_SOT363-6
C284 C283
C282 C285 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 23 of 51
A B C D E
 5 4 3 2 1

OE# A Y

D L L L D

L H H
H X Z
Change R184 and R185 from 2K to 4.7K
for HDMI detect issue on preMP

+HDMI_5V_OUT
+3VS +HDMI_5V_OUT HDMI@
R145
C310 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC+ HDMI_HPD_U 1 2 HDMI_HPD_C
<7> UMA_HDMI_TXC+
2 1K_0402_5%
C321 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC- C264 2
<7> UMA_HDMI_TXC-

2
0.1U_0402_16V4Z R186 C265

1
C326 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0+ HDMI@ U9 100K_0402_5% 0.1U_0402_16V4Z
<7> UMA_HDMI_TX0+ 1 HDMI@ HDMI@

OE#
P
1

1
C313 VGA_DVI_TXD0- HDMI_HPD 1
<7> UMA_HDMI_TX0- 1 2 0.1U_0402_16V7K HDMI@ 2 A Y 4
R184 R185

1
G
C309 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1+ 4.7K_0402_5% 4.7K_0402_5% 74AHCT1G125GW_SOT353-5
<7> UMA_HDMI_TX1+
HDMI@ HDMI@ HDMI@

3
2
C314 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1-
<7> UMA_HDMI_TX1- <7> UMA_HDMI_CLK

2
G
C318 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2+
<7> UMA_HDMI_TX2+
3 1 HDMI_SCLK

2
C322 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2-
<7> UMA_HDMI_TX2-

D
Q18
BSH111_SOT23-3
3 1 HDMI@ HDMI_SDATA HDMI@
C <7> UMA_HDMI_DATA C
2 1 +3VS

D
R571
Q19 2.2K_0402_5%
BSH111_SOT23-3
HDMI@ HDMI_HPD
HDMI_HPD <7>

VGA_DVI_TXC- 1 @ 2 HDMI_R_CK-
R157 0_0402_5%
L8 HDMI@ HDMI_R_CK+ 1 2 HDMI@
1 R195 604_0402_1%
1 2 2 HDMI_R_CK- 1 2 HDMI@
R197 604_0402_1% Add C201 and C214 for EMI request on PVT
4 3 HDMI_R_D1- 1 2 HDMI@
4 3 R198 604_0402_1% HDMI@
KINGCORE WCM-2012HS-670T HDMI_R_D1+ 1 2 HDMI@ D53 F2
VGA_DVI_TXC+ 1 @ 2 HDMI_R_CK+ R202 604_0402_1% +5VS 2 1 +HDMI_5V_OUT_F 1 2 +HDMI_5V_OUT
R173 0_0402_5% HDMI_R_D0+ 1 2 HDMI@ 1 1
D95 @ R201 604_0402_1% PMEG2010AEH_SOD123 0.5A_8V_KMC3S050RY C259 C214
HDMI_R_D0+1 1 109 HDMI_R_D0+ HDMI_R_D0- 1 2 HDMI@ 1 HDMI@ HDMI@ 560P_0402_50V7K

0.1U_0402_16V4Z
VGA_DVI_TXD0- 1 @ 2 HDMI_R_D0- R203 604_0402_1% C201 @
R175 0_0402_5% HDMI_R_D0- 2 2 98 HDMI_R_D0- HDMI_R_D2- 1 560P_0402_50V7K 2 2
2 HDMI@
L9 HDMI@ R205 604_0402_1% @
HDMI_R_D2+ 4 4 7 7 HDMI_R_D2+ HDMI_R_D2+ 1 2
1 1 2 2 2 HDMI@
R206 604_0402_1%
D

1
HDMI_R_D2- 5 5 66 HDMI_R_D2-
4 3 +5VS 2 Q24
4 3 G
3 3 2N7002_SOT23-3
KINGCORE WCM-2012HS-670T S HDMI@

3
VGA_DVI_TXD0+ 1 @ 2 HDMI_R_D0+ 8
B R180 0_0402_5% B

AZ1045-04F_DFN2510P10E-10-9

VGA_DVI_TXD1- 1 @ 2 HDMI_R_D1-
R182 0_0402_5%

1 1
L10 HDMI@
2 2 D94
HDMI Connector
@
HDMI_R_D1+ 1 1 109 HDMI_R_D1+ JHDMI @
4 3 D96 @ HDMI_HPD_C 19
4 3 HDMI_R_D1- 2 2 98 HDMI_R_D1- HDMI_HPD_C HDMI_SDATA HP_DET
6 I/O4 I/O2 3 +HDMI_5V_OUT 18 +5V
KINGCORE WCM-2012HS-670T 17
VGA_DVI_TXD1+ @ HDMI_R_D1+ HDMI_R_CK+ 4 4 7 7 HDMI_R_CK+ HDMI_SDATA DDC/CEC_GND
1 2 16 SDA
R183 0_0402_5% HDMI_SCLK 15
HDMI_R_CK- 5 5 6 6 HDMI_R_CK- SCL
+5VS 5 VDD GND 2 14 Reserved
13 CEC
VGA_DVI_TXD2- 1 @ 2 HDMI_R_D2- 3 3 HDMI_R_CK- 12 20
R187 0_0402_5% CK- GND
11 CK_shield GND 21
L11 HDMI@ 8 4 1 HDMI_SCLK HDMI_R_CK+ 10 22
+HDMI_5V_OUT I/O3 I/O1 CK+ GND
1 HDMI_R_D0-
1 2 2 AZC099-04S.R7G_SOT23-6
9 D0- GND 23
8 D0_shield
AZ1045-04F_DFN2510P10E-10-9 HDMI_R_D0+ 7
HDMI_R_D1- D0+
4 4 3 3 6 D1-
5 D1_shield
KINGCORE WCM-2012HS-670T 2/9: Add for ESD request HDMI_R_D1+ 4
VGA_DVI_TXD2+ @ HDMI_R_D2+ HDMI_R_D2- D1+
1 2 2/9: Add for ESD request 3 D2-
R188 0_0402_5% 2
HDMI_R_D2+ D2_shield
1 D2+
HONGL_13-13201904CP
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 24 of 51
5 4 3 2 1
 A B C D E

U1A HUDM3R3@

HUDSON-2
APU_PCIE_RST#_R AE2 AF3 PCI_CLK0 R257 1 2 22_0402_5% PCIE_RST# is for PCIE devices on APU
PCIE_RST# PCICLK0 CLK_PCI_TPM_FCH <33>
LPC_RST#_R PCI_CLK1

PCI CLKS
AD5 A_RST# PCICLK1/GPO36 AF1 PCI_CLK1 <28>
AF5 APU_PCIE_RST#_R R225 1 2 33_0402_5%
PCICLK2/GPO37 APU_PCIE_RST# <31,32>
C202 1 2 0.1U_0402_16V7K UMI_MTX_FRX_P0 AE30 AG2 PCI_CLK3 Strap
<5> UMI_MTX_C_FRX_P0 UMI_TX0P PCICLK3/GPO38 PCI_CLK3 <28>

2
C203 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N0 AE32 AF6 PCI_CLK4 1
<5> UMI_MTX_C_FRX_N0 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 <28>
C204 1 2 0.1U_0402_16V7K UMI_MTX_FRX_P1 AD33 C221 R223
<5> UMI_MTX_C_FRX_P1 UMI_TX1P
C209 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N1 AD31 AB5 100K_0402_5%
<5> UMI_MTX_C_FRX_N1 UMI_TX1N PCIRST#
C210 1 2 0.1U_0402_16V7K UMI_MTX_FRX_P2 AD28 150P_0402_50V8J @
<5> UMI_MTX_C_FRX_P2 UMI_TX2P 2
C211 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N2 AD29
<5> UMI_MTX_C_FRX_N2

1
C213 0.1U_0402_16V7K UMI_MTX_FRX_P3 UMI_TX2N
<5> UMI_MTX_C_FRX_P3 1 2 AC30 UMI_TX3P AD0/GPIO0 AJ3
C212 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N3 AC32 AL5
<5> UMI_MTX_C_FRX_N3 UMI_TX3N AD1/GPIO1
1 UMI_FTX_C_MRX_P0 AD2/GPIO2 AG4
RV61 2 @
A_RST# is for LPC devices 1
<5> UMI_FTX_C_MRX_P0 AB33 UMI_RX0P AD3/GPIO3 AL6 1 0_0402_5%
UMI_FTX_C_MRX_N0 AB31 AH3 LPC_RST#_R R226 1 2 33_0402_5%

PCI EXPRESS INTERFACES

<5> UMI_FTX_C_MRX_N0 UMI_RX0N AD4/GPIO4 LPC_RST# <33,36,37>
UMI_FTX_C_MRX_P1 AB28 AJ5
<5> UMI_FTX_C_MRX_P1 UMI_RX1P AD5/GPIO5

2
UMI_FTX_C_MRX_N1 AB29 AL1 +3VGS
<5> UMI_FTX_C_MRX_N1 UMI_RX1N AD6/GPIO6 1
UMI_FTX_C_MRX_P2 Y33 AN5 C251 0.1U_0402_16V4Z C222 R224
<5> UMI_FTX_C_MRX_P2 UMI_RX2P AD7/GPIO7
UMI_FTX_C_MRX_N2 Y31 AN6 1 2 100K_0402_5%
<5> UMI_FTX_C_MRX_N2 UMI_RX2N AD8/GPIO8
UMI_FTX_C_MRX_P3 Y28 AJ1 150P_0402_50V8J @
<5> UMI_FTX_C_MRX_P3 UMI_RX3P AD9/GPIO9

5
UMI_FTX_C_MRX_N3 UV13 2
<5> UMI_FTX_C_MRX_N3 Y29 AL8

1
UMI_RX3N AD10/GPIO10 PXS_RST#
AL3 2

P
R220 1 AD11/GPIO11 B
2 590_0402_1% PCIE_CALRP AF29 PCIE_CALRP AD12/GPIO12 AM7 Y 4 GPU_RST# <12>
+PCIE_VDDR_FCH R221 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRN AD13/GPIO13 AJ6 APU_PCIE_RST# 1 A

G
AD14/GPIO14 AK7
V33 AN8

3
GPP_TX0P AD15/GPIO15 MC74VHC1G08DFT2G SC70 5P
V31 GPP_TX0N AD16/GPIO16 AG9
W30 GPP_TX1P AD17/GPIO17 AM11
W32 GPP_TX1N AD18/GPIO18 AJ10
AB26 GPP_TX2P AD19/GPIO19 AL12
AB27 GPP_TX2N AD20/GPIO20 AK11
AA24 GPP_TX3P AD21/GPIO21 AN12
AA23 AG12 +3VS
GPP_TX3N AD22/GPIO22 PCI_AD23
AD23/GPIO23 AE12 PCI_AD23 <28>
AA27 AC12 PCI_AD24
GPP_RX0P AD24/GPIO24 PCI_AD24 <28>
PCI_AD25 GPIO30 @
AA26 GPP_RX0N AD25/GPIO25 AE13 PCI_AD25 <28> Strap 1 2 1 2
W27 PCI_AD26 R337 10K_0402_5% R332 10K_0402_5%

PCI INTERFACE
GPP_RX1P AD26/GPIO26 AF13 PCI_AD26 <28>
V27 AH13 PCI_AD27
GPP_RX1N AD27/GPIO27 PCI_AD27 <28>
V26 AH14 VGA_PWRGD_R 1 @ 2 VGA_PWRGD <26,49> 1 2 GPIO31 1 @ 2
GPP_RX2P AD28/GPIO28 R254 0_0402_5% R340 10K_0402_5% R339 10K_0402_5%
W26 GPP_RX2N AD29/GPIO29 AD15
W24 AC15 GPIO30 Change to GPIO51
GPP_RX3P AD30/GPIO30 GPIO31
W23 GPP_RX3N AD31/GPIO31 AE16
CBE0# AN3
CBE1# AJ8
CBE2# AN10
2 2
+1.1VS_CKVDD R228 1 2 2K_0402_1% CLK_CALRN F27 CLK_CALRN CBE3# AD12
FRAME# AG10
DEVSEL# AK9
Input from external clock generator IRDY# AL10 Function GPIO30 GPIO31
G30 PCIE_RCLKP TRDY# AF10
NC for internal clock generator PowerXpress 0 0
SS G28 PCIE_RCLKN PAR AE10
AH1
APU_DISP_CLKP STOP#
<7> APU_DISP_CLKP R26 DISP_CLKP PERR# AM9 Reserved 0 1
APU Display APU_DISP_CLKN T26 AH8
<7> APU_DISP_CLKN DISP_CLKN SERR#
REQ0# AG15 Discrete 1 0
NSS H33
H31
DISP2_CLKP REQ1#/GPIO40 AG13
AF15 UMA 1 1
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42 AM17
APU_CLKP T24 AD16
<7> APU_CLKP APU_CLKP GNT0#
APU APU_CLKN T23 AD13 R227 1 @ 2 0_0402_5%
<7> APU_CLKN APU_CLKN GNT1#/GPO44 PXS_RST# <26>
AD21 R252 1 @ 2 0_0402_5%
GNT2#/SD_LED/GPO45 PXS_PWREN <14,26,44,49>
CLK_PCIE_VGA J30 AK17
<12> CLK_PCIE_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46
GPU CLK_PCIE_VGA# K29 AD19
<12> CLK_PCIE_VGA# SLT_GFX_CLKN CLKRUN#
LOCK# AH9
H27 GPP_CLK0P +RTCBATT_D +RTCBATT

NOGCLK@
H28 GPP_CLK0N INTE#/GPIO32 AF18

0.1U_0402_10V7K

RB751V-40_SOD323-2
INTF#/GPIO33 AE18
J27 GPP_CLK1P INTG#/GPIO34 AC16 1

C256
K26 GPP_CLK1N INTH#/GPIO35 AD18

1
CLK_WLAN F33 D13
CLOCK GENERATOR

<31> CLK_WLAN GPP_CLK2P 2

D14
WLAN CLK_WLAN# F31 RB751V-40_SOD323-2
<31> CLK_WLAN# GPP_CLK2N LPC_CLK0 R255 1 2 22_0402_5%
SS CLK_LAN E33
LPCCLK0 B25 CLK_PCI_EC <28,36>
Strap
<32> CLK_LAN

2
CLK_LAN# GPP_CLK3P LPC_CLK1 R258 1
LAN <32> CLK_LAN# E31 GPP_CLK3N LPCCLK1 D25 2 22_0402_5% CLK_PCI_DDR <28,37>
D27 LPC_AD0 +RTCBATT
LAD0 LPC_AD0 <33,36,37> +3VL
M23 C28 LPC_AD1
3 GPP_CLK4P LAD1 LPC_AD1 <33,36,37> 3
M24 A26 LPC_AD2 LPC_AD2 <33,36,37>
GPP_CLK4N LAD2 LPC_AD3
LPC

LAD3 A29 LPC_AD3 <33,36,37>

M27 A31 LPC_FRAME# If use GCLK, please delete D14
GPP_CLK5P LFRAME# LPC_FRAME# <33,36,37>
M26 GPP_CLK5N LDRQ0# B27
Place close to Y2 LDRQ1#/CLK_REQ6#/GPIO49 AE27
N25 AE19 SERIRQ SERIRQ <33,36>
GCLK@ GPP_CLK6P SERIRQ/GPIO48
N26 GPP_CLK6N
1 2 32K_X1 DMA active. The FCH drives the DMA_ACTIVE# to
<31> FCH_RTCX1_R
R207 0_0402_5% R23
R24
GPP_CLK7P
G25 DMA_ACTIVE# APU to notify DMA activity. This will cause the APU
GPP_CLK7N DMA_ACTIVE# DMA_ACTIVE# <7>
PROCHOT# E28 APU_PROCHOT#
APU_PROCHOT# <7> to reestablish the UMI link quicker.
GCLK@ N27 E26 APU_PWRGD
GPP_CLK8P APU_PG APU_PWRGD <7,47>
25M_X1
APU

<31> FCH_X1_R 1 2 R27 GPP_CLK8N LDT_STP# G26 S5_CORE_EN is for S5+ mode
R208 0_0402_5% F26 APU_RST#
APU_RST# APU_RST# <7> used to turn off +1.1VALW and
Place close to Y1 J26 14M_25M_48M_OSC
+3VALW of FCH on S5+ mode
S5_CORE_EN H7 T25
F1 RTC_CLK_R 1 2 Strap
RTCCLK RTC_CLK <28,36>
F3 R260 0_0402_5%
NOGCLK@ C220 1 INTRUDER_ALERT#
2 27P_0402_50V8J 25M_X1 C31 25M_X1 VDDBT_RTC_G E6 +RTCVCC_R
S5 PLUS
1

G2 32K_X1
Y1 R229 32K_X1
NOGCLK@ 1M_0402_5% 25M_X2 C33 +RTCVCC +RTCBATT_D
25MHZ_20PF_7A25000012 NOGCLK@ 25M_X2
2

G4 32K_X2 20 mils R271 R277 R268

32K_X2
1 2 1 2 1 2+RTCBATT_R 1 2
NOGCLK@ C230 27P_0402_50V8J 120_0402_5% 120_0402_5% 1K_0402_5%
1 1

1
HUDSON-M3_FCBGA656 C250 C252 JCMOS 1
@ C295
0.1U_0402_16V4Z 1U_0402_6.3V6K

2
4 2 2 0.1U_0402_16V4Z 4
NOGCLK@ C248 1 32K_X1 2
2 18P_0402_50V8J

CMOS Setting
1

Y2
R230 32.768KHZ_12.5P_1TJF125DP1A000D Place under DDR
20M_0402_5% NOGCLK@ Door
NOGCLK@
Security Classification Compal Secret Data Compal Electronics, Inc.
1
2

1 2 32K_X2 2011/11/28 2013/12/31 Title

NOGCLK@ C249 18P_0402_50V8J
Issued Date Deciphered Date
Change C248/C249 to 18P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number Rev
for RTC issue on pre-MP AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 25 of 51
A B C D E
 A B C D E

PCIE_RST2# is for PCIE devices on FCH U1D HUDM3R3@

HUDSON-2
T50

USB MISC
AB6 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC G8
EC_LID_OUT# R2
<36> EC_LID_OUT# RI#/GEVENT22#
T57 W7 B9 USB_RCOMP R329 1 2 11.8K_0402_1%
SLP_S3# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
<36> SLP_S3# T3 SLP_S3#
SLP_S5# W2 H1
<36> SLP_S5# SLP_S5# USB_FSD1P/GPIO186
For FCH internal debug use PBTN_OUT# J4 H3
+3VALW_FCH <36> PBTN_OUT# PWR_BTN# USB_FSD1N
FCH_PWRGD N7 Hudson-M2/M3
(Internal 10K pull-down) <36> FCH_PWRGD PWR_GOOD

USB 1.1
H6

ACPI / WAKE UP EVENTS

TEST0 T9
USB_FSD0P/GPIO185
H5
OHCI (DEV-20, FUN-5)
@ TEST0 TEST1 TEST0 USB_FSD0N
1 2 T10 TEST1/TMS
R273 2.2K_0402_5% TEST2 V9 H10
1 TEST2 USB_HSD13P 1
1 @ 2 TEST1 G10
R274 2.2K_0402_5% GATEA20 USB_HSD13N
<36> GATEA20 AE22 GA20IN/GEVENT0# Hudson-M2
1 @ 2 TEST2 K10
R275 2.2K_0402_5% KB_RST#
AG19
USB_HSD12P
J12
OHCI (DEV-22, FUN-0)
<36> KB_RST# KBRST#/GEVENT1# USB_HSD12N
<36> EC_SCI#
EC_SCI#
R9 LPC_PME#/GEVENT3#
EHCI (DEV-22, FUN-2)
EC_SMI#
C26 G12 USB20_P11
<36> EC_SMI# LPC_SMI#/GEVENT23# USB_HSD11P USB20_P11 <34>
T31
T5 F12 USB20_N11 USB 3.0-Left2 Hudson-M3
LPC_PD#/GEVENT5# USB_HSD11N USB20_N11 <34>
U4
FCH_PCIE_WAKE# K1
SYS_RESET#/GEVENT19#
K12 USB20_P10 XHCI (DEV-16, FUN-0)
<32> FCH_PCIE_WAKE# WAKE#/GEVENT8# USB_HSD10P USB20_P10 <34>
T55 V7 IR_RX1/GEVENT20# USB_HSD10N K13 USB20_N10
USB20_N10 <34> USB 3.0-Left1 XHCI (DEV-16, FUN-1)
H_THERMTRIP# R10
<7> H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2#
+3VS 1 2 WD_PWRGD AF19 B11
R279 10K_0402_5% WD_PWRGD USB_HSD9P
USB_HSD9N D11
EC_RSMRST# U2
<36> EC_RSMRST# RSMRST#
USB_HSD8P E10
AG24 CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N F10
CLKREQ_LAN# AE24 Hudson-M2/M3
<32> CLKREQ_LAN# CLK_REQ3#/SATA_IS1#/GPIO63
AE26 C10
AF22
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P
A10
OHCI (DEV-19, FUN-0)

USB 2.0
CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N
AH17 SATA_IS4#/FANOUT3/GPIO55
EHCI (DEV-19, FUN-2)
AG18 SATA_IS5#/FANIN3/GPIO59 USB_HSD6P H9
FCH_SPKR AF24 G9
<35> FCH_SPKR SPKR/GPIO66 USB_HSD6N
FCH_SCLK0

GPIO
<10,11,31> FCH_SCLK0 AD26 SCL0/GPIO43
SM Bus 0-->S0 PWR domain FCH_SDATA0 AD25 A8
<10,11,31> FCH_SDATA0 SDA0/GPIO47 USB_HSD5P
FCH_SCLK1 T7 C8
SM Bus 1-->S5 PWR domain FCH_SDATA1 R7
SCL1/GPIO227 USB_HSD5N
SDA1/GPIO228
(for ASF device only) <31> CLKREQ_WLAN#
CLKREQ_WLAN# AG25 CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P F8 USB20_P4
USB20_P4 <22>
AG22 E8 USB20_N4 Int. Camera
CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N USB20_N4 <22>
T30 J2 IR_LED#/LLB#/GPIO184 USB20_P3
<25,49> VGA_PWRGD AG26 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P C6 USB20_P3 <31>
V8 A6 USB20_N3 WLAN (BT) Hudson-M2/M3
DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N USB20_N3 <31>
LAN_EN W8
<32> LAN_EN
T54 Y6
GBE_LED0/GPIO183
C5 USB20_P2 OHCI (DEV-18, FUN-0)
2 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P USB20_P2 <33> 2
VGA_PD: Support CRT power saving V10 GBE_LED2/GEVENT10# USB_HSD2N A5 USB20_N2
USB20_N2 <33> Cardreader EHCI (DEV-18, FUN-2)
AA8
L: MLDAC power on R295 1 2 0_0402_5% AF25
GBE_STAT0/GEVENT11#
C1 USB20_P1 <Support Wakeup>
<13> PEG_CLKREQ# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P USB20_P1 <30>
H: MLDAC power off USB_HSD1N C3 USB20_N1
USB20_N1 <30> USB-Right2
R113 2 @ 1 100K_0402_5%
M7 E1 USB20_P0 USB-Right1
BLINK/USB_OC7#/GEVENT18# USB_HSD0P USB20_P0 <30>
ODD_DA#_FCH R8 E3 USB20_N0
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 <30> (Debug Port)
T59

USB OC
T1 USB_OC5#/IR_TX0/GEVENT17#
ODD_PLUGIN# P6 C16 USBSS_CALRP R330 1 2 1K_0402_1%
<30> ODD_PLUGIN# USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP
T58 F5 A16 USBSS_CALRN R334 1 2 1K_0402_1%
T56 USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN
P5 USB_OC2#/TCK/GEVENT14# +FCH_VDD_11_SSUSB_S
USB_OC1# is for left USB3.0 ports USB_OC1# J7 A14
<34> USB_OC1# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
USB_OC0# is for right USB2.0 ports USB_OC0# T8 C14
<30> USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N

USB_SS_RX3P C12
USB_SS_RX3N A12

R320 1 2 33_0402_5% HDA_BITCLK AB3 D15

<35> AZ_BITCLK_HD AZ_BITCLK USB_SS_TX2P
R321 1 2 33_0402_5% HDA_SDOUT AB1 B15
<35> AZ_SDOUT_HD AZ_SDOUT USB_SS_TX2N
AZ_SDIN0_HD

HD AUDIO
<35> AZ_SDIN0_HD AA2 AZ_SDIN0/GPIO167
AZ_SDIN1_HD Y5 E14 Hudson-M3

USB 3.0
AZ_SDIN2_HD AZ_SDIN1/GPIO168 USB_SS_RX2P
Y3 F14
AZ_SDIN3_HD Y1
AZ_SDIN2/GPIO169 USB_SS_RX2N XHCI (DEV-16, FUN-0)
AZ_SDIN3/GPIO170
<35> AZ_SYNC_HD
R322 1 2 33_0402_5% HDA_SYNC AD6 AZ_SYNC USB_SS_TX1P F15 USB30_TX1P
USB30_TX1P <34> XHCI (DEV-16, FUN-1)
R323 1 2 33_0402_5% HDA_RST# AE4 G15 USB30_TX1N
<35> AZ_RST_HD# AZ_RST# USB_SS_TX1N USB30_TX1N <34>
USB30_RX1P
USB 3.0-Left2
USB_SS_RX1P H13 USB30_RX1P <34>
G13 USB30_RX1N
USB_SS_RX1N USB30_RX1N <34>
T26 K19 J16 USB30_TX0P
PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB30_TX0P <34>
T27 J19 H16 USB30_TX0N
PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB30_TX0N <34>
J21 SPI_CS2#/GBE_STAT2/GPIO166 USB30_RX0P
USB 3.0-Left1
USB_SS_RX0P J15 USB30_RX0P <34>
3 K15 USB30_RX0N 3
USB_SS_RX0N USB30_RX0N <34>
D21 PS2KB_DAT/GPIO189
C20 H19 R326 1 2 10K_0402_5% SM Bus 2-->S5 PWR domain
PS2KB_CLK/GPIO190 SCL2/GPIO193 R328 10K_0402_5%
<25> PXS_RST# D23 PS2M_DAT/GPIO191 SDA2/GPIO194 G19 1 2
PXS_PWREN C22 EMBEDDED CTRL G22 R338 1 2 10K_0402_5%
+3VALW_FCH <14,25,44,49> PXS_PWREN PS2M_CLK/GPIO192 SCL3_LV/GPIO195
G21 R343 1 2 10K_0402_5%
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197 E22
1 @ 2 H_THERMTRIP# H22
R278 10K_0402_5% T33 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2
F21 KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 J22 EC_PWM2 <28> Strap
1 @ 2 EC_LID_OUT# T32 E20 H21
R272 10K_0402_5% T35 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
F20 KSO_2/GPIO211
1 2 FCH_PCIE_WAKE# T34 A22 K21
R276 10K_0402_5% +3VS T37 KSO_3/GPIO212 KSI_0/GPIO201
E18 KSO_4/GPIO213 KSI_1/GPIO202 K22
1 2 USB_OC0# T36 A20 F22
R318 10K_0402_5% FCH_SCLK0 T38 KSO_5/GPIO214 KSI_2/GPIO203
1 2 J18 KSO_6/GPIO215 KSI_3/GPIO204 F24
1 2 USB_OC1# R286 2.2K_0402_5% T39 H18 E24
R319 10K_0402_5% FCH_SDATA0 T45 KSO_7/GPIO216 KSI_4/GPIO205
1 2 G18 KSO_8/GPIO217 KSI_5/GPIO206 B23
1 2 FCH_SCLK1 R287 2.2K_0402_5% T44 B21 C24
R288 10K_0402_5% @ CLKREQ_WLAN# T46 KSO_9/GPIO218 KSI_6/GPIO207
1 2 K18 KSO_10/GPIO219 KSI_7/GPIO208 F18
1 2 FCH_SDATA1 R291 8.2K_0402_5% T47 D19
R289 10K_0402_5% @ CLKREQ_LAN# T41 KSO_11/GPIO220
1 2 A18 KSO_12/GPIO221
1 2 PXS_PWREN R284 8.2K_0402_5% T40 C18 +3VALW_FCH +3VS
R292 10K_0402_5% T42 KSO_13/GPIO222
B19 KSO_14/GPIO223
T43 B17 +3VS
KSO_15/GPIO224

2
T49 A24
T48 KSO_16/GPIO225 R312 R311
D17 KSO_17/GPIO226 Place R425 and C363
10K_0402_5% 10K_0402_5%
close to FCH for ESD @

2
HUDSON-M3_FCBGA656

1
Q32A
1 @ 2 PXS_PWREN ODD_DA#_FCH 1 @ 2 ODD_DA#_Q 6 1 ODD_DA# <30>
R293 10K_0402_5% 1 R425 0_0402_5%
4 2 1 EC_RSMRST# C363 2N7002DW-T/R7_SOT363-6 4
R280 100K_0402_5% Q5530A 0.1U_0402_16V4Z
1 @ 2 HDA_BITCLK 2N7002KDWH_SOT363-6 @
R324 10K_0402_5% PXS_PWREN 2
6 1
1 @ 2 AZ_SDIN0_HD
R325 10K_0402_5% Q5530B +3VALW_FCH
1 @ 2 PXS_RST# 2N7002KDWH_SOT363-6
2

R290 1K_0402_5% 4 3 10K_0402_5% 2 1 R216

1 @ 2 AZ_SDIN1_HD
R331 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 @ 2 AZ_SDIN2_HD EC_PXCONTROL 2011/11/28 2013/12/31 Title
EC_PXCONTROL <36> Issued Date Deciphered Date
5

R333 10K_0402_5%
1 @ 2 AZ_SDIN3_HD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
R335 10K_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 26 of 51
A B C D E
 A B C D E

U1B HUDM3R3@

HUDSON-2
HDMI_EN# (Internal 8.2K PU)
HDMI@
SATA_FTX_DRX_P0 HDMI_EN#
<30> SATA_FTX_DRX_P0
SATA_FTX_DRX_N0
AK19 SATA_TX0P SD_CLK/SCLK_2/GPIO73 AL14 2
R443
1
1K_0402_1%
Need HDMI_EN# Strap ? HDMI_EN#
<30> SATA_FTX_DRX_N0 AM19 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 AN14 H L
HDD SATA_FRX_C_DTX_N0 SD_CD/GPIO75 AJ12
<30> SATA_FRX_C_DTX_N0 AL20 SATA_RX0N SD_WP/GPIO76 AH12

SD CARD
SATA_FRX_C_DTX_P0 AN20 AK13 Non-HDMI
<30> SATA_FRX_C_DTX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78 AM13 SKU SKU HDMI SKU
SATA_FTX_DRX_P1 AN22 AH15
<30> SATA_FTX_DRX_P1 SATA_TX1P SD_DATA2/GPIO79
SATA_FTX_DRX_N1 AL22 AJ14
<30> SATA_FTX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80
14" ODD SATA_FRX_C_DTX_N1
<30> SATA_FRX_C_DTX_N1 AH20 SATA_RX1N GBE_COL AC4
SATA_FRX_C_DTX_P1 AJ20 AD3
<30> SATA_FRX_C_DTX_P1 SATA_RX1P GBE_CRS
GBE_MDCK AD9
SATA_FTX_DRX_P2 AJ22 W10
<30> SATA_FTX_DRX_P2 SATA_TX2P GBE_MDIO
1 SATA_FTX_DRX_N2 AH22 AB8 1
<30> SATA_FTX_DRX_N2 SATA_TX2N GBE_RXCLK
15"/17" ODD SATA_FRX_C_DTX_N2 GBE_RXD3 AH7
<30> SATA_FRX_C_DTX_N2 AM23 SATA_RX2N GBE_RXD2 AF7 If an SPI ROM is shared between FCH
SATA_FRX_C_DTX_P2 AK23 AE7
<30> SATA_FRX_C_DTX_P2 SATA_RX2P GBE_RXD1 and the Embedded Controller, a 10-k
GBE_RXD0 AD7
AH24 SATA_TX3P GBE_RXCTL/RXDV AG8 pull-up resistor to +3.3V_S5 is installed
AJ24 SATA_TX3N GBE_RXERR AD1
AB7

GBE LAN
GBE_TXCLK +3VALW_FCH
AN24 SATA_RX3N GBE_TXD3 AF9
AL24 SATA_RX3P GBE_TXD2 AG6
+1.5V AE8
+3VALW_FCH GBE_TXD1 FCH_SPI_CS1# @
AL26 SATA_TX4P GBE_TXD0 AD8 1 2
AN26 AB9 R137 10K_0402_5%
SATA_TX4N GBE_TXCTL/TXEN
1

AC2

SERIAL ATA
GBE_PHY_PD

1
R285 AJ26 AA7
10K_0402_5% R437 SATA_RX4N GBE_PHY_RST# GBE_PHY_INTR
AH26 SATA_RX4P GBE_PHY_INTR W9 1 2 +3VALW_FCH
@ 10K_0402_5% R352 10K_0402_5%
AN29
2 2

SATA_TX5P FCH_SPI_MISO
2 AL28 SATA_TX5N SPI_DI/GPIO164 V6
B

@ V5 FCH_SPI_MOSI
SPI_DO/GPIO163 +3VS

SPI ROM
Q33 AK27 V3 FCH_SPI_CLK
SATA_RX5N SPI_CLK/GPIO162
E

3 1 FCH_ALERT# AM27 T6 FCH_SPI_CS1#

<7> APU_ALERT# SATA_RX5P SPI_CS1#/GPIO165
C

ROM_RST#/SPI_WP#/GPIO161 V1
MMBT3904_NL_SOT23-3 AL29 UMA_CRT_DATA 1 2
NC6 R454 2.2K_0402_5%
AN31 NC7
L30 UMA_CRT_R UMA_CRT_CLK 1 2
VGA_RED UMA_CRT_R <23>
AL31 R455 2.2K_0402_5%
NC8
AL33 NC9
L32 UMA_CRT_G
VGA_GREEN UMA_CRT_G <23>
AH33 NC10
AH31 UMA_CRT_R 1 2
NC11 UMA_CRT_B R367 150_0402_1%
VGA_BLUE M29 UMA_CRT_B <23>
AJ33 UMA_CRT_G 1 2

VGA DAC
NC12 R368 150_0402_1%
AJ31 NC13
M28 UMA_CRT_HSYNC UMA_CRT_B 1 2
VGA_HSYNC/GPO68 UMA_CRT_HSYNC <23>
To avoid LED flashing N30 UMA_CRT_VSYNC R369 150_0402_1%
VGA_VSYNC/GPO69 UMA_CRT_VSYNC <23>

2 M33 UMA_CRT_DATA 2
+5VS VGA_DDC_SDA/GPO70 UMA_CRT_DATA <23>
2 1 SATA_CALRP AF28 N32 UMA_CRT_CLK
SATA_CALRP VGA_DDC_SCL/GPO71 UMA_CRT_CLK <23>
R336 1K_0402_1%
1 2 SATA_LED# +AVDD_SATA 2 1 SATA_CALRN AF27
R444 10K_0402_5% R130 931_0402_1% SATA_CALRN VGA_DAC_RSET
VGA_DAC_RSET K31 1 2
2 1 R366 715_0402_1%
R446 20K_0402_5% SATA_LED# AD22
<38> SATA_LED# SATA_ACT#/GPIO67
V28 ML_VGA_AUXP
AUX_VGA_CH_P ML_VGA_AUXP <7>
V29 ML_VGA_AUXN
AUX_VGA_CH_N ML_VGA_AUXN <7>
AF21

VGA MAINLINK
SATA_X1 AUXCAL
AUXCAL U28 1 2 +VDDAN_11_ML
R364 100_0402_1%
T31 ML_VGA_TXP0
ML_VGA_L0P ML_VGA_TXP0 <7>
T33 ML_VGA_TXN0
ML_VGA_L0N ML_VGA_TXN0 <7>
AG21 T29 ML_VGA_TXP1
SATA_X2 ML_VGA_L1P ML_VGA_TXP1 <7> +FCH_VDDAN_33_DAC_R
T28 ML_VGA_TXN1
ML_VGA_L1N ML_VGA_TXN1 <7>
R32 ML_VGA_TXP2
+3VS ML_VGA_L2P ML_VGA_TXP2 <7>
R30 ML_VGA_TXN2 FCH_CRT_HPD 1 2
ML_VGA_L2N ML_VGA_TXN2 <7>
ODD_SEL SATA port SKU ML_VGA_L3P P29
P28
ML_VGA_TXP3
ML_VGA_TXN3
ML_VGA_TXP3 <7>
R365 10K_0402_5%
ML_VGA_L3N ML_VGA_TXN3 <7>
2

High Port 1 14" R146

10K_0402_5%
ML_VGA_HPD/GPIO229 C29 FCH_CRT_HPD
FCH_CRT_HPD <7>

AH16 N2 1 2
1

FANOUT0/GPIO52 VIN0/GPIO175
Low Port 2 15"/17" ODD_SEL
AM15
AJ16
FANOUT1/GPIO53 HW MONITOR M3
R101
1 2
10K_0402_5%
<30> ODD_SEL FANOUT2/GPIO54 VIN1/GPIO176 R102 10K_0402_5%
AK15 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177 L2 1 2
T16 AN16 R105 10K_0402_5%
FANIN1/GPIO57
AL16 FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 N4 1 2
R106 10K_0402_5%
VIN4/SLOAD_1/GPIO179 P1 1 2
ODD_PWR K6 R128 10K_0402_5%
<39> ODD_PWR TEMPIN0/GPIO171
P3 SLP_CHG#1 2
VIN5/SCLK_1/GPIO180 R134 10K_0402_5%
3 1 2 K5 TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 M1 1 2 3
R111 10K_0402_5% R115 10K_0402_5% Enable integrated pull-down/up
M5 1 2
1 2 K3
VIN7/GBE_LED3/GPIO182 R114 10K_0402_5% and leave unconnected
R103 10K_0402_5% TEMPIN2/GPIO173

NC1 AG16
FCH_ALERT# M6 AH10
TEMPIN3/TALERT#/GPIO174 NC2
NC3 A28
NC4 G27
NC5 L4

HUDSON-M3_FCBGA656

+3VALW_FCH

SLP_CHG# 1 @ 2
<34> SLP_CHG#
R126 10K_0402_5%

+3VALW_FCH
4M Byte C498
1 2
U13
FCH_SPI_CS1# 1 8 0.1U_0402_16V4Z
FCH_SPI_MISO CS# VCC
2 SO/SIO1 HOLD# 7
+3VALW_FCH 3 6 FCH_SPI_CLK
WP# SCLK FCH_SPI_MOSI
4 GND SI/SIO0 5

MX25L3206EM2I-12G_SO8
For EMI
@ @
R402 C257
4 FCH_SPI_CLK 2 1 2 1 4
10_0402_5%
10P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 27 of 51
A B C D E
 A B C D E

STRAP PINS CRT Power Down

Circuit
PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK
+3VS +FCH_VDDAN_33_DAC_R
1 1
PULL ALLOW ENABLE NON_FUSION EC CLKGEN LPC ROM S5 PLUS
L32
HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED (INTERNAL MODE
1 2
STRAP 10K PULL-UP) DISABLED MBK1608221YZF_2P

2.2U_0603_6.3V6K
DEFAULT DEFAULT DEFAULT

0.1U_0402_16V7K
1 1
PULL FORCE DISABLE FUSION EC CLKGEN SPI ROM S5 PLUS C277 C276
LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE
STRAP MODE ENABLED 2 2
DEFAULT DEFAULT DEFAULT DEFAULT

+3VS +3VS +3VS +3VALW_FCH +3VALW_FCH +3VALW_FCH +3VALW_FCH

1

1
R231 R241 R242 R243 R238 R245 R240
@ @ @ @
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
2

2
PCI_CLK1
<25> PCI_CLK1
PCI_CLK3
2 <25> PCI_CLK3 2
PCI_CLK4
<25> PCI_CLK4
CLK_PCI_EC
<25,36> CLK_PCI_EC
CLK_PCI_DDR
<25,37> CLK_PCI_DDR
EC_PWM2
<26> EC_PWM2
RTC_CLK
<25,36> RTC_CLK
1

1
R232 R233 R234 R237 R244 R239 R246
@ @ @
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2

2
DEBUG STRAPS
FCH HAS 15K INTERNAL PU-UP FOR PCI_AD[27:23]
3 3

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

+3VALW
USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI
PULL PLL ILA PLL PCIE STRAPS MEM BOOT
HIGH AUTORUN
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 2
C523 Vgs=-4.5V,Id=3A,Rds<97mohm

PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI 0.1U_0402_10V7K

2
1
LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT S

3
R5 Q3 PJ2

2
AUTORUN 1 2 2
G
JUMP_43X79
<39> FCH_PWR_EN#
@
+3VALW_FCH

1
47K_0402_5% 2 AO3413_SOT23 D

1
C521
0.01U_0402_25V7K
PCI_AD27 1
<25> PCI_AD27 2
1
PCI_AD26 C520
<25> PCI_AD26
C522 1U_0402_6.3V6K
PCI_AD25 4.7U_0805_10V4Z 1
<25> PCI_AD25 2
PCI_AD24
<25> PCI_AD24
PCI_AD23
<25> PCI_AD23

4 4
1

R247 R248 R249 R250 R251

@ @ @ @ @
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 28 of 51
A B C D E
 A B C D E

+VCC_FCH_R +1.1VS
U1C HUDM3R3@ U1E HUDM3R3@
+3VS +VCC_FCH_R
10mils HUDSON-2
1 2
HUDSON-2

2.2U_0603_6.3V6K
50mils R193 0_0805_5%

0.1U_0402_16V7K

0.1U_0402_16V7K
+3VS

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0805_6.3V6M
1 2 +VDDIO_33_PCIGP AB17 T14 A3 T25
VDDIO_33_PCIGP_1 VDDCR_11_1 VSS VSS

22U_0805_6.3V6M
L30 R20 0_0603_5% AB18 T17 1 1 1 1 1 1 A33 T27
VDDIO_33_PCIGP_2 VDDCR_11_2 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VDDPL_3.3V C311 C312 C334 C335 C315 C317

PCI/GPIO I/O
1 2 AE9 VDDIO_33_PCIGP_3 VDDCR_11_3 T20 B7 VSS VSS U6

2.2U_0603_6.3V6K
MBK1608221YZF_2P

0.1U_0402_16V7K
1 1 1 1 1 AD10 VDDIO_33_PCIGP_4 VDDCR_11_4 U16 B13 VSS VSS U14
220 ohm C266 C267 C269 C270 C271 AG7 102mA 1007mA U18 D9 U17
VDDIO_33_PCIGP_5 VDDCR_11_5 2 2 2 2 2 2 VSS VSS

CORE S0
1 1 AC13 VDDIO_33_PCIGP_6 VDDCR_11_6 V14 D13 VSS VSS U20
C272 C273 AB12 V17 E5 U21
1 2 2 2 2 2 VDDIO_33_PCIGP_7 VDDCR_11_7 VSS VSS 1
AB13 VDDIO_33_PCIGP_8 VDDCR_11_8 V20 E12 VSS VSS U30
AB14 VDDIO_33_PCIGP_9 VDDCR_11_9 Y17 E16 VSS VSS U32
2 2 +1.1VS_CKVDD +1.1VS
AB16 VDDIO_33_PCIGP_10 E29 VSS VSS V11
+VDDPL_3.3V
10mils 20mils +1.1VS_CKVDD
F7 VSS VSS V16
H24 VDDPL_33_SYS 47mA VDDAN_11_CLK_1 H26 1 2 F9 VSS VSS V18

2.2U_0603_6.3V6K
10mils R371 0_0603_5%

0.1U_0402_16V7K

0.1U_0402_16V7K
VDDAN_11_CLK_2 J25 F11 VSS VSS W4
+FCH_VDDAN_33_DAC_R

1U_0402_6.3V6K

1U_0402_6.3V6K
+FCH_VDDPL_33_MLDAC +VDDPL_33_DAC 20mA

CLKGEN I/O
1 2 V22 VDDPL_33_DAC VDDAN_11_CLK_3 K24 F13 VSS VSS W6
R34 0_0402_5% 10mils L22 1 1 1 1 1 F16 W25
+FCH_VDDPL_33_MLDAC +VDDPL_33_ML VDDAN_11_CLK_4 C319 C320 C336 C337 C323 VSS VSS
1 2 1 2 U22 VDDPL_33_ML 12mA 340mAVDDAN_11_CLK_5 M22 F17 VSS VSS W28
R49 0_0603_5% R35 0_0402_5% 10mils N21 F19 Y14
VDDAN_11_CLK_6 VSS VSS
2.2U_0603_6.3V6K

L33 VDDPL_33_SSUSB_S +FCH_VDDAN_33_DAC_R 30mA

0.1U_0402_16V7K
T22 VDDAN_33_DAC VDDAN_11_CLK_7 N22 F23 VSS VSS Y16
2 2 2 2 2
+3VS 1 2
MBK1608221YZF_2P
For Hudson M3 USB3.0 only +FCH_VDDPL_33_SSUSB
10mils VDDAN_11_CLK_8 P22 F25 VSS VSS Y18
1 1
For Hudson M2, connect to GND
L18 VDDPL_33_SSUSB_S 11mA F29 VSS VSS AA6
@ C275 C274 10mils G6 AA12
+FCH_VDDPL_33_USB +PCIE_VDDR_FCH +1.1VS VSS VSS
D7 VDDPL_33_USB_S 14mA 50mils G16 VSS VSS AA13
2 2 +VDDPL_33_PCIE
10mils VDDAN_11_PCIE_1 AB24
+PCIE_VDDR_FCH
G32 VSS VSS AA14
AH29 VDDPL_33_PCIE 11mA VDDAN_11_PCIE_2 Y21 1 2 H12 VSS VSS AA16

PCI EXPRESS

2.2U_0603_6.3V6K
10mils R194 0_0805_5%

0.1U_0402_16V7K

0.1U_0402_16V7K
VDDAN_11_PCIE_3 AE25 H15 VSS VSS AA17

1U_0402_6.3V6K

1U_0402_6.3V6K
+VDDPL_33_SATA 12mA

GROUND
AG28 VDDPL_33_SATA VDDAN_11_PCIE_4 AD24 H29 VSS VSS AA25
LDO_CAP: Internally generated 1.8V 1088mA
VDDAN_11_PCIE_5 AB23 1 1 1 1 1 J6 VSS VSS AA28
@ 15mils AA22 C327 C328 C338 C339 C499 J9 AA30
+3VALW_FCH supply for the RGB output LDO_CAP VDDAN_11_PCIE_6 VSS VSS
1 2 M31 LDO_CAP VDDAN_11_PCIE_7 AF26 J10 VSS VSS AA32
L34 +1.1VS C298 2.2U_0603_6.3V6K AG27 J13 AB25
+FCH_VDDPL_33_SSUSB L24 VDDAN_11_PCIE_8 2 2 2 2 2 VSS VSS
1 2 10mils J28 VSS VSS AC6
2.2U_0603_6.3V6K

MBK1608221YZF_2P +VDDPL_11_DAC V21 7mA

0.1U_0402_16V7K

1 2 1 2 VDDPL_11_DAC J32 VSS VSS AC18

220 ohm MBK1608221YZF_2P R37 0_0402_5% +1.1VS
+VDDAN_11_ML 60mils +AVDD_SATA
K7 VSS VSS AC28

C279
1
C278
1 30mils 220 ohm/2A VDDAN_11_SATA_1 AA21
+AVDD_SATA
K16 VSS VSS AD27
20mils VDDAN_11_SATA_4 Y20 1 2 K27 VSS VSS AE6

2.2U_0603_6.3V6K
R370 0_0805_5%

0.1U_0402_16V7K

0.1U_0402_16V7K
1 2 Y22 VDDAN_11_ML_1 VDDAN_11_SATA_2 AB21 K28 VSS VSS AE15

MAIN LINK
0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0805_6.3V6M
R12 0_0603_5%

SERIAL ATA
V23 VDDAN_11_ML_2 VDDAN_11_SATA_3 AB22 L6 VSS VSS AE21
2 2

4.7U_0603_6.3V6K
V24 VDDAN_11_ML_3 226mA VDDAN_11_SATA_5 AC22 1 1 1 1 1 1 L12 VSS VSS AE28
1 1 1 V25 1337mA AC21 C501 C502 C340 C341 C505 C500 L13 AF8
C128 C129 C132 VDDAN_11_ML_4 VDDAN_11_SATA_6 VSS VSS
VDDAN_11_SATA_7 AA20 L15 VSS VSS AF12
2 2
VDDAN_11_SATA_8 AA18 L16 VSS VSS AF16
+3VALW_FCH 2 2 2 2 2 2
VDDAN_11_SATA_9 AB20 L21 VSS VSS AF33
L35 2 2 2
VDDAN_11_SATA_10 AC19 M13 VSS VSS AG30
1 2 +FCH_VDDPL_33_USB AB10 +3VALW_FCH M16 AG32
VDDIO_33_GBE_S VSS VSS
2.2U_0603_6.3V6K

MBK1608221YZF_2P 10mils
0.1U_0402_16V7K

M21 VSS VSS AH5

220 ohm AB11 N18 +VDDIO_33_S 1 2 M25 AH11

GBE LAN
VDDCR_11_GBE_S_1 VDDIO_33_S_1 VSS VSS

2.2U_0603_6.3V6K
R26 0_0402_5%

0.1U_0402_16V7K

0.1U_0402_16V7K
1 1 AA11 VDDCR_11_GBE_S_2 VDDIO_33_S_2 L19 N6 VSS VSS AH18
C280 C281 M18 N11 AH19
VDDIO_33_S_3 VSS VSS

3.3V_S5 I/O
1 2 AA9 VDDIO_GBE_S_1 VDDIO_33_S_4 V12 1 1 1 N13 VSS VSS AH21
R129 0_0402_5% AA10 59mA V13 C342 C343 C506 N23 AH23
2 2 +3VALW_FCH VDDIO_GBE_S_2 VDDIO_33_S_5 VSS VSS
VDDIO_33_S_6 Y12 N24 VSS VSS AH25
L56 30mils Y13 P12 AH27
+VDDAN_33_USB VDDIO_33_S_7 2 2 2 VSS VSS
1 2 G7 VDDAN_33_USB_S_1 VDDIO_33_S_8 W11 P18 VSS VSS AJ18
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805 H8 P20 AJ28
+3VS VDDAN_33_USB_S_2 +3VALW_FCH VSS VSS
220 ohm/3A J8 VDDAN_33_USB_S_3 P21 VSS VSS AJ29
L36 1 1 1 1 1 K8 10mils L28 P31 AK21
+VDDPL_33_PCIE C133 C134 C135 C136 C137 VDDAN_33_USB_S_4 +VDDXL_3.3V VSS VSS
1 2 K9 VDDAN_33_USB_S_5 5mA VDDXL_33_S G24 1 2 P33 VSS VSS AK25
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
MBK1608221YZF_2P MBK1608221YZF_2P
0.1U_0402_16V7K

0.1U_0402_16V7K
M9 VDDAN_33_USB_S_6 R4 VSS VSS AL18
220 ohm 2 2 2 2 2
M10 VDDAN_33_USB_S_7 470mA 220 ohm R11 VSS VSS AM21
1 1 N9 VDDAN_33_USB_S_8 1 1 R25 VSS VSS AM25
C294 C293 N10 C510 C509 R28 AN1
VDDAN_33_USB_S_9 VSS VSS
M12 VDDAN_33_USB_S_10 T11 VSS VSS AN18
N12 VDDAN_33_USB_S_11 T16 VSS VSS AN28
2 2 2 2
M11 VDDAN_33_USB_S_12 T18 VSS VSS AN33
+1.1VALW
L58 +1.1VALW
20mils N8 T21

USB
+VDDANCR_11_USB VSSAN_HWM VSSPL_DAC
1 2 U12 VDDAN_11_USB_S_1 10mils VSSAN_DAC L28
2.2U_0603_6.3V6K

MBK1608221YZF_2P 140mA +VDDCR_1.1V

0.1U_0402_16V7K

U13 VDDAN_11_USB_S_2 VDDCR_11_S_1 N20 1 2 K25 VSSXL VSSANQ_DAC K33

+3VS 220 ohm 187mA VDDCR_11_S_2 M20 R373 0_0603_5% N28
VSSIO_DAC

1U_0402_6.3V6K

1U_0402_6.3V6K
L22 1 1 H25
+VDDPL_33_SATA C303 C302 VSSPL_SYS
1 2 1 1 EFUSE R6
2.2U_0603_6.3V6K

MBK1608221YZF_2P C512 C518

0.1U_0402_16V7K

220 ohm 2 2
3 1 1 3
C297 C296 2 2 HUDSON-M3_FCBGA656

+1.1VALW
2 2 L59 +1.1VALW Connect to GND through a dedicated via
+VDDCR_1.1V_USB
10mils L29
1 2 T12 VDDCR_11_USB_S_1 42mA 10mils
2.2U_0603_6.3V6K

MBK1608221YZF_2P 70mA VDDPL_11_SYS_S +VDDPL_1.1V

0.1U_0402_16V7K

0.1U_0402_16V7K

T13 VDDCR_11_USB_S_2 J24 1 2

2.2U_0603_6.3V6K
220 ohm MBK1608221YZF_2P

0.1U_0402_16V7K
1 1 1 220 ohm
C316 C304 C324 1 1
C514 C513
2 2 2
2 2

+3VALW_FCH
+FCH_VDD_11_SSUSB_S
20mils 10mils +VDDAN_33_HWM
P16 VDDAN_11_SSUSB_S_1 12mA VDDAN_33_HWM_S M8 1 2

2.2U_0603_6.3V6K
+VDDAN_SSUSB R51 0_0402_5%

0.1U_0402_16V7K
1 2 M14 VDDAN_11_SSUSB_S_2
1U_0402_6.3V6K

R131 0_0603_5%
0.1U_0402_16V7K

0.1U_0402_16V7K

N14 VDDAN_11_SSUSB_S_3
40mils P13 VDDAN_11_SSUSB_S_4 282mA 1 1
+FCH_VDD_11_SSUSB_S

1 1 1 P14 C516 C515

C138 C325 C331 VDDAN_11_SSUSB_S_5
USB SS

2 2
2 2 2 30mils
N16 VDDCR_11_SSUSB_S_1
N17 +3VS
VDDCR_11_SSUSB_S_2
P17 VDDCR_11_SSUSB_S_3 424mA 10mils +VDDIO_AZ
M17 VDDCR_11_SSUSB_S_4 26mA VDDIO_AZ_S AA4 1 2

2.2U_0603_6.3V6K
R53 0_0402_5%

0.1U_0402_16V7K
POWER
L61 1 1
+1.1VALW 2 1 1 2 +VDDCR_11_SSUSB HUDSON-M3_FCBGA656 C519 C517
10U_0603_6.3V6M

1U_0402_6.3V6K

R132 0_0603_5%
0.1U_0402_16V7K

0.1U_0402_16V7K

4 4
FBMA-L11-201209-221LMA30T_0805
2 2
42 ohm/4A 1 1 1 1
C140 C139 C332 C333

2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 29 of 51
A B C D E
 A B C D E

SATA HDD Conn. SATA ODD Conn

JHDD @
Close to JHDD
1 JODD @
GND SATA_FTX_C_DRX_P0 C369 1
RX+ 2 2 0.01U_0402_25V7K SATA_FTX_DRX_P0 <27> GND 1
3 SATA_FTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K 2 SATA_FTX_C_DRX_P1 C376 1 2 0.01U_0402_25V7K
RX- SATA_FTX_DRX_N0 <27> A+ SATA_FTX_DRX_P1 <27>
4 3 SATA_FTX_C_DRX_N1 C377 1 2 0.01U_0402_25V7K
GND A- SATA_FTX_DRX_N1 <27>
5 SATA_FRX_DTX_N0 C368 1 2 0.01U_0402_25V7K 4
TX- SATA_FRX_C_DTX_N0 <27> GND
6 SATA_FRX_DTX_P0 C370 1 2 0.01U_0402_25V7K 5 SATA_FRX_DTX_N1 C378 1 2 0.01U_0402_25V7K
TX+ SATA_FRX_C_DTX_P0 <27> B- SATA_FRX_C_DTX_N1 <27>
7 6 SATA_FRX_DTX_P1 C375 1 2 0.01U_0402_25V7K
GND B+ SATA_FRX_C_DTX_P1 <27>
GND 7
1 ODD_PLUGIN# 1
DP 8 ODD_PLUGIN# <26>
+5V 9 +5VS_ODD +5VS_ODD
3.3V 8 +3VS +5V 10 1 Place components closely ODD CONN.
9 11 ODD_DA# C365 1.1A
3.3V MD ODD_DA# <26>
10 14 12 0.1U_0402_10V7K
3.3V GND1 GND @
GND 11 15 GND2 GND 13 1 1 1 1 1 1
C364 2 C355 C354 C379
GND 12
13 SANTA_206001-1 0.1U_0402_10V7K @ @ C380 C360
GND @ 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 0.1U_0402_10V7K
5V 14 +5VS 2 2 2 2 2 2
5V 15
16 0.1U_0402_10V7K
5V
GND 17
+5VS
Add C364 and C365 for EMI request on PVT
Reserved 18 Place closely JHDD SATA CONN.
GND 19 1.2A
23 GND 12V 20
24 GND 12V 21 1 1 1 1
22 C356 C357 C358 C359
12V 10U_0603_6.3V6M 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
SUYIN_127043FB022G278ZR
2 2 2 2

SATA ODD Conn (for 15"/17")

2 JODDB
1
@
1
Power Button & RUSB connector 2

2 SATA_FTX_C_DRX_P2 C384 1 2 0.01U_0402_25V7K

2 SATA_FTX_DRX_P2 <27>
3 SATA_FTX_C_DRX_N2 C382 1 2 0.01U_0402_25V7K
3 SATA_FTX_DRX_N2 <27>
4 4
5 SATA_FRX_DTX_N2 C381 1 2 0.01U_0402_25V7K
5 SATA_FRX_C_DTX_N2 <27>
6 SATA_FRX_DTX_P2 C383 1 2 0.01U_0402_25V7K
6 SATA_FRX_C_DTX_P2 <27>
7 7
8 ODD_PLUGIN#
8 JUSIO
9 9 +5VS_ODD
10 10 1 1
11 ODD_DA# 2 USB20_P1_R
11 2 USB20_N1_R
12 12 ODD_SEL <27> 3 3
GND 13 4 4
14 5 USB20_P0_R
GND 5 USB20_N0_R
6 6
ACES_88058-120N 7
7 ON/OFFBTN#
8 8 ON/OFFBTN# <36,38>
9 +5VS_PWR_ON_LED 2 1 +5VS
9 R4
10 10 +USB_VCCA
11 390_0402_5%
11
12 12
GND 13
GND 14

ACES_88058-120N W=80mils
@ +5VALW
2.5A +USB_VCCA
For EMI
U14
2 IN OUT 6 2 1
3 7 C361 1000P_0402_50V7K
USB_EN# IN OUT
<34,36> USB_EN# 4 EN/ENB OUT 8
3 3
1 GND OCB 5 USB_OC0# <26>
1
SY6288DCAC_MSOP8
SA00004KB00 C362
4.7U_0805_10V4Z
SA00003TV00 2 @

USB20_P1 1 @ 2 RR48 USB20_P1_R USB20_P0 1 @ 2 RR31 USB20_P0_R

<26> USB20_P1 <26> USB20_P0
0_0402_5% 0_0402_5%
LR8 LR7
4 4 3 3 4 4 3 3

1 1 2 2 1 1 2 2

WCM-2012-900T_0805 WCM-2012-900T_0805
USB20_N1 1 2 RR47 USB20_N1_R USB20_N0 1 2 RR30 USB20_N0_R
<26> USB20_N1 <26> USB20_N0
@ 0_0402_5% @ 0_0402_5%

1
R77 R85
300_0402_5% 300_0402_5%
@ @
2

2
1 1
C291 C292
4 4
10P_0402_50V8J 10P_0402_50V8J
2 @ 2 @

Reserved for EHCI CRC errors Reserved for EHCI CRC errors
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 30 of 51
A B C D E
 WLAN&BT Combo module circuits
Slot 1 Half PCIe Mini Card-WLAN +3V_WLAN
BT BT
on module on module
40 mils For SED Enable Disable

1
+3V_WLAN +1.5VS_WLAN +3V_WLAN
For SED
C261
0.1U_0402_10V7K 0.1U_0402_10V7K 47P_0402_50V8J BT_CTRL H L

5
1 1 1 1 1 1 @ UM5

1
1

P
<25,32> APU_PCIE_RST# IN1
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254 4 WLAN_RST#_R
47P_0402_50V8J @ @ @ 47P_0402_50V8J +1.5VS_WLAN O
<36> WLAN_RST# 2

2
IN2

2
2 2 2 @ 2 2 2 @
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z SN74AHC1G08DCKR_SC70-5 RM21

3
1
Add WLAN_RST# on DVT 100K_0402_5%
C260
47P_0402_50V8J

1
@
For RF WLAN_RST# 1 @ 2
BT_CTRL 1 R327 2 E51_RXD_R RM19 0_0402_5%
+1.5VS <36> BT_CTRL
1K_0402_5%

For isolate BT_CTRL and

1
Compal Debug Card.
PJ33
PAD-OPEN 2x2m
@

2
+1.5VS_WLAN +3V_WLAN
JWLAN @
1 1 2 2
3 3 4 4
BT_CTRL 10_0402_5%2BT_CTRL_R 5 6
@ R1443 5 6
<26> CLKREQ_WLAN# 7 7 8 8
9 9 10 10
<25> CLK_WLAN# 11 11 12 12
<25> CLK_WLAN 13 13 14 14
15 15 16 16
R62
17 17 18 18
WLAN_OFF# 1
0_0402_5%
@
+3VALW TO +3V_WLAN
19 19 20 20 2 WL_OFF# <36>
21 22 WLAN_RST#_R
21 22
<5> PCIE_FRX_WLANTX_N1 23 23 24 24
25 26 +3VS
<5> PCIE_FRX_WLANTX_P1 25 26
27 27 28 28
29 30 +3VS Vgs=-4.5V,Id=3A,Rds<97mohm
29 30 FCH_SCLK0 <10,11,26>
<5> PCIE_FTX_C_WLANRX_N1 31 31 32 32 FCH_SDATA0 <10,11,26>
<5> PCIE_FTX_C_WLANRX_P1 33 33 34 34

1
35 35 36 36 USB20_N3 <26> 2
WLAN/ WiFi 37 38 USB20_P3 <26> R142 C907
37 38

2
+3V_WLAN 39 40 100K_0402_5%
39 40 0.1U_0402_10V7K
41 41 42 42 @
1
1
43 44

2
43 44

3
S
45 46 R63 R143 PJ26
R45 45 46 300_0402_5%
G
Q212 PAD-OPEN 2x2m
47 47 48 48 <36> WLAN_PWR# 1 2 2
<36> E51_TXD 10_0402_5%2 49 50 @ AO3413_SOT23

1
E51_RXD_R 49 50 47K_0402_5% D
<36> E51_RXD 1 2 51 52 2
2

1
0_0402_5% 51 52
1
R47 53 54 C286 C908 +3V_WLAN
GND1 GND2
Debug card using 10P_0402_50V8J 0.01U_0402_25V7K
1
2 @
BELLW_80003-7041
Add WLAN power circuit on DVT
Reserved for EHCI CRC errors

Change to GCLK to SLG3NB270V

SA00005DP00 for 27MHz
for VGA

+3V_LAN +3VL +1.8VGS +3VS

1
CCL6
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1
CCL12
0.1U_0402_10V7K

1 1 1 UCL1 2.2U_0603_6.3V6K
22U_0805_6.3V6M GCLK@ 2
1 GCLK@
CCL2 CCL1 CCL3 GCLK@
GCLK@ GCLK@ CCL7 GCLK@ 2
+RTCBATT 10 VBAT VDD_RTC_OUT 14 +RTCBATT_D
2 2 GCLK@ 2
2
+3VL 15 +V3.3A
+3VALW 2 VDD
9 FCH_RTCX1_R_R 1 2
32kHz FCH_RTCX1_R <25>
RCL9 GCLK@ 0_0402_5%

+1.8VGS 11 12 VGA_X1_R 1 2
VDDIO_27M 27MHz VGA_X1 <13>
R799 GCLK@ 33_0402_5%
+3V_LAN 8 6 LAN_X1_R_R 1 2
VDDIO_25M_A 25MHz_A LAN_X1_R <32>
RCL2 GCLK@ 33_0402_5% 1
+3VS 3 5 FCH_X1_R_R 1 2
VDDIO_25M_B 25MHz_B FCH_X1_R <25>
RCL1 GCLK@ 33_0402_5% CCL10
CLK_X1 1 5P_0402_50V8C
CLK_X2 XTAL_IN 2 @
16 XTAL_OUT
EMI request 11/06
GND1
GND2
GND3

GND4

SLG3NB270VTR_TQFN16_2X3
4
7
13

17

change part number to LAN_X1_R_R 1 @ 2

SJ10000EF00 RCL5 0_0402_5%

Reserved for Swing Level adjustment

GCLK@
YCL1 25MHZ 12PF X3G025000DK1H-X ( Close GCLK side )
CLK_X1 1 3 CLK_X2
1 3
GND GND
2 2 4 2
CCL4 CCL5
1
18P_0402_50V8J
1
18P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
GCLK@ GCLK@ 2011/11/28 2013/12/31 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 31 of 51
 A B C D E

UL1 +3V_LAN CL3 to CL6 close to Pin 27,39,47,48

+LAN_VDD10 CL7 to CL8 close to Pin 12,42
<5> PCIE_FRX_C_LANTX_P0 CL1 1 2 0.1U_0402_10V7K PCIE_FRX_LANTX_P0 22 31
HSOP LED3/EEDO LL1
8111FVB@
LED1/EESK 37 1 2
<5> PCIE_FRX_C_LANTX_N0 CL2 1 2 0.1U_0402_10V7K PCIE_FRX_LANTX_N0 23 40 +LAN_REGOUT 1 2 CL3 0.1U_0402_10V7K
HSON LED0 2.2UH +-5% NLC252018T-2R2J-N 1 2
PCIE_FTX_C_LANRX_P0 17 30 RL2 2 @ 1 10K_0402_5% 1 1 CL4 0.1U_0402_10V7K
<5> PCIE_FTX_C_LANRX_P0 HSIP EECS
LAN_EN PCIE_FTX_C_LANRX_N0 18 32 RL1 2 @ 1 10K_0402_5% Layout Note: LL1 must be 1 2
<26> LAN_EN <5> PCIE_FTX_C_LANRX_N0 HSIN EEDI

2
within 200mil to Pin36, CL13 CL9 CL5 0.1U_0402_10V7K

G
2N7002_SOT23-3 CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_10V7K 1 2
CLKREQ_LAN# 1 3 LANCLK_REQ# 16 1 LAN_MDI0+ 200mil to LL1 8111FVB@ 2 2 8111FVB@ CL6 0.1U_0402_10V7K
<26> CLKREQ_LAN# CLKREQB MDIP0
QL53 2 LAN_MDI0- 1 2

S
APU_PCIE_RST# MDIN0 LAN_MDI1+ 8111FVB@ CL7 0.1U_0402_10V7K
<25,31> APU_PCIE_RST# 25 PERSTB MDIP1 4
1 LAN_MDI1- 1
MDIN1 5 1 2
CLK_LAN 19 7 LAN_MDI2+ 8111FVB@ CL8 0.1U_0402_10V7K
<25> CLK_LAN REFCLK_P NC/MDIP2
@ CLK_LAN# 20 8 LAN_MDI2-
<25> CLK_LAN# REFCLK_N NC/MDIN2
1 2 10 LAN_MDI3+
RL28 0_0402_5% NC/MDIP3 LAN_MDI3-
NC/MDIN3 11
LAN_X1 43 CKXTAL1 +LAN_VDD10 +LAN_EVDD10
LAN_X2 44 13 +LAN_VDD10 CL19, CL20,CL21 close to pin 13,29,45, respectively
CKXTAL2 DVDD10 +LAN_VDD10
29 1 2 CL22 close to pin 3, respectively
DVDD10 LL2 0_0603_5%
DVDD10 41 CL23,CL24,CL25 close to pin 6,9,41, respectively
FCH_PCIE_WAKE# 28 1 1
<26> FCH_PCIE_WAKE# LANWAKEB
1 2
+3VS RL24 2 1 10K_0402_5% LANCLK_REQ# ISOLATE# 26 27 CL18 CL17 CL19 0.1U_0402_10V7K
ISOLATEB DVDD33 +3V_LAN
39 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2
DVDD33 2 2 CL20 0.1U_0402_10V7K
+3V_LAN RL25 2 @ 1 10K_0402_5% FCH_PCIE_WAKE# 14 12 1 2
NC/SMBCLK AVDD33 +3V_LAN
RL21 2 @ 1 10K_0402_5% 15 42 CL21 0.1U_0402_10V7K
RL22 1 @ NC/SMBDATA AVDD33
+3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 Close to Pin 21 1 2
48 8111FVB@ CL22 0.1U_0402_10V7K
AVDD33
1 2
@ ENSWREG 33 8111FVB@ CL23 0.1U_0402_10V7K
+3VS LAN_EN ENSWREG +3V_LAN +LAN_VDDREG
1 2 EVDD10 21 +LAN_EVDD10 1 2
RL26 0_0402_5% +LAN_VDDREG 34 8111FVB@ CL24 0.1U_0402_10V7K
VDDREG
35 VDDREG AVDD10 3 +LAN_VDD10 1 2 1 2
6 8111FVB@ LL3 0_0603_5% 1 1 8111FVB@ CL25 0.1U_0402_10V7K
AVDD10
1

AVDD10 9
1 2 46 45 CL28 CL29
1K_0402_5% RL5 2.49K_0402_1% RSET AVDD10 4.7U_0603_6.3V6K 0.1U_0402_10V7K
RL6 +LAN_REGOUT 8111FVB@ 2 2 8111FVB@
24 GND REGOUT 36
@ 49 60 mils
2

PGND
For P/N and footprint
ISOLATE# 1 2 WOL_EN#
2 RL433 0_0402_5% RTL8111F-CGT_QFN48_6x6
Please place them to ISPD page 2
8111FVB@ RL8 GCLK@
1 2 LAN_X2
<31> LAN_X1_R
0_0402_5% UL1
RL7
15K_0402_5% RTL8105E RTL8111E/F CL43 10PF_0402_50V9
Sx Enable Sx Disable S0 1 2 1 2
Wake up Wake up Pin14 NC NC RL29 22_0402_5% 8105E-VL/VD 8105E-VL/VD
GCLK@ GCLK@ +3V_LAN
8111F/F-VB
Pin15 NC 10K ohm PD 8105E-VD 10/100M
PWM Mode LDO Mode 8105ELDO@
WOL_EN# LOW HIGH HIGH

1
Pin38 NC 1K ohm PH RL4 0 ohm NC
NOGCLK@ YL1 25MHZ_20PF_7V25000016 RL4 (Pull High)
0_0402_5%
LAN_X1 1 3 LAN_X2 8111FVB@ NC 0 ohm
+3VALW TO +3V_LAN 1 3
RL23 (Pull Down)

2
GND GND ENSWREG
1 1

1
+3VALW CL26 2 4 CL27
27P_0402_50V8J 27P_0402_50V8J RL23
+3VALW NOGCLK@ NOGCLK@ 0_0402_5%
2 2 8105ELDO@
+3VALW_FCH

2
1

2 Placement near to YH2

RL147 CL483 Vgs=-4.5V,Id=3A,Rds<97mohm
100K_0402_5% @
@ 0.1U_0402_10V7K
LAN Conn.
2

1
2

S
3

@ RL432 @ QL51 PJ29 PJ31

2

G
<36> WOL_EN# 1 2 2
@ @ +3V_LAN JRJ45 @
1

47K_0402_5% 2 AO3413_SOT23 D PAD-OPEN 2x2mPAD-OPEN 2x2m Main: SP050006N00 RJ45_MIDI0+ 1

1

3 @ PR1+ 3
1

CL482 2nd: SP050005W00 RJ45_MIDI0- 2 PR1-

0.01U_0402_25V7K
1 UL3 RJ45_MIDI1+
2 3 PR2+ For ESD

1
1
CL682 LAN_MDI1+ 1 16 RJ45_MIDI1+ RJ45_MIDI2+ 4 D92

1
CL681 LAN_MDI1- TD+ TX+ RJ45_MIDI1- CL39 1000P_0402_50V7K PR3+
1U_0402_6.3V6K 2 TD- TX- 15 AZC199-02SPR7G_SOT23-3
4.7U_0805_10V4Z 1 RJ45_MIDI2- @
3 CT CT 14 2 1 1 2 5 PR3-
2

3
@ 4 13 RL11 75_0402_1%
NC NC CL40 1000P_0402_50V7K RJ45_MIDI1-
5 12 6

3
NC NC PR2-
6 CT CT 11 2 1 1 2
LAN_MDI0+ 7 10 RJ45_MIDI0+ RL12 75_0402_1% RJ45_MIDI3+ 7 9
LAN_MDI0- RD+ RX+ RJ45_MIDI0- PR4+ GND
8 RD- RX- 9 GND 10
RJ45_MIDI3- 8
D99 @ PR4-
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

2
LAN_MDI1+ 6 3 LAN_MDI0+ 10/100M transformer_NS681695 SANTA_130452-S
I/O4 I/O2 UL4 8111FVB@ D93

2
AZC199-02SPR7G_SOT23-3
LAN_MDI2+ 1 16 RJ45_MIDI2+ 8111FVB@
LAN WOL
LAN_EN ISOLATEB TD+ TX+ @

1
+3V_LAN 5 2 LAN_MDI2- 2 15 RJ45_MIDI2- CL41 1000P_0402_50V7K 8111FVB@
VDD GND TD- TX-
S0 Sx S0 Sx 3 14 2 1 1 2

1
CT CT RL13 75_0402_1%
4 NC NC 13 For ESD
---------------------------------------------- 5 NC NC 12 CL42 1000P_0402_50V7K
LAN_MDI1- 4 1 LAN_MDI0- 6 11 2 1 1 2
0 0 0 0 1 1 I/O3 I/O1 LAN_MDI3+ CT CT RJ45_MIDI3+ RL15 75_0402_1%
7 RD+ RX+ 10
AZC099-04S.R7G_SOT23-6 LAN_MDI3- 8 9 RJ45_MIDI3- 8111FVB@ 8111FVB@
0 1 0 0 1 1 RD- RX-

1 0 1 1 1 1 D100 @ 10/100M transformer_NS681695

1 1 1 1 1 0* LAN_MDI2+ 6 3 LAN_MDI3+ 1 RJ45_GND CL36 1 2 1000P_1808_3KV7K LANGND
I/O4 I/O2
1 1
CL34 CL37 CL38
4 0.1U_0402_25V6 @ 4
* +3V_LAN 5 VDD GND 2
2
2
220P_0402_50V6K
2
4.7U_0603_6.3V6K
Place CL34 colse
S3: after SUSP# assert low over 100ms to LAN chip
S4/S5: after SYSON assert low over 100ms LAN_MDI2- 4 1 LAN_MDI3-
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title
2/9: Add for ESD request SCHEMATIC,MB LA-8863
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 32 of 51
A B C D E
 A B C D E

CardReader Conn.

JCRIO @
1 14 GND 1
@ R3 13
+3VS_CR GND
+3VS 1 2 12 12
11 11
0_0603_5% USB20_N2_R 10 USB20_P2 1 2 RR67 USB20_P2_R
10 <26> USB20_P2
USB20_P2_R 9 0_0402_5%
9 @ LR9
8 8
HP_R 7 4
<35> HP_R
HP_L 7 4 3 3
<35> HP_L 6 6
5 5
MIC1_L 4 1 2
<35> MIC1_L 4 1 2
MIC1_R 3
<35> MIC1_R 3
MIC_SENSE 2 WCM-2012-900T_0805
<35> MIC_SENSE 2
NBA_PLUG 1 USB20_N2 1 2 RR66 USB20_N2_R
<35> NBA_PLUG 1 <26> USB20_N2
0_0402_5%
ACES_88058-120N

@ @
300_0402_5% 10P_0402_50V8J
1 2 1 2
R73 C290

Reserved for EHCI CRC errors

2 2

CT2 CT4
0.1U_0402_10V7K 0.1U_0402_10V7K
TPM9655@ TPM9655@
CT5
0.1U_0402_10V7K

TPM1.2 on board 0.1U_0402_10V7K

TPM9655@

0.1U_0402_10V7K
+3VS

+VSB_TPM RT12 2 1 0_0603_5% +3VS

TPM9655@

1
1 2 TPM_XTALI 2 2 2 RT13 2 RT10 2 1 0_0603_5% +3VALW
CT1 22P_0402_50V8J 0_0603_5% TPM9635@
TPM9635@ CT2 CT4 CT5 TPM9655@ CT8
TPM9635@ TPM9635@ TPM9635@ TPM9635@

2
1

1 1 1 +VDD_TPM 1 0.1U_0402_10V7K CT8

2

@ RT1 0.1U_0402_10V7K
YT1 10M_0402_5% TPM9655@
32.768KHZ_12.5P_1TJF125DP1A000D +VSB_TPM
TPM9635@ 0.1U_0402_10V7K
1

UT1

24
19
10

5
3 TPM_XTALO 3
1 2
CT6 22P_0402_50V8J

VSB
VDD
VDD
VDD
TPM9635@ LPC_AD0 26
<25,36,37> LPC_AD0 LAD0
LPC_AD1 23
<25,36,37> LPC_AD1 LAD1
LPC_AD2 20
<25,36,37> LPC_AD2 LAD2
LPC_AD3 17 6 TPM_GPIO PAD @ T61
<25,36,37> LPC_AD3 LAD3 GPIO
LPC_FRAME# 22 2 TPM_GPIO2 PAD @ T62
<25,36,37> LPC_FRAME# LFRAME# GPIO2
<25,36,37> LPC_RST# LPC_RST# 16 Base I/O Address
LPC_PD# LRESET#
28 LPCPD#
0 = 02Eh
SERIRQ 27 1 =* 04Eh +3VS
<25,36> SERIRQ SERIRQ
<25> CLK_PCI_TPM_FCH 21 LCLK TPM9635@

1
@ 1 2 1 @ 2 SLB 9635 TT 1.2 0_0402_5%
+VSB_TPM 10P_0402_50V8J CT7 RT4 10_0402_5% 15 8 RT5 1 2 TPM9635@
RT11 1 CLKRUN# TEST1
2 0_0402_5% TESTB1/BADD 9 RT3
TPM9635@ 4.7K_0402_5%
1

2
PP
RT7 3
NC

2
@ 4.7K_0402_5% TPM_XTALO 14 12 TPM9655@
XTALO NC 0_0402_5% RT6
1
2

+3VS TPM_XTALI NC RT14 1 LPC_RST#

13 XTALI/32K IN 2 4.7K_0402_5%
@
1

GND
GND
GND
GND

1
1

RT8
RT2 TPM9635@ RT8 TPM9655@
TPM9635@ 0_0402_5% 0_0402_5% SLB 9635 TT 1.2_TSSOP28
25
18
11
4

4.7K_0402_5% TPM9635@
2
2

4 4

LPC_PD#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 33 of 51
A B C D E
 5 4 3 2 1

+5VALW
USB20_DN10 1 2 RR44 USB20_N10
0_0402_5%

1
USB20_DP10 1 2 RR45 USB20_P10
RB73 0_0402_5%
4.7K_0402_5% @
PJ30
@
U15 @ 2 1

2
CEN SLP_CHG# 2 1
USB20_DN10
1 CEN CB 8
USB20_N10
SLP_CHG# <27> +5VALW W=60mils
2 7
RB74
1
USB20_DP10
SELCDP
3
DM
DP
TDM
TDP 6 USB20_P10
USB20_N10 <26>
USB20_P10 <26>
2.5A
UR3
+USB_VCCB
For EMI
PAD-OPEN 2x2m
Q8 @
4 SELCDP VDD 5 +5VALW
4.7K_0402_5% 9 2 6 2 1
@ Thermal Pad IN OUT CR38 1000P_0402_50V7K

S
D 3 IN OUT 7 +USB_VCCC 1 3 +USB_VCCB D
SLG55584AVTR_TDFN8_2X2 1 1 USB_CHG_EN# 4 8
<36> USB_CHG_EN#
2

@ @ EN/ENB OUT AO3413_SOT23

1 GND OCB 5 USB_OC1# <26>
CB25 CB49 1 1 @ 2

G
+5VALW

2
+5VALW 0.1U_0402_16V7K 10U_0603_6.3V6M SY6288DCAC_MSOP8 R568 100K_0402_5%
2 2 CR39
SA00004KB00
4.7U_0805_10V4Z USB_EN#
SA00003TV00 2 @ <30,36> USB_EN#

Pull-up for SLGC55584AV

1

RB75
4.7K_0402_5%
2

@ W=80mils
USB20_DP10 1 @ 2 RR26 USB20_P10_L USB20_P11 1 2 RR38 USB20_P11_L +USB_VCCB
<26> USB20_P11
SELCDP 0_0402_5% @ 0_0402_5%
LR3 WCM-2012-900T_0805
@ 4 4.7U_0805_10V4Z 0.1U_0402_10V7K
4 3 3 4 4 3 3
1

RB76 1 1 1 1
4.7K_0402_5% 1 2 1 CR46 CR45 CR44
1 2 1 2 2 + CR40
WCM-2012-900T_0805 LR4
Pull-down for SLGC55584V
2

USB20_DN10 2 2 2
1 2 RR25 USB20_N10_L
<26> USB20_N11
USB20_N11 1 @ 2 RR39 USB20_N11_L
@ 0_0402_5% 0_0402_5% 2
1000P_0402_50V7K

1
220U_6.3V_M
R71 R72
C 300_0402_5% 300_0402_5% C
SLP_CHG# SELCDP Function @ @ 150uFx2 or 220uFx1

2
DCP autodetect with 1 1
0 X mouse/keyboard wakeup C288 C289
+USB_VCCC
10P_0402_50V8J 10P_0402_50V8J W=80mils
1 0 S0 charging with SDP only 2 @ 2 @
4.7U_0805_10V4Z
1
1 1 S0 charging with CDP or SDP only Reserved for EHCI CRC errors Reserved for EHCI CRC errors 1 1 1
+ CR47 CR42 CR43 CR41
@ 1000P_0402_50V7K
2 2 2 2
USB30_RX0N 1 @ 2 RR19 USB30_RX0N_L
<26> USB30_RX0N
0_0402_5% 220U_6.3V_M 0.1U_0402_10V7K
LR1
4 4 3 3

1 1 2 2
KINGCORE WCM-2012HS-670T DR7 @
USB30_RX0P 1 2 RR20 USB30_RX0P_L USB30_TX0P_C_L 1 1 109 USB30_TX0P_C_L
<26> USB30_RX0P
@ 0_0402_5% JUSBA
DR1
@ USB30_TX0N_C_L 2 2 98 USB30_TX0N_C_L USB30_TX0P_C_L 9
USB30_TX0N_C SSTX+
<26> USB30_TX0N 1 2 1 @ 2 RR32 USB30_TX0N_C_L USB20_P10_L 2
2 +USB_VCCB 1 VBUS
CB22 0.1U_0402_16V7K 0_0402_5% 1 USB30_RX0P_L 4 4 77 USB30_RX0P_L USB30_TX0N_C_L 8
B LR2 USB20_N10_L 3 1 USB20_N10_L SSTX- B
3 2 D-
4 3 USB30_RX0N_L 5 5 66 USB30_RX0N_L 7
4 3 USB20_P10_L GND
AZC199-02SPR7G_SOT23-3 3 D+ GND 10
3 3 USB30_RX0P_L 6 SSRX+ GND 11
1 1 2 2 4 GND GND 12
8 USB30_RX0N_L 5 13
KINGCORE WCM-2012HS-670T SSRX- GND
<26> USB30_TX0P 1 2 USB30_TX0P_C 1 2 RR22 USB30_TX0P_C_L Change ESD Diode for EMI request YSCLAMP0524P_SLP2510P8-10-9 OCTEK_USB-09EAEB
CB21 0.1U_0402_16V7K @ 0_0402_5% @

USB30_RX1N 1 @ 2 RR42 USB30_RX1N_L DR8 @

<26> USB30_RX1N
0_0402_5% USB30_TX1P_C_L 1 1 109 USB30_TX1P_C_L JUSBB
LR5 USB30_TX1P_C_L 9
DR4 SSTX+
4 3 @ USB30_TX1N_C_L 2 2 98 USB30_TX1N_C_L +USB_VCCC 1
4 3 USB20_P11_L 2 USB30_TX1N_C_L VBUS
2 8 SSTX-
1 USB30_RX1P_L 4 4 77 USB30_RX1P_L USB20_N11_L 2
USB20_N11_L 3 1 D-
1 1 2 2 3 7 GND
USB30_RX1N_L 5 5 66 USB30_RX1N_L USB20_P11_L 3 10
KINGCORE WCM-2012HS-670T USB30_RX1P_L D+ GND
AZC199-02SPR7G_SOT23-3 6 SSRX+ GND 11
USB30_RX1P 1 2 RR40 USB30_RX1P_L 3 3 4 12
<26> USB30_RX1P GND GND
@ 0_0402_5% USB30_RX1N_L 5 13
8 SSRX- GND
<26> USB30_TX1N 1 2 USB30_TX1N_C 1 @ 2 RR43 USB30_TX1N_C_L OCTEK_USB-09EAEB
CB24 0.1U_0402_16V7K 0_0402_5% Change ESD Diode for EMI request YSCLAMP0524P_SLP2510P8-10-9 @
LR6
A 4 4 3 3 A

1 1 2 2
KINGCORE WCM-2012HS-670T
1 2 USB30_TX1P_C 1 2 RR41 USB30_TX1P_C_L
<26> USB30_TX1P
CB23 0.1U_0402_16V7K @ 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 34 of 51
5 4 3 2 1
 A B C D E

35mA for 3.3V level

close to pin 25 close to pin 38 RA18
UA1 +3VS 1 2 0.1U_0402_16V4Z +DVDD_IO +AVDD 0.1U_0402_10V7K 0.1U_0402_10V7K 1 2 +5VS
RA28 0_0603_5% 2 1 2 1 1 0_0603_5%
MIC1_R_R 4.7U_0603_6.3V6K CA58 MIC1_R_C_R 22 1 +DVDD_IO 1 1
MIC1_R_L 4.7U_0603_6.3V6K CA57 MIC1_R_C_L MIC1_R DVDD +3VS_DVDD CA4 CA42 CA47 CA37 CA50 CA39
21 MIC1_L DVDD_IO 9
CA3 @ 10U_0603_6.3V6M
MIC2_R +AVDD 10U_0603_6.3V6M 1 2 1 2 2
17 MIC2_R AVDD1 25
MIC2_L +AVDD 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M
16 MIC2_L AVDD2 38

+MIC1_VREFO_L 31 39 +PVDD RA17

MIC1_VREFO_L PVDD1 +PVDD 0.1U_0402_16V4Z +3VS_DVDD LA6
+MIC1_VREFO_R 30 MIC1_VREFO_R PVDD2 46 +3VS 2 1
+MIC2_VREFO 29 0_0603_5% 1 1 +PVDD 1 2 0.1U_0402_10V7K +5VS
1 MIC2_VREFO 1
1 2 PBY160808T-601Y-N_2P 1 1
15 45 SPKR+ CA46 CA45 CA33 0.1U_0402_10V7K
LINE2_R SPK_OUT_R+ SPKR- 10U_0603_6.3V6M CA35 CA34 CA36
14 LINE2_L SPK_OUT_R- 44
2 2 close to pin39 10U_0603_6.3V6M
2 1 2 2
20 40 SPKL+ 10U_0603_6.3V6M
MONO_OUT SPK_OUT_L+ SPKL-
SPK_OUT_L- 41
1 2 MONO_IN 12 place close to chip
CA59 100P_0402_50V8J PCBEEP 75_0402_1% 1
0.01U_0402_25V7K 10 33 RA19 HP_R <33> CA32 0.1U_0402_10V7K
<26> AZ_SYNC_HD SYNC HPOUT_R
@ CA65 1 2 32 RA20
HPOUT_L 75_0402_1% HP_L <33>
<26> AZ_RST_HD# 11 RESET# 2
close to pin19 SDATA_OUT 5 AZ_SDOUT_HD <26>
close to pin 28 8 AZ_SDIN0_HD_R 2 1
SDATA_IN AZ_SDIN0_HD <26>
2 RA30 1AC_JDREF 19 JDREF
RA23 33_0402_5%
10U_0603_6.3V6M 1 2CA60 20K_0402_1% 28 6 AZ_BITCLK_HD
LDO_CAP BCLK AZ_BITCLK_HD <26>
27 VREF
2 1CPVEE 34 CPVEE
AC_VREF CA54 2.2U_0603_10V6K 35 23 @ CA51 For EMI
CBN NC AZ_BITCLK_HD 2
1 1 2 1 36 24 1 1 2 @
CA53 2.2U_0603_10V6K CBP NC
48 10_0402_5% RA29 please place near codec
CA55 CA56 NC 10P_0402_50V8J
2.2U_0603_6.3V6K <22> INT_MIC_DATA 2 GPIO0/DMIC_DATA
2 2 @ INT_MIC_CLK_R 3 GPIO1/DMIC_CLK AVSS1 26
0.1U_0402_10V7K 37
AVSS2
PVSS1 42
SENSE_A 13 43
SENSE_A PVSS2
2 @ 1 SENSE_B 18 SENSE_B DVSS 7
RA34 20K_0402_1%
47
AGND EC Beep
2 <36> EC_MUTE# 4
EAPD
PD# Thermal Pad 49 <36> EC_BEEP# 1
RA51
2 Beep sound 2
47K_0402_5%
ALC259-VC2-CG_MQFN48_6X6

For EMI PCI Beep RA52

CA70
1 2 1 2 MONO_IN
<26> FCH_SPKR
RA42
INT_MIC_CLK_R DGND 47K_0402_5%
0.1U_0402_10V7K
<22> INT_MIC_CLK
FBMA-10-100505-301T
CAM@ EC_MUTE# Internal AMP
1 Hight Enable
LOW Disable

2
CA52 CAM@
220P_0402_50V7K RA49 CA69
2 100P_0402_50V8J
4.7K_0402_5%

1
EC_MUTE#
+MIC2_VREFO
2W 4ohm =40mil placement near Audio Codec

2
1W 8ohm =20mil
Analog MIC SPKL+
LA7
SPK_L1
RA50
2 1 4.7K_0402_5%
0_0603_5% 2
CA71 To solve noise issue

1
1

@ 2
RA24 10U_0603_6.3V6M CA74
1 1U_0402_6.3V4Z
4.7K_0402_5%
AMIC@ 2 @
CA72 1
2

@
AMIC@ AMIC@ LA8 10U_0603_6.3V6M
CA26 RA25 JMIC SPKL- 1 SPK_L2
2 1
3 MIC2_L 3
2 1 1U_0402_6.3V4Z 2 1 1K_0402_5% INT_MIC 1 0_0603_5%
2
1
2 SPKR+
LA9
SPK_R1
Ext.MIC/LINE IN JACK
2 1
CA27 3 0_0603_5% 2
MIC2_R 2 GND
1 1U_0402_6.3V4Z 2 1 1K_0402_5% 1 2 4 GND
CA76
CA28 RA26 220P_0402_50V7K @
AMIC@ AMIC@ AMIC@ ACES_50271-0020N-001 10U_0603_6.3V6M 2 RA47 2 1 +MIC1_VREFO_R
@ 1 CA73 1K_0402_5% RA48 2.2K_0402_5%
close to Codec 2 1U_0402_6.3V4Z MIC1_R_R 2 1 MIC1_R <33>
1 1 CA75 @
CA6 CA5 @ 1
@ @ LA10 10U_0603_6.3V6M MIC1_R_L 2 1
1 MIC1_L <33>
470P_0402_50V8J 470P_0402_50V8J SPKR- 2 1 SPK_R2 1K_0402_5%
2 2 0_0603_5% RA45 2 1 +MIC1_VREFO_L
RA46 2.2K_0402_5%

Add CA5 and CA6 for EMI request on PVT

Add bypass caps for EMI request on PVT
SPK Conn. @ DA10 AZ5125-02S.R7G_SOT23-3
CA64 1 2 0.1U_0603_50V7K 2
Sense Pin Impedance Codec Signals Function place close to chip CA63 1 2 0.1U_0603_50V7K @
1
3
CA67 1 2 0.1U_0603_50V7K
39.2K PORT-I (PIN 32, 33) Headphone out <33> MIC_SENSE 2 1 SENSE_A CA61 1 2 0.1U_0603_50V7K @ JSPK
RA32 20K_0402_1% SPK_R1 1
CA66 1 1
2 0.1U_0603_50V7K SPK_R2 2 2
20K PORT-B (PIN 21, 22) Ext. MIC SPK_L1 3
CA62 1 3
SENSE A 2 0.1U_0603_50V7K SPK_L2 4 4

10K PORT-C (PIN 23, 24) <33> NBA_PLUG 1 2 @ ACES_85204-0400N

4 RA33 39.2K_0402_1% CA77 1 4
2 0.1U_0603_50V7K 2 @
RA31 0_0603_5% 1
5.1K (PIN 48) @ 3
CA68 1 2 0.1U_0603_50V7K
DA11 AZ5125-02S.R7G_SOT23-3
39.2K PORT-E (PIN 14, 15) @

SENSE B 20K PORT-F (PIN 16, 17) Analog MIC

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

10K PORT-H (PIN 20) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019IT
Date: Friday, March 23, 2012 Sheet 35 of 51
A B C D E
 5 4 3 2 1

+3VL +3VL

0.1U_0402_10V7K 0.1U_0402_10V7K 1000P_0402_50V7K CB3

1 1 1 1 1 1 0.1U_0402_10V7K
CB1 CB2 CB5 CB7 1 2
0.1U_0402_10V7K
For EMI CB4 CB6
2 2 2 2 2 2

111
125
0.1U_0402_10V7K 1000P_0402_50V7K

22
33
96

67
9
CLK_PCI_EC UB1 BATT_TEMPA 1 2
CB9 100P_0402_50V8J

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0
1
RB3 ACIN_D 1 2
10_0402_5% CB10 100P_0402_50V8J
@ GATEA20 1 21 WL_BT_LED#
D <26> GATEA20 GATEA20/GPIO00 GPIO0F WL_BT_LED# <38> D
KB_RST# 2 23 EC_BEEP#
<26> KB_RST# EC_BEEP# <35>
2
SERIRQ KBRST#/GPIO01 BEEP#/GPIO10
1 <25,33> SERIRQ 3 SERIRQ GPIO12 26
CB11 LPC_FRAME# 4 27
<25,33,37> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
22P_0402_50V8J LPC_AD3 5
<25,33,37> LPC_AD3 LPC_AD3
@ LPC_AD2 7 PWM Output
2 <25,33,37> LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMPA
<25,33,37> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMPA <40>
LPC_AD0 10 LPC & MISC 64
<25,33,37> LPC_AD0 LPC_AD0 GPIO39
65 ADP_I
ADP_I/GPIO3A ADP_I <40,41>
CLK_PCI_EC 12 AD Input 66
<25,28> CLK_PCI_EC CLK_PCI_EC GPIO3B
LPC_RST# 13 75
<25,33,37> LPC_RST# PCIRST#/GPIO05 GPIO42
EC_RST# 37 76 EC_ENBKL
+3VL EC_RST# IMON/GPIO43 EC_ENBKL <21>
RB2 EC_SCI# 20
<26> EC_SCI# EC_SCII#/GPIO0E
47K_0402_5% WLAN_PWR# 38
<31> WLAN_PWR# GPIO1D
1 2 EC_RST# 68
DAC_BRIG/GPIO3C EN_DFAN1
Add WLAN_PWR# on DVT EN_DFAN1/GPIO3D 70 EN_DFAN1 <5>
1 2 DA Output IREF/GPIO3E 71
CB12 0.1U_0402_10V7K KSI0 55 72
KSI1 KSI0/GPIO30 CHGVADJ/GPIO3F
56 KSI1/GPIO31
KSI2 57
KSI3 KSI2/GPIO32 EC_MUTE#
58 KSI3/GPIO33 EC_MUTE#/GPIO4A 83 EC_MUTE# <35>
KSI4 59 84 USB_EN#
KSI4/GPIO34 USB_EN#/GPIO4B USB_EN# <30,34>
KSI5 60 85 EC_SMB_CK3
KSI5/GPIO35 CAP_INT#/GPIO4C EC_SMB_CK3 <21>
KSI6 61 PS2 Interface 86 EC_SMB_DA3
KSI6/GPIO36 EAPD/GPIO4D EC_SMB_DA3 <21>
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <38>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <38>
KSO1 40
KSO2 KSO1/GPIO21 +3VL
41 KSO2/GPIO22
KSO3 42 97 VGATE
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE <47>
KSO4 43 98 WOL_EN#
KSO4/GPIO24 WOL_EN/GPXIOA01 WOL_EN# <32>
KSO5 LID_SW#
KSO6
44 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 99
VCIN0_PH VCIN0_PH connect to
1
RB35
2
47K_0402_5%
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 VCIN0_PH <40>
KSO7 46 KSO7/GPIO27 SPI Device Interface power portion (9012 only)
C KSO8 +5VS C
47 KSO8/GPIO28
KSO9 48 119
KSI[0..7] KSO10 KSO9/GPIO29 SPIDI/GPIO5B TP_CLK
<37> KSI[0..7] 49 KSO10/GPIO2A SPIDO/GPIO5C 120 1 2
KSO11 50 SPI Flash ROM 126 RB8 4.7K_0402_5%
KSO[0..15] KSO12 KSO11/GPIO2B SPICLK/GPIO58
<37> KSO[0..15] 51 KSO12/GPIO2C SPICS#/GPIO5A 128
KSO13 52 TP_DATA 1 2
KSO14 KSO13/GPIO2D RB9 4.7K_0402_5%
53 KSO14/GPIO2E
KSO15 54 73
KSO15/GPIO2F ENBKL/GPIO40
81 KSO16/GPIO48 PECI_KB930/GPIO41 74
RP7 82 89 SYSON 1 2
EC_SMB_CK1 KSO17/GPIO49 FSTCHG/GPIO50 BATT_FULL_LED# RB10 4.7K_0402_5%
+3VL 1 8 BATT_CHG_LED#/GPIO52 90 BATT_FULL_LED# <38>
2 7 EC_SMB_DA1 91 WLAN_RST# Add WLAN_RST# on DVT
CAPS_LED#/GPIO53 WLAN_RST# <31>
+3VL 3 6 EC_SMB_CK2 EC_SMB_CK1 77 GPIO 92
<40,41> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54
4 5 EC_SMB_DA2 EC_SMB_DA1 78 93 BATT_CHG_LOW_LED#
<40,41> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_CHG_LOW_LED# <38>
EC_SMB_CK2 79 SM Bus 95 SYSON
<9,13> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <39,43>
2.2K_0804_8P4R_5% EC_SMB_DA2 80 121 VR_ON
<9,13> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <39,46,47>
PM_SLP_S4#/GPIO59 127

SLP_S3# 6 100 EC_RSMRST#

<26> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <26>
SLP_S5# 14 101 EC_LID_OUT#
<26> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <26>
+3VS 1 2 EC_SMB_CK3 <26> EC_SMI#
EC_SMI# 15 102 PROCHOT_IN
PROCHOT_IN <40>
PROCHOT_IN connect VCOUT0_PH_L 1 @ 2 VS_ON <42>
EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05
RB135 2.2K_0402_5% 16 GPIO0A H_PROCHOT#_EC/GPXIOA06 103 H_PROCHOT_EC to power portion (9012 only) RB34 0_0402_5%
1 2 EC_SMB_DA3 <26> EC_PXCONTROL
EC_PXCONTROL 17 GPIO0B VCOUT0_PH/GPXIOA07 104 VCOUT0_PH_L VCOUT0_PH connect to power portion (9012 only)
RB136 2.2K_0402_5% USB_CHG_EN# 18 GPO 105 BKOFF#
<34> USB_CHG_EN# GPIO0C BKOFF#/GPXIOA08 BKOFF# <22>
BT_CTRL 19 GPIO 106 PBTN_OUT# RB18
<31> BT_CTRL GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <26>
25 107 FCH_PWR_EN 330K_0402_5%
EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 FCH_PWR_EN <39,44>
FAN_SPEED1 28 108 2 1 +3VL
<5> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
WL_OFF# 29
<31> WL_OFF# EC_PME#/GPIO15
E51_TXD 30
<31> E51_TXD EC_TX/GPIO16
E51_RXD 31 110 ACIN_D ACIN_D 2 1
<31> E51_RXD EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <13,41>
FCH_PWRGD 32 112 EC_ON_R RB751V40_SC76-2 DB1
B <26> FCH_PWRGD PCH_PWROK/GPIO18 EC_ON/GPXIOD02 B
PWR_SUSP_LED# 34 114 ON/OFFBTN#
<38> PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# <30,38>
36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <38>
116 SUSP#
SUSP#/GPXIOD05 SUSP# <39,43,44>
117 VGA_SEL
GPXIOD06
PECI_KB9012/GPXIOD07 118
+3VL
AGND/AGND

T14 122 SUSP# 1 2

@ XCLKO XCLKI/GPIO5D +EC_V18R RB21 10K_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND

<25,28> RTC_CLK 1 2 123 XCLKO/GPIO5E V18R 124

@ RB20 0_0402_5% 1
GND0

1 2 LPC_RST# VR_ON 1 2

2
CB13 1U_0402_6.3V6K CB15 RB23 10K_0402_5%
1

1 4.7U_0805_10V4Z RB24
@ RB22 CB16 KB9012QF-A3_LQFP128_14X14 2
10K_0402_5%
11
24
35
94
113

69

1 2 SUSP# 100K_0402_5% 20P_0402_50V8

CB14 180P_0402_50V8J TH@

1
2
2

VGA_SEL

2
RB25
Close to EC 10K_0402_5%
H_PROCHOT# <7,47>
CH@

1
Low Active (+1.5V)
RB27 Voltage Comparator Pins FOR 9012 A3 RB36 D
100K_0402_5% EC_ON_R 1 2 H_PROCHOT_EC 2
EC_ON <42>
1 2 E51_TXD G Q34
VCIN0 pin109 2.2K_0402_5% High Active S 2N7002K_SOT23-3
>1.2V <1.2V 1
VCIN1 pin102

3
1U_0402_6.3V6K VGA_SEL
CB50
High Low
VCOUT0 pin104 2
HIGH LOW
Pin117 HIGH LOW
A +3VS A
VCOUT1 pin103 LOW HIGH
Address 82h 9Ah H_PROCHOT_EC 1 @ 2
RB6 10K_0402_5%
For KB9012 EC_ON low pulse work around

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019IT
Date: Friday, March 23, 2012 Sheet 36 of 51
5 4 3 2 1
 1 2 3 4 5 6 7 8

LPC Debug Port

JDB @
1 1 +3VS
2 2
A
3 3 LPC_RST# <25,33,36> A
4 CLK_PCI_DDR
4 CLK_PCI_DDR <25,28>
5 5 LPC_FRAME# <25,33,36>
6 6 LPC_AD3 <25,33,36>
7 7 LPC_AD2 <25,33,36>
8 8 LPC_AD1 <25,33,36>
9 9 LPC_AD0 <25,33,36>
10 10
GND 11
GND 12
E-T_3801K-F10N-01L C457 R393
1 2 1 2 CLK_PCI_DDR

22P_0402_50V8J 22_0402_5%
@ @

For EMI

B For EMI B

KEYBOARD CONN. Close to JKB

KSO2 1 2
C404 100P_0402_50V8J
KSO1 1 2
C405 100P_0402_50V8J
KSI[0..7] KSO0 1 2
KSI[0..7] <36>
C406 100P_0402_50V8J
KSO[0..15] KSO4 1 2
KSO[0..15] <36>
C407 100P_0402_50V8J
KSO3 1 2
C408 100P_0402_50V8J
KSO5 1 2
C409 100P_0402_50V8J
KSO14 1 2
C410 100P_0402_50V8J
JKB
KSO6 1 2
1 C411 100P_0402_50V8J
1 KSO15 KSO7
2 2 1 2
3 KSO14 C412 100P_0402_50V8J
3 KSO13 KSO13
4 4 1 2
5 KSO12 C413 100P_0402_50V8J
5 KSO11 KSO8
6 6 1 2
7 KSO10 C415 100P_0402_50V8J
7 KSO9 KSO9
8 8 1 2
9 KSO8 C416 100P_0402_50V8J
9 KSO7 KSO10
10 10 1 2
C KSI7 C417 100P_0402_50V8J C
11 11
12 KSI6 KSO11 1 2
12 KSO6 C418 100P_0402_50V8J
13 13
14 KSI5 KSO12 1 2
14 KSO5 C419 100P_0402_50V8J
15 15
16 KSI4 KSO15 1 2
16 KSI3 C420 100P_0402_50V8J
17 17
18 KSI2 KSI7 1 2
18 KSI1 C421 100P_0402_50V8J
19 19
20 KSO4 KSI2 1 2
20 KSI0 C422 100P_0402_50V8J
21 21
22 KSO3 KSI3 1 2
22 KSO2 C423 100P_0402_50V8J
23 23
26 24 KSO1 KSI4 1 2
GND 24 KSO0 C424 100P_0402_50V8J
27 GND 25 25
KSI0 1 2
ACES_50524-02501-001 C425 100P_0402_50V8J
KSI5 1 2
@
C427 100P_0402_50V8J
KSI6 1 2
C429 100P_0402_50V8J
KSI1 1 2
C431 100P_0402_50V8J

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 37 of 51
1 2 3 4 5 6 7 8
 5 4 3 2 1

Power Button Touchpad Connector

+3VL

2
For debug R395

D 100K_0402_5% +3VL +5VS +5VALW D

SW4 JTP @

1
1 3 ON/OFFBTN# 1
ON/OFFBTN# <30,36> 1
TOP side 2 2
2 4 1 TP_CLK 3
<36> TP_CLK 3
C458 TP_DATA 4
<36> TP_DATA 4
SMT1-05-A_4P 0.1U_0402_25V6 5

6
5
@ LID_SW# 5
<36> LID_SW# 6 6
2 BATT_FULL_LED#
<36> BATT_FULL_LED# 7 7
SW3 BATT_CHG_LOW_LED# 8
<36> BATT_CHG_LOW_LED# 8
1 3 PWR_SUSP_LED# 9
<36> PWR_SUSP_LED# 9
BOT side HDD_LED# 10
WL_BT_LED# 10
2 4 For EMI request <36> WL_BT_LED# 11 11 G1 13
12 12 G2 14
SMT1-05-A_4P
6
5

ACES_50504-0120N-001

C C

CPU VGA FCH

Screw Hole H1
H_4P2
H2
H_4P6
H3
H_4P2x4P6
H4
H_3P5
H5
H_3P0
H8
H_3P0
@ @ @ @ @ @

HDD LED SATA_LED# <27>

1
2

+3VS 2 R404 1 6 1 TP
10K_0402_5%
5

Q9A
2N7002DW-T/R7_SOT363-6 H17 H20
HDD_LED# 3 4 H_3P0N H_3P0N
@ @
Q9B 2N7002DW-T/R7_SOT363-6

1
1 @ 2
R50 0_0402_5%

PTH
NPTH

H7 H10 H11 H12 H13 H14 H15 H21 H9 H16

B H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0x4P0N H_3P0N B

ISPD U1 HUDM3R1@ @ @ @ @ @ @ @ @ @ @

1
SA000043IN0
218-0755042 A13 HUDSON-M3

UV1 CHUNBW@ U1 HUDM3UNBW@

PCB Fedical Mark PAD
H18
SA000056220 SA000043IO0 H_3P0
@
FD1 FD2 FD3 FD4

@ @ @ @
1

CHELSEA PRO 218-0755042 A13 HUDSON-M3

1
UV1 THUNBW@ ZZZ

SA00004WI70 DA80000ST00
THAMES XT PCB LA-7291P
A A

PJP1 45@

Security Classification Compal Secret Data Compal Electronics, Inc.

PJP1 2011/11/28 2013/12/31 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Monday, March 26, 2012 Sheet 38 of 51
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

Vgs=10V,Id=9A,Rds=18.5mohm
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS +1.5V +1.5VS

4.7U_0805_10V4Z 4.7U_0805_10V4Z +5VS Vgs=10V,Id=9A,Rds=18.5mohm 4.7U_0805_10V4Z

1 1 1 1 1 1
Q29 C459 C460 Q30 C461 C462 Q31 C463 C464

470_0805_5%

470_0805_5%

470_0805_5%
8 D S 1 8 D S 1 For EMI 8 D S 1

2
7 2 7 2 1U_0402_6.3V6K 7 2
D S 2 2 R406 D S 2 2 R407 D S 2 2 R408

0.1U_0402_16V4Z

0.1U_0402_16V4Z
6 D S 3 6 D S 3 6 D S 3
5 D G 4 5 D G 4 2 2 5 D G 4
1U_0402_6.3V6K C822 C821 1U_0402_6.3V6K
1 SI4800BDY_SO8 1 R409 2 SI4800BDY_SO8 1 R418 2 SI4800BDY_SO8 1 R411 2 1
+VSB +VSB +VSB

3 1

3 1

3 1
120K_0402_5%

0.01U_0402_25V7K
120K_0402_5% @ @ 220K_0402_5%
0.022U_0402_25V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 1 1 1

6
C466 1 1

0.1U_0402_25V6
C465 R412 Q10A C467 C468 R413 Q11A C469 C470 R414 Q12A
820K_0402_5% Q10B 820K_0402_5% Q11B 820K_0402_5% Q12B
2 2 SUSP 2 2 SUSP 2 2 SUSP
2 5 2 5 2 5
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
2

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

4
+1.1VS

+1.1VALW to +1.1VS +0.75VS +5VALW

2
R417
+1.1VALW +1.1VS 470_0805_5% +5VALW R477 R422
470_0805_5% 100K_0402_5%
Vgs=10V,Id=14.5A,Rds=6mohm 4.7U_0805_10V4Z

3 1

2
1 1

1
Q44 C476 C472 R5545 SUSP
8 1 100K_0402_5%
D S

6
7 2 Q209B
D S 2 2 SUSP Q6B Q6A
6 3 5

1
D S 2N7002DW-T/R7_SOT363-6 FCH_PWR_EN#
5 D G 4 <28> FCH_PWR_EN#
1U_0402_6.3V6K 5 SUSP 2
<36,43,44> SUSP#

4
FDS6676AS_SO8 1 R415 2 +VSB
220K_0402_5% 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
4.7U_0805_10V4Z

1 1

1
1

3
0.1U_0402_25V6

2 C474 C477 R416 Q209A Q32B 2

820K_0402_5%
2 2 SUSP 2N7002DW-T/R7_SOT363-6
2 1 2 <36,44> FCH_PWR_EN 5
2N7002DW-T/R7_SOT363-6 R385 0_0402_5%
2

1
2 +1.5V +1.2VS
1

4
C200
0.1U_0402_16V4Z R5529

2
@ 100K_0402_5%
1 R478 +5VALW R479 +5VALW

2
Need to delay after 470_0805_5% 470_0805_5%
+3VS ramp up

2
3 1

3 1
R432 R448
100K_0402_5% 100K_0402_5%

Q210B Q211B

1
5 SYSON# 5 VR_ON#
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

6
4

4
Q210A Q211A

<36,43> SYSON 2 <36,46,47> VR_ON 2

2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

1
+5VS_ODD
+5VS TO +5VS_ODD
3 3

2
R457
470_0805_5%

6 1
Q53A Vgs=-4.5V,Id=3A,Rds<97mohm
2 ODD_PWR#
+5VS
2N7002DW-T/R7_SOT363-6

1
+5VALW

2
C471

2
R441 0.1U_0402_16V7K
100K_0402_5% PJ28

2
1
JUMP_43X79

3
S
R440 Q45 @

1
G

1
ODD_PWR# 1 2 2

1
47K_0402_5% 2
D

1
AO3413_SOT23

3
C217 +5VS_ODD
Q53B 0.01U_0402_25V7K
1
5 2N7002DW-T/R7_SOT363-6 1 1
<27> ODD_PWR
C679 C680

4
4.7U_0805_10V4Z 1U_0402_6.3V6K
4 @ 2 2 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 39 of 51
A B C D E
 A B C D

PL1
HCB2012KF-121T50_0805 PH1 under CPU botten side :
1 2 VIN CPU thermal protection at 93 +-3 degree C Please locate these parts
PL2
Near EC chip
HCB2012KF-121T50_0805 Recovery at 56 +-3 degree C
ADPIN 1 2

@ PJP1
+3VL

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J
+ 1

100P_0402_50V8J
1

1
2 <36,41> ADP_I
1
+ 1

PC1

PC2

PC3

PC4

12.1K_0402_1%
2

1
1K_0402_1%
3

2
-

PR4
PR1
- 4

SINGA_2DW-0005-B03

2
PR2 PR5
0_0402_5% 0_0402_5%

100K_0402_1%_TSM0B104F4251RZ
<36> PROCHOT_IN 1 2 <36> VCIN0_PH 1 2

1
20K_0402_1%
PR3

PH1
1

2
PL3
HCB2012KF-121T50_0805
1 2
VMB
PJP2 PL4
1 HCB2012KF-121T50_0805
1
2 2 1 2 BATT+
3 EC_SMCA
3 EC_SMDA
4 4

0.01U_0402_25V7K
5 TS_A
5

10U_0805_25V6K
6 6
PJSOT24CW_SOT323-3

+VSBP
2
7 3 1
7 B+
1

1
PC6

PC7

0.22U_0603_25V7K

0.1U_0603_25V7K
CCM_C250137GR007M262ZR PC5

100K_0402_1%
PD1

1000P_0402_50V7K
2

PC9
1
PR6
@

PC8
2

2
VL

2
PQ1

2
@PD2
@ PD2 PR7 TP0610K-T1-E3_SOT23-3
PJSOT24CW_SOT323-3 22K_0402_1%
2 1 2 VSB_N_001

1VSB_N_003
1
3 PR8
100K_0402_1%

1 2 PR9
EC_SMB_CK1 <36,41> D

1
PR10 100_0402_1% 0_0402_5%
<42,44> POK 1 2VSB_N_002 2 PQ2
1 2 G SSM3K7002FU_SC70-3
EC_SMB_DA1 <36,41>

.1U_0402_16V7K
PR11 100_0402_1% S

3
1

PC10
PJP3
1 2 +3VL +VSBP 2 1 +VSB
PR12 100K_0402_1%

2
PAD-OPEN 2x2m
BATT_TEMPA <36>

3 3

RTC Battery

- PBJ1 + PR14
560_0603_5%
PR15
560_0603_5%
2 1 1 2 1 2 +RTCBATT

@ MAXEL_ML1220T10

SP093MX0000
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
SCHEMATIC,MB LA-8863
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 23, 2012
4019IT Sheet 40 of 51
A B C D
 A B C D

for reverse input protection

1
PQ209
2
G SI1304BDL-T1-E3_SC70-3
S

3
PR225 PR226
1 2 1 2

1
1M_0402_5% 3M_0402_5% 1

1UH_NRS4018T1R0NDGJ_3.2A_30%
VIN PQ203 P1 PQ205 P2 PQ207
DMG4406LSS_SO8 PR211 B+ PL201 CHG_B+ DMG4406LSS_SO8
TPCA8057-H_PPAK56-8-5
0.01_1206_1%
1 1 8 1 4 1 2 8 1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2 2 7 7 2

0.1U_0402_25V6
5 3 3 6 2 3 6 3
2200P_0402_50V7K

0.1U_0402_25V6
5 5

PC216
1

1
0_0402_5%

PC211

PC212

PC213

PC214

PC215

0.01U_0402_50V7K
@ PR231

1
VIN

0_0402_5%
PC231

PR232
4

PC234
2

2
@ @ @
PC230

2
1

2
3

2
@

2
PD230
2

BQ24725_ACDRV_1 BAS40CW_SOT323-3

0.1U_0402_25V6
BQ24725_BATDRV 1 2BQ24725_BATDRV_1

PC235
0.047U_0402_25V7K PR233

1 1

10_1206_1%
1 2 4.12K_0603_1%
PC237

PR228
PC236 1 2
0.1U_0402_25V6

5
2.2_0603_5%
PR229
PD231

BQ24725_VCC
2
0.1U_0603_25V7K
RB751V-40_SOD323-2
PQ201

1
PC238
AON7408L

BQ24725_BST 2

BQ24725_REGN2
DH_CHG 4
4.12K_0603_1%

4.12K_0603_1%

2
PC239 2

BQ24725_LX
2
1

1 2 BATT+
PR234

PR235

DH_CHG
PL202
1U_0603_25V6K PC205 4.7UH_ETQP3W4R7WFN_5.5A_20% PR222

3
2
1
0.02_1206_1%

BQ24725_ACP

BQ24725_ACN
1 2
BQ24725_LX 1 2 CHG 1 4
2

1U_0603_25V6K

5
20

19

18

17

16
2 3
PU200 PQ202

2200P_0402_50V7K

0.01U_0402_50V7K
CSON1
CSOP1
1

680P_0402_50V7K 4.7_1206_5%
VCC

PHASE

HIDRV

BTST

REGN

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PR206
21 FDMC7692S_MLP8-5

0.1U_0402_25V6

0.1U_0402_25V6
PAD

PC224

PC225
PC221

PC222

PC223
1

1
1 15 DL_CHG 4
ACN LODRV @

PC240

PC241
2

2
2 14 @
ACP GND PR236

3
2
1

2
1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_1%

PC206
BQ24725_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP

1
PR237

2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN1 2 CSON1 @

2
ACDRV SRN

+3VALW 1 2 BQ24725_ACOK 5 ACOK BATDRV 11 BQ24725_BATDRV PC242

@PR238
@ PR238 10K_0402_1% 0.1U_0603_16V7K
ACDET

IOUT

SDA

ILIM
SCL
1 2 +3VALW
+3VL
6

10
PR239 10K_0402_1%
3
PR241 3

BQ24725_ILIM 1 2

0.01U_0402_25V7K
1 2
<13,36> ACIN

100K_0402_1%
PR240 10K_0402_1% 150K_0402_1%

PC243
PR242

1
BQ24725_ACDET

VIN 1 2

2
154K_0402_1%

PR243
2
1

270K_0402_1%
PR244
2

Vin Dectector
0.1U_0402_25V6

66.5K_0402_1%

100P_0402_50V8J

EC_SMB_CK1 <36,40>
1

Min. Typ Max.

1

2
PR245

1
PC246

100_0402_5%
PC244

PR246

H-->L 17.23V
EC_SMB_DA1 <36,40>
2

L--> H 17.63V
2

PC245
ILIM and external DPM 2 1 ADP_I <36,40>
100P_0402_50V8J
3.97A
Please locate the RC
4
Near EC chip 4

2011-02-22

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019IT
Date: Friday, March 23, 2012 Sheet 41 of 51
A B C D
 A B C D E

2VREF_8205

1
PC333
1U_0603_16V6K

2
1 1

PR330 PR350
13.7K_0402_1% 30K_0402_1%
1 2 1 2

PR331 PR351
B+ 3/5V_B+
20K_0402_1% 20K_0402_1%
3/5V_B+
PL331 1 2 FB_3V FB_5V 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
PR337 PR357
2200P_0402_50V7K

2200P_0402_50V7K

10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0402_25V6

0.1U_0402_25V6
120K_0402_1% 120K_0402_1%
1 2 1 2
1

1
PC338

PC339

PC340

PC353

PC354

PC358
6

1
PU330
2

5
ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
PC341
4 10U_0805_6.3V6M 25
PQ331 P PAD

2
AON7408L
7 24 4 PQ351
VO2 VO1 AON7408L

1
2
3
PC335 8 23 PR355 PC355
0.1U_0402_10V7K PR333 VREG3 PGOOD 2.2_0402_5% 0.1U_0402_10V7K
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2

3
2
1
2 2.2_0402_5% BOOT2 BOOT1 2
PL332 UG_3V 10 21 UG_5V PL352
4.7UH_ETQP3W4R7WFN_5.5A_20% UGATE2 UGATE1 2.2UH_ETQP3W2R2WFN_8.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
5

5
LG_3V 12 19 LG_5V
LGATE2 LGATE1

SKIPSEL
1

1
4.7_1206_5%

4.7_1206_5%

220U_6.3V_M
220U_D2_4VY_R15M

VREG5
PR336

PR356
1 1

GND

VIN

NC
EN
+ +
PC331

PC351
4 POK <40,44> 4
@ PR334
1 SNUB_3V 2

13

14

15

16

17

18

SNUB_5V 2
499K_0402_1% RT8205LZQW(2)_WQFN24_4X4
2 PQ352 2
3/5V_B+ 1 2
PQ332 FDMC7692S_MLP8-5
1
2
3

3
2
1

680P_0402_50V7K
FDMC7692S_MLP8-5

1
680P_0402_50V7K

1
PC336

PC356
PR338 PC342
100K_0402_1% 1U_0603_10V6K VL
2

2
1
@
PC359
4.7U_0805_10V6K

2
3/5V_B+

1
ENTRIP1

ENTRIP2

2VREF_8205
PC360

2
0.1U_0603_25V7K
3 3

D D
6

PQ333A 2N_3_5V_001 5 PQ333B

SSM6N7002FU_US6 G G SSM6N7002FU_US6

S S
1

PR339 PJP333
100K_0402_5% PJP352
+3VLP 2 1 +3VL
PR340 1 2 VL +5VALWP 1 2 +5VALW (7A,280mils ,Via NO.= 14)
2.2K_0402_1% PAD-OPEN 2x2m
1

1 2 PAD-OPEN 4x4m
<36> EC_ON PR341
PQ334
DRC5115E0L_SOD323-3 PJP332
0_0402_5%
+3VALWP 1 2 +3VALW (5A,200mils ,Via NO.= 10)
1 2 2
<36> VS_ON PAD-OPEN 4x4m
4.7U_0805_25V6-K
1

PC343

3
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019IT A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 23, 2012 Sheet 42 of 51
A B C D E
 5 4 3 2 1

0.75Volt +/- 5%
TDC 0.7A
Peak Current 1A
PL151
HCB1608KF-121T30_0603
D B+ 1 2 1.5V_B+ D
PR155
BST_1.5V 1 2 BOOT_1.5V +1.5V
2.2_0402_5%

2200P_0402_50V7K

10U_0805_25V6K
0.1U_0402_25V6

4.7U_0805_25V6-K
DH_1.5V +0.75VSP

0.22U_0402_10V6K
PC153

PC154

PC157

PC158

PC155

10U_0805_6.3V6K

10U_0805_6.3V6K

10U_0805_6.3V6K
SW_1.5V

1
PC260

PC261

PC262
@

1
5
DL_1.5V

16

17

18

19

20
PU150

2
PHASE

UGATE

BOOT

VTT
VLDOIN
21 @
PAD
4 15 LGATE VTTGND 1

PQ151 PR152 14 2
PL152 AON7408L 20K_0402_1% PGND VTTSNS

1
2
3
1UH_VMPI0703AR-1R0M-Z01_11A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC159 CS RT8207MZQW_WQFN20_3X3 GND

5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
PR157 VDDP VTTREF
1

5.1_0603_5%
330U_D2_2V_Y

1
C
+
1 2 VDD_1.5V 11 VDD VDDQ 5 +1.5VP C
PC152

PGOOD
@ PR156 4

1
4.7_1206_5%

TON
PQ152 +5VALW PC161

FB
S5

S3
SNUB_+1.5VP 2

1
2 FDMC7692S_MLP8-5 0.033U_0402_16V7K

2
PC160

1
2
3

10

6
1U_0603_10V6K
+5VALW

2
PR154
10.2K_0402_1%
FB_1.5V 2 1 +1.5VP

TON_1.5V
1

@ PC156
680P_0402_50V7K
2

Mode Level +0.75VSP VTTREF_1.5V

2
PR158
S5 L off off

1
887K_0402_1% PR160 PC162
S3 L off on PR159 1.5V_B+ 1 2 10K_0402_1% .1U_0402_16V7K
S0 H on on 0_0402_5%

2
1 2 EN_1.5V
<36,39> SYSON

1
Note: S3 - sleep ; S5 - power off

EN_0.75VSP
1 @ PC163
0.1U_0402_10V7K
B B
2

PR162
0_0402_5%
PJP152
2 1
1 2 <36,39,44> SUSP#
PAD-OPEN 4x4m

1
PJP153

+1.5VP
1 2
+1.5V (12A,480mils ,Via NO.= 24) @ PC164
0.1U_0402_10V7K

2
PAD-OPEN 4x4m

PJP76

+0.75VSP
1 2
+0.75VS (1A,40mils ,Via NO.= 3)
PAD-OPEN 3x3m

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019IT
Date: Friday, March 23, 2012 Sheet 43 of 51
5 4 3 2 1
 5 4 3 2 1

1.1valwp
Peak Current 4A

680P_0402_50V7K
current limited 6A

2
PC116

1 SNUB_+1.1VALWP
D D

4.7_1206_5%
2
PR116
PU110
PL111 SY8036LDBC_DFN10_3x3 PL112

1
4
HCB1608KF-121T30_0603 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1 2 1.1VALWP_B+ 10 2 1 2
+5VALW

PG
PVIN LX
+1.1VALWP
9 PVIN LX 3

2
10K_0402_1%

220P_0402_25V8K
68P_0402_50V8J
22U_0805_6.3V6K

22U_0805_6.3V6K

22U_0805_6.3V6K

22U_0805_6.3V6K
8 SVIN

100P_0402_25V8K

220P_0402_25V8K

2200P_0402_50V7K
68P_0402_50V8J

22P_0402_50V8J
PR108

@ PC117

@ PC118
22U_0805_6.3V6K

22U_0805_6.3V6K
PR106

1
@ PC106

@ PC107

@ PC108
0_0402_5% 6
<36,39> FCH_PWR_EN FB
1

PC104

PC112

PC113

PC114

PC115
1 2 EN_1.1VALWP
5 EN

PC109

PC110

PC111

SS
TP

LX

2
2

1
@PC119
@ PC119

11

2
12K_0402_1%
0.1U_0402_10V7K

2
@

PR109
PR107
0_0402_5%
<40,42> POK 1 2

1
C C

PJP112
+1.1VALWP 1 2 +1.1VALW
PAD-OPEN 4x4m (4A,240mils ,Via NO.= 8)

PU180

SY8033BDBC_DFN10_3X3

PL181 PL182

4
HCB1608KF-121T30_0603 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2 VIN_1.8VSP 10 2 LX_1.8VSP 1 2

PG
+5VALW PVIN LX +1.8VGSP

68P_0402_50V8J
B B
9 PVIN LX 3

1
1

1
4.7_1206_5%

PC188
PC184 8 SVIN

PR186
22U_0805_6.3V6M PR181
6 FB_1.8VSP 20K_0402_1%
2

2
FB

22U_0805_6.3V6M

22U_0805_6.3V6M
5

2
EN

1
NC

NC
TP

PC182

PC183
11 FB_1.8VSP

2
SNUB_1.8VSP
<36,39,43> SUSP# 1 2 EN_1.8VSP

1
@ PR183
0.1U_0402_10V7K

0_0402_5% PR182
1

10K_0402_1%
1

PC187

2
680P_0603_50V7K
@ PR184
1 2 47K_0402_5%
2

1
<14,25,26,49> PXS_PWREN

PC186
2

PR718
47K_0402_1%

PJP182

A +1.8VGSP
1 2
+1.8VGS (3A,120mils ,Via NO.= 6) A
PAD-OPEN 4x4m

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/29 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019IT
Date: Friday, March 23, 2012 Sheet 44 of 51
5 4 3 2 1
 A B C D

1
+VDDCI 1

TDC 2.2A

PL1001
OCP current 3A
PL1000

4
HCB1608KF-121T30_0603 PU1000 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2 10 2 LX_VDDCIP 1 2
+5VALW

PG
PVIN LX +VDDCIP

22P_0402_50V8J
9 PVIN LX 3

22U_0805_6.3V6M
4.7_0805_5%
1

22U_0805_6.3V6M
PC1000
PC1001 8 PR1006
SVIN

1
PR1001
22U_0805_6.3V6M 10_0402_5%

PC1003

PC1005
6 FB_VDDCIP

2
EN_VDDCIP FB
5

2
EN

NC

NC
TP
SY8033BDBC_DFN10_3X3 1 2
FB=0.6Volt

11

1
T@ PR1003

680P_0603_50V7K
PR1002 4.99K_0402_1%

PC1002
1 2 PR1004
<14,49> PX_MODE

2
1

0.1U_0402_10V7K
0_0402_5% 2 1 VDDCI_SEN <15>

47K_0402_5%

PC1004
1
PR1005
0_0402_5%
@

2
@ +3VGS

1
2 2

1
T@ PR1007

1
29.4K_0402_1% PR1008
10K_0402_5%

2
PR1000
10K_0402_1% PR1009
D

2
1
10K_0402_5%

2
2 2 1
G VDDCI_VID <13>

1
S

1
PQ1000
2N7002W-T/R7_SOT323-3 @ PC1006 PR1010 @
4700P_0402_25V7K 100K_0402_5%

2
VDDCI_VID

1V 0.95V
High
PR1003 5.23K_0402_1% PR1003 4.99K PR1003 5.23K
C@ SD034499180 SD034523180
PR1007 29.4K PR1007 86.6K
SD034294280 SD034866280
PR1007 86.6K_0402_1% 0.9V 0.91V
C@ Low
PR1003 4.99K PR1003 5.23K
SD034499180 SD034523180

Thames Chelsea

3 3

@PJP102
@PJP102
+VDDCIP 1 2 +VDDCI
JUMP_43X118

(2.2A,100mils ,Via NO.= 5)

@ PJP103

+VDDCI 2 2 1 1 +1.0VGS
JUMP_43X39

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/16 Deciphered Date 2012/08/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019IT
Date: Friday, March 23, 2012 Sheet 45 of 51
A B C D
 5 4 3 2 1

PL121
HCB1608KF-121T30_0603
+1.2VSP_B+ 2 1
B+

2200P_0402_50V7K

68P_0402_50V8J
10U_0805_25V6K
0.1U_0402_25V6
1

1
PC121

PC124
PC120

PC123
2

2
5
D PQ121 D
AON7408L_DFN8-5
PR125
2.2_0603_5% PC125
4
1 2 1 2

PU120 0.1U_0603_25V7K
1 10 BST_+1.2VSP

3
2
1
PGOOD VBST
PR127
1 2 TRIP_+1.2VSP 2 TRIP DRVH 9 UG_+1.2VSP PL122
105K_0402_1% 2.2UH_ETQP3W2R2WFN_8.5A_20%
<36,39,47> VR_ON PR120 EN_+1.2VSP 3 8 SW_+1.2VSP 1 2
0_0402_5% EN SW
+1.2VSP
1 2 FB_+1.2VSP 4 7 +1.2VSP_5V
VFB V5IN
+5VALW
2
47K_0402_1%

0.1U_0402_16V7K

RF_+1.2VSP 5 6 LG_+1.2VSP
TST DRVL
1

1
PR121

PQ122 1

1
@ PC127

330U_D2_2.5VY_R15M
TP 11
+

PC122
FDMC7692S_MLP8-5
PC128 PR126
2

1
TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M 4.7_1206_5%
1

2
@ PR129 2
4
470K_0402_1% Ipeak=8.5A

1
PC126
Imax=5.95A
2

1000P_0603_50V7K

3
2
1

2
F=290K
C @ @ C
PC129 PR130
2 1 2 1

PJP122 +1.2VS
PR131 1000P_0402_50V7K 1.2K_0402_1% +1.2VSP 2 2 1 1
7.15K_0402_1% @ JUMP_43X118
2 1
(8.5A,340mils ,Via NO.=17)

+1.2VSP
Iocp=13A
2

PR132
10K_0402_1%
1

B B

PU25
APL5508-25DC-TRL_SOT89-3
+3VS PJP252
2 IN OUT 3 +2.5VSP
+2.5VSP 2 1 +2.5VS
2 1

1
GND @ JUMP_43X39

4.7U_0805_6.3V6K
1

1
(0.75A,40mils ,Via NO.=22)

PC251
@ PR250
PC250 1 10K_1206_5%
1U_0603_10V6K
2

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/29 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019IT
Date: Friday, March 23, 2012 Sheet 46 of 51
5 4 3 2 1
 5 4 3 2 1

PC501 PR527
330P_0402_50V7K 2K_0402_1%
2 1 2 1
<7> APU_VDDNB_SEN PC527
PR528 PR529 @ PR530
2.8K_0402_1% 137K_0402_1%390P_0402_50V7K 32.4K_0402_1%
2 1 2 1 2 1 2 1
PL501
CPU_B+
PR500 PR531 PC528 PR532 PC529 HCB2012KF-121T50_0805

10U_0805_25V6K
10_0402_5% 0_0402_5% 1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J 1 2 B+
D D

560P_0402_50V7K

2200P_0402_50V7K
10U_0805_25V6K
2 1 2 1 2 1 2 1 2 1 PL502
+APU_CORE_NB

100U_25V_M
100U_25V_M

68P_0402_50V8J
100U_25V_M
1 1 1 HCB2012KF-121T50_0805

0.1U_0402_25V6
5
@PC531

TPCA8065-H_SOP-ADV8-5
1 2
+

1
+

PC535
+

PC532

PC570

PC533

PC534

PC537

PC530
VSUMP_NB

PC569
1000P_0402_50V7K

PC536
2.61K_0402_1%
10K_0402_5%_ERTJ0ER103J
1

PQ501
2 1

2
2 2 2
PR533

@
0.047U_0402_16V7-K

0.1U_0402_25V6
UGATE_NB1 4
2

11K_0402_1%

2
PR534
12

PC538

PC539
PH2

3
2
1
PL503
1

PR535 0.36UH_MMD10DZR36MS1_24A_20%
634_0402_1% PHASE_NB1 1 4
+APU_CORE_NB
2

VSUMN_NB 2 1 FCCM_NB

1
PC505

0_0603_5%
2 3

PR536
1

1
@ PC541

5
@ PR537 PR505 0.22U_0603_25V7K
PC540 100_0402_1% 220P_0402_50V7K BOOT_NB1 2 1 2 1 PQ502 PR506 PR538
0.1U_0603_50V7K 2 1 2 1 LGATE_NB1 TPCA8057-H_PPAK56-8-5 4.7_1206_5% 3.65K_0402_1%
2

PR539 @ 0_0603_5% VSUMP_NB 2 1

2
2 1 PHASE_NB1

1 2
10K_0402_1% LGATE_NB1 4 PR540
UGATE_NB1 1_0402_1%
After rev1.1 must change to 133k VSUMN_NB 2 1
APU_CORE_NB
PC506
TDC 25A

2
680P_0603_50V7K

48

47

46

45

44

43

42

41

40

39

38

37
2

Peak Current 33A

3
2
1
PU500
2

PR541

ISUMP_NB
ISEN1_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

FCCM_NB

PWM2_NB

LGATEX

PHASEX

UGATEX
127K_0402_1% PC542 PR542 OCP current 40A
1000P_0402_25V6K 10_0402_5% CPU_B+
Load line -4mV/A
1

+5VS 2 1 1 36 BOOT_NB1
1

PR543 27.4K_0402_1% ISEN2_NB BOOTX PR544

2 1 2 35 2 1
FSW=300kHz
NTC_NB VIN
PH3 BOOT2 0_0603_5%
DCR 1.1mohm +/-5%
3 IMON_NB BOOT2 34

1
470K_0402_5%_TSM0B474J4702RE PR545 0_0402_5% TYP MAX
C 2 1 2 1 SVC 4 33 UGATE2 PC543 C
<7,36> H_PROCHOT# <7> APU_SVC
PR546 0_0402_5%
SVC UGATE2
0.22U_0603_25V7K CPU_B+ H/S Rds(on) :11.7mohm , 14.5mohm

2
2 1 5 32 PHASE2
VR_HOT_L PHASE2 L/S Rds(on) :2.6mohm , 3.2mohm
1

PR548 0_0402_5%
+5VALW

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.01U_0402_25V7K
PR547
<7> APU_SVD 2 1 SVD 6 SVD LGATE2 31 LGATE2
10.5K_0402_1% PR549 0_0402_5% ISL6277HRTZ-T_TQFN48_6X6 PR582 0_0402_5%
+1.5VP 2 1 VDDIO 7 VDDIO VDDP 30 2 1
2 1 PR550 0_0402_5% PR583 PR551
2

1
PC544

PC547

PC545

PC546
<7> APU_SVT 2 1 SVT 8 SVT VDD 29 2 1 2 1

5
1U_0603_16V6K

TPCA8065-H_SOP-ADV8-5
PC568 1U_0603_16V6K PR552 0_0402_5% 1_0603_5%
0_0402_5%
<36,39,46> VR_ON 2 1 ENABLE 9 28

2
ENABLE PWM_Y

1
After rev1.1 must change to 133k

1U_0603_16V6K
PR553 0_0402_5%

PQ503
PC549
PR554
<7,25> APU_PWRGD 2 1 PWROK 10 PWROK LGATE1 27 LGATE1

PC548
118K_0402_1% PR508

2
1 2 11 26 PHASE1 UGATE1 2 1UGATE1-1 4
IMON PHASE1
PC550 12 25 UGATE1 0_0603_5%
1000P_0402_25V6K NTC UGATE1

PGOOD
PL504

BOOT1
ISUMN
ISUMP

COMP
ISEN3

ISEN2

ISEN1

+3VS
VSEN

1 2 0.36UH_FDUE1030D-H-R36M=P3_32A_20%
RTN

3
2
1
FB2

+5VS
FB

TP
PHASE1 1 4
PR555 27.4K_0402_1% PR557 +APU_CORE
13

14

15

16

17

18

19

20

21

22

23

24

49

1
2 1 0_0402_5% PC515 ISEN1 2 PR556 1 2 3 1 2 ISEN2

5
2 1 ISEN3 PR515 0.22U_0603_25V7K 10K_0402_1%

1
PH4 PR558 BOOT1 2 1 2 1 PR516 PR559
470K_0402_5%_TSM0B474J4702RE 2 1 ISEN2 BOOT1 100K_0402_5% 4.7_1206_5% PR561 10K_0402_1%
2 1 0_0603_5% 3.65K_0402_1%

2
PR560
@PR560
@ ISEN1 VSUM+ 2 1
1
0.22U_0402_10V6K

0.22U_0402_10V6K

10_0402_5% LGATE1 4

1 2
1

@PR563
@ PR563 VGATE <36> PC516
1

PR562 10K_0402_1% 680P_0603_50V7K PR564

PQ506
PC553 1_0402_1%
10.5K_0402_1%
10P_0402_25V8K TPCA8059-H_PPAK56-8-5 VSUM- 2 1
APU_core
2

3
2
1

2
PC551

PC552

2 1 TDC 36A
2

VSUM-
CPU_B+ Peak Current 50A
B
VSUM+ OCP current 60A B

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K
2.61K_0402_1%

@ PR567

0.01U_0402_25V7K
PC554 PR566 PC555
Load line -2.1mV/A
1

1000P_0402_50V7K301_0402_1% 100P_0402_50V8J 32.4K_0402_1%

5
330P_0402_50V7K
PR565

0.022U_0402_16V7K

0.22U_0402_10V6K

TPCA8065-H_SOP-ADV8-5
2 1 2 1 2 1 2 1 FSW=300kHz
2

1
PC558

PC559

PC562

PC563
DCR 1.1mohm +/-5%
2

2
11K_0402_1%

PQ505
PR569 PR570 PC561
12

TYP MAX
PR568

PC556

PC560

PC557

2.26K_0402_1% 137K_0402_1% 390P_0402_50V7K PR509

2
PH5 2 1 2 1 2 1 UGATE2 2 1UGATE2-1 4
H/S Rds(on) :11.7mohm , 14.5mohm
1

10K_0402_5%_ERTJ0ER103J
1

PR572 0_0603_5%
604_0402_1% PR571 PC564 L/S Rds(on) :2.6mohm , 3.2mohm
2

VSUM- 2 1 2K_0402_1% 680P_0402_50V7K PL505

3
2
1
2 1 2 1 0.36UH_FDUE1030D-H-R36M=P3_32A_20%
@ PC566
1

@ PR573 PHASE2 1 4
PC565 100_0402_1% 820P_0402_50V7K PR575 +APU_CORE
0.1U_0603_50V7K 2 1 2 1 10_0402_5% PC525 ISEN2 2 PR574 1 2 3 1 2 ISEN1
2

1
2 1 +APU_CORE PR525 0.22U_0603_25V7K 10K_0402_1%
PR577 BOOT2 2 1 2 1 PR526 PR576
0_0402_5% 4.7_1206_5% PR578 10K_0402_1%
2 1 APU_VDD_SEN <7> 0_0603_5% 3.65K_0402_1%
VSUM+ 2 1

1 2
LGATE2 4
PR580 PC526
0_0402_5% 680P_0603_50V7K PR579
0.01U_0402_25V7K

2 1 PQ508 1_0402_1%

2
PR581 VSUM- 2 1

3
2
1
10_0402_5% APU_VDD_RUN_FB_L <7> TPCA8059-H_PPAK56-8-5
2

2 1
PC567
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 47 of 51
5 4 3 2 1
 A
B
C
D
PC813 PC806 PC801
0.22U_0402_16V7K 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1

2
1
+
PC821 PC814
330U_D2_2V_Y 0.22U_0402_16V7K
2 1

+APU_CORE
+APU_CORE

5
5

PC815 PC807 PC802

0.01U_0402_50V7K 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1

2
1
+
+APU_CORE

PC816
PC822 0.01U_0402_50V7K
330U_D2_2V_Y 2 1

PC817

Local
0.01U_0402_50V7K PC808 PC803
2 1 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1

2
1
+
PC823
330U_D2_2V_Y

PC818 @ PC811 PC809 PC804

180P_0402_50V8J 22U_0805_6.3VAM 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1 2 1

PC819
180P_0402_50V8J

2
1
+
2 1
PC824
330U_D2_2V_Y
@

PC820 PC812 PC810 PC805

180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1 2 1

4
4

PC970 PC944 PC965 PC932

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC955 PC945 PC966 PC931

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1 PC832 PC827
0.22U_0402_16V7K 22U_0805_6.3V6M
2 1 2 1
+VGA_CORE

PC971 PC946 PC964 PC923

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1 PC833
0.22U_0402_16V7K
2 1
PC957 PC947 PC937 PC924 PC828
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 22U_0805_6.3V6M

Issued Date
2 1 2 1 2 1 2 1 PC834 2 1
+VGA_CORE

180P_0402_50V8J
PC829

Security Classification
2 1
+APU_CORE_NB

PC958 PC948 PC938 PC925 22U_0805_6.3V6M

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 2 1
+VDDC

2 1 2 1 2 1 2 1 PC835

3
3

180P_0402_50V8J PC830
2 1 10U_0805_6.3V6K
PC959 PC949 PC969 PC926 2 1
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
@

2 1 2 1 2 1 2 1 PC836 PC831
180P_0402_50V8J 22U_0805_6.3V6M
2 1 2 1
PC960 PC950 PC940 PC928

2011/07/29
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC961 PC951 PC941 PC927

+APU_CORE_NB

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M

2 1 2 1 2 1 2 1

PC962 PC952 PC942 PC929

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1
2
1
+

PC963 PC953 PC943 PC933

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M PC825
capacitors under processor on bottom side of board

Compal Secret Data

2 1 2 1 2 1 2 1 330U_D2_2V_Y

Deciphered Date
2
1
+

PC921 PC934 PC826

10U_0603_6.3V6M 1U_0402_6.3V6K 330U_D2_2V_Y
2 1 2 1
+APU_CORE_NB

2
2

PC922 PC939
10U_0603_6.3V6M 1U_0402_6.3V6K
2 1 2 1
Local

PC930 PC935
10U_0603_6.3V6M 1U_0402_6.3V6K
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2 1 2 1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PC954
1U_0402_6.3V6K
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

2 1
Size
Title

Date:

PC968
1U_0402_6.3V6K
2 1

PC956
1U_0402_6.3V6K
Document Number

2 1
+VDDCI

Friday, March 23, 2012

PC936
1U_0402_6.3V6K
2 1

PC967
1U_0402_6.3V6K
1
1

4019IT

2 1
Sheet

PC972
1U_0402_6.3V6K
48

2 1
of

PC973
+VDDCI

1U_0402_6.3V6K
Compal Electronics, Inc.

2 1
SCHEMATIC,MB LA-8863

51
+VDDCI

Rev
A
A
B
C
D
 A B C D E F G H

10K_0402_1%PR724
10K_0402_1%PR724 GPU_VID1 2 @
1 2 1 PR725 10K_0402_1%
1 1

<13>

<13>

<13>

<13>
GPU_VID1

GPU_VID2

GPU_VID3

GPU_VID4
PX_MODE

<14,45>
10K_0402_1%PR726
10K_0402_1%PR726 1 2 GPU_VID2 2 1@
@PR727
PR727 10K_0402_1%

+3VGS
10K_0402_1%PR728
10K_0402_1%PR728 1 2 GPU_VID3 2 1@PR729 10K_0402_1%

10K_0402_1%PR730 @ 1 2 GPU_VID4 2 1 PR731 10K_0402_1% +3VGS

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
+5VS

+VGA_B+

PR732

0.1U_0402_16V7K
2

0_0402_5%
80.6K_0402_1%
PL701

2
PC739

PR733
HCB2012KF-121T50_0805

PR734

PR735

PR736

PR737

PR738

PR739

PR740
1 2 B+
@ PR741 PL702

1
@ 10_0603_1%

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
HCB2012KF-121T50_0805

2200P_0402_25V7K
0.1U_0402_25V6
1 2

PC746
1

1
PC740

PC741

PC742

PC745
S TR AON7518 1N DFN

S TR AON7518 1N DFN
32 VGA_EN

VID1

VID2

VID3

VID4
+3VS

2
1
VGA_VCC

5
PU700 PC747

PQ701
1U_0603_10V6K

PQ703
31

30

29

28

27

26

25

2
PR742
1K_0402_1%

VID0

VID1

VID2

VID3

VID4

VID5

VID6
EN
24 PR705 PC705 4 4

2
VCC 0.22U_0603_25V7K
<25,26> VGA_PWRGD 1 2.2_0603_5%
PWRGD
PC748
BST 23 VGA_BOOST 1 2VGA_BOOST-11 2
1

1000P_0402_50V7K PR743 2 IMON PR723 PL703

40.2K_0402_1% 22 VGA_DRVH 2 1 VGA_DRVH1

3
2
1
DRVH

3
2
1
2 PR744 1 2 3 0_0603_5% 0.36UH_FDUE1040J-H-R36M-P3_33A_20% 2
2

0_0402_5% CLKEN# VGA_SW

21 3 2
<15> VSSSENSE_VGA 2 1 4
SW +VGA_CORE
FBRTN PR745

4.7_1206_5%
ADP3211AMNR2G_QFN32_5X5 20 2 1 +5VS 4 1
PVCC

1
1 2 VGA_FB 5 0_0603_5%

TPCA8059-H_PPAK56-8-5
PQ702
FB
Ipeak=59A

PR706
VGA_DRVL

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
19 2 1

TPCA8059-H_PPAK56-8-5
DRVL 1 1 1 1
1

PQ704
PC749 PC751 VGA_COMP 6
COMP + + + + Imax=45.7A

PC796

PC797

PC798

PC799
PR746 220P_0402_50V7K 47P_0402_50V8J 18 PC750
0_0402_5% VGA_VCC 7 PGND 2.2U_0603_10V6K 4 4
F=300kHZ
2

2
GPU
<15> VCCSENSE_VGA 2 1 1 2 1 2VGA_COMP-1
1 2 AGND 17
2 2 2 2
VGA_ILIM 8
Total capacitor

680P_0603_50V8J
CSCOMP
ILIM

1
PR747 PC756 PR748 33

CSREF
AGND
1320u

RAMP

LLINE

CSFB

PC716
1K_0402_1% 470P_0402_50V8J 20K_0402_1%

IREF

RPM

3
2
1

3
2
1
RT
ESR=2.25m ohm

2
9

10

11

12

13

14

15

16
2

PR707
3.92K_0402_1%
VGA_IREF

VGA_RAMP

VGA_CSFB

VGA_CSCOMP
VGA_RT
VGA_RPM
VGA_CSCOMP 1

Thames XT
237K_0402_1%

301K_0402_1%

PR752 422K_0402_1%
PR749

PR750

PR751
80.6K_0402_1%

VID4 VID3 VID1

1
1

0 0 0 X

1
1

1
0 1 0 1.0V
PR753
2

Connect to input caps PC757 PC758 220K_0402_1% 1 0 0 0.9V

2

2
1000P_0402_50V7K 1200P_0402_50V7K
1

2
PR755 2 1 0 1 0.875V
1K_0402_1%
3 3
+VGA_B+ 2 1 VGA_RAMP-1 PR754
107K_0603_1%
1

PC759 PC760
1000P_0402_50V7K 1000P_0402_50V7K
2

+1.1VALW +5VALW
1

PL101

HCB1608KF-121T30_0603 1 2
1

0_0402_5%

@ PR756
2

PR757

0_0402_5%
1U_0603_6.3V6M
1

PC708
1

PC706
2

22U_0805_6.3V6M
2

VGA_CSCOMP
2

PU701
6 VCNTL
PR719 5 3 +1.0VGSP
VIN VOUT
9 VIN VOUT 4
1

39P_0402_50V8J

22U_0805_6.3V6M

22U_0805_6.3V6M

0_0402_5%
1

1 2 8 PR721
<14,25,26,44> PXS_PWREN EN
PC738

PC731

PC732

1 2 7 2 12K_0402_1%
GND

+3VS POK FB
+VGA_PCIE
2

@ PR720
2
1

1K_0402_1%
TDC 3.6A
1

@ PC736 APL5916KAI-TRL_SO8
1

0.01U_0402_25V7K Peak Current 5.2A

2

T@ PR722
47.5K_0402_1%
4 4
2

PR722 63.4K_0402_1%
C@
Thames XT Chelsea Pro

@PJP702
@PJP702
+1.0VGSP 1 2 +1.0VGS VGA_PCIE 1.0V 0.95V Security Classification Compal Secret Data Compal Electronics, Inc.
JUMP_43X118 Issued Date 2009/10/02 Deciphered Date 2010/10/02 Title
SCHEMATIC,MB LA-8863
PR722 47.5K 63.4K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SD034475280 SD03463K280 A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 49 of 51
A B C D E F G H
 5 4 3 2 1

HW PIR (Product Improve Record)

QMLE4 LA-8863P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2012/02/10
Item Date Page Solution Request
--------------------------------------------------------------------------------------------------------------------------
D 1. 1/10 P32 Add PJ31 For saving power consumption D

2. 1/12 P38 Change JTP symbol to SP01001BF10 For ME request

3. 1/30 P35 Add internal MIC to MB For customer request
4. 2/2 P14 Remove PX4.0 circuit Support PX5.0
5. 2/2 P31 Add PJ26,PJ33, WLAN power circuit and reset pin For customer request
6. 2/2 P33 Update JCRIO pin definition Change int. MIC to MB
7. 2/2 P35 Remove CA64, add RA32 and RA33 Move sense resistors to MB
8. 2/3 P31 Change JWLAN symbol to SP07000TB00 For ME request
9. 2/3 P31 Add WLAN_PWR# and WLAN_RST# For customer request
10. 2/7 P32 Change UL3 and UL4 PN to SP050005V00 For shortage
--------------------------------------------------------------------------------------------------------------------------

REVISION CHANGE: 0.2 TO 0.3

GERBER-OUT DATE: 2012/03/12
Item Date Page Solution
--------------------------------------------------------------------------------------------------------------------------
1. 3/1 P12 Update RTC scematic For avoiding +3VL short to GND
C 2. 2/29 P22 Change R108 pull-high from +3VS to +3VALW For LVDS sequence issue C

3. 3/7 P26 Add R292 and reserve R293 To avoid PXS_PWREN floating
4. 3/7 P7 Unstuff R121~R124,R118,R119 For debug use
5. 3/7 P27 Update U13 footprint
6. 3/7 P27/30 Connect SATA port2 to 15"ODD connector, and add GPIO54 To solve SATA EA fail issue
7. 3/8 Change RB20,RB34,R3,RV102,R425,R136,R31,R32,R33,RV284,RV287
R62,RV277 to short pad
8. 3/12 P24 Add C201 and C214 For EMI request
9. 3/12 P30 Add C364 and C365 For EMI request
10. 3/12 P35 Add CA5, CA6, CA64, CA67, CA68 and CA77 For EMI request
11. 3/14 P8 Add C147 co-layout with C100 To avoid damage by SMT process
12. 3/14 P10 Add C148 co-layout with C218 To avoid damage by SMT process
--------------------------------------------------------------------------------------------------------------------------

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/28 Deciphered Date 2013/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019IT
Date: Friday, March 23, 2012 Sheet 50 of 51
5 4 3 2 1
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

----------------------------------------------------------------------------------------------------------------------------------------
1. 2012/02/14 P40-PWR-DCIN/BATT CONN/OTP Delete PR12,PR13 Circuit modify
2. 2012/02/14 P41-PWR-CHARGER Change PR211 to 0.01_1206_1%,PL201 to1UH 4*4*2 Circuit modify
Add PC207,PC208,PC217,PC218,Delete PC232,PC233
3. 2012/02/14 P43-PWR-1.5VP/+0.75VSP Change PL152 to SH00000KS00 Circuit modify
4. 2012/02/14 P44-PWR-+1.1VALWP/+1.8VSP Change PR718 to 47K,add PC187 HW request
5. 2012/02/14 P46-+1.2VSP/+2.5VSP Change PL122 to 2.2uH(SH00000MR00), Circuit modify
PR127 to SD034105380
6. 2012/02/14 P37-PWR +CPU_CORE Change PQ502 to TPCA8057 Circuit modify
D D
7. 2012/03/06 P40-PWR-DCIN/BATT CONN/OTP Add PR12(100KΩ) Circuit modify

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB LA-8863
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019IT A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 23, 2012 Sheet 51 of 51
5 4 3 2 1
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