This is the coding of simple multiplier. Output comes as it is.

Simulation/test bench

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity simplemultiplier is

port(

clk:in std_logic;

multiplier :in std_logic_vector(3 downto 0);

multiplicand:in std_logic_vector(3 downto 0);

output: out std_logic_vector(7 downto 0)

);

end simplemultiplier;

architecture Behavioral of simplemultiplier is

begin

process(multiplier,multiplicand,clk)

variable m , n :std_logic_vector(7 downto 0);

begin

if clk'event and clk = '1'

then

m := "00000000";

n := "0000" & multiplicand;

for i in 0 to 3 loop
 if multiplier(i)= '1' then

m := m+ n;

end if;

n:= n(6 downto 0) & '0';

end loop;

output(7 downto 0) <= m(7 downto 0);

end if;

end process;

end behavioral;

this is the main code

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY output_vhd IS

END output_vhd;

ARCHITECTURE behavior OF output_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT simplemultiplier

PORT(

clk : IN std_logic;

multiplier : IN std_logic_vector(3 downto 0);

multiplicand : IN std_logic_vector(3 downto 0);

output : OUT std_logic_vector(7 downto 0)

 );

END COMPONENT;

--Inputs

SIGNAL clk : std_logic := '0';

SIGNAL multiplier : std_logic_vector(3 downto 0) := (others=>'0');

SIGNAL multiplicand : std_logic_vector(3 downto 0) := (others=>'0');

--Outputs

SIGNAL output : std_logic_vector(7 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: simplemultiplier PORT MAP(

clk => clk,

multiplier => multiplier,

multiplicand => multiplicand,

output => output

);

clock_period: process

begin

clk<='0';

wait for 6.25 ns;

clk<='1';

wait for 6.25 ns;

end process clock_period;

tb : PROCESS

BEGIN
 multiplier <="0010";

multiplicand <="0001";

wait for 100 ns;

-- Wait 100 ns for global reset to finish

multiplier<="0011";

multiplicand <="0010";

wait for 100 ns;

multiplier <="0100";

multiplicand <="0011";

wait for 100 ns;

multiplier<="0101";

multiplicand<="0100";

wait for 100 ns;

multiplier <="0110";

multiplicand<="0101";

wait for 100 ns;

END PROCESS;

END;