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Question 1)

DMA performs data transfer operation. The different DMA transfer modes are as
follows:-
1) Burst or block transfer DMA
2) Cycle steal or single byte transfer DMA.
1) Burst or block transfer DMA

 It is the fastest DMA mode. In this two or more data bytes are transferred
continuously.
 Processor is disconnected from system bus during DMA transfer. N number of
machine cycles are adopted into the machine cycles of the processor where N is
the number of bytes to be transferred.
 DMA sends HOLD signal to processor to request for system bus and waits for
HLDA signal.
 After receiving HLDA signal, DMA gains control of system bus and transfers one
byte. After transferring one byte, it increments memory address, decrements
counter and transfers next byte.
 In this way, it transfer all data bytes between memory and I/O devices. After
transferring all data bytes, the DMA controller disables HOLD signal & enters into
slave mode.

2) Cycle steal or single byte transfer DMA.

 In this mode only one byte is transferred at a time. This is slower than burst
DMA.
 DMA sends HOLD signal to processor and waits for HLDA signal on receiving
HLDA signal, it gains control of system bus and executes only one DMA cycle.
 After transfer one byte, it disables HOLD signal and enters into slave mode.
 Processor gains control of system bus and executes next machine cycle. If count
is not zero and data is available then the DMA controller sends HOLD signal to
the processor and transfer next byte of data block.

Question 2)
PAGE 12
MODULE 2
MY NOTES

Question 3)
PAGE 17
MODULE 2
Question 4)
PAGE 13 AND 14
MODULE 2
MY NOTES

Question 5)
PAGE 18
MODULE 2
MY NOTES

Question 6)Problem solved in class

Question 7)
RDRAM uses Rambus Inline Memory Module (RIMM) technology, which is installed in pairs,
transfers data from rising and falling clock signal edges and doubles physical clock rates.
The RDRAM 16-bit bus uses a set of data processing features with a steady sequence stream,
known as pipelining, that facilitate the output of one instruction prior to the input of the next
instruction. Pipelining transfers RAM data to cache memory, allowing up to eight simultaneous
data processing series. Pipelining also improves performance by increasing average successful
message delivery rates when processing streams of data.

ROM stands for Read Only Memory. The memory from which we can only read but cannot
write on it. This type of memory is non-volatile. The information is stored permanently in
such memories during manufacture. A ROM stores such instructions that are required to
start a computer. This operation is referred to as bootstrap. ROM chips are not only used
in the computer but also in other electronic items like washing machine and microwave
oven.
There are five basic ROM types:
 ROM.
 PROM.
 EPROM.
 EEPROM.
 Flash memory.
Question 8)
Memory Controller Diagram and explanation
page 12
module 3
my notes

Memory access time is how long it takes for a character in RAM to be transferred to or from the
CPU. Fast RAM chips have an access time of 10 nanoseconds (ns) or less.

memory latency is the time (the latency) between initiating a request for a byte or word
in memory until it is retrieved by a processor. If the data are not in the processor's cache, it takes
longer to obtain them, as the processor will have to communicate with the external memory cells.

Memeory Cycle time is the time, usually measured in nanosecond s, between the start of one
random access memory ( RAM ) access to the time when the next access can be started. ... Cycle
time consists of latency (the overhead of finding the right place for the memory access and
preparing to access it) and transfer time.

Memory bandwidth is the rate at which data can be read from or stored into a
semiconductor memory by a processor. Memory bandwidth is usually expressed in units of
bytes/second

Question 9)Problem Solved in class

Question 10) Cache is a small high-speed memory. Stores data from some frequently used
addresses (of main memory).
Cache hit Data found in cache. Results in data transfer at maximum speed.
Cache miss Data not found in cache. Processor loads data from M and copies into cache. This
results in extra delay, called miss penalty.

The fraction or percentage of accesses that result in a hit is called the hit rate. The fraction
or percentage of accesses that result in a miss is called the miss rate. The “extra” time required
to fetch a block into a level of the memory hierarchy from the lower level is called miss penalty.
Question 11)
PAGE 18,19,20
MODULE 3
MY NOTES

Question 12)
PAGE 3 and 4
MODULE 3
MY NOTES

Question 13)
PAGE 1
MODULE 3
MY NOTES

Question 14)
PAGE 19, 20
MODULE 2
MY NOTES

Question 15)
PAGE 12
MODULE 2
MY NOTES

Question 16)
PAGE 12
MODULE 2
MY NOTES
But this is for output operation so the diagram changes

Question 17)
PAGE 13, 14 and 15
MODULE 2
MY NOTES

Question 18)
PAGE 18 to 21
MODULE 3
MY NOTES
Question 19)
Cache is a small high-speed memory. Stores data from some frequently used addresses (of main
memory).
Cache hit Data found in cache. Results in data transfer at maximum speed.
Cache miss Data not found in cache. Processor loads data from M and copies into cache. This
results in extra delay, called miss penalty.

The fraction or percentage of accesses that result in a hit is called the hit rate. The fraction
or percentage of accesses that result in a miss is called the miss rate. The “extra” time required
to fetch a block into a level of the memory hierarchy from the lower level is called miss penalty.

Cache Coherence:
A protocol for managing the caches of a multiprocessor system so that no data is lost or
overwritten before the data is transferred from a cache to the target memory. ... In a directory-
based system, the data being shared is placed in a common directory that maintains
the coherence between caches

Question 20)Problem solved in class

Question 21)
PAGE 9 and 10
MODULE 3
MY NOTES

Question 22)
PAGE 5 Diagram 8.4
MODULE 3
MY NOTES
Question 23)
PAGE 5 Diagram 8.4 STATIC MEMORY SYSTEM
PAGE 6 Diagram 8.6 DYNAMIC MEMORY SYSTEM
MODULE 3
MY NOTES

Question 24) problem solved in class

Question 25)
Prefetching is a technique for speeding up fetch operations by beginning a fetch operation whose
result is expected to be needed soon. Usually this is before it is known to be needed, so there is a
risk of wasting time by prefetching data that will not be used. The technique can be applied in
several circumstances:
Cache prefetching is a technique used by computer processors to boost execution performance by
fetching instructions or data from their original storage in slower memory to a faster local memory
before it is actually needed

Question 26)
PAGE 12
MODULE 2
MY NOTES

Question 27) Problem solved in cache

Question 28)
PAGE 22 and 23
MODULE 3
MY NOTES
Write back
Write back is a storage method in which data is written into the cache every time a change occurs,
but is written into the corresponding location in main memory only at specified intervals or under
certain conditions.

When a data location is updated in write back mode, the data in cache is called fresh, and the
corresponding data in main memory, which no longer matches the data in cache, is called stale. If
a request for stale data in main memory arrives from another application program, the cache
controller updates the data in main memory before the application accesses it.

Question 29)
PAGE 16 and 17
MODULE 2
MY NOTES

Question 30)
PAGE 13, 14 and 15
MODULE 2
MY NOTES

Question 31)
PAGE 22 and 23
MODULE 3
MY NOTES

Question 32)

ROM stands for Read Only Memory. The memory from which we can only read but cannot
write on it. This type of memory is non-volatile. The information is stored permanently in
such memories during manufacture. A ROM stores such instructions that are required to
start a computer. This operation is referred to as bootstrap. ROM chips are not only used
in the computer but also in other electronic items like washing machine and microwave
oven.
There are five basic ROM types:
 ROM.
 PROM.
 EPROM.
 EEPROM.
 Flash memory.

MEMORY HIERARCHY
PAGE 17
MODULE 3

Question 33)
PAGE 6
MODULE 3
MY NOTES