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5 4 3 2 1

PAGE TITLE
GA-970A-D3P Revision : 1.0
26 ATX, FRONT PANEL ,EC
PAGE TITLE 27 VCORE PWM IR3564B
D 01 COVER SHEET 28 VCORE MOS D

02 BOM & PCB MODIFY HISTORY 29 POWER SEQUENCE ,VCC18 ,EUP

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03 BLOCK DIAGRAM 30 NB/SB POWER,VCC12HT,VDDA25

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04 CPU HYPER TRANSPORT 31 DDR PWR, EUP

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05 CPU DDRIII MEMORY 32 USB3 VL805

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06 CPU CONTROL 33 USB3 VL805 F_USB3, R_USB3

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07 CPU POWER & GND 34 PCIE X4

fi
08 DDRIII CHANNEL A 35 REALTEK RTL8111F

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C C
09 DDRIII CHANNEL B

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10 RD980 HT,SYS I/F

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11 RD980 PCIE I/F ,SWITCH

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12 RD980 POWER & GND

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13 ICS 9LPRS477D

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14 SB950 PCIE/PCI/CPU/LPC/CLK

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15 SB950 ACPI/USB/GPIO/AUDIO

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16 SB950 SATA/SPI/IDE/HWM

G Do
B B

17 SB950 POWER & GND


18 PCI EXPRESS x16
19 PCI_E x1 SLOT 1,2,3
20 PCI SLOT 1, 2
21 IT8728 EX LPC IO ,Dual-BIOS ,TPM
22 F_USB, R_USB, I_PWR
23 VT2021 CODEC

A 24 AUDIO JACK A

25 FAN/HWMO KB/MS

Title
COVER SHEET
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Wednesday, May 08, 2013 Sheet 1 of 35
5 4 3 2 1
5 4 3 2 1

Model Name:GA-970A-D3P Circuit or PCB layout change for next version


Version: 1.0 Date Change Item Reason
Component value change history P-Code: U98094-0 2012.07.17 MODIFY TO 970A-D3 REV1.3
D D
1.I/O 8720 change 8728
Date Change Item Reason 2012.07.17 新新erp 0.5w control線
2.新 線線
3.5VDUAL版 版改PWROK控 控控

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2012.07.17 9M970AD3-00-30A PCB Ver 3.0 4.Etron usb3.0 pin88.89 接GND(新
新新新IC)

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2012.08.09 9M970AD3-00-30B PCB Ver 3.01 2012.08.09 ADD EPR POWER ISSUE

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2012.10.02 9M970AD3-00-30C PCB Ver 3.02 EPR GP53 ISSUE

2013.2.1 9M970AD3P-00-10A PCB Ver 1.0 2012.10.02 調調POWER +-5%不


不不ISSUE 移移 " EASY ENERGY SAVER" 9M970AD3-00-30C

en
2013.2.21 1. Remove I PHONE Charge

2. Change EJ168 → VL805 (F_USB3, R_USB3)

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3. Change PWM ISL6329+6609 → IR3564A+IR8550

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4. MLCC Down Size 10u/8/X5R → 10u/6/X5R

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5. USB Fuse Down Size 1206 →0805

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C C

6. Remove Vcore Thermal Protect

te C o p
b y o t C
i g a n
G Do
B B

A A

2013.02.21

Title
BOM & PCB HISTORY
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 2 of 35
5 4 3 2 1
5 4 3 2 1

DDRIII 1066,1333 UNBUFFERED UNBUFFERED


AMD DDRIII DIMM1 8 DDRIII DIMM3 8

128bit
AM3+
D Clock D

Generator AM3b SOCKET DDRIII 1066,1333 UNBUFFERED UNBUFFERED


ICS 9LPRS477D 13 4,5,6,7 DDRIII DIMM2 9 DDRIII DIMM4 9

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HyperTransport 16x16

OUT
DDRIII FIRST LOGICAL DIMM DDRIII SECOND LOGICAL DIMM
LINK

IN
ti
ATI NB
RX980

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HyperTransport LINK0 CPU I/F

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1 X16 PCIE Graphics I/F
5 X1 PCIE I/F
AM3+ RX980 CORE & PCIE

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POWER POWER

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27 28 30

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PCIE SLOT 16X 16X

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X16 18 DDR3 MEMORY SB950 CORE & PCIE
C POWER POWER C

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31 30
1X PCIE INTERFACE

10,11,12

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GIGABIT VIA USB3 PCIE SLOT3 PCIE SLOT2 PCIE SLOT

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X1 X1 X1 4X

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RTL8111F 35 VL805 32 33 19 19 19 PCIE

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ATI SB
USB-6 USB-5 USB-4 USB-3 USB-2 USB-1 USB-0 USB 2.0

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SB950 VT2021

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HD AUDIO I/F
22 22 22 22 22 22 22 14 USB2.0 HD AUDIO CODEC
23, 24

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6 SATA III
1 X4 PCIE I/F SATA#0 SATA#1 SATA#2 SATA#3 SATA#4 SATA#5

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SATA III I/F
USB-13 USB-12 USB-11 USB-10 USB-9 USB-8 USB-7 USB 2.0 AZALIA 16 16 16 16 16 16

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22 22 35 35 25 25 22 ACPI

G Do
B LPC I/F PCIE SLOT B
X4 PCIE
INT RTC X4 34
HW MONITOR
PCI BUS GBE PHY SPI
14,15,16,17 SPI I/F
Dual-BIOS
16

PCI SLOT 1 PCI SLOT 2


20 20
LPC BUS
SB_SPI_CS ITE_SPI_CS1/2

TPM ITE LPC SIO


21 IT8728F/EX 21

A A

COM KB/ MS HW
25 MONITOR 25
25

Title
BLOCK DIAGRAM
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 3 of 35

www.vinafix.com
5 4 3 2 1
CPU_VDD_RUN = VCORE
L0_CADIN_L[0..15]

L0_CADIN_H[0..15]
L0_CADIN_L[0..15] {10}
CPU_VDDA_RUN = VDDA25
L0_CADIN_H[0..15] {10}
L0_CADOUT_L[0..15]
L0_CADOUT_L[0..15] {10} VLDT_RUN = VCC12_HT
L0_CADOUT_H[0..15]
L0_CADOUT_H[0..15] {10}
CPU_VDDIO_SUS = DDR15V
CPU_VDDR = CPU_VDDR12

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M2CPUA
VLDT_A = VCC12_HT

a
HYPERTRANSPORT
L0_CLKIN_H1 N6 AD5 L0_CLKOUT_H1
{10} L0_CLKIN_H1 L0_CLKIN_H(1) L0_CLKOUT_H(1) L0_CLKOUT_H1 {10}

i
L0_CLKIN_L1 L0_CLKOUT_L1
{10}
{10}
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_H0
P6
N3
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
AD4
AD1 L0_CLKOUT_H0 L0_CLKOUT_L1
L0_CLKOUT_H0
{10}
{10} VLDT_B = HT12B

t
L0_CLKIN_L0 N2 AC1 L0_CLKOUT_L0
{10} L0_CLKIN_L0 L0_CLKIN_L(0) L0_CLKOUT_L(0) L0_CLKOUT_L0 {10}
L0_CTLIN_H1 V4 Y6 L0_CTLOUT_H1
{10} L0_CTLIN_H1 L0_CTLIN_H(1) L0_CTLOUT_H(1) L0_CTLOUT_H1 {10}
L0_CTLIN_L1 V5 W6 L0_CTLOUT_L1

n
{10} L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L(1) L0_CTLOUT_L(1) L0_CTLOUT_H0 L0_CTLOUT_L1 {10}
{10} L0_CTLIN_H0 U1 L0_CTLIN_H(0) L0_CTLOUT_H(0) W2 L0_CTLOUT_H0 {10}
L0_CTLIN_L0 V1 W3 L0_CTLOUT_L0
{10} L0_CTLIN_L0 L0_CTLIN_L(0) L0_CTLOUT_L(0) L0_CTLOUT_L0 {10}

e
L0_CADIN_H15 U6 Y5 L0_CADOUT_H15
L0_CADIN_L15 L0_CADIN_H(15) L0_CADOUT_H(15) L0_CADOUT_L15
V6 L0_CADIN_L(15) L0_CADOUT_L(15) Y4
L0_CADIN_H14 T4 AB6 L0_CADOUT_H14

d
L0_CADIN_L14 L0_CADIN_H(14) L0_CADOUT_H(14) L0_CADOUT_L14
T5 L0_CADIN_L(14) L0_CADOUT_L(14) AA6
L0_CADIN_H13 R6 AB5 L0_CADOUT_H13

i
L0_CADIN_L13 L0_CADIN_H(13) L0_CADOUT_H(13) L0_CADOUT_L13
T6 L0_CADIN_L(13) L0_CADOUT_L(13) AB4
L0_CADIN_H12 P4 AD6 L0_CADOUT_H12

f
L0_CADIN_L12 L0_CADIN_H(12) L0_CADOUT_H(12) L0_CADOUT_L12
P5 L0_CADIN_L(12) L0_CADOUT_L(12) AC6
L0_CADIN_H11 M4 AF6 L0_CADOUT_H11
L0_CADIN_L11 L0_CADIN_H(11) L0_CADOUT_H(11) L0_CADOUT_L11
M5 L0_CADIN_L(11) L0_CADOUT_L(11) AE6

n y
L0_CADIN_H10 L6 AF5 L0_CADOUT_H10
L0_CADIN_L10 L0_CADIN_H(10) L0_CADOUT_H(10) L0_CADOUT_L10
M6 L0_CADIN_L(10) L0_CADOUT_L(10) AF4
L0_CADIN_H9 K4 AH6 L0_CADOUT_H9
L0_CADIN_L9 L0_CADIN_H(9) L0_CADOUT_H(9) L0_CADOUT_L9

o
K5 L0_CADIN_L(9) L0_CADOUT_L(9) AG6
L0_CADIN_H8 J6 AH5 L0_CADOUT_H8
L0_CADIN_L8 L0_CADIN_H(8) L0_CADOUT_H(8) L0_CADOUT_L8
K6 L0_CADIN_L(8) L0_CADOUT_L(8) AH4
L0_CADIN_H7 U3 Y1 L0_CADOUT_H7

C
L0_CADIN_L7 L0_CADIN_H(7) L0_CADOUT_H(7) L0_CADOUT_L7
U2 W1

p
L0_CADIN_H6 L0_CADIN_L(7) L0_CADOUT_L(7) L0_CADOUT_H6
R1 L0_CADIN_H(6) L0_CADOUT_H(6) AA2
L0_CADIN_L6 T1 AA3 L0_CADOUT_L6
L0_CADIN_H5 L0_CADIN_L(6) L0_CADOUT_L(6) L0_CADOUT_H5
R3 L0_CADIN_H(5) L0_CADOUT_H(5) AB1

e o
L0_CADIN_L5 R2 AA1 L0_CADOUT_L5
L0_CADIN_H4 L0_CADIN_L(5) L0_CADOUT_L(5) L0_CADOUT_H4
N1 L0_CADIN_H(4) L0_CADOUT_H(4) AC2
L0_CADIN_L4 L0_CADOUT_L4

t
P1 L0_CADIN_L(4) L0_CADOUT_L(4) AC3
L0_CADIN_H3 L1 AE2 L0_CADOUT_H3
L0_CADIN_L3 L0_CADIN_H(3) L0_CADOUT_H(3) L0_CADOUT_L3
M1 AE3

C
L0_CADIN_H2 L0_CADIN_L(3) L0_CADOUT_L(3) L0_CADOUT_H2
L3 AF1

y
L0_CADIN_L2 L0_CADIN_H(2) L0_CADOUT_H(2) L0_CADOUT_L2
L2 L0_CADIN_L(2) L0_CADOUT_L(2) AE1
L0_CADIN_H1 J1 AG2 L0_CADOUT_H1
L0_CADIN_H(1) L0_CADOUT_H(1)

t
L0_CADIN_L1 K1 AG3 L0_CADOUT_L1
L0_CADIN_L(1) L0_CADOUT_L(1)

b
L0_CADIN_H0 J3 AH1 L0_CADOUT_H0
L0_CADIN_L0 L0_CADIN_H(0) L0_CADOUT_H(0) L0_CADOUT_L0
J2 L0_CADIN_L(0) L0_CADOUT_L(0) AG1

a o
CPU-SK/942AM3b/S/GF/[10SC1-A01942-01R_10SC1-A01942-02R]

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G Do n M2CPU
AM3RM/SC/BL/MB/[12KRC-04K812-31R_12KRC-04K812-32R]

COUPON1 COUPON1 1 2 COUPON/X VCC


COUPON2 COUPON2 1 2 COUPON/X

Title
CPU HYPER TRANSPORT
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 4 of 35
M2CPUC
M2CPUB
MEMORY INTERFACE B
AJ19 AH13 MDB63
MEMORY INTERFACE A MB0_CLK_H(2) MB_DATA(63) MDB[0..63] {9}
AG21 AE14 MDA63 AK19 AL13 MDB62
MA0_CLK_H(2) MA_DATA(63) MDA[0..63] {8} MB0_CLK_L(2) MB_DATA(62)
AG20 AG14 MDA62 A18 AL15 MDB61
MA0_CLK_L(2) MA_DATA(62) MDA61 MB0_CLK_H(1) MB_DATA(61) MDB60
G19 MA0_CLK_H(1) MA_DATA(61) AG16 A19 MB0_CLK_L(1) MB_DATA(60) AJ15
H19 AD17 MDA60 B11P DCLKB3 U31 AF13 MDB59
MA0_CLK_L(1) MA_DATA(60) {9} DCLKB3 MB0_CLK_H(0) MB_DATA(59)
A11P DCLKA3 U27 AD13 MDA59 B11N -DCLKB3 U30 AG13 MDB58
{8} DCLKA3 MA0_CLK_H(0) MA_DATA(59) {9} -DCLKB3 MB0_CLK_L(0) MB_DATA(58)
A11N -DCLKA3 U26 AE13 MDA58 AL14 MDB57
{8} -DCLKA3 MA0_CLK_L(0) MA_DATA(58) MB_DATA(57)
AG15 MDA57 -CSB1 AE30 AK15 MDB56
MA_DATA(57) {9} -CSB1 MB0_CS_L(1) MB_DATA(56)
-CSA1 AC25 AE16 MDA56 -CSB0 AC31 AL16 MDB55
{8} -CSA1 MA0_CS_L(1) MA_DATA(56) {9} -CSB0 MB0_CS_L(0) MB_DATA(55)
-CSA0 AA24 AG17 MDA55 AL17 MDB54
{8} -CSA0 MA0_CS_L(0) MA_DATA(55) MB_DATA(54)
AE18 MDA54 MODT_B0 AD29 AK21 MDB53
MA_DATA(54) {9} MODT_B0 MB0_ODT(0) MB_DATA(53)
MODT_A0 AC28 AD21 MDA53 AL21 MDB52
{8} MODT_A0 MA0_ODT(0) MA_DATA(53) MB_DATA(52)
AG22 MDA52 AL19 AH15 MDB51
MA_DATA(52) MDA51 MB1_CLK_H(2) MB_DATA(51) MDB50
AE20 MA1_CLK_H(2) MA_DATA(51) AE17 AL18 MB1_CLK_L(2) MB_DATA(50) AJ16

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AE19 AF17 MDA50 C19 AH19 MDB49
MA1_CLK_L(2) MA_DATA(50) MDA49 MB1_CLK_H(1) MB_DATA(49) MDB48
G20 MA1_CLK_H(1) MA_DATA(49) AF21 D19 MB1_CLK_L(1) MB_DATA(48) AL20
G21 AE21 MDA48 DCLKB0 W 29 AJ22 MDB47
MA1_CLK_L(1) MA_DATA(48) {9} DCLKB0 MB1_CLK_H(0) MB_DATA(47)

a
A00P DCLKA0 V27 AF23 MDA47 B00P -DCLKB0 W 28 AL22 MDB46
{8} DCLKA0 -DCLKA0 MA1_CLK_H(0) MA_DATA(47) MDA46 {9} -DCLKB0 MB1_CLK_L(0) MB_DATA(46) MDB45
A00N {8} -DCLKA0 W 27 MA1_CLK_L(0) MA_DATA(46) AE23 B00N MB_DATA(45) AL24

ti
AJ26 MDA45 AE29 AK25 MDB44
MA_DATA(45) MDA44 {9} -CSB3 MB1_CS_L(1) MB_DATA(44) MDB43
{8} -CSA3 AD27 MA1_CS_L(1) MA_DATA(44) AG26 {9} -CSB2 AB31 MB1_CS_L(0) MB_DATA(43) AJ21
AA25 AE22 MDA43 AH21 MDB42
{8} -CSA2 MA1_CS_L(0) MA_DATA(43) MB_DATA(42)
AG23 MDA42 MODT_B2 AD31 AH23 MDB41
MA_DATA(42) {9} MODT_B2 MB1_ODT(0) MB_DATA(41)
MODT_A2 AC27 AH25 MDA41 AJ24 MDB40
{8} MODT_A2 MA1_ODT(0) MA_DATA(41) MB_DATA(40)
AF25 MDA40 AL27 MDB39

n
MA_DATA(40) MDA39 -SCASB MB_DATA(39) MDB38
MA_DATA(39) AJ28 {9} -SCASB AC29 MB_CAS_L MB_DATA(38) AK27
-SCASA AB25 AJ29 MDA38 -SWEB AC30 AH31 MDB37
{8} -SCASA MA_CAS_L MA_DATA(38) {9} -SWEB MB_W E_L MB_DATA(37)
-SWEA MDA37 -SRASB MDB36

e
{8} -SWEA AB27 MA_W E_L MA_DATA(37) AF29 {9} -SRASB AB29 MB_RAS_L MB_DATA(36) AG30
-SRASA AA26 AE26 MDA36 AL25 MDB35
{8} -SRASA MA_RAS_L MA_DATA(36) MB_DATA(35)
AJ27 MDA35 SBAB2 N31 AL26 MDB34
SBAA2 MA_DATA(35) MDA34 {9} SBAB2 SBAB1 MB_BANK(2) MB_DATA(34) MDB33
N25 AH27 AA31 AJ30

d
{8} SBAA2 MA_BANK(2) MA_DATA(34) {9} SBAB1 MB_BANK(1) MB_DATA(33)
SBAA1 Y27 AG29 MDA33 SBAB0 AA28 AJ31 MDB32
{8} SBAA1 MA_BANK(1) MA_DATA(33) {9} SBAB0 MB_BANK(0) MB_DATA(32)
SBAA0 AA27 AF27 MDA32 E31 MDB31

i
{8} SBAA0 MA_BANK(0) MA_DATA(32) MDA31 CKEB1 MB_DATA(31) MDB30
MA_DATA(31) E29 {9} CKEB1 M31 MB_CKE(1) MB_DATA(30) E30
CKEA1 L27 E28 MDA30 CKEB0 M29 B27 MDB29

f
{8} CKEA1 MA_CKE(1) MA_DATA(30) {9} CKEB0 MB_CKE(0) MB_DATA(29)
CKEA0 M25 D27 MDA29 A27 MDB28
{8} CKEA0 MA_CKE(0) MA_DATA(29) MB_DATA(28)
C27 MDA28 MAAB15 N28 F29 MDB27
MAAA15 MA_DATA(28) MDA27 {9} MAAB[0..15] MAAB14 MB_ADD(15) MB_DATA(27) MDB26
M27 MA_ADD(15) MA_DATA(27) G26 N29 MB_ADD(14) MB_DATA(26) F31

n y
{8} MAAA[0..15] MAAA14 N24 F27 MDA26 MAAB13 AE31 A29 MDB25
MAAA13 MA_ADD(14) MA_DATA(26) MDA25 MAAB12 MB_ADD(13) MB_DATA(25) MDB24
AC26 MA_ADD(13) MA_DATA(25) C28 N30 MB_ADD(12) MB_DATA(24) A28
MAAA12 N26 E27 MDA24 MAAB11 P29 A25 MDB23
MAAA11 MA_ADD(12) MA_DATA(24) MDA23 MAAB10 MB_ADD(11) MB_DATA(23) MDB22

o
P25 MA_ADD(11) MA_DATA(23) F25 AA29 MB_ADD(10) MB_DATA(22) A24
MAAA10 Y25 E25 MDA22 MAAB9 P31 C22 MDB21
MAAA9 MA_ADD(10) MA_DATA(22) MDA21 MAAB8 MB_ADD(9) MB_DATA(21) MDB20
N27 MA_ADD(9) MA_DATA(21) E23 R29 MB_ADD(8) MB_DATA(20) D21
MAAA8 R24 D23 MDA20 MAAB7 R28 A26 MDB19
MAAA7 MA_ADD(8) MA_DATA(20) MDA19 MAAB6 MB_ADD(7) MB_DATA(19) MDB18
P27 E26 R31 B25

C
MAAA6 MA_ADD(7) MA_DATA(19) MDA18 MAAB5 MB_ADD(6) MB_DATA(18) MDB17
R25 C26 R30 B23

p
MAAA5 MA_ADD(6) MA_DATA(18) MDA17 MAAB4 MB_ADD(5) MB_DATA(17) MDB16
R26 MA_ADD(5) MA_DATA(17) G23 T31 MB_ADD(4) MB_DATA(16) A22
MAAA4 R27 F23 MDA16 MAAB3 T29 B21 MDB15
MAAA3 MA_ADD(4) MA_DATA(16) MDA15 MAAB2 MB_ADD(3) MB_DATA(15) MDB14
T25 MA_ADD(3) MA_DATA(15) E22 U29 MB_ADD(2) MB_DATA(14) A20

e o
MAAA2 U25 E21 MDA14 MAAB1 U28 C16 MDB13
MAAA1 MA_ADD(2) MA_DATA(14) MDA13 MAAB0 MB_ADD(1) MB_DATA(13) MDB12
T27 MA_ADD(1) MA_DATA(13) F17 AA30 MB_ADD(0) MB_DATA(12) D15
MAAA0 MDA12 MDB11

t
W 24 MA_ADD(0) MA_DATA(12) G17 MB_DATA(11) C21
G22 MDA11 DQSB7 AK13 A21 MDB10
DQSA7 MA_DATA(11) MDA10 -DQSB7 MB_DQS_H(7) MB_DATA(10) MDB9
AD15 F21 AJ13 A17

C
-DQSA7 MA_DQS_H(7) MA_DATA(10) MDA9 DQSB6 MB_DQS_L(7) MB_DATA(9) MDB8
AE15 G18 AK17 A16

y
DQSA6 MA_DQS_L(7) MA_DATA(9) MDA8 -DQSB6 MB_DQS_H(6) MB_DATA(8) MDB7
AG18 MA_DQS_H(6) MA_DATA(8) E17 AJ17 MB_DQS_L(6) MB_DATA(7) B15
-DQSA6 AG19 G16 MDA7 DQSB5 AK23 A14 MDB6
MA_DQS_L(6) MA_DATA(7) MB_DQS_H(5) MB_DATA(6)

t
DQSA5 AG24 E15 MDA6 -DQSB5 AL23 E13 MDB5
MA_DQS_H(5) MA_DATA(6) MB_DQS_L(5) MB_DATA(5)

b
-DQSA5 AG25 G13 MDA5 DQSB4 AL28 F13 MDB4
DQSA4 MA_DQS_L(5) MA_DATA(5) MDA4 -DQSB[0..8] -DQSB4 MB_DQS_H(4) MB_DATA(4) MDB3
AG27 MA_DQS_H(4) MA_DATA(4) H13 AL29 MB_DQS_L(4) MB_DATA(3) C15
-DQSA4 MDA3 -DQSB[0..8] {9} DQSB3 MDB2

o
AG28 MA_DQS_L(4) MA_DATA(3) H17 D31 MB_DQS_H(3) MB_DATA(2) A15

a
-DQSA[0..8] DQSA3 D29 E16 MDA2 DQSB[0..8] -DQSB3 C31 A13 MDB1
-DQSA[0..8] {8} MA_DQS_H(3) MA_DATA(2) DQSB[0..8] {9} MB_DQS_L(3) MB_DATA(1)
-DQSA3 C29 E14 MDA1 DQSB2 C24 D13 MDB0
DQSA[0..8] DQSA2 MA_DQS_L(3) MA_DATA(1) MDA0 MB_CK[0..7] -DQSB2 MB_DQS_H(2) MB_DATA(0)
DQSA[0..8] {8} C25 G14 MB_CK[0..7] {9} C23

n
-DQSA2 MA_DQS_H(2) MA_DATA(0) MB_DQS_L(2)

g
D25 DQSB1 D17 J31 DQSB8
MA_CK[0..7] DQSA1 MA_DQS_L(2) DQSA8 DMB[0..8] -DQSB1 MB_DQS_H(1) MB_DQS_H(8) -DQSB8
MA_CK[0..7] {8} E19 MA_DQS_H(1) MA_DQS_H(8) J28 DMB[0..8] {9} C17 MB_DQS_L(1) MB_DQS_L(8) J30

i
-DQSA1 F19 J27 -DQSA8 DQSB0 C14
DMA[0:8] DQSA0 MA_DQS_L(1) MA_DQS_L(8) -DQSB0 MB_DQS_H(0) DMB8
DMA[0..8] {8} F15 MA_DQS_H(0) C13 MB_DQS_L(0) MB_DM(8) J29
-DQSA0 G15 J25 DMA8

G Do
MA_DQS_L(0) MA_DM(8) DMB7 MB_CK7
AJ14 MB_DM(7) MB_CHECK(7) K29
DMA7 AF15 K25 MA_CK7 DMB6 AH17 K31 MB_CK6
DMA6 MA_DM(7) MA_CHECK(7) MA_CK6 DMB5 MB_DM(6) MB_CHECK(6) MB_CK5
AF19 MA_DM(6) MA_CHECK(6) J26 AJ23 MB_DM(5) MB_CHECK(5) G30
DMA5 AJ25 G28 MA_CK5 DMB4 AK29 G29 MB_CK4
DMA4 MA_DM(5) MA_CHECK(5) MA_CK4 DMB3 MB_DM(4) MB_CHECK(4) MB_CK3
AH29 MA_DM(4) MA_CHECK(4) G27 C30 MB_DM(3) MB_CHECK(3) L29
DMA3 B29 L24 MA_CK3 DMB2 A23 L28 MB_CK2
DMA2 MA_DM(3) MA_CHECK(3) MA_CK2 DMB1 MB_DM(2) MB_CHECK(2) MB_CK1
E24 MA_DM(2) MA_CHECK(2) K27 B17 MB_DM(1) MB_CHECK(1) H31
DMA1 E18 H29 MA_CK1 DMB0 B13 G31 MB_CK0
DMA0 MA_DM(1) MA_CHECK(1) MA_CK0 MB_DM(0) MB_CHECK(0)
H15 MA_DM(0) MA_CHECK(0) H27
CPU-SK/942AM3b/S/GF/[10SC1-A01942-01R_10SC1-A01942-02R]
CPU-SK/942AM3b/S/GF/[10SC1-A01942-01R_10SC1-A01942-02R]

MEM CHA MEM CHB

CPU
CPU

TO DIMMB0 & DIMMB1


TO DIMMA0 & DIMMA1 Title
CPU DDRIII MEMORY
B0 B1 Size Document Number Rev
A0 A1 Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 5 of 35
-CPURST

DDR15V
AC5
100P/4/NPO/50V/J
-CPURST AR1 300/4

-LDT_STOP AR2 300/4

AC4 150P/4/NPO/50V/J/X

VDDA25
DDR15V
ABC1 ABC2 ABC3
4.7u/6/X5R/6.3V/K 0.22U/6/X7R/16V/K
M2CPUD
3.3n/4/X7R/50V/K MISC
C10 VDDA1
3.9n/4/X7R/50V/K D10 AR16 AR17 AR19 3VDUAL
VDDA2

l
{13} CPUCLK0_H CPUCLK0_H AC6 CLKIN_H 1K/4/1 1K/4/1 300/4 AR18
A8 1K/4/1
AR3 CLKIN_H
B8 CLKIN_L

a
{13} CPUCLK0_L CPUCLK0_L AC7 169/4/1 CLKIN_L AR24
CPU_PWRGD C9 D2 8.2K/4/1
PW ROK VID(5)

ti
3.9n/4/X7R/50V/K -LDT_STOP D8 D1
{10,14} -LDT_STOP -CPURST LDTSTOP_L VID(4)
{10,14} -CPURST C7 RESET_L VID(3) C1 SVC SVC {27}
THERMTRIP_CPU_L
THERMTRIP_CPU_L {15,31}
VID(2) E3 SVD SVD {27}

3
AR27 1K/4/1 CPU_PRESENT_L AL3 E2 VID1 AR20 300/4 AQ5
DDR15V CPU_PRESENT_L VID(1)
VID(0) E1
AR4 1K/4/1

n
DG:AM3 1.04 {21} SID
DDR15V
{21} SIC * SIC
SID
AL6
AK6
SIC THERMTRIP_L AK7
AL7
THERMTRIP_L
-PROCHOT
MMBT2222A/SOT23/600mA/40
SOT23

1
SID PROCHOT_L

e
AR5 1K/4/1 AR22 1K/4/1 AR23 1K/4/1
DDR15V
{15} CPU_TDI* CPU_TDI AL10 TDI TDO AK10
DDR15V

3
CPU_TRST- AJ10 AQ4
CPU_TCK TRST_L
AH10

d
{15} CPU_TCK TCK
CPU_TMS AL9
{15} CPU_TMS TMS MMBT2222A/SOT23/600mA/40

i
CPU_DBREQ- A5 B6 SOT23
DBREQ_L DBRDY

1
AR21 1K/4/1

f
{27} COREFB+ G2 VDD_FB_H VDDIO_FB_H AK11
{27} COREFB- G1 VDD_FB_L VDDIO_FB_L AL11
AR25 0/4/SHT/X -PROCHOT_CPU
-PROCHOT_CPU {14,27}

n y
E12 VTT_SENSE PSI_L F1
DDR15V

CPU_TEST25_H

o
CPU_M_VREF F12 V8 AR52 46.4/4/1 VCC12_HT AR28 510/4/1/X
AR6 39.2/4/1 CPU_MZN M_VREF HTREF1 AR53 46.4/4/1 AR29 510/4/1
DDR15V AH11 M_ZN HTREF0 V7
AR7 39.2/4/1/X CPU_MZP AJ11 CPU_TEST25_L AR30 510/4/1/X
M_ZP AR31 510/4/1
CPU_TEST25_H A10 C11 AR54 80.6/4/1/X

C
CPU_TEST25_L B10 TEST25_H TEST29_H
D11

p
3VDUAL VCC3 AR8 1K/4/1 CPU_TEST19 TEST25_L TEST29_L
F10 TEST19
AR9 1K/4/1 CPU_TEST18 E9 AR47 1K/4/1/X CPU_TDI
TEST18 DDR15V
AJ7 AR48 1K/4/1/X CPU_TRST-
TEST13 DDR15V

e o
F6 AR49 1K/4/1/X CPU_TCK
TEST9 DDR15V
AR13 AR14 DDR15V AR50 1K/4/1/X CPU_TMS
CPU_TEST24 CPU_DBREQ-

t
8.2K/4/1 8.2K/4/1 D6 AK8 AR36 1K/4/1 DDR15V AR51 300/4/X
TEST17 TEST24 CPU_TEST23 AR55 1K/4/1
E7 TEST16 TEST23 AH8
F8 AJ9 CPU_TEST22 AR35 1K/4/1

C
DDR15V PWM_PWRGD {27} TEST15 TEST22
C5 AL8 CPU_TEST21 AR32 1K/4/1

y
TEST14 TEST21
3

AR10 1K/4/1 CPUTEST12 AH9 AJ8 CPU_TEST20 AR34 1K/4/1


AQ1 AQ2 AC8 TEST12 TEST20
D D

t
0.1u/4/Y5V/16V/Z/X E5 J10
TEST7 TEST28_H

b
AR11 AJ5 H9
300/4 G S G S TEST6 TEST28_L CPU_TEST27 AR33 1K/4/1
AG9 THERMDC TEST27 AK9 DDR15V
{21} GNDA CPU_TEST26 AR26 1K/4/1

o
{21} TMPIN2 AG8 AK5
2

THERMDA TEST26

a
AR12 1K/4/1 AH7 G7
{14} CPU_PG_SB TEST3 TEST10
AJ6 TEST2 TEST8 D4
MMBT2222A/SOT23/600mA/40 2N7002/SOT23/25pF/5 AC10

g n
2.2n/4/X7R/50V/K/X CPU-SK/942AM3b/S/GF/[10SC1-A01942-01R_10SC1-A01942-02R]

i
DDR15V

G Do
AR15
1K/4/1
3VDUAL
CPU_PWRGD 3VDUAL
AMD comment for validation.
3

AR45
AQ3 AC9 1K/4/1
D
0.1u/4/Y5V/16V/Z/X AR46
AQ7
8.2K/4/1
G S

G
M2CPUE 2
3

D
INTERNAL MISC SB_IDLEEXIT- {15}
2

L25 E20 MA_RESET_L CPU_IDLEEXIT- 1


RSVD1 MA_RESET- MA_RESET_L {8}
L26 B19 MB_RESET_L

S
RSVD2 MB_RESET- MB_RESET_L {9}
2N7002/SOT23/25pF/5 L31 AR37 1K/4/1 DDR15V
RSVD3 CPU_ALERT- 2N7002/SOT23/25pF/5
L30 RSVD4 RSVD19 AL4
AK4 AR40 1K/4/1
RSVD20
RSVD21 AK3
AR41 1K/4/1 DDR15V
DDR15V VCC3
CPUVREF DCLKA2
RSVD22
M_VDDIO_PW RGD
F2
F3 CPU_IDLEEXIT- 3VDUAL
{8} DCLKA2 W 26 DCLKA2
-DCLKA2 W 25 G4 COREFB_NB+ AR38
{8} -DCLKA2 MODT_A3 DCLKA2- COREFB_NB+ COREFB_NB- COREFB_NB+ {27}
40 MILS WIDTH AE27 G3 1K/4/1
{8} MODT_A3 MODT_A3 COREFB_NB- COREFB_NB- {27}
SAR1 DCLKA1 U24 G5 CPUG5 AR42 1K/4/1 DDR15V AR39
{8} DCLKA1 DCLKA1 CORE_TYP_DET AQ6
CPU_M_VREF 15/4/1 -DCLKA1 V24 8.2K/4/1
{8} -DCLKA1 DCLKA1-

G
MODT_A1 AE28 AD25 AR56 1K/4/1/X 2
{8} MODT_A1 MODT_A1 RSVD27
AE24 3

D
RSVD28 CPU_ALERT- SB_ALERT- {16}
RSVD29 AE25 1
AJ18

S
RSVD30
RSVD31 AJ20
2N7002/SOT23/25pF/5
RSVD32 C18
1

SABC1 SABC2 DCLKB2 Y31 C20


{9} DCLKB2 DCLKB2 RSVD33
SABC3 SAR2 -DCLKB2 Y30 G24
{9} -DCLKB2 DCLKB2- RSVD34
1U/6/X7R/16V/K 15/4/1 MODT_B3 AG31 G25 AR43 1K/4/1
{9} MODT_B3 DDR15V
2

1N/4/X7R/50V/K DCLKB1 MODT_B3 RSVD35


{9} DCLKB1 V31 DCLKB1 RSVD36 H25
-DCLKB1 W 31 V29 MB_EVENT_L
{9} -DCLKB1 DCLKB1- MB_EVENT_L MB_EVENT_L {9}
MODT_B1 AF31 W 30 MA_EVENT_L
{9} MODT_B1 MODT_B1 MA_EVENT_L MA_EVENT_L {8}
0.1U/4/X7R/16V/K AR44 1K/4/1 DDR15V Title

Layout: Place within CPU CONTROL


Size Document Number Rev
500mils of the CPU socket. Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 6 of 35
VLDT_RUN_B is connected to the VLDT_RUN power VCORE_NB
supply through the package or on the die. It is only connected
on the board to decoupling near the CPU package.
ABC5 ABC6 ABC7 ABC8 ABC9 ABC10
22u/8/X5R/6.3V/M 0.22U/6/X7R/16V/K 180P/4/NPO/50V/J
22u/8/X5R/6.3V/M 4.7u/6/X5R/6.3V/K 0.01u/4/X7R/25V/K

DDR15V GND
M2CPUF VCORE M2CPUI BUTTOM SIDE
VDD1 M2CPUG VCORE M2CPUH HT12B
A4 A3 VCC12_HT VDDIO
VDD1 VSS1
VCORE_NB A6 VDD2 VSS2 A7 VDD2 VDD3 AJ4 VLDT_A1 VLDT_B1 H6
AA8 A9 L14 AK20 AA20 N17 AJ3 H5 SABC4 SABC5 SABC6 SABC7 SABC8
VCORE VDD3 VSS3 VDD1 VSS1 VDD1 VSS1 VLDT_A2 VLDT_B2
AA10 A11 L16 AK22 AA22 N19 AJ2 H2 ABC4 0.22U/6/X7R/16V/K 0.01U/4/X7R/25V/K
VDD4 VSS4 VDD2 VSS2 VDD2 VSS2 VLDT_A3 VLDT_B3 10u/6/X5R/6.3V/M 4.7u/6/X5R/6.3V/K0.22U/6/X7R/16V/K 180P/4/NPO/50V/J
AA12 VDD5 VSS5 AA4 L18 VDD3 VSS3 AK24 AB13 VDD3 VSS3 N21 AJ1 VLDT_A4 VLDT_B4 H1
AA14 AA5 M2 AK26 AB15 N23 VCC12_HT VCC12_HT
VDD6 VSS6 VDD4 VSS4 VDD4 VSS4

l
AA16 VDD7 VSS7 AA7 M3 VDD5 VSS5 AK28 AB17 VDD5 VSS5 P2 D12 VDDR_4 VDDR_5 AG12
GND GND
AA18 VDD8 VSS8 AA9 M7 VDD6 VSS6 AK30 AB19 VDD6 VSS6 P3 C12 VDDR_3 VDDR_6 AH12
AB7 VDD9 VSS9 AA11 M9 VDD7 VSS7 AL5 AB21 VDD7 VSS7 P8 B12 VDDR_2 VDDR_7 AJ12
DDR15V

a
AB9 AA13 M11 B4 AB23 P10 A12 AK12 DDR15V
VDD10 VSS10 VDD8 VSS8 VDD8 VSS8 VDDR_1 VDDR_8
AB11 VDD11 VSS11 AA15 M13 VDD9 VSS9 B9 AC12 VDD9 VSS9 P12 VDDR_9 AL12

i
AC4 VDD12 VSS12 AA17 M15 VDD10 VSS10 B11 AC14 VDD10 VSS10 P14 AB24 VDDIO1
AC5 VDD13 VSS13 AA19 M17 VDD11 VSS11 B14 AC16 VDD11 VSS11 P16 AB26 VDDIO2 VSS1 K24

t
AC8 VDD14 VSS14 AA21 M19 VDD12 VSS12 B16 AC18 VDD12 VSS12 P18 AB28 VDDIO3 VSS2 K26
AC10 AA23 N8 B18 AC20 P20 AB30 K28 SABC9 SABC10 SABC11 SABC12 SABC13
VDD15 VSS15 VDD13 VSS13 VDD13 VSS13 VDDIO4 VSS3 22u/8/X5R/6.3V/M 4.7u/6/X5R/6.3V/K 180P/4/NPO/50V/J
AD2 VDD16 VSS16 AB2 N10 VDD14 VSS14 B20 AC22 VDD14 VSS14 P22 AC24 VDDIO5 VSS4 K30
AD3 AB3 N12 B22 AD11 R7 AD26 L7 22u/8/X5R/6.3V/M 10u/6/X5R/6.3V/M

n
VDD17 VSS17 VDD15 VSS15 VDD15 VSS15 VDDIO6 VSS5
AD7 VDD18 VSS18 AB8 N14 VDD16 VSS16 B24 AD23 VDD16 VSS16 R9 AD28 VDDIO7 VSS6 L9
AD9 VDD19 VSS19 AB10 N16 VDD17 VSS17 B26 AE12 VDD17 VSS17 R11 AD30 VDDIO8 VSS7 L11

e
AE10 AB12 N18 B28 AF11 R13 AF30 L13 GND
VDD20 VSS20 VDD18 VSS18 VDD18 VSS18 VDDIO29 VSS8
AF7 VDD21 VSS21 AB14 P7 VDD19 VSS19 B30 L20 VDD19 VSS19 R15 M24 VDDIO9 VSS9 L15
AF9
AG4
VDD22 VSS22 AB16
AB18
P9
P11
VDD20 VSS20 C3
D14
L22
M21
VDD20 VSS20 R17
R19
M26
M28
VDDIO10 VSS10 L17
L19 VCORE BUTTOM SIDE

d
VDD23 VSS23 VDD21 VSS21 VDD21 VSS21 VDDIO11 VSS11
AG5 VDD24 VSS24 AB20 P13 VDD22 VSS22 D16 M23 VDD22 VSS22 R21 M30 VDDIO12 VSS12 L21
AG7 AB22 P15 D18 N20 R23 P24 L23

i
VDD25 VSS25 VDD23 VSS23 VDD23 VSS23 VDDIO13 VSS13
AH2 VDD26 VSS26 AC7 P17 VDD24 VSS24 D20 N22 VDD24 VSS24 T8 P26 VDDIO14 VSS14 M8
AH3 AC9 P19 D22 P21 T10 P28 M10

f
VDD27 VSS27 VDD25 VSS25 VDD25 VSS25 VDDIO15 VSS15 SABC14 SABC15 SABC16 SABC17 SABC18
B3 VDD28 VSS28 AC11 R4 VDD26 VSS26 D24 P23 VDD26 VSS26 T12 P30 VDDIO16 VSS16 M12
B5 AC13 R5 D26 R22 T14 T24 M14 0.22U/4/X5R/6.3V/K 0.22U/4/X5R/6.3V/K 180P/4/NPO/50V/J
VDD29 VSS29 VDD27 VSS27 VDD27 VSS27 VDDIO17 VSS17 0.22U/4/X5R/6.3V/K 0.01U/4/X7R/25V/K
VCORE_NB B7 VDD30 VSS30 AC15 R8 VDD28 VSS28 D28 T23 VDD28 VSS28 T16 T26 VDDIO18 VSS18 M16

n y
VCORE C2 VDD31 VSS31 AC17 R10 VDD29 VSS29 D30 U22 VDD29 VSS29 T18 T28 VDDIO19 VSS19 M18
C4 VDD32 VSS32 AC19 R12 VDD30 VSS30 E11 V23 VDD30 VSS30 T20 T30 VDDIO20 VSS20 M20
C6 AC21 R14 F4 W 22 T22 V25 M22 GND
VDD33 VSS33 VDD31 VSS31 VDD31 VSS31 VDDIO21 VSS21

o
VCORE_NB C8 VDD34 VSS34 AC23 R16 VDD32 VSS32 F14 Y23 VDD32 VSS32 U4 V26 VDDIO22 VSS22 N4
VCORE D3 VDD35 VSS35 AD8 R18 VDD33 VSS33 F16 VSS33 U5 V28 VDDIO23 VSS23 N5
D5 VDD36 VSS36 AD10 R20 VDD34 VSS34 F18 VSS34 U7 V30 VDDIO24 VSS24 N7
D7 VDD37 VSS37 AD12 T2 VDD35 VSS35 F20 VSS35 U9 Y24 VDDIO25 VSS25 N9
VCORE_NB D9 AD14 T3 F22 U11 Y26 N11

C
VDD38 VSS38 VDD36 VSS36 VSS36 VDDIO26 VSS26
VCORE E4 AD16 T7 F24 U13 Y28 N13

p
VDD39 VSS39 VDD37 VSS37 VSS37 VDDIO27 VSS27
E6 VDD40 VSS40 AD20 T9 VDD38 VSS38 F26 VSS38 U15 Y29 VDDIO28 VSS28 N15
E8 VDD41 VSS41 AD22 T11 VDD39 VSS39 F28 VSS39 U17
VCORE_NB E10 VDD42 VSS42 AD24 T13 VDD40 VSS40 F30 VSS40 U19

e o
VCORE F5 VDD43 VSS43 AE4 T15 VDD41 VSS41 G9 VSS41 U21
GND
F7 VDD44 VSS44 AE5 T17 VDD42 VSS42 G11 VSS42 U23

t
F9 VDD45 T19 VDD43 VSS43 H8 VSS43 V2
F11 AE11 T21 H10 V3 VCORE_NB
VCORE_NB VDD46 VSS46 VDD44 VSS44 VSS44
G6 AF2 AE9 Missing pins on package U8 H12 V10
AMD Validation

C
VCORE VDD47 VSS47 VDD45 VSS45 VSS45
G8 AF3 U10 H14 B2 V12

y
VDD48 VSS48 and socket used for VDD46 VSS46 NB/RSVD VSS46
G10 AF8 U12 H16 V14
G12
VDD49 VSS49
AF10
mechanical keying. =>AM3 U14
VDD47 VSS47
H18 AM3 Only
VSS47
V16
VCORE_NB VDD50 VSS50 VDD48 VSS48 VSS48

t
VCORE H7 AF12 U16 V18 SABC50 SABC48 SABC49 ABC39 ABC40 ABC41
VDD51 VSS51 VDD49 VSS49

b
H11 VDD52 VSS52 AF14 U18 VDD50 VSS50 H24 H22 Missing pins on package H20 NP/VSS1 VSS50 V20 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M/X 22u/8/X5R/6.3V/M/X 22u/8/X5R/6.3V/M/X
H23 VDD53 VSS53 AF16 U20 VDD51 VSS51 H26 and socket used for AE7 NP/VSS2 VSS51 V22

o
J8 AF18 V9 H28 W9
VDD54 VSS54 VDD52 VSS52 mechanical keying. =>AM3 VSS52

a
J12 VDD55 VSS55 AF20 V11 VDD53 VSS53 H30 VSS53 W 11
J14 VDD56 VSS56 AF22 V13 VDD54 VSS54 J4 VSS54 W 13
GND
J16 AF24 V15 J5 W 15

n
VDD57 VSS57 VDD55 VSS55 VSS55

g
J18 VDD58 VSS58 AF26 V17 VDD56 VSS56 J7 VSS56 W 17
J20 VDD59 VSS59 AF28 V19 VDD57 VSS57 J9 VSS57 W 19

i
J22 AG10 V21 J11 W 21 VCORE
J24
VDD60 VSS61
AG11 W4
VDD58 VSS58
J13
VSS58
W 23
BUTTOM SIDE
VDD61 VSS62 VDD59 VSS59 VSS59
K7 AH14 W5 J15 Y8

G Do
VDD62 VSS63 VDD60 VSS60 VSS60
K9 VDD63 VSS64 AH16 W8 VDD61 VSS61 J17 VSS61 Y10
K11 VDD64 VSS65 AH18 W 10 VDD62 VSS62 J19 VSS62 Y12
K13 AH20 W 12 J21 W7 SABC19 SABC20 SABC21 SABC22 SABC23 SABC24 SABC25 SABC26
VDD65 VSS66 VDD63 VSS63 VSS63 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M
K15 VDD66 VSS67 AH22 W 14 VDD64 VSS64 J23 VSS64 Y20
K17 AH24 W 16 K2 Y22 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M
VDD67 VSS68 VDD65 VSS65 VSS65
K19 VDD68 VSS69 AH26 W 18 VDD66 VSS66 K3
K21 VDD69 VSS70 AH28 W 20 VDD67 VSS67 K8
GND GND
K23 VDD70 VSS71 AH30 Y2 VDD68 VSS68 K10
L4 AK2 Y3 K12 VCORE
VDD71 VSS72 VDD69 VSS69
L5 VDD72 VSS73 AK14 Y7 VDD70 VSS70 K14
L8 VDD73 VSS74 AK16 Y9 VDD71 VSS71 K16
L10 VDD74 VSS75 AK18 Y11 VDD72 VSS72 K18
L12 VDD75 VSS240 Y14 Y13 VDD73 VSS73 K20
Y17 Y16 Y15 K22 SABC27 SABC28 SABC29 SABC30 SABC31 SABC32 SABC33
VDD150 VSS241 VDD74 VSS74 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M
Y19 VDD151 Y21 VDD75 VSS75 Y18
22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M
GND
GND
GND
VCC12_HT 1021 EMI

VCC12_HT

VCORE VCC12_HT
ABC11 ABC12 ABC13 ABC14 ABC15 ABC16
10u/6/X5R/6.3V/M 0.22U/6/X7R/16V/K 180P/4/NPO/50V/J AMD Validation
4.7u/6/X5R/6.3V/K 0.22U/6/X7R/16V/K 0.1u/4/X7R/16V/K
ABC35 ABC36 ABC37 ABC38
SABC34 SABC35 SABC36 SABC37 SABC38 SABC39 SABC40 ABC21 ABC22 ABC23 ABC24 ABC25 ABC26 ABC27 100P/4/NPO/50V/J 100P/4/NPO/50V/J 100P/4/NPO/50V/J/X
GND 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 10u/6/X5R/6.3V/M 0.22U/6/X7R/16V/K 1N/4/X7R/50V/K 0.1u/4/X7R/16V/K 100P/4/NPO/50V/J/X
22u/8/X5R/6.3V/M/X 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 4.7u/6/X5R/6.3V/K 0.01u/4/X7R/25V/K 180P/4/NPO/50V/J

DDR15V GND
VCORE VCC12_HT
AMD Validation
ABC17 ABC18 ABC19 ABC20
10u/6/X5R/6.3V/M 10u/6/X5R/6.3V/M 0.22U/6/X7R/16V/K 0.22U/6/X7R/16V/K SABC41 SABC42 SABC43 SABC44 SABC45 SABC46 SABC47 ABC28 ABC29 ABC30 ABC31 ABC32 ABC33 ABC34 Title
22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 0.22U/6/X7R/16V/K 0.01u/4/X7R/25V/K 180P/4/NPO/50V/J
22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 22u/8/X5R/6.3V/M 4.7u/6/X5R/6.3V/K 1N/4/X7R/50V/K 0.1u/4/X7R/16V/K CPU POWER & GND
Size Document Number Rev
GND Custom
GND
GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 7 of 35
8 7 6 5 4 3 2 1

DDRVTT DDRVTT
DDR3_4 DDR3_2

120 48 120 48
VTT FREE VTT FREE
240 49 240 49
VTT FREE MA_EVENT_L VTT FREE MA_EVENT_L
187 MA_EVENT_L {6} 187 MA_EVENT_L {6}
FREE FREE
2 198 2 198
VSS FREE VSS FREE
5 5
VSS VSS
8 79 8 79
VSS RSVD VSS RSVD
11 11
VSS MODT_A1 MODT_A[0..3] VSS MODT_A3
14 77 MODT_A1 {6} MODT_A[0..3] {5,6} 14 77 MODT_A3 {6}
VSS ODT1 MODT_A0 VSS ODT1 MODT_A2
17 195 MODT_A0 {5} 17 195 MODT_A2 {5}
VSS ODT0 -DQSA[0..8] VSS ODT0
20 -DQSA[0..8] {5} 20
VSS VSS
23 68 23 68
VSS NC/PAR_IN DQSA[0..8] VSS NC/PAR_IN
26 53 DQSA[0..8] {5} 26 53
VSS NC/ERR_OUT VSS NC/ERR_OUT
29 167 29 167
VSS NC/TEST4 DMA[0..8] VSS NC/TEST4
32 DMA[0..8] {5} 32
VSS MA_CK0 VSS MA_CK0
35 39 35 39
VSS CB0 MA_CK1 MA_CK[0..7] VSS CB0 MA_CK1
38 40 MA_CK[0..7] {5} 38 40
VSS CB1 MA_CK2 VSS CB1 MA_CK2
D 41 45 41 45 D
VSS CB2 MA_CK3 VSS CB2 MA_CK3
44 46 44 46
VSS CB3 MA_CK4 VSS CB3 MA_CK4
47 158 47 158
VSS CB4 MA_CK5 SMBDATA VSS CB4 MA_CK5
80 159 80 159
VSS CB5 MA_CK6 SMBCLK VSS CB5 MA_CK6
83 164 83 164
VSS CB6 MA_CK7 VSS CB6 MA_CK7
86 165 86 165

l
VSS CB7 VSS CB7
89 89
VSS VSS
92 92
VSS DQSA0 C205 C206 VSS DQSA0
95 7 95 7
VSS DQS0 -DQSA0 100p/4/NPO/50V/J/X 100p/4/NPO/50V/J/X VSS DQS0 -DQSA0
98 6 98 6

a
VSS DQS0* VSS DQS0*
101 101
VSS DQSA1 VSS DQSA1
104 16 104 16
VSS DQS1 VSS DQS1

ti
107 15 -DQSA1 107 15 -DQSA1
VSS DQS1* VSS DQS1*
110 110
VSS DQSA2 VSS DQSA2
113 25 113 25
VSS DQS2 -DQSA2 VSS DQS2 -DQSA2
116 24 116 24
VSS DQS2* VSS DQS2*
119 119
VSS DQSA3 VSS DQSA3
121 34 121 34
VSS DQS3 -DQSA3 VSS DQS3 -DQSA3
124 33 124 33
VSS DQS3* VSS DQS3*

n
127 127
VSS DQSA4 VSS DQSA4
130 85 130 85
VSS DQS4 -DQSA4 VSS DQS4 -DQSA4
133 84 133 84
VSS DQS4* VSS DQS4*
136 136

e
VSS DQSA5 VSS DQSA5
139 94 139 94
VSS DQS5 -DQSA5 DDR15V VSS DQS5 -DQSA5
142 93 142 93
VSS DQS5* VSS DQS5*
145 145
VSS DQSA6 VSS DQSA6
148
VSS DQS6
103 Trace min 10/10 148
VSS DQS6
103
-DQSA6 -DQSA6

d
151 102 151 102
VSS DQS6* R101 VSS DQS6*
154 154
VSS DQSA7 15/4/1 VREFDQ_A VSS DQSA7
157 112 157 112

i
VSS DQS7 -DQSA7 VSS DQS7 -DQSA7
160 111 160 111
VSS DQS7* VREFDQ_A VSS DQS7*
163 163
VSS VSS

f
166 43 DQSA8 166 43 DQSA8
VSS DQS8 -DQSA8 VSS DQS8 -DQSA8
199 42 199 42
VSS DQS8* R23 VSS DQS8*
202 202
VSS DMA0 15/4/1 VSS DMA0
205 125 205 125
VSS DM0/DQS9 VSS DM0/DQS9
208 126 208 126

n y
VSS NC/DQS9* VSS NC/DQS9*
211 211
VSS DMA1 VSS DMA1
214 134 214 134
VSS DM1/DQS10 VSS DM1/DQS10
217 135 217 135
VSS NC/DQS10* VSS NC/DQS10*
220 220

o
C VSS DMA2 VSS DMA2 C
223 143 223 143
VSS DM2/DQS11 DDR15V VSS DM2/DQS11
226 144 226 144
VSS NC/DQS11* VSS NC/DQS11*
229 229
VSS DMA3 VSS DMA3
232 152 232 152
VSS DM3/DQS12 R24 VSS DM3/DQS12
235 153 235 153
VSS NC/DQS12* 15/4/1 VSS NC/DQS12*
239 239

C
VSS DMA4 VSS DMA4
203 203

p
DM4/DQS13 VREFCA_A DM4/DQS13
NC/DQS13*
204 Trace min 10/10 NC/DQS13*
204

51 212 DMA5 VREFCA_A 51 212 DMA5


VDD DM5/DQS14 VDD DM5/DQS14
54 213 54 213
VDD NC/DQS14* VDD NC/DQS14*

e o
57 57
VDD DMA6 VDD DMA6
60 221 60 221
VDD DM6/DQS15 R2 VDD DM6/DQS15
62 222 62 222

t
VDD NC/DQS15* 15/4/1 VDD NC/DQS15*
65 65
VDD DMA7 VDD DMA7
66 230 66 230
DDR15V VDD DM7/DQS16 DDR15V VDD DM7/DQS16
69 231 69 231

C
VDD NC/DQS16* VDD NC/DQS16*
72 72
VDD

y
DMA8 VDD DMA8
75 161 75 161
VDD DM8/DQS17 VDD DM8/DQS17
78 162 78 162
VDD NC/DQS17* VDD NC/DQS17*
170 170
VDD VDD
173 173

t
VDD MDA0 VDD MDA0

b
176 3 MDA[0..63] {5} 176 3 MDA[0..63] {5}
VDD DQ0 MDA1 VDD DQ0 MDA1
179 4 179 4
VDD DQ1 MDA2 VDD DQ1 MDA2
182 9 182 9
VDD DQ2 MDA3 VDD DQ2 MDA3
183 10 183 10

o
VDD DQ3 MDA4 VDD DQ3 MDA4

a
186 122 186 122
VDD DQ4 MDA5 VDD DQ4 MDA5
189 123 189 123
VDD DQ5 MDA6 VDD DQ5 MDA6
191 128 191 128
VDD DQ6 MDA7 VDD DQ6 MDA7
194 129 194 129
VDD DQ7 VDD DQ7

n
C275 0.1u/4/X7R/16V/K 197 12 MDA8 C276 0.1u/4/X7R/16V/K 197 12 MDA8

g
VDD DQ8 MDA9 VDD DQ8 MDA9
13 13
DQ9 MDA10 DQ9 MDA10
236 18 236 18

i
VCC3 VDDSPD DQ10 MDA11 VCC3 VDDSPD DQ10 MDA11
19 19
DQ11 MDA12 DQ11 MDA12
131 131
VREFCA_A DQ12 MDA13 C278 0.1u/4/X7R/16V/K VREFCA_A DQ12 MDA13
67 132 67 132
VREFCA DQ13 VREFCA DQ13

G Do
C279 0.1u/4/X7R/16V/KVREFDQ_A 1 137 MDA14 C280 0.1u/4/X7R/16V/K VREFDQ_A 1 137 MDA14
VREFDQ DQ14 MDA15 VREFDQ DQ14 MDA15
138 138
DQ15 MDA16 DQ15 MDA16
21 21
SMBCLK DQ16 MDA17 SMBCLK DQ16 MDA17
{9,13,15,27,31} SMBCLK 118 22 {9,13,15,27,31} SMBCLK 118 22
SMBDATA SCL DQ17 MDA18 SMBDATA SCL DQ17 MDA18
{9,13,15,27,31} SMBDATA 238 27 {9,13,15,27,31} SMBDATA 238 27
B SDA DQ18 MDA19 SDA DQ18 MDA19 B
237 28 VCC3 237 28
SA1 DQ19 MDA20 SA1 DQ19 MDA20
117 140 117 140
SA0 DQ20 MDA21 SA0 DQ20 MDA21
141 141
SBAA2 DQ21 MDA22 SBAA2 DQ21 MDA22
{5} SBAA2 52 146 {5} SBAA2 52 146
SBAA1 BA2 DQ22 MDA23 SBAA1 BA2 DQ22 MDA23
{5} SBAA1 190 147 {5} SBAA1 190 147
SBAA0 BA1 DQ23 MDA24 SBAA0 BA1 DQ23 MDA24
{5} SBAA0 71 30 {5} SBAA0 71 30
BA0 DQ24 MDA25 BA0 DQ24 MDA25
31 31
CKEA1 DQ25 MDA26 CKEA1 DQ25 MDA26
{5} CKEA1 169 36 {5} CKEA1 169 36
CKEA0 CKE1 DQ26 MDA27 CKEA0 CKE1 DQ26 MDA27
{5} CKEA0 50 37 {5} CKEA0 50 37
CKE0 DQ27 MDA28 CKE0 DQ27 MDA28
149 149
DQ28 MDA29 -CSA3 DQ28 MDA29
{5} -CSA1 76 150 {5} -CSA3 76 150
-CSA0 S1* DQ29 MDA30 -CSA2 S1* DQ29 MDA30
{5} -CSA0 193 155 {5} -CSA2 193 155
S0* DQ30 MDA31 S0* DQ30 MDA31
156 156
-DCLKA1 DQ31 MDA32 -DCLKA3 DQ31 MDA32
{6} -DCLKA1 64 81 {5} -DCLKA3 64 81
DCLKA1 CK1/NU* DQ32 MDA33 DCLKA3 CK1/NU* DQ32 MDA33
{6} DCLKA1 63 82 {5} DCLKA3 63 82
CK1/NU DQ33 MDA34 CK1/NU DQ33 MDA34
87 87
-DCLKA0 DQ34 MDA35 -DCLKA2 DQ34 MDA35
{5} -DCLKA0 185 88 {6} -DCLKA2 185 88
DCLKA0 CK0* DQ35 MDA36 DCLKA2 CK0* DQ35 MDA36
{5} DCLKA0 184 200 {6} DCLKA2 184 200
CK0 DQ36 MDA37 CK0 DQ36 MDA37
201 201
MAAA0 DQ37 MDA38 MAAA0 DQ37 MDA38
188 206 188 206
MAAA1 A0 DQ38 MDA39 MAAA1 A0 DQ38 MDA39
{5} MAAA[0..15] 181 207 {5} MAAA[0..15] 181 207
MAAA2 A1 DQ39 MDA40 MAAA2 A1 DQ39 MDA40
61 90 61 90
MAAA3 A2 DQ40 MDA41 MAAA3 A2 DQ40 MDA41
180 91 180 91
MAAA4 A3 DQ41 MDA42 MAAA4 A3 DQ41 MDA42
59 96 59 96
MAAA5 A4 DQ42 MDA43 MAAA5 A4 DQ42 MDA43
58 97 58 97
MAAA6 A5 DQ43 MDA44 MAAA6 A5 DQ43 MDA44
178 209 178 209
MAAA7 A6 DQ44 MDA45 MAAA7 A6 DQ44 MDA45
56 210 56 210
MAAA8 A7 DQ45 MDA46 MAAA8 A7 DQ45 MDA46
177 215 177 215
MAAA9 A8 DQ46 MDA47 MAAA9 A8 DQ46 MDA47
175 216 175 216
MAAA10 A9 DQ47 MDA48 MAAA10 A9 DQ47 MDA48
70 99 70 99
MAAA11 A10/AP DQ48 MDA49 MAAA11 A10/AP DQ48 MDA49
55 100 55 100
MAAA12 A11 DQ49 MDA50 MAAA12 A11 DQ49 MDA50
174 105 174 105
MAAA13 A12 DQ50 MDA51 MAAA13 A12 DQ50 MDA51
196 106 196 106
MAAA14 A13 DQ51 MDA52 MAAA14 A13 DQ51 MDA52
172 218 172 218
MAAA15 A14 DQ52 MDA53 MAAA15 A14 DQ52 MDA53
171 219 171 219
A15 DQ53 MDA54 A15 DQ53 MDA54
224 224
MA_RESET_L 168 DQ54 MDA55 MA_RESET_L 168 DQ54 MDA55
{6} MA_RESET_L 225 {6} MA_RESET_L 225
-SCASA RESET* DQ55 MDA56 -SCASA RESET* DQ55 MDA56
{5} -SCASA 74 108 {5} -SCASA 74 108
-SRASA CAS* DQ56 MDA57 -SRASA CAS* DQ56 MDA57
{5} -SRASA 192 109 {5} -SRASA 192 109
-SWEA RAS* DQ57 MDA58 -SWEA RAS* DQ57 MDA58
{5} -SWEA 73 114 {5} -SWEA 73 114
WE* DQ58 MDA59 WE* DQ58 MDA59
A 115 115 A
DQ59 MDA60 DQ59 MDA60
227 227
DQ60 MDA61 DQ60 MDA61
228 228
DQ61 MDA62 DQ61 MDA62
233 233
DQ62 MDA63 DQ62 MDA63
234 234
DQ63 DDR15V Decouple DQ63
DDRVTT Decouple
DDR3/240/BK/VA/D DDR3/240/GR/VA/D
DDR15V DDRVTT

BC2 BC7 DDRVTT


0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K

BC3 BC8
0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K Title
BC118 BC152
BC6 BC9 4.7u/6/X5R/6.3V/K/X 4.7u/6/X5R/6.3V/K/X DDR III CHANNEL A
0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 8 of 35
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

DDR3_3
DDR3_1
DDRVTT 120 48
VTT FREE
240 49 DDRVTT 120 48
VTT FREE MB_EVENT_L VTT FREE
187 MB_EVENT_L {6} 240 49
FREE VTT FREE MB_EVENT_L
2 198 187 MB_EVENT_L {6}
VSS FREE FREE
5 2 198
VSS VSS FREE
8 79 5
VSS RSVD VSS
11 8 79
VSS MODT_B1 VSS RSVD
14 77 MODT_B1 {6} 11
VSS ODT1 MODT_B0 VSS MODT_B3
17 195 MODT_B0 {5} 14 77 MODT_B3 {6}
VSS ODT0 VSS ODT1 MODT_B2
20 17 195 MODT_B2 {5}
VSS VSS ODT0
23 68 20
VSS NC/PAR_IN VSS
26 53 23 68
VSS NC/ERR_OUT VSS NC/PAR_IN
29 167 26 53
VSS NC/TEST4 VSS NC/ERR_OUT
32 29 167
VSS MB_CK0 VSS NC/TEST4
35 39 32
VSS CB0 MB_CK1 -DQSB[0..8] VSS MB_CK0
38 40 -DQSB[0..8] {5} 35 39
VSS CB1 MB_CK2 VSS CB0 MB_CK1
41 45 38 40
VSS CB2 MB_CK3 VSS CB1 MB_CK2
D 44 46 41 45 D
VSS CB3 MB_CK4 DQSB[0..8] VSS CB2 MB_CK3
47 158 DQSB[0..8] {5} 44 46
VSS CB4 MB_CK5 VSS CB3 MB_CK4
80 159 47 158
VSS CB5 MB_CK6 VSS CB4 MB_CK5
83 164 80 159
VSS CB6 MB_CK7 DMB[0..8] VSS CB5 MB_CK6
86 165 DMB[0..8] {5} 83 164
VSS CB7 VSS CB6 MB_CK7
89 86 165

l
VSS VSS CB7
92 89
VSS DQSB0 MODT_B[0..3] VSS
95 7 MODT_B[0..3] {5,6} 92
VSS DQS0 -DQSB0 VSS DQSB0
98 6 95 7
VSS DQS0* VSS DQS0 -DQSB0
101 98 6

a
VSS DQSB1 MB_CK[0..7] VSS DQS0*
104 16 MB_CK[0..7] {5} 101
VSS DQS1 -DQSB1 VSS DQSB1
107 15 104 16
VSS DQS1* VSS DQS1

ti
110 107 15 -DQSB1
VSS DQSB2 VSS DQS1*
113 25 110
VSS DQS2 -DQSB2 VSS DQSB2
116 24 113 25
VSS DQS2* VSS DQS2 -DQSB2
119 116 24
VSS DQSB3 VSS DQS2*
121 34 119
VSS DQS3 -DQSB3 VSS DQSB3
124 33 121 34
VSS DQS3* VSS DQS3 -DQSB3
127 124 33
VSS VSS DQS3*

n
130 85 DQSB4 127
VSS DQS4 -DQSB4 VSS DQSB4
133 84 130 85
VSS DQS4* VSS DQS4 -DQSB4
136 133 84
VSS DQSB5 VSS DQS4*
139 94 136

e
VSS DQS5 -DQSB5 VSS DQSB5
142 93 139 94
VSS DQS5* VSS DQS5 -DQSB5
145 142 93
VSS DQSB6 VSS DQS5*
148 103 145
VSS DQS6 -DQSB6 VSS DQSB6
151 102 148 103
VSS DQS6* VSS DQS6 -DQSB6

d
154 151 102
VSS DQSB7 VSS DQS6*
157 112 154
VSS DQS7 -DQSB7 VSS DQSB7
160 111 157 112

i
VSS DQS7* VSS DQS7 -DQSB7
163 160 111
VSS DQSB8 VSS DQS7*
166 43 163
VSS DQS8 VSS

f
199 42 -DQSB8 166 43 DQSB8
VSS DQS8* VSS DQS8 -DQSB8
202 199 42
VSS DMB0 VSS DQS8*
205 125 202
VSS DM0/DQS9 VSS DMB0
208 126 205 125
VSS NC/DQS9* VSS DM0/DQS9
211 208 126

n y
VSS DMB1 VSS NC/DQS9*
214 134 211
VSS DM1/DQS10 VSS DMB1
217 135 214 134
VSS NC/DQS10* VSS DM1/DQS10
220 217 135
VSS DMB2 VSS NC/DQS10*
223 143 220

o
C VSS DM2/DQS11 VSS DMB2 C
226 144 223 143
VSS NC/DQS11* VSS DM2/DQS11
229 226 144
VSS DMB3 VSS NC/DQS11*
232 152 229
VSS DM3/DQS12 VSS DMB3
235 153 232 152
VSS NC/DQS12* VSS DM3/DQS12
239 235 153
VSS DMB4 VSS NC/DQS12*
203 239

C
DM4/DQS13 VSS DMB4
204 203

p
NC/DQS13* DM4/DQS13
204
DMB5 NC/DQS13*
51 212
VDD DM5/DQS14 DMB5
54 213 51 212
VDD NC/DQS14* VDD DM5/DQS14
57 54 213
VDD VDD NC/DQS14*

e o
60 221 DMB6 57
VDD DM6/DQS15 VDD DMB6
62 222 60 221
VDD NC/DQS15* VDD DM6/DQS15
65 62 222

t
VDD DMB7 VDD NC/DQS15*
66 230 65
DDR15V VDD DM7/DQS16 VDD DMB7
69 231 66 230
VDD NC/DQS16* VDD DM7/DQS16
72 69 231

C
VDD DMB8 VDD NC/DQS16*
75 161 72
VDD DM8/DQS17

y
VDD DMB8
78 162 DDR15V 75 161
VDD NC/DQS17* VDD DM8/DQS17
170 78 162
VDD VDD NC/DQS17*
173 170
VDD MDB0 VDD
176 3 173

t
VDD DQ0 MDB1 VDD MDB0

b
179 4 176 3 MDB[0..63] {5}
VDD DQ1 MDB2 MDB[0..63] {5} VDD DQ0 MDB1
182 9 179 4
VDD DQ2 MDB3 VDD DQ1 MDB2
183 10 182 9
VDD DQ3 MDB4 VDD DQ2 MDB3
186 122 183 10

o
VDD DQ4 MDB5 VDD DQ3 MDB4

a
189 123 186 122
VDD DQ5 MDB6 VDD DQ4 MDB5
191 128 189 123
VDD DQ6 MDB7 VDD DQ5 MDB6
194 129 191 128
VDD DQ7 MDB8 VDD DQ6 MDB7
197 12 194 129
VDD DQ8 VDD DQ7

n
13 MDB9 197 12 MDB8

g
DQ9 MDB10 0.1u/4/X7R/16V/K C282 VDD DQ8 MDB9
VCC3 236 18 13
VDDSPD DQ10 MDB11 DQ9 MDB10
19 236 18

i
DQ11 MDB12 VCC3 VDDSPD DQ10 MDB11
131 VREFCA_A 19
C283 0.1u/4/X7R/16V/K VREFCA_A DQ12 MDB13 DQ11 MDB12
67 132 131
C285 0.1u/4/X7R/16V/K VREFDQ_A VREFCA DQ13 MDB14 C284 0.1u/4/X7R/16V/K VREFCA_A DQ12 MDB13
1 137 67 132
VREFDQ DQ14 VREFCA DQ13

G Do
138 MDB15 C286 0.1u/4/X7R/16V/K VREFDQ_A 1 137 MDB14
DQ15 MDB16 VREFDQ DQ14 MDB15
21 138
SMBCLK DQ16 MDB17 DQ15 MDB16
{8,13,15,27,31} SMBCLK 118 22 VREFDQ_A 21
SMBDATA SCL DQ17 MDB18 SMBCLK DQ16 MDB17
{8,13,15,27,31} SMBDATA 238 27 {8,13,15,27,31} SMBCLK 118 22
SDA DQ18 MDB19 SMBDATA SCL DQ17 MDB18
237 28 {8,13,15,27,31} SMBDATA 238 27
B SA1 DQ19 MDB20 SDA DQ18 MDB19 B
VCC3 117 140 237 28
SA0 DQ20 MDB21 SA1 DQ19 MDB20
141 VCC3 117 140
SBAB2 DQ21 MDB22 SA0 DQ20 MDB21
{5} SBAB2 52 146 141
SBAB1 BA2 DQ22 MDB23 SBAB2 DQ21 MDB22
{5} SBAB1 190 147 {5} SBAB2 52 146
SBAB0 BA1 DQ23 MDB24 SBAB1 BA2 DQ22 MDB23
71 30 {5} SBAB1 190 147
{5} SBAB0 BA0 DQ24 MDB25 SBAB0 BA1 DQ23 MDB24
31 71 30
CKEB1 DQ25 MDB26 {5} SBAB0 BA0 DQ24 MDB25
{5} CKEB1 169 36 31
CKEB0 CKE1 DQ26 MDB27 CKEB1 DQ25 MDB26
{5} CKEB0 50 37 {5} CKEB1 169 36
CKE0 DQ27 MDB28 CKEB0 CKE1 DQ26 MDB27
149 {5} CKEB0 50 37
-CSB1 DQ28 MDB29 CKE0 DQ27 MDB28
{5} -CSB1 76 150 149
-CSB0 S1* DQ29 MDB30 -CSB3 DQ28 MDB29
{5} -CSB0 193 155 {5} -CSB3 76 150
S0* DQ30 MDB31 -CSB2 S1* DQ29 MDB30
156 {5} -CSB2 193 155
-DCLKB1 DQ31 MDB32 S0* DQ30 MDB31
{6} -DCLKB1 64 81 156
DCLKB1 CK1/NU* DQ32 MDB33 -DCLKB3 DQ31 MDB32
{6} DCLKB1 63 82 {5} -DCLKB3 64 81
CK1/NU DQ33 MDB34 DCLKB3 CK1/NU* DQ32 MDB33
87 {5} DCLKB3 63 82
-DCLKB0 DQ34 MDB35 CK1/NU DQ33 MDB34
{5} -DCLKB0 185 88 87
DCLKB0 CK0* DQ35 MDB36 -DCLKB2 DQ34 MDB35
{5} DCLKB0 184 200 {6} -DCLKB2 185 88
CK0 DQ36 MDB37 DCLKB2 CK0* DQ35 MDB36
201 {6} DCLKB2 184 200
MAAB0 DQ37 MDB38 CK0 DQ36 MDB37
{5} MAAB[0..15] 188 206 201
MAAB1 A0 DQ38 MDB39 MAAB0 DQ37 MDB38
181 207 {5} MAAB[0..15] 188 206
MAAB2 A1 DQ39 MDB40 MAAB1 A0 DQ38 MDB39
61 90 181 207
MAAB3 A2 DQ40 MDB41 MAAB2 A1 DQ39 MDB40
180 91 61 90
MAAB4 A3 DQ41 MDB42 MAAB3 A2 DQ40 MDB41
59 96 180 91
MAAB5 A4 DQ42 MDB43 MAAB4 A3 DQ41 MDB42
58 97 59 96
MAAB6 A5 DQ43 MDB44 MAAB5 A4 DQ42 MDB43
178 209 58 97
MAAB7 A6 DQ44 MDB45 MAAB6 A5 DQ43 MDB44
56 210 178 209
MAAB8 A7 DQ45 MDB46 MAAB7 A6 DQ44 MDB45
177 215 56 210
MAAB9 A8 DQ46 MDB47 MAAB8 A7 DQ45 MDB46
175 216 177 215
MAAB10 A9 DQ47 MDB48 MAAB9 A8 DQ46 MDB47
70 99 175 216
MAAB11 A10/AP DQ48 MDB49 MAAB10 A9 DQ47 MDB48
55 100 70 99
MAAB12 A11 DQ49 MDB50 MAAB11 A10/AP DQ48 MDB49
174 105 55 100
MAAB13 A12 DQ50 MDB51 MAAB12 A11 DQ49 MDB50
196 106 174 105
MAAB14 A13 DQ51 MDB52 MAAB13 A12 DQ50 MDB51
172 218 196 106
MAAB15 A14 DQ52 MDB53 MAAB14 A13 DQ51 MDB52
171 219 172 218
A15 DQ53 MDB54 MAAB15 A14 DQ52 MDB53
224 171 219
MB_RESET_L 168 DQ54 MDB55 A15 DQ53 MDB54
{6} MB_RESET_L 225 224
-SCASB RESET* DQ55 MDB56 MB_RESET_L 168 DQ54 MDB55
{5} -SCASB 74 108 {6} MB_RESET_L 225
-SRASB CAS* DQ56 MDB57 -SCASB RESET* DQ55 MDB56
{5} -SRASB 192 109 {5} -SCASB 74 108
-SWEB RAS* DQ57 MDB58 -SRASB CAS* DQ56 MDB57
{5} -SWEB 73 114 {5} -SRASB 192 109
WE* DQ58 MDB59 -SWEB RAS* DQ57 MDB58
115 {5} -SWEB 73 114
DQ59 MDB60 WE* DQ58 MDB59
A 227 115 A
DQ60 MDB61 DQ59 MDB60
228 227
DQ61 MDB62 DQ60 MDB61
233 228
DQ62 MDB63 DQ61 MDB62
234 233
DQ63 DQ62 MDB63
234
DQ63
DDR3/240/BK/VA/D DDR15V Decouple DDRVTT Decouple
DDR3/240/GR/VA/D
DDR15V DDR15V

BC131 DDRVTT
0.1u/4/X7R/16V/K
BC148
BC10 BC11 BC129 0.1u/4/X7R/16V/K
22U/8/X5R/6.3V/M 22U/8/X5R/6.3V/M 0.1u/4/X7R/16V/K Title
BC149
BC125 0.1u/4/X7R/16V/K DDR III CHANNEL B
0.1u/4/X7R/16V/K Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 9 of 35
8 7 6 5 4 3 2 1
5 4 3 2 1

U3A U3C

L0_CADOUT_H15 T25 PART 1/5 N23 L0_CADIN_H15 K21 PART 3/5 J8


L0_CADOUT_L15 HT_RXCAD15P HT_TXCAD15P L0_CADIN_L15 {13} NBHT_REFCLKP HT_REFCLKP GPP1_REFCLKP NBGFX_CLKP {13}
T24 HT_RXCAD15N HT_TXCAD15N N24 {13} NBHT_REFCLKN J21 HT_REFCLKN GPP1_REFCLKN H8 NBGFX_CLKN {13}
L0_CADOUT_H14 U24 M24 L0_CADIN_H14
L0_CADOUT_L14 HT_RXCAD14P HT_TXCAD14P L0_CADIN_L14
U23 M25
L0_CADOUT_H13 V25
HT_RXCAD14N HT_TXCAD14N
L23 L0_CADIN_H13 CLOCKs GPP2_REFCLKP V8
U8
NBGFX1_CLKP {13}
HT_RXCAD13P HT_TXCAD13P GPP2_REFCLKN NBGFX1_CLKN {13}
L0_CADOUT_L13 V24 L24 L0_CADIN_L13
L0_CADOUT_H12 HT_RXCAD13N HT_TXCAD13N L0_CADIN_H12
W 24 HT_RXCAD12P HT_TXCAD12P K24 GPP3_REFCLKP AA15 NBGPP_CLKP {13}
L0_CADOUT_L12 W 23 K25 L0_CADIN_L12 B17 AA14
L0_CADOUT_H11 HT_RXCAD12N HT_TXCAD12N L0_CADIN_H11 {13} NB_OSC OSCIN GPP3_REFCLKN NBGPP_CLKN {13}
AA24 HT_RXCAD11P HT_TXCAD11P H24
L0_CADOUT_L11 AA23 H25 L0_CADIN_L11
L0_CADOUT_H10 HT_RXCAD11N HT_TXCAD11N L0_CADIN_H10
AB25 HT_RXCAD10P HT_TXCAD10P G23
D L0_CADOUT_L10 AB24 G24 L0_CADIN_L10 {6,14} -CPURST -CPURST D15 D
L0_CADOUT_H9 HT_RXCAD10N HT_TXCAD10N L0_CADIN_H9 NB_PWROK SYSRESETb
AC24 HT_RXCAD9P HT_TXCAD9P F24 {15,29} NB_PWROK A17 POW ERGOOD
L0_CADOUT_L9 AC23 F25 L0_CADIN_L9 NBLDT_STOP- E15 DFT_GPIO1 NR21 1K/4/1/X
L0_CADOUT_H8 AD25
HT_RXCAD9N HT_TXCAD9N
E23 L0_CADIN_H8 D21
LDTSTOPb PM VCC18
HT_RXCAD8P HT_TXCAD8P {14} ALLOW_LDTSTOP ALLOW _LDTSTOP
L0_CADOUT_L8 AD24 E24 L0_CADIN_L8 DFT_GPIO2 NR22 1K/4/1/X
HT_RXCAD8N HT_TXCAD8N

l
L0_CADOUT_H7 T28 N26 L0_CADIN_H7
L0_CADOUT_L7 HT_RXCAD7P HT_TXCAD7P L0_CADIN_L7
T27 HT_RXCAD7N HT_TXCAD7N N27
L0_CADOUT_H6 U27 M27 L0_CADIN_H6 B19 B26 DFT_GPIO0 NR18 1K/4/1/X
HT_RXCAD6P HT_TXCAD6P PCIE_RESET_GPIO1 DFT_GPIO0/NMI#

HYPERTRANSPORT IF
a
L0_CADOUT_L6 U26 M28 L0_CADIN_L6 D17 A25 DFT_GPIO1 NR19 1K/4/1/X
L0_CADOUT_H5 HT_RXCAD6N HT_TXCAD6N L0_CADIN_H5 PCIE_RESET_GPIO2 DFT_GPIO1 DFT_GPIO2 NR10 1K/4/1
V28 HT_RXCAD5P HT_TXCAD5P L26 D19 PCIE_RESET_GPIO3 DFT_GPIO2 B24

ti
L0_CADOUT_L5 V27 L27 L0_CADIN_L5 E19 B25 DFT_GPIO3 NR12 1K/4/1/X
L0_CADOUT_H4 HT_RXCAD5N HT_TXCAD5N L0_CADIN_H4 PCIE_RESET_GPIO4 DFT_GPIO3 DFT_GPIO4 NR11 1K/4/1
W 27 HT_RXCAD4P HT_TXCAD4P K27 E17 PCIE_RESET_GPIO5 DFT_GPIO4 B23
L0_CADOUT_L4 W 26 K28 L0_CADIN_L4 A23 DFT_GPIO5 NR17 1K/4/1/X
L0_CADOUT_H3 HT_RXCAD4N HT_TXCAD4N L0_CADIN_H3 DFT_GPIO5/SYNCFLOODIN#
AA27 HT_RXCAD3P HT_TXCAD3P H27
L0_CADOUT_L3 AA26 H28 L0_CADIN_L3 NR25 1K/4/1/X PWM_GPIO1 E16
L0_CADOUT_H2 HT_RXCAD3N HT_TXCAD3N L0_CADIN_H2 NR26 1K/4/1/X PWM_GPIO2 PW M_GPIO1
AB28 G26 B15
MISC.

n
L0_CADOUT_L2 HT_RXCAD2P HT_TXCAD2P L0_CADIN_L2 NR27 1K/4/1/X PWM_GPIO3 PW M_GPIO2 DBG_GPIO0 NR23 1K/4/1/X VCC18
AB27 HT_RXCAD2N HT_TXCAD2N G27 F16 PW M_GPIO3 DBG_GPIO0/SERR_FATA# C22 VCC18
L0_CADOUT_H1 AC27 F27 L0_CADIN_H1 NR28 1K/4/1/X PWM_GPIO4 A15 B22 DBG_GPIO1 NR24 4.75K/4/1
L0_CADOUT_L1 HT_RXCAD1P HT_TXCAD1P L0_CADIN_L1 PWM_GPIO5 PW M_GPIO4 DBG_GPIO1/SIC DBG_GPIO2

e
AC26 F28 VCC18 NR29 1K/4/1/X C16 B21 NR16 4.75K/4/1
L0_CADOUT_H0 HT_RXCAD1N HT_TXCAD1N L0_CADIN_H0 NR30 1K/4/1/X PWM_GPIO6 PW M_GPIO5 DBG_GPIO2/SID DBG_GPIO3 NR20 1K/4/1/X
AD28 HT_RXCAD0P HT_TXCAD0P E26 B16 PW M_GPIO6 DBG_GPIO3/NON_FATA_CORR# A21
L0_CADOUT_L0 AD27 E27 L0_CADIN_L0 NR14
HT_RXCAD0N HT_TXCAD0N 2K/4/1

d
L0_CLKOUT_H1 Y25 J23 L0_CLKIN_H1 VCC18 NR8 1K/4/1 NBI2C_CLK B20
{4} L0_CLKOUT_H1 HT_RXCLK1P HT_TXCLK1P L0_CLKIN_H1 {4} I2C_CLK
L0_CLKOUT_L1 Y24 J24 L0_CLKIN_L1 NR9 1K/4/1 NBI2C_DATA C20 E21 STRP_DATA STRP_DATA

i
{4} L0_CLKOUT_L1 L0_CLKOUT_H0 HT_RXCLK1N HT_TXCLK1N L0_CLKIN_H0 L0_CLKIN_L1 {4} I2C_DATA STRP_DATA
{4} L0_CLKOUT_H0 Y28 HT_RXCLK0P HT_TXCLK0P J26 L0_CLKIN_H0 {4}
L0_CLKOUT_L0 Y27 J27 L0_CLKIN_L0

f
{4} L0_CLKOUT_L0 HT_RXCLK0N HT_TXCLK0N L0_CLKIN_L0 {4}
Y21 NR15
L0_CTLOUT_H1 L0_CTLIN_H1 THERMALDIODE_P TESTMODE NR13 1.8K/4/1 2K/4/1/X
{4} L0_CTLOUT_H1 R24 HT_RXCTL1P HT_TXCTL1P P24 L0_CTLIN_H1 {4} AA21 THERMALDIODE_N TESTMODE A19
{4} L0_CTLOUT_L1 L0_CTLOUT_L1 R23 P25 L0_CTLIN_L1
HT_RXCTL1N HT_TXCTL1N L0_CTLIN_L1 {4}

n y
{4} L0_CTLOUT_H0 L0_CTLOUT_H0 R27 P27 L0_CTLIN_H0
L0_CTLOUT_L0 HT_RXCTL0P HT_TXCTL0P L0_CTLIN_L0 L0_CTLIN_H0 {4}
{4} L0_CTLOUT_L0 R26 P28 RX980/BGA692
C HT_RXCTL0N HT_TXCTL0N L0_CTLIN_L0 {4} C
HT_RXCALN HT_TXCALP

o
NR0 1.21K/4/1 D25 D28 NR1 1.21K/4/1
HT_RXCALP HT_RXCALP HT_TXCALP HT_TXCALN
D24 HT_RXCALN HT_TXCALN D27

RX980/BGA692 DFT_GPIO5: STRAP_DEBUG_BUS_GPIO_ENABLEb

C p
Enables the Test Debug Bus using GPIO.
1 : Disable ( Can still be enabled using

o
VCC18

e
nbcfg register access)
0 : Enable

t
L0_CADIN_L[0..15]
L0_CADIN_L[0..15] {4}
NR31

C
L0_CADIN_H[0..15] 1K/4/1

y
L0_CADIN_H[0..15] {4}
NBLDT_STOP- DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]
VCC18

t
3
b
NQ2 These pin straps are used to configure PCI-E GPP mode.
L0_CADOUT_L[0..15] D

o
L0_CADOUT_L[0..15] {4} GPIO4:3:2

a
NR32
L0_CADOUT_H[0..15] 1K/4/1 G S 000 : 4:2:4 B
L0_CADOUT_H[0..15] {4}
001 : 4:1:1:4 C

1
g n
010 : 1:1:1:1:1:1:4 L (Hardware Default)
011 : 2:1:1:1:1:4 E

3
i
NQ1 MMBT2222A/SOT23/600mA/40 100 : 2:2:1:1:4 K
D
101: 2:2:2:4 C2

G Do
B G S 110: Hardware default (mode L) or EEPROM B
111: Hardware default (mode L) or EEPROM

1
1

NR33 1K/4/1 101 : 01100


{6,14} -LDT_STOP
NB_HS
111 : 01011
1

MMBT2222A/SOT23/600mA/40

DFT_GPIO1: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM


2

1 : Bypass the loading of EEPROM straps and use Hardware Default


2

Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
NB_HS/[12SP2-SA0702-01R_12SP2-SA0702-02R]

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

Enables the Test Debug Bus using PCIE bus


1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

A A

Title
RX980 HT, SYS I/F
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 10 of 35
5 4 3 2 1
5 4 3 2 1

U3B

EXP_A_RXP15
PART 2/5 EXP_A_TXP15
N6 GPP1_RX15P GPP1_TX15P N3
EXP_A_RXN15 N5 N2 EXP_A_TXN15
EXP_A_RXP14 GPP1_RX15N GPP1_TX15N EXP_A_TXP14
M5 GPP1_RX14P GPP1_TX14P M2
EXP_A_RXN14 M4 M1 EXP_A_TXN14
EXP_A_RXP13 GPP1_RX14N GPP1_TX14N EXP_A_TXP13
L6 GPP1_RX13P GPP1_TX13P L3
EXP_A_RXN13 L5 L2 EXP_A_TXN13
EXP_A_RXP12 GPP1_RX13N GPP1_TX13N EXP_A_TXP12
K5 GPP1_RX12P GPP1_TX12P K2
EXP_A_RXN12 K4 K1 EXP_A_TXN12
EXP_A_RXP11 GPP1_RX12N GPP1_TX12N EXP_A_TXP11
J6 GPP1_RX11P GPP1_TX11P J3
EXP_A_RXN11 J5 J2 EXP_A_TXN11
EXP_A_RXP10 GPP1_RX11N GPP1_TX11N EXP_A_TXP10
H5 GPP1_RX10P GPP1_TX10P H2
D EXP_A_RXN10 H4 H1 EXP_A_TXN10 D
EXP_A_RXP9 GPP1_RX10N GPP1_TX10N EXP_A_TXP9
G6 GPP1_RX9P GPP1_TX9P G3
EXP_A_RXN9 G5 G2 EXP_A_TXN9
EXP_A_RXP8 GPP1_RX9N GPP1_TX9N EXP_A_TXP8
F5 GPP1_RX8P GPP1_TX8P F2
EXP_A_RXN8 F4 F1 EXP_A_TXN8
GPP1_RX8N GPP1_TX8N

l
EXP_A_RXP7 D2 E3 EXP_A_TXP7
EXP_A_RXN7 GPP1_RX7P GPP1_TX7P EXP_A_TXN7
D1 GPP1_RX7N GPP1_TX7N E2

PCIE GPP1
EXP_A_RXP6 B5 A4 EXP_A_TXP6
GPP1_RX6P GPP1_TX6P

a
EXP_A_RXN6 C5 B4 EXP_A_TXN6
EXP_A_RXP5 GPP1_RX6N GPP1_TX6N EXP_A_TXP5
D6 GPP1_RX5P GPP1_TX5P A6

i
EXP_A_RXN5 E6 B6 EXP_A_TXN5
EXP_A_RXP4 GPP1_RX5N GPP1_TX5N EXP_A_TXP4
E7 GPP1_RX4P GPP1_TX4P B7

t
EXP_A_RXN4 F7 C7 EXP_A_TXN4
EXP_A_RXP3 GPP1_RX4N GPP1_TX4N EXP_A_TXP3
D8 GPP1_RX3P GPP1_TX3P A8
EXP_A_RXN3 E8 B8 EXP_A_TXN3
EXP_A_RXP2 GPP1_RX3N GPP1_TX3N EXP_A_TXP2
E9 B9

n
EXP_A_RXN2 GPP1_RX2P GPP1_TX2P EXP_A_TXN2
F9 GPP1_RX2N GPP1_TX2N C9
EXP_A_RXP1 D10 A10 EXP_A_TXP1
EXP_A_RXN1 GPP1_RX1P GPP1_TX1P EXP_A_TXN1

e
E10 GPP1_RX1N GPP1_TX1N B10
EXP_A_RXP0 E11 B11 EXP_A_TXP0
EXP_A_RXN0 GPP1_RX0P GPP1_TX0P EXP_A_TXN0
F11 GPP1_RX0N GPP1_TX0N C11

i d
AC9 GPP2_RX15P GPP2_TX15P AF9
AD9 AG9

f
GPP2_RX15N GPP2_TX15N
AD8 GPP2_RX14P GPP2_TX14P AG8
AE8 GPP2_RX14N GPP2_TX14N AH8
AC7 GPP2_RX13P GPP2_TX13P AF7

n y
AD7 GPP2_RX13N GPP2_TX13N AG7
AD6 GPP2_RX12P GPP2_TX12P AG6
C AE6 AH6 C
GPP2_RX12N GPP2_TX12N

o
AF5 GPP2_RX11P GPP2_TX11P AG4
AG5 GPP2_RX11N GPP2_TX11N AH4
AF2 GPP2_RX10P GPP2_TX10P AE3
AF1 GPP2_RX10N GPP2_TX10N AE2
AD2 AC3

C
GPP2_RX9P GPP2_TX9P
AD1 AC2

p
GPP2_RX9N GPP2_TX9N
PCIE GPP2

AB5 GPP2_RX8P GPP2_TX8P AB2


AB4 GPP2_RX8N GPP2_TX8N AB1
AA6 GPP2_RX7P GPP2_TX7P AA3

e o
AA5 GPP2_RX7N GPP2_TX7N AA2
Y5 GPP2_RX6P GPP2_TX6P Y2

t
Y4 GPP2_RX6N GPP2_TX6N Y1
W6 GPP2_RX5P GPP2_TX5P W3
W5 W2

C
GPP2_RX5N GPP2_TX5N
V5 V2

y
GPP2_RX4P GPP2_TX4P
V4 GPP2_RX4N GPP2_TX4N V1
U6 GPP2_RX3P GPP2_TX3P U3

t
U5 GPP2_RX3N GPP2_TX3N U2

b
T5 GPP2_RX2P GPP2_TX2P T2
T4 GPP2_RX2N GPP2_TX2N T1

o
R6 GPP2_RX1P GPP2_TX1P R3

a
R5 GPP2_RX1N GPP2_TX1N R2
P5 GPP2_RX0P GPP2_TX0P P2
P4 GPP2_RX0N GPP2_TX0N P1

n
EXP_A_TXP[0..15]

g
EXP_A_TXP[0..15] {18}

i
EXP_A_TXN[0..15]
EXP_A_TXN[0..15] {18}
AD11 GPP3_RX9P GPP3_TX9P AH10
AC11 AG10

G Do
GPP3_RX9N GPP3_TX9N EXP_A_RXP[0..15]
AE12 GPP3_RX8P GPP3_TX8P AG11 EXP_A_RXP[0..15] {18}
B B
AD12 AF11
PCIE GPP3

GPP3_RX8N GPP3_TX8N EXP_A_RXN[0..15]


AD13 GPP3_RX7P GPP3_TX7P AH12 EXP_A_RXN[0..15] {18}
AC13 GPP3_RX7N GPP3_TX7N AG12 PCI_E slot TX need CAP close to slot side
AE14 GPP3_RX6P GPP3_TX6P AG13
AD14 GPP3_RX6N GPP3_TX6N AF13
AD15 AH14 GPP_TX5P_C NC4 0.1u/4/X7R/16V/K
{19} PCIE5_IP GPP3_RX5P GPP3_TX5P PCIE5_OP {19}
AC15 AG14 GPP_TX5N_C NC3 0.1u/4/X7R/16V/K
{19} PCIE5_IN GPP3_RX5N GPP3_TX5N PCIE5_ON {19}
ML_IP AE16 AG15 GPP_TX4P_C NC6 0.1u/4/X7R/16V/K
{35} ML_IP GPP3_RX4P GPP3_TX4P ML_OP {35}
ML_IN AD16 AF15 GPP_TX4N_C NC5 0.1u/4/X7R/16V/K
{35} ML_IN GPP3_RX4N GPP3_TX4N ML_ON {35}
AD17 GPP3_RX3P GPP3_TX3P AH16
AC17 GPP3_RX3N GPP3_TX3N AG16
PCIE2_IP AE18 AG17 GPP_TX2P_C NC10 0.1u/4/X7R/16V/K
{19} PCIE2_IP GPP3_RX2P GPP3_TX2P PCIE2_OP {19}
PCIE2_IN AD18 AF17 GPP_TX2N_C NC9 0.1u/4/X7R/16V/K
{19} PCIE2_IN GPP3_RX2N GPP3_TX2N PCIE2_ON {19}
PCIE1_IP AD19 AH18 GPP_TX1P_C NC20 0.1u/4/X7R/16V/K
{19} PCIE1_IP GPP3_RX1P GPP3_TX1P PCIE1_OP {19}
PCIE1_IN AC19 AG18 GPP_TX1N_C NC19 0.1u/4/X7R/16V/K
{19} PCIE1_IN GPP3_RX1N GPP3_TX1N PCIE1_ON {19}
USB3_IP AH20 AG19 GPP_TX0P_C NC2 0.1u/4/X7R/16V/K
{32} USB3_IP GPP3_RX0P GPP3_TX0P USB3_OP {32}
USB3_IN AG20 AF19 GPP_TX0N_C NC1 0.1u/4/X7R/16V/K
{32} USB3_IN GPP3_RX0N GPP3_TX0N USB3_ON {32}

AC21 AG22 A_TX3P_C NC11 0.1u/4/X7R/16V/K


PCIE ALINK

{14} A_RX3P SB_RX3P SB_TX3P A_TX3P {14}


AD21 AH22 A_TX3N_C NC12 0.1u/4/X7R/16V/K
{14} A_RX3N SB_RX3N SB_TX3N A_TX3N {14}
{14} A_RX2P AD22 AF21 A_TX2P_C NC14 0.1u/4/X7R/16V/K
SB_RX2P SB_TX2P A_TX2P {14}
{14} A_RX2N AE22 AG21 A_TX2N_C NC13 0.1u/4/X7R/16V/K
SB_RX2N SB_TX2N A_TX2N {14}
AF25 AF23 A_TX1P_C NC15 0.1u/4/X7R/16V/K
{14} A_RX1P SB_RX1P SB_TX1P A_TX1P {14}
{14} A_RX1N AG25 AG23 A_TX1N_C NC16 0.1u/4/X7R/16V/K
SB_RX1N SB_TX1N A_TX1N {14}
{14} A_RX0P AG26 AG24 A_TX0P_C NC18 0.1u/4/X7R/16V/K
SB_RX0P SB_TX0P A_TX0P {14}
AH26 AH24 A_TX0N_C NC17 0.1u/4/X7R/16V/K
{14} A_RX0N SB_RX0N SB_TX0N A_TX0N {14}
PLACE THESE CAP CLOSE TO NB.
A A
NR2 1.27K/4/1 AE20
NR3 1.82K/4/1 PCE_BCALRP
NB_VCC AD20 PCE_BCALRN
NR4 1.27K/4/1 AE10
NR5 1.82K/4/1 PCE_RCALRP
AD10 PCE_RCALRN
NR6 1.27K/4/1 F14
NR7 1.82K/4/1 PCE_TCALRP
E14 PCE_TCALRN Title

RX980/BGA692
RX980 PCIE I/F
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 11 of 35
5 4 3 2 1
5 4 3 2 1

AG27
AC10
AC12
AC14
AC16
AC18
AC20
AC25
AC28

AD26

AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AA11
AA13
AA17
AA19
AA20
AA25
AA28

AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB23
AB26

AE11
AE13
AE15
AE17
AE19
AE21
AE23

AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
W22
W25
W28

AG3
AC1
AC4
AC5
AC8

AD3
AD4

AH3
AH5
AH7
AH9
AA1
AA4
AA7
AA9

AB3
AB6
AB8

AE1
AE5
AE7
AE9
U11
U12
U13
U15
U17
U18
U22
U25
U28

AF4
AF6
AF8
V12
V13
V14
V15
V16
V17
V21
V23
V26

Y23
Y26
T11
T12
T14
T16
T18
T21
T23
T26

W1
W4
W7
U1
U4
U7

V3
V6

Y3
Y6
Y8
T3
T6
U3E T8
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
PART 5/5

GROUND
D D

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

a
RX980/BGA692
A5
A7
A9
A11
A14
A16
A20
A22
A24
A26
B3
B14
B27
C2
C4
C6
C8
C10
C14
C15
C17
C19
C21
C23
D3
D5
D7
D9
D11
D14
D16
D20
D26
E1
E4
E20
E25
E28
F3
F8
F10
F15
F17
F18
F19
F20
F21
F23
F26
G1
G4
G9
G11
G15
G16
G17
G18
G19
G20
G25
G28
H3
H6
H10
H15
H16
H17
H18
H19
H20
H21
H23
H26
J1
J4
J7
J22
J25
J28
K3
K6
K8
K23
K26
L1
L4
L7
L12
L13
L15
L17
L18
L22
L25
L28
M3
M6
M8
M11
M12
M14
M16
M17
M18
M21
M23
M26
N1
N4
N7
N11
N13
N15
N17
N18
N22
N25
N28
P3
P6
P8
P11
P12
P14
P16
P18
P21
P23
P26
R1
R4
R7
R11
R13
R15
R17
R18
R22
R25
R28
n ti
NB_VCC
VDDHT=>1.1V@3.25A
K22
L21
M22
U3D

VDDHT_1
VDDHT_2
VDDHT_3

fi d e
PART 4/5 VDDC_1
VDDC_2
VDDC_3
L14
L16
M13
NB_VCC

1.1V@8500mA

n y
C1613 N21 M15
SC42 0.1U/6/X7R/25V/K C1614 VDDHT_4 VDDC_4 SNC1 C1608 SC50 SC51 SC41 SC40 SBC3
P22 VDDHT_5 VDDC_5 N12
C 1U/6/X7R/16V/K 10u/6/X5R/6.3V/M R21 N14 0.1U/6/X7R/25V/K 0.1U/6/X7R/25V/K 0.1U/6/X7R/25V/K 1U/6/X7R/16V/K 1U/6/X7R/16V/K 22u/8/X5R/6.3V/M 1u/4/X5R/6.3V/K C
VDDHT_6 VDDC_6

o
T22 VDDHT_7 VDDC_7 N16
U21 VDDHT_8 VDDC_8 P13
V22 VDDHT_9 VDDC_9 P15
W 21 VDDHT_10 VDDC_10 P17
Y22 R12

C
VDDHT_11 VDDC_11
AA22 R14

p
VDDHT_12 VDDC_12
AB22 VDDHT_13 VDDC_13 R16
AC22 VDDHT_14 VDDC_14 T13
VDDC_15 T15

e o
AD23 VDDHT_15 VDDC_16 T17
AE24 VDDHT_16 VDDC_17 U14
VCC12_HT

t
AE25 VDDHT_17 VDDC_18 U16
AE26 VDDHT_18 VDDHTTX=>1.2V@1A
AE27 C24

C
NB_VCC VDDHT_19 VDDHTTX_1
AE28 C25

y
VDDHT_20 VDDHTTX_2
AF27 VDDHT_21 VDDHTTX_3 C26
C27 C1626 C1627 C1628 C1631 SC46 SC47
VDDHTTX_4

t
VDDPCIE=>1.1V@5.5A VDDHTTX_5 C28 0.1U/6/X7R/25V/K 0.1U/6/X7R/25V/K 0.1U/6/X7R/25V/K 1U/6/X7R/16V/K 1U/6/X7R/16V/K 10u/6/X5R/6.3V/M

b
A3 VDDPCIE_1 VDDHTTX_6 D22
B2 VDDPCIE_2 VDDHTTX_7 D23

o
C1 VDDPCIE_3 VDDHTTX_8 E22

a
C1616 SC43 C1618 C3 F22 VCC18
1U/6/X7R/16V/K 0.1U/6/X7R/25V/K VDDPCIE_4 VDDHTTX_9
10u/6/X5R/6.3V/M D4 VDDPCIE_5 VDDHTTX_10 G22
E5 VDDPCIE_6 VDDHTTX_11 H22

g n
F6 C1635 SBC1 C1637
VDDPCIE_7 10u/6/X5R/6.3V/M 1U/4/X5R/6.3V/K 0.1U/4/X7R/16V/K
G7 VDDPCIE_8 VDD18_1 A18

i
G8 VDDPCIE_9 VDD18_2 B18
G10 C18 VDDA18=>1.8V@0.1A VCC18
VDDPCIE_10 VDD18_3
H7 D18

G Do
VDDPCIE_11 VDD18_4
H9 VDDPCIE_12 VDD18_5 E18
B B
H11 VDDPCIE_13
K7 VDDPCIE_14
L8 VDDPCIE_15 VDDA18HTPLL G21 VDDA18HTPLL=>1.8V@0.05A SC48 SC49 C1640 C1641 C1642
M7 1U/6/X7R/16V/K 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K 0.1U/4/X7R/16V/K
VDDPCIE_16
N8 VDDPCIE_17 22U/8/X5R/6.3V/M
POWER

P7 VDDPCIE_18 VDDA18PCIE_21 G14


R8 VDDPCIE_19 VDDA18PCIE_20 H14
NB_VCC T7 VDDPCIE_20
V7 VDDPCIE_21 VDDA18PCIE=>1.8V@2A
W8 A12 VCORE
VDDPCIE_22 VDDA18PCIE_1 VCC18
Y7 VDDPCIE_23 VDDA18PCIE_2 A13
AA8 VDDPCIE_24 VDDA18PCIE_3 B12
SC44 SC45 SBC2 C1624 SNC2 AA10 B13 C1634
10u/6/X5R/6.3V/M 1U/6/X7R/16V/K 1u/4/X5R/6.3V/K 0.1U/6/X7R/25V/K VDDPCIE_25 VDDA18PCIE_4 2.2U/6/X5R/6.3V/K
AA12 VDDPCIE_26 VDDA18PCIE_5 C12
0.1U/6/X7R/25V/K AA16 C13 C147 C148 C149 C150 C151
VDDPCIE_27 VDDA18PCIE_6 0.1u/4/X7R/16V/K/X 0.1u/4/X7R/16V/K/X 0.1u/4/X7R/16V/K/X 0.1u/4/X7R/16V/K/X 0.1u/4/X7R/16V/K/X
AA18 VDDPCIE_28 VDDA18PCIE_7 D12
AB7 VDDPCIE_29 VDDA18PCIE_8 D13
AB9 VDDPCIE_30 VDDA18PCIE_9 E12
AB11 VDDPCIE_31 VDDA18PCIE_10 E13
AB13
AB15
VDDPCIE_32
VDDPCIE_33
VDDA18PCIE_11
VDDA18PCIE_12
F12
F13 HT Link Stitching Caps
AB17 VDDPCIE_34 VDDA18PCIE_13 G12
AB19 VDDPCIE_35 VDDA18PCIE_14 G13
AC6 VDDPCIE_36 VDDA18PCIE_15 H12
AD5 VDDPCIE_37 VDDA18PCIE_16 H13
AE4 VDDPCIE_38 VDDA18PCIE_17 L11
AF3 VDDPCIE_39 VDDA18PCIE_18 V11 VCC18
AG2 VDDPCIE_40 VDDA18PCIE_19 V18
SBC29 SBC36 SBC38
1u/4/X5R/6.3V/K 1u/4/X5R/6.3V/K 1u/4/X5R/6.3V/K
A
RX980/BGA692 A

NB_VCC

Title
BC141 SBC28 SBC37
1u/4/X5R/6.3V/K 1u/4/X5R/6.3V/K 1u/4/X5R/6.3V/K RX980 POWER & GND
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 12 of 35
5 4 3 2 1
5 4 3 2 1

NB CLOCK INPUT TABLE


VCC3
NB CLOCKS RS740 RX780 RS780

HT_REFCLKP
66M SE(SE) 100M DIFF 100M DIFF
HT_REFCLKN NC 100M DIFF 100M DIFF
BC59 BC893 BC894 BC895 BC896 BC897 BC898 BC899 BC900
10u/6/X5R/6.3V/M 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K REFCLK_P
14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V) 100M DIFF
REFCLK_N NC NC vref
100M DIFF
GFX_REFCLK* 100M DIFF 100M DIFF 100M DIFF

D 1- PLACE ALL THE SERIES TERMINATION GPP_REFCLK NC 100M DIFF 100M DIFF(OUT) D
RESISTORS AS CLOSE TO U800 AS
POSSIBLE GPPSB_REFCLK 100M DIFF 100M DIFF 100M DIFF

2- ROUTE ALL SRCCLKTx AND SRCCLKCx

l
AS DIFFERENT PAIR RULE * the GFX_REFCLK input is required for all cases

3- PUT DECOUPLING CAPS CLOSE TO U800

a
POWER PIN

ti
Place R800/801 less than 500 mils away from U800
R851 less than 100 mils away from R800/801
route CPU clock as 100ohm differential pair

en
VCC3
U185A
BC902

d
44 VDDA CPUKG0T_LPRS 50 CPUCLK0_H {6}
43 49

i
GNDA CPUKG0C_LPRS CPUCLK0_L {6}
0.1u/4/X7R/16V/K 46
CPUKG1T_LPRS
60 45

f
VDDREF CPUKG1C_LPRS
61 GNDREF
ATIG0T_LPRS 38 NBGFX_CLKP {10}
VCC3 39 VDDSATA ATIG0C_LPRS 37 NBGFX_CLKN {10}

n y
42 36 R1 0/4
GNDSATA ATIG1T_LPRS NBGFX1_CLKP {10}
BC62 BC904 BC903 35 R5 0/4
ATIG1C_LPRS NBGFX1_CLKN {10}
C 10u/6/X5R/6.3V/M 64 32 C
VDD48 ATIG2T_LPRS SRCCLK_3GIO_A {18}

o
1U/6/X7R/16V/K 3 31
GND48 ATIG2C_LPRS -SRCCLK_3GIO_A {18}
0.1u/4/X7R/16V/K 30
ATIG3T_LPRS
48 VDDCPU ATIG3C_LPRS 29
47 GNDCPU
27 168_CLK {32}

C
SB_SRC0T_LPRS
VCC3 56 26 168_CLK- {32}

p
VDDHTT SB_SRC0C_LPRS
53 GNDHTT SB_SRC1T_LPRS 23 PCIE2_CLK {19}
Parallel Resonance 34
SB_SRC1C_LPRS 22 -PCIE2_CLK {19}
VDDATIG

o
Crystal

e
SRC0T_LPRS 21 NBGPP_CLKP {10}
11 VDDSRC1 SRC0C_LPRS 20 NBGPP_CLKN {10}

t
16 VDDSRC2 SRC1T_LPRS 19 PCIE1_CLK {19}
25 VDDSB_SRC SRC1C_LPRS 18 -PCIE1_CLK {19}
15

C
SRC2T_LPRS SRCCLK_LAN {35}
28 14

y
GNDATIG1 SRC2C_LPRS -SRCCLK_LAN {35}
33 GNDATIG2 SRC3T_LPRS 13 SBSRC_CLKP {14}
C1750 22p/4/NPO/50V/J 12 VCC3
SRC3C_LPRS SBSRC_CLKN {14}

t
10 9 IDT_DOC1 R1766 8.2K/4
GNDSRC1 SRC4T_LPRS PCIE3_CLK {19} IDT_DOC1

b
17 GNDSRC2 SRC4C_LPRS 8 -PCIE3_CLK {19}
X7 24 7 IDT_DOC2 R1767 8.2K/4
GNDSB_SRC SRC5T_LPRS IDT_DOC2 IDT_DOC2
14.318M/16p/20ppm/49US/40/D

o
SRC5C_LPRS 6 IDT_DOC1

a
watch dog -- 62 X1 SRC6T/SATAT_LPRS 41 PCIEX4P {34}
RESTORE# 接 RESET C1751 22p/4/NPO/50V/J 63 40
X2 SRC6C/SATAC_LPRS PCIEX4N {34}

n
RESET_C

g
R106 10/4 52 55
{26,29} RESET RESTORE# HTT0T/66M_LPRS NBHT_REFCLKP {10}
HTT0C/66M_LPRS 54 NBHT_REFCLKN {10}

i
R110 10/4 SMBCLK_C 4 R135 8.2K/4
{8,9,15,27,31} SMBCLK SMBCLK VCC3
R113 10/4 SMBDATA_C 5 2 SIO_CLOCK_R R2492 33/4
{8,9,15,27,31} SMBDATA SMBDAT 48MHz_0 LPC48 {21}
1 48M_USB_R R2493 33/4

G Do
48MHz_1 USB48M {15}
R2494 1K/4/1 51 R137 8.2K/4/1
B VCC3 PD# B
R2501 8.2K/4/1 59 Pin1: High=>DOC input, Low=>SRC5
REF0/SEL_HTT66
OSC_14M_NB R2496 8.2K/4/1 58 Pin2: High=>SRCCLK7 , Low=>CPUKG1(477)
REF1/SEL_SATA
RS740 3.3V 33R serial R2503 75/4/1 57
{10} NB_OSC REF2
RX780 1.8V 82.5R/130R
R2505 ICS9LPRS477DKLF/MLF64/[10HL6-180477-40R]
RS780 1.1V 158R/90.9R 100/4/1
(Single-ended)
Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.
SMBCLK_C
SMBDATA_C
U185B
C201 C202
10P/4/NPO/50V/J/X 10P/4/NPO/50V/J/X 65 THERMAL GND
eGND65

ICS9LPRS477DKLF/MLF64/[10HL6-180477-40R]
REF0/SEL_HTT66 HTT CLOCK

0 100.00 DIFFERENTIAL
A A

1 66.66 SINGLE END

REF1/SEL_SATA SRC6/SATA

0 Title
100.00 DIFFERENTIAL SPREADING SRC CLOCK
ICS 9LPRS477D
Size Document Number Rev
1 100.00 NON-SPREADING DIFFERENTIAL SATA CLOCK Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 13 of 35
5 4 3 2 1
5 4 3 2 1

U2A

PR2 33/4 P1
SB800 Part 1 of 5
W2 PCLK0 PR8 33/4 LPC33 VCC3
{34} SBPCIE_RST- PCIE_RST# PCICLK0 LPC33 {21}
PR3 33/4 L1 W1 PCLK1 PR9 33/4 PCICLK1
{18,21} -A_RST A_RST# PCICLK1/GPO36 PCICLK1 {20}
W3 PCLK2 PR10 33/4 PCICLK2 PCLK1 PR14 8.2K/4
PCICLK2/GPO37 PCICLK2 {20}

PCI CLKS
PC3 0.1u/4/X7R/16V/K AD26 W4 PCLK3
{11} A_RX0P A_TX0P PCICLK3/GPO38
PC4 0.1u/4/X7R/16V/K AD27 Y1 PCLK4 PR25 22/4 TPM33
{11} A_RX0N A_TX0N PCICLK4/14M_OSC/GPO39 TPM33 {21}
PC5 0.1u/4/X7R/16V/K AC28
{11} A_RX1P A_TX1P -PPCIRST
PLACE THESE PCIE AC COUPLING PC6 0.1u/4/X7R/16V/K AC29 V2 PR13 33/4 -PPCIRST {20} Low: Force PCIE GEN1, Up: Allow PCIE GEN2
{11} A_RX1N A_TX1N PCIRST#
CAPS CLOSE TO SB850 PC7 0.1u/4/X7R/16V/K AB29
{11} A_RX2P A_TX2P
PC8 0.1u/4/X7R/16V/K AB28
{11} A_RX2N A_TX2N AD[0..31] {20}
PC9 0.1u/4/X7R/16V/K AB26 AA1 AD0
{11} A_RX3P A_TX3P AD0/GPIO0
PC10 0.1u/4/X7R/16V/K AB27 AA4 AD1
{11} A_RX3N A_TX3N AD1/GPIO1 AD2
D
AD2/GPIO2 AA3 D
AD3
S.B HEATSINK {11}
{11}
A_TX0P
A_TX0N
AE24
AE23
A_RX0P
A_RX0N
AD3/GPIO3
AD4/GPIO4
AB1
AA5 AD4
AD25 AB2 AD5
{11} A_TX1P A_RX1P AD5/GPIO5
AD24 AB6 AD6

PCI EXPRESS INTERFACES


{11} A_TX1N A_RX1N AD6/GPIO6

l
AC24 AB5 AD7
{11} A_TX2P A_RX2P AD7/GPIO7
AC25 AA6 AD8 PCLK2 PR18 8.2K/4
{11} A_TX2N A_RX2N AD8/GPIO8
{11} A_TX3P AB25 AC2 AD9
A_RX3P AD9/GPIO9

a
{11} A_TX3N AB24 AC3 AD10 PCLK3 PR92 8.2K/4
A_RX3N AD10/GPIO10 AD11
AD11/GPIO11 AC4

ti
PR5 590/4/1 AD29 AC1 AD12
PR4 2K/4/1 PCIE_CALRP AD12/GPIO12 AD13
VCC_SB AD28 PCIE_CALRN AD13/GPIO13 AD1
AD2 AD14
PC11 0.1u/4/X7R/16V/K SB_PETXP0 AD14/GPIO14 AD15
{34} PCIE4_OP0 AA28 GPP_TX0P AD15/GPIO15 AC6
PC12 0.1u/4/X7R/16V/K SB_PETXN0 AA29 AE2 AD16 PCLK2 PCLK3
{34} PCIE4_ON0 SB_PETXP1 GPP_TX0N AD16/GPIO16 AD17
PC46 0.1u/4/X7R/16V/K Y29 AE1

n
{34} PCIE4_OP1 GPP_TX1P AD17/GPIO17
PC47 0.1u/4/X7R/16V/K SB_PETXN1 Y28 AF8 AD18 PULL WATCHDOG TIMER USE
{34} PCIE4_ON1 SB_PETXP2 GPP_TX1N AD18/GPIO18 AD19
PC48 0.1u/4/X7R/16V/K Y26 AE3
{34} PCIE4_OP2
SB_PETXN2 GPP_TX2P AD19/GPIO19 AD20 HIGH ON NB_PWRGD DEBUG

e
PC49 0.1u/4/X7R/16V/K Y27 AF1
{34} PCIE4_ON2 GPP_TX2N AD20/GPIO20 ENABLED STRAPS
PC50 0.1u/4/X7R/16V/K SB_PETXP3 W 28 AG1 AD21
{34} PCIE4_OP3 SB_PETXN3 GPP_TX3P AD21/GPIO21 AD22
PC51 0.1u/4/X7R/16V/K W 29 AF2
{34} PCIE4_ON3 GPP_TX3N AD22/GPIO22
AE9 AD23 PULL WATCHDOG TIMER IGNORE

d
AD23/GPIO23 AD24
AA22 AD9 ON NB_PWRGD DEBUG
{34} PCIE4_IP0
Y21
GPP_RX0P AD24/GPIO24
AC11 AD25 LOW

i
{34} PCIE4_IN0 GPP_RX0N AD25/GPIO25 DISABLED STRAPS
1

AA25 AF6 AD26


{34} PCIE4_IP1 GPP_RX1P AD26/GPIO26 AD27
SB_HS AA24 AF4 DEFAULT DEFAULT

f
1

{34} PCIE4_IN1 GPP_RX1N AD27/GPIO27


W 23 AF3 AD28
{34} PCIE4_IP2 GPP_RX2P AD28/GPIO28 AD29 VCC3
{34} PCIE4_IN2 V24 GPP_RX2N AD29/GPIO29 AH2
W 24 AG2 AD30
{34} PCIE4_IP3 GPP_RX3P AD30/GPIO30

n y
W 25 AH3 AD31 PCLK4 PR17 8.2K/4
{34} PCIE4_IN3 GPP_RX3N AD31/GPIO31 -C_BE0
AA8 PR16 22p/4/NPO/50V/J
CBE0# -C_BE0 {20}
C AD5 -C_BE1 C
CBE1# -C_BE1 {20}

PCI INTERFACE
-C_BE2

o
CBE2# AD8 -C_BE2 {20} EMI ISSUE
AA10 -C_BE3
CBE3# -C_BE3 {20}
SB_HS/[12SP2-SA0504-01R_12SP2-SA0504-02R_12SP2-SA0504-03R] AE8 -FRAME
FRAME# -FRAME {20}
2

AB9 -DEVSEL
DEVSEL# -DEVSEL {20}
M23 AJ3 -IRDY BIOS after boot setting
{13} SBSRC_CLKP -IRDY {20}

C
2

PCIE_RCLKP/NB_LNK_CLKP IRDY# -TRDY


P23 AE7
{13} SBSRC_CLKN -TRDY {20} EC AOD-ACC

p
PCIE_RCLKN/NB_LNK_CLKN TRDY# PAR
PAR AC5 PAR {20}
U29 AF5 -STOP
NB_DISP_CLKP STOP# -PERR -STOP {20}
U28 NB_DISP_CLKN PERR# AE6 -PERR {20}

e o
AE4 -SERR
SERR# -SERR {20}
T26 AE11 -REQ0 LPC_CLK0 PR20 8.2K/4
NB_HT_CLKP REQ0# -REQ0 {20}
-REQ1

t
T27 NB_HT_CLKN REQ1#/GPIO40 AH5 -REQ1 {20}
AH4 -REQ2 LPC_CLK1 PR22 8.2K/4
REQ2#/CLK_REQ8#/GPIO41 -REQ2 {20}
V21 AC12 -REQ3

C
CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 -REQ3 {20}
T21 AD12 -GNT0

y
CPU_HT_CLKN GNT0# -GNT0 {20}
AJ5 -GNT1
GNT1#/GPO44 -GNT1 {20}
V23 SLT_GFX_CLKP GNT2#/GPO45 AH6

t
T23 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AB12 LPC_CLK0 LPC_CLK1

b
AB11 CLKRUN- Rev.A12
CLKRUN# -PLOCK
L29 GPP_CLK0P LOCK# AD7 -PLOCK {20}
PULL IMC CLKGEN

o
L28 GPP_CLK0N

a
AJ6 -INTA
INTE#/GPIO32 -INTB
-INTA {20} HIGH ENABLED ENABLED
N29 GPP_CLK1P INTF#/GPIO33 AG6 -INTB {20}
N28 AG4 -INTC AOD Extreme
GPP_CLK1N INTG#/GPIO34 -INTC {20}

g n
AJ4 -INTD PULL IMC CLKGEN
INTH#/GPIO35 -INTD {20}
M29 DISABLED DISABLED
GPP_CLK2P LOW

i
M28 GPP_CLK2N DEFAULT DEFAULT
T25

G Do
GPP_CLK3P LPC_CLK0
V25 H24
CLOCK GENERATOR
B GPP_CLK3N LPCCLK0 LPC_CLK1 B
LPCCLK1 H25
L24 J27 LAD0
GPP_CLK4P LAD0 LAD1 LAD0 {21}
L23 GPP_CLK4N LAD1
LAD2
J26
H29 LAD2 LAD1 {21}
LAD2 {21}
20mil 20mil
P25 H28 LAD3 PQ1 RTCVDD
LPC
GPP_CLK5P LAD3 -LFRAME LAD3 {21}
M25 GPP_CLK5N LFRAME# G28 -LFRAME {21} 3VSB_IO
J25 -LDRQ0 PR28 1K/4/1
LDRQ0# -LDRQ0 {21}
P29 AA18 PR0 8.2K/4
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 VCC3 {21} VBAT
P28 AB19 SERIRQ VBAT_2 RB 1K/4/1
GPP_CLK6N SERIRQ/GPIO48 SERIRQ {21}
BAT54C/SOT23/200mA PBC24 PBC25
Note: LDT_PG, LDT_STP# & LDT_RST# are OD
N26
N27
GPP_CLK7P
GPP_CLK7N
PR24 8.2K/4 VCC18
and require a PU to the CPU I/O rail. They are
20mil 0.1U/6/X7R/25V/K 1U/6/Y5V/10V/Z

ALLOW _LDTSTP/DMA_ACTIVE# G21 ALLOW_LDTSTOP {10}also in the S5 domain to prevent glitching at

1
T29 H21 -PROCHOT_CPU
GPP_CLK8P PROCHOT# -PROCHOT_CPU {6,27}
power up.
RTC_XI T28 K19 BAT CLR_CMOS
GPP_CLK8N LDT_PG CPU_PG_SB {6}
G22 -LDT_STOP BAT-SK/BK/P/S/D/SN RTCVDD
-LDT_STOP {6,10}
CPU

PR6 LDT_STP# -CPURST


LDT_RST# J24 -CPURST {6,10}
20M/4 L25 14M_25M_48M_OSC

2
RTC_XO CR2032 BAT PH/1*2/BK/2.54/VA/D
RTC_XI CR2032
32K_X1 C1 +
25MHZ_X1 L26 C2 RTC_XO CLR_CMOS
25M_X1 32K_X2
4

1 2 PX1 D2 RTC_CLK PR26 22/4 SHORT CLEAR CMOS


RTCCLK SUSCLK {21}
RTC

32.768K/12.5p/20ppm/TF38/35K/D B2 -INTR_ALERT PR27 100K/4/X


INTRUDER_ALERT# RTCVDD
PR7 1M/4 25MHZ_X2 L27 B1 RTCVDD OPEN NORMAL
3

25M_X2 VDDBT_RTC_G

PC13 PC14 PX2 SB950/BGA605/[10HB1-06B950-10R] PBC2 NOT ADD ICT FOR RTCVDD PIN
18P/4/NPO/50V/J 18P/4/NPO/50V/J 1 2 0.1U/6/X7R/25V/K
A A
25M/20p/30ppm/49US/20/D
3VDUAL_SB
PC15 PC16
PX1 22P/4/NPO/50V/J 22P/4/NPO/50V/J RTC_CLK PR90 8.2K/4/X

SHW/D0.64*5.08*6.74
CLKRUN- PR94 8.2K/4/X VCC3 Title
SB950 PCIE/PCI/CPU/LPC
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 14 of 35
5 4 3 2 1
5 4 3 2 1

SB_TEST2 PR29 8.2K/4


SB_TEST1 PR30 8.2K/4
SB_TEST0 PR31 8.2K/4

VCC3 U2D
{20} -PCIPME J2 PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC A10 USB48M {13}
-SUS_STAT PR32 8.2K/4 -RI K1
SMBCLK {25} -RI RI#/GEVENT22#
PR55 1K/4/1 D3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP G19 USB_RP PR54 11.8K/4/1
SMBDATA PR56 1K/4/1 F1
WD_PWRGD {21,29} -SLP_S3 SLP_S5- SLP_S3#
PR33 8.2K/4 H1
{21,29} SLP_S5- SLP_S5#

ACPI / WAKE UP EVENTS


GP80_SB R17 8.2K/4 PR69 0/4/SHT/X -PWRBTN F2
{21} -PSOUT PW R_BTN#

USB 1.1 USB MISC


D
3VDUAL_SB {29} SB_PWROK
-SUS_STAT
H5
G6
PW R_GOOD SB800 J10 D
SB_TEST2 SUS_STAT# USB_FSD1P/GPIO186
B3 TEST0 Part 4 of 5 USB_FSD1N H11
VRHOT PR86 8.2K/4/X SB_TEST1 C4
-RI PR34 8.2K/4 SB_TEST0 TEST1/TMS
F6 TEST2 USB_FSD0P/GPIO185 H9
SMBCLK1 PR57 2.2K/4/1 AD21 J8
{21} A20GATE GA20IN/GEVENT0# USB_FSD0N

l
SMBDATA1 PR58 2.2K/4/1 AE21
{21} -KBRST KBRST#/GEVENT1#
-PCIE_WAKE PR59 2.2K/4/1/X -LPCPME K2 B12 +USBP13
{21} -LPCPME LPC_PME#/GEVENT3# USB_HSD13P +USBP13 {22}
-PCIPME PR60 2.2K/4/1/X 3VDUAL R26 0/4 GP80_SB J29 A12 -USBP13
{21} GP80 LPC_SMI#/GEVENT23# USB_HSD13N -USBP13 {22}

a
-USBSMI PR76 8.2K/4/1 3VDUAL H2
PR68 22/4 GEVENT5# +USBP12
{26} -SYS_RST J1 SYS_RESET#/GEVENT19# USB_HSD12P F11 +USBP12 {22}

ti
SB_PWROK -PCIE_WAKE H6 E11 -USBP12
{18,19,32,34,35} -PCIE_WAKE W AKE#/GEVENT8# USB_HSD12N -USBP12 {22}
PC17 22P/4/N/50V/X F3
THERMTRIP_CPU_L IR_RX1/GEVENT20# +USBP11
{6,31} THERMTRIP_CPU_L J6 THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P E14 +USBP11 {35}
PBC4 PR67 0/4/X WD_PWRGD AC19 E12 -USBP11
{10,29} NB_PWROK NB_PW RGD USB_HSD11N -USBP11 {35}
100P/4/NPO/50V/J/X
-RSMRST G1 J12 +USBP10

n
{21} -RSMRST RSMRST# USB_HSD10P +USBP10 {35} 3VDUAL_SB
3VDUAL_SB PR91 20K/4/1/X -RSMRST J14 -USBP10
SMBCLK USB_HSD10N -USBP10 {35}
{34} PE4_PRSNT- AD19 CLK_REQ4#/SATA_IS0#/GPIO64
SMBDATA +USBP9 IMC_GPIO200

e
AA16 A13 PR61 2.2K/4/1
{19} PE2_PRSNT- CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P +USBP9 {25}
PBC3 PE1_PRSNT- AB21 B13 -USBP9
{19} PE1_PRSNT- PE0_PRSNT- SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N -USBP9 {25} IMC_GPIO199
2.2u/8/X5R/10V/K/X AC18 PR62 2.2K/4/1
{18} PE0_PRSNT- CLK_REQ0#/SATA_IS3#/GPIO60
PBC5 PBC6 AF20 D13 +USBP8

d
{19} PE3_PRSNT- SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P -USBP8 +USBP8 {25}
100P/4/NPO/50V/J/X 100P/4/NPO/50V/J/X AE19 C13
SATA_IS5#/FANIN3/GPIO59 USB_HSD8N -USBP8 {25}
SPKR AF19

i
{26} SPKR SPKR/GPIO66
SMBCLK AD22 G12 +USBP7 IMC_GPIO200 IMC_GPIO199
{8,9,13,27,31} SMBCLK SCL0/GPIO43 USB_HSD7P +USBP7 {22}

USB 2.0
AZ_BIT_CLK SMBDATA AE22 G14 -USBP7

f
{8,9,13,27,31} SMBDATA SDA0/GPIO47 USB_HSD7N -USBP7 {22}
{18,19,34} SMBCLK1 SMBCLK1 F5 ROM TYPE:
SMBDATA1 SCL1/GPIO227 +USBP6
{18,19,34} SMBDATA1 F4 SDA1/GPIO228 USB_HSD6P G16 +USBP6 {22}
PBC7 AH21 G18 -USBP6 H, H = Reserved
CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N -USBP6 {22}

n y
100P/4/NPO/50V/J/X AB18 CLK_REQ1#/FANOUT4/GPIO61 +USBP5 DEFAULT
E1 D16 H, L = SPI ROM

GPIO
IR_LED#/LLB#/GPIO184 USB_HSD5P +USBP5 {22}
C AJ21 C16 -USBP5 C
VCC3 SMARTVOLT2/SHUTDOW N#/GPIO51 USB_HSD5N -USBP5 {22}
DDR3_RST-

o
VCC3 PR38 8.2K/4 H4 DDR3_RST#/GEVENT7# L, H = LPC ROM
D5 B14 +USBP4
GBE_LED0/GPIO183 USB_HSD4P +USBP4 {22}
AZ_SDATA_OUT PR36 8.2K/4/X D7 A14 -USBP4 L, L = FWH ROM
GBE_LED1/GEVENT9# USB_HSD4N -USBP4 {22}
PR35 8.2K/4 G5 GBE_LED2/GEVENT10# +USBP3
K3 E18 +USBP3 {22}

C
GBE_STAT0/GEVENT11# USB_HSD3P -USBP3
Low: Performance Mode(D), {6} SB_IDLEEXIT- AA20 E16 -USBP3 {22}

p
CLK_REQG#/GPIO65/OSCIN USB_HSD3N
Up: Low Power Mode. +USBP2
USB_HSD2P J16 +USBP2 {22}
-AZ_RST PR37 8.2K/4 H3 J18 -USBP2
BLINK/USB_OC7#/GEVENT18# USB_HSD2N -USBP2 {22}

e o
{27} VRHOT D1 USB_OC6#/IR_TX1/GEVENT6#
Low: Disable PCI MEM boot(D), PR44 0/4/X E4 B17 +USBP1
{32} -USBSMI USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P +USBP1 {22}

USB OC
-USBP1

t
Up: Enable PCI MEM boot D4 USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N A17 -USBP1 {22}
E8 USB_OC3#/AC_PRES/TDO/GEVENT15#
F7 A16 +USBP0

C
{22} -USBOC_R1 USB_OC2#/TCK/GEVENT14# USB_HSD0P +USBP0 {22}
E7 B16 -USBP0

y
USB_OC1#/TDI/GEVENT13# USB_HSD0N -USBP0 {22}
{22} -USBOC_F1 F8 USB_OC0#/TRST#/GEVENT12#

b t
PR63 22/4 M3 D25 SCL2 PR52 8.2K/4 DDR15V
{23} AZ_BIT_CLK AZ_BITCLK SCL2/GPIO193 3VDUAL_SB
PR64 22/4 SDA2 PR53 8.2K/4

o
{23} AZ_SDATA_OUT N1 AZ_SDOUT SDA2/GPIO194 F23

a
{23} AZ_SDATA_IN0 L2 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 B26
M2 E26

HD AUDIO
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 PR50
M1 AZ_SDIN2/GPIO169 EC_PW M0/EC_TIMER0/GPIO197 F25

g n
M4 E22 8.2K/4/1
PR65 22/4 AZ_SDIN3/GPIO170 EC_PW M1/EC_TIMER1/GPIO198 IMC_GPIO199
{23} AZ_SYNC N2 AZ_SYNC EC_PW M2/EC_TIMER2/GPIO199 F22

i
PR66 22/4 P2 E21 IMC_GPIO200 2
{23} -AZ_RST AZ_RST# EC_PW M3/EC_TIMER3/GPIO200
3 CPU_TMS
CPU_TMS {6}
G24 IMC_TMS 1

G Do
PR39 8.2K/4 GBE_COL KSI_0/GPIO201
T1 GBE_COL KSI_1/GPIO202 G25
B PR40 8.2K/4 GBE_CRS PQ8 B
T4 GBE_CRS KSI_2/GPIO203 E28

SOT23
L6 E29 MMBT3904/SOT23/200mA/30
PR41 8.2K/4 GBE_MDIO GBE_MDCK KSI_3/GPIO204
3VDUAL L5 GBE_MDIO KSI_4/GPIO205 D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
U1 C29 DDR15V
GBE_RXD3 KSI_6/GPIO207
U3 GBE_RXD2 KSI_7/GPIO208 C28
T2

GBE LAN
GBE_RXD1
U2 GBE_RXD0 KSO_0/GPIO209 B28
T5 A27 IMC_TDO PR49
GBE_RXCTL/RXDV KSO_1/GPIO210

EMBEDDED CTRL
PR42 8.2K/4 GBE_RXERR V5 B27 8.2K/4/1
GBE_RXERR KSO_2/GPIO211 IMC_TMS
P5 GBE_TXCLK KSO_3/GPIO212 D26
M5 A26 IMC_TCK 2
GBE_TXD3 KSO_4/GPIO213 CPU_TCK
P9 GBE_TXD2 KSO_5/GPIO214 C26 3 CPU_TCK {6}
T7 A24 IMC_TCK 1
GBE_TXD1 KSO_6/GPIO215
P7 GBE_TXD0 KSO_7/GPIO216 B25
M7 A25 PQ7
GBE_TXCTL/TXEN KSO_8/GPIO217

SOT23
P4 D24 MMBT3904/SOT23/200mA/30
GBE_PHY_PD KSO_9/GPIO218
M9 GBE_PHY_RST# KSO_10/GPIO219 B24
PR43 8.2K/4 GBE_INTR V7 C24
3VDUAL GBE_PHY_INTR KSO_11/GPIO220 DDR15V
KSO_12/GPIO221 B23
E23 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 A23
E24 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223 D22
EMBEDDED CTRL
F21 SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 C22
G29 A22 PR47
FC_RST#/GPO160 KSO_16/GPIO225 8.2K/4/1
KSO_17/GPIO226 B22
D27 PS2KB_DAT/GPIO189
F28 PS2KB_CLK/GPIO190 2
F29 3 CPU_TDI
PS2M_DAT/GPIO191 IMC_TDO CPU_TDI {6}
E27 PS2M_CLK/GPIO192 1

A
PQ5 A

SOT23
SB950/BGA605/[10HB1-06B950-10R] MMBT3904/SOT23/200mA/30

Title
SB950 ACPI/USB/GPIO/AUDIO
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 15 of 35
5 4 3 2 1
5 4 3 2 1

U2B

SP_TX0P_C AH9
SB800 AH28
SP_TX0M_C SATA_TX0P FC_CLK
AJ9 SATA_TX0N Part 2 of 5 FC_FBCLKOUT AG28
FC_FBCLKIN AF26
SP_RX0M_C AJ8
SP_RX0P_C SATA_RX0N
PLACE SATA_CAL AH8 SATA_RX0P FC_OE#/GPIOD145 AF28
AG29
RES VERY CLOSE SP_TX1P_C AH10
FC_AVD#/GPIOD146
AG26
SP_TX1M_C SATA_TX1P FC_W E#/GPIOD148
TO BALL OF U600 AJ10 SATA_TX1N FC_CE1#/GPIOD149 AF27
FC_CE2#/GPIOD150 AE29
SP_RX1M_C AG10 AF29
SP_RX1P_C SATA_RX1N FC_INT1/GPIOD144
D
NOTE: AF10 SATA_RX1P FC_INT2/GPIOD147 AH27 D

R650 IS 1K 1% FOR 25MHz SP_TX2P_C AG12 AJ27


SP_TX2M_C SATA_TX2P FC_ADQ0/GPIOD128
AF12 AJ26
XTAL, 4.99K 1% FOR 100MHz SATA_TX2N FC_ADQ1/GPIOD129
AH25
FC_ADQ2/GPIOD130

l
GPIOD
INTERNAL CLOCK SP_RX2M_C AJ12 AH24
SP_RX2P_C SATA_RX2N FC_ADQ3/GPIOD131
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23

a
SP_TX3P_C AH14 AJ22
SP_TX3M_C SATA_TX3P FC_ADQ6/GPIOD134
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21

i
FC_ADQ8/GPIOD136 AF21
SP_RX3M_C AG14 AH22
SATA_RX3N FC_ADQ9/GPIOD137

t
SP_RX3P_C AF14 AJ23
SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
SP_TX4P_C AG17 AJ24
SP_TX4M_C SATA_TX4P FC_ADQ12/GPIOD140
AF17 AJ25

n
SATA_TX4N FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142 AG25
SP_RX4M_C AJ17 AH26
SP_RX4P_C SATA_RX4N FC_ADQ15/GPIOD143

e
AH17

SERIAL ATA
SATA_RX4P
SP_TX5P_C AJ18
SP_TX5M_C SATA_TX5P
AH18 W5

d
SATA_TX5N FANOUT0/GPIO52
FANOUT1/GPIO53 W6
SP_RX5M_C AH19 Y9

i
SP_RX5P_C SATA_RX5N FANOUT2/GPIO54
AJ19 SATA_RX5P
W7

f
FANIN0/GPIO56
FANIN1/GPIO57 V9
PR75 1K/4/1 SATA_CALRP AB14 W8
PR74 931/4/1 SATA_CALRN SATA_CALRP FANIN2/GPIO58
VCC_SB AA14 SATA_CALRN

n y
TEMPIN0/GPIO171 B6
TEMPIN1/GPIO172 A6
C -SATA_LED AD11 A5 C
{26} -SATA_LED SATA_ACT#/GPIO67 TEMPIN2/GPIO173

o
TEMPIN3/TALERT#/GPIO174 B5 SB_ALERT- {6}
TEMP_COMM C7

VIN0/GPIO175 A3
SATA_X1

HW MONITOR
TP5 AD16 B4

C
SATA_X1 VIN1/GPIO176
A4

p
VIN2/GPIO177
VIN3/GPIO178 C5
VIN4/GPIO179 A7
VIN5/GPIO180 B7

e o
VIN6/GBE_STAT3/GPIO181 B8
SATA_X2 AC16 A8
TP7 SATA_X2 VIN7/GBE_LED3/GPIO182

y t C
SB_SPI_DI PR70 22/4 SB_SPI_DI_R J5 G27
SB_SPI_DO PR71 22/4 SB_SPI_DO_R SPI_DI/GPIO164 NC1
E2 Y2
SPI ROM

SPI_DO/GPIO163 NC2 VCC3

t
SB_SPI_CLK PR72 22/4 SB_SPI_CLK_R K4 SPI_CLK/GPIO162

b
-SB_SPI_CS_ITE PR73 22/4 SB_SPI_CS- K9
{21} -SB_SPI_CS_ITE SPI_CS1#/GPIO165 M_BIOS
G2 ROM_RST#/GPIO161

a o
-ITE_SPI_CS 1 8 SPC23 0.1U/4/Y5V/16V/Z
{21} -ITE_SPI_CS CS# VDD
SB950/BGA605/[10HB1-06B950-10R]
SB_SPI_DI 2 7 -SPI_HOLD0
SO HOLD#

g n
-BIOS_WP 3 6 SB_SPI_CLK
W P# SCK

i
4 5 SB_SPI_DO
VSS SI

G Do
B 32M/SPI/SO8/200mil/S B

PLACE SATA AC COUPLING


B_BIOS
CAPS CLOSE TO SB850
-ITE_SPI_CS1 1 8
{21} -ITE_SPI_CS1 CS# VDD VCC3
SB_SPI_DI 2 7 -SPI_HOLD0
SO HOLD#
SATA3_0 SATA3_1 -BIOS_WP 3 6 SB_SPI_CLK
SATA2/7/BK/H/OP/VA/D/1/B W P# SCK
SATA2/7/BK/H/OP/VA/D/1/B 4 5 SB_SPI_DO
VSS SI
1 GND GND 7
SP_TX0P_C PC18 0.01u/4/X7R/25V/K SATA0TXPC 2 A+ SATA1RXPC PC30 0.01u/4/X7R/25V/K SP_RX1P_C
SP_TX0M_C PC19 0.01u/4/X7R/25V/K SATA0TXNC B+ 6 SATA1RXNC PC31 0.01u/4/X7R/25V/K SP_RX1M_C 32M/SPI/SO8/200mil/S
3 A- B- 5
4 GND GND 4
SP_RX0M_C PC20 0.01u/4/X7R/25V/K SATA0RXNC 5 B- SATA1TXNC PC32 0.01u/4/X7R/25V/K SP_TX1M_C
SP_RX0P_C PC21 0.01u/4/X7R/25V/K SATA0RXPC A- 3 SATA1TXPC PC33 0.01u/4/X7R/25V/K SP_TX1P_C
6 B+ A+ 2
7 GND GND 1

SATA3_2 SATA3_3
SATA2/7/BK/H/OP/VA/D/1/B VCC3
SATA2/7/BK/H/OP/VA/D/1/B
1 GND GND 7 -SPI_HOLD0 PR77 1K/4/1
SP_TX2P_C PC22 0.01u/4/X7R/25V/K SATA2TXPC 2 A+ SATA3RXPC PC34 0.01u/4/X7R/25V/K SP_RX3P_C
SP_TX2M_C PC23 0.01u/4/X7R/25V/K SATA2TXNC B+ 6 SATA3RXNC PC35 0.01u/4/X7R/25V/K SP_RX3M_C -BIOS_WP PR78 1K/4/1
3 A- B- 5 VCC_SB
4 GND GND 4
SP_RX2M_C PC24 0.01u/4/X7R/25V/K SATA2RXNC 5 B- SATA3TXNC PC36 0.01u/4/X7R/25V/K SP_TX3M_C -ITE_SPI_CS PR79 330/4
SP_RX2P_C PC25 0.01u/4/X7R/25V/K SATA2RXPC A- 3 SATA3TXPC PC37 0.01u/4/X7R/25V/K SP_TX3P_C PBC8 PBC9
6 B+ A+ 2
7 GND GND 1 1U/6/Y5V/10V/Z 0.1u/4/Y5V/16V/Z -ITE_SPI_CS1 PR80 330/4
A A

SATA3_4 SATA3_5
SATA2/7/BK/H/OP/VA/D/1/B VCC3
SATA2/7/BK/H/OP/VA/D/1/B
1 GND GND 7
SP_TX4P_C PC26 0.01u/4/X7R/25V/K SATA4TXPC 2 A+ SATA5RXPC PC38 0.01u/4/X7R/25V/K SP_RX5P_C PBC10 PBC11
SP_TX4M_C PC27 0.01u/4/X7R/25V/K SATA4TXNC B+ 6 SATA5RXNC PC39 0.01u/4/X7R/25V/K SP_RX5M_C 1U/6/Y5V/10V/Z 0.1u/4/Y5V/16V/Z
3 A- B- 5
4 GND GND 4
SP_RX4M_C PC28 0.01u/4/X7R/25V/K SATA4RXNC 5 B- SATA5TXNC PC40 0.01u/4/X7R/25V/K SP_TX5M_C Title
A- 3
SP_RX4P_C PC29 0.01u/4/X7R/25V/K SATA4RXPC 6 B+
7 GND GND 1
A+ 2
SATA5TXPC PC41 0.01u/4/X7R/25V/K SP_TX5P_C
SB950 SATA/IDE/HWM/SPI
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 16 of 35
5 4 3 2 1
5 4 3 2 1

PLACE ALL THE DECOUPLING CAPS ON VCC_SB


THIS SHEET CLOSE TO SB AS POSSIBLE.
SPC19 PC44 PBC17
0.1U/4/Y5V/16V/Z 1U/6/Y5V/10V/Z 10u/6/X5R/6.3V/M

VCC3 U2C U2E


50mA SB800 Part 3 of 5 1.125A
D AH1
V6
VDDIO_33_PCIGP_1 VDDCR_11_1 N13
R15 Y14
SB800 AJ2
D
VDDIO_33_PCIGP_2 VDDCR_11_2 VSSIO_SATA_1 VSS_1
Y19 VDDIO_33_PCIGP_3 VDDCR_11_3 N17 Y16 VSSIO_SATA_2 VSS_2 A28

CORE S0
AE5 U13 SPC20 SPC21 SPC22 AB16 A2
PBC13 SPC27 SPC1 SPC2 SPC3 SPC4 VDDIO_33_PCIGP_4 VDDCR_11_4 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z 1U/6/Y5V/10V/Z VSSIO_SATA_3 VSS_3
AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17 AC14 VSSIO_SATA_4 VSS_4 E5

l
10u/6/X5R/6.3V/M 1U/6/Y5V/10V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z AA2 V12 AE12 D23
VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_5 VSS_5

PCI/GPIO I/O
AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 AE14 VSSIO_SATA_6 VSS_6 E25
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W 12 AF9 VSSIO_SATA_7 VSS_7 E6

a
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W 18 AF11 VSSIO_SATA_8 VSS_8 F24
AA9 VDDIO_33_PCIGP_10 AF13 VSSIO_SATA_9 VSS_9 N15

i
AF7 VDDIO_33_PCIGP_11 50mA AF16 VSSIO_SATA_10 VSS_10 R13
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 VCC_SB AG8 VSSIO_SATA_11 VSS_11 R17

t
VDDAN_11_CLK_2 K29 AH7 VSSIO_SATA_12 VSS_12 T10
VDDAN_11_CLK_3 J28 AH11 VSSIO_SATA_13 VSS_13 P10
K26 SPC25 AH13 V11
VDDAN_11_CLK_4 VSSIO_SATA_14 VSS_14

CLKGEN I/O
J21 0.1U/4/Y5V/16V/Z AH16 U15

n
VDDAN_11_CLK_5 VSSIO_SATA_15 VSS_15
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 AJ7 VSSIO_SATA_16 VSS_16 M18

FLASH I/O
AE25 VDDIO_18_FC_2 VDDAN_11_CLK_7 K21 AJ11 VSSIO_SATA_17 VSS_17 V19

e
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 AJ13 VSSIO_SATA_18 VSS_18 M11
AC22 VDDIO_18_FC_4 AJ16 VSSIO_SATA_19 VSS_19 L12
VSS_20 L18
V1 A9 J7

d
VDDRF_GBE_S VSSIO_USB_1 VSS_21
B10 P3
POWER M10 30mA K11
VSSIO_USB_2 VSS_22
V4

i
VDDIO_33_GBE_S 3VDUAL_SB VSSIO_USB_3 VSS_23
35mA B9 VSSIO_USB_4 VSS_24 AD6
AE28 D10 AD4

f
VCC3

GBE LAN
VCC_SB VDDPL_33_PCIE VSSIO_USB_5 VSS_25
D12 VSSIO_USB_6 VSS_26 AB7
1.2A D14 VSSIO_USB_7 VSS_27 AC9

PCI EXPRESS
U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 VCC11_DUAL 172mA D17 VSSIO_USB_8 VSS_28 V8

n y
V22 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 L9 E9 VSSIO_USB_9 VSS_29 W9
V26 VDDAN_11_PCIE_3 F9 VSSIO_USB_10 VSS_30 W 10
C PBC0 SPC26 SPC5 SPC6 SPC24 V27 F12 AJ28 C
VDDAN_11_PCIE_4 VSSIO_USB_11 VSS_31

o
10u/6/X5R/6.3V/M 1U/6/Y5V/10V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z V28 M6 3VDUAL_SB 30mA F14 B29
VDDAN_11_PCIE_5 VDDIO_GBE_S_1 VSSIO_USB_12 VSS_32
V29 VDDAN_11_PCIE_6 VDDIO_GBE_S_2 P8 F16 VSSIO_USB_13 VSS_33 U4
W 22 VDDAN_11_PCIE_7 C9 VSSIO_USB_14 VSS_34 Y18
W 26 VDDAN_11_PCIE_8 G11 VSSIO_USB_15 VSS_35 Y10
F18 Y12

GROUND
C
VSSIO_USB_16 VSS_36
D9 Y11

p
3VDUAL_SB VSSIO_USB_17 VSS_37
20mA H12 VSSIO_USB_18 VSS_38 AA11
VCC_SB VCC3 AD14 30mA H14 AA12
VDDPL_33_SATA VSSIO_USB_19 VSS_39
1A VDDIO_33_S_1 A21 H16 VSSIO_USB_20 VSS_40 G4

e o
AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 H18 VSSIO_USB_21 VSS_41 J4
AF18 B21 J11 G8

SERIAL ATA
VDDAN_11_SATA_4 VDDIO_33_S_3 SPC0 PBC16 SPC16 SPC17 SPC18 VSSIO_USB_22 VSS_42

t
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10 J19 VSSIO_USB_23 VSS_43 G9

3.3V_S5 I/O
PBC27 SPC7 SPC8 SPBC1 AG19 L10 1U/6/Y5V/10V/Z 10u/6/X5R/6.3V/M 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z K12 M12
1U/6/Y5V/10V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z 10u/6/X5R/6.3V/M VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_24 VSS_44
AE18 J9 K14 AF25

C
VDDAN_11_SATA_5 VDDIO_33_S_6 VSSIO_USB_25 VSS_45
AD18 T6 K16 H7

y
VDDAN_11_SATA_6 VDDIO_33_S_7 VSSIO_USB_26 VSS_46
AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 K18 VSSIO_USB_27 VSS_47 AH29
H19 VSSIO_USB_28 VSS_48 V10

t
VSS_49 P6

b
3VDUAL_SB N4
VSS_50

CORE S5
300mA VDDCR_11_S_1 F26 VCC11_DUAL 172mA Y4 EFUSE VSS_51 L4

o
A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26 VSS_52 L8

a
A19 VDDAN_33_USB_S_2 D8 VSSAN_HW M
A20 VDDAN_33_USB_S_3 VDDIO_AZ_S M8 3VDUAL_SB 15mA
PBC14 PBC29 PBC28 SPC9 SPC10 SPC11 B18 M19 M20
VDDAN_33_USB_S_4 VSSXL VSSPL_SYS

g n
10u/6/X5R/6.3V/M 1U/6/Y5V/10V/Z 1U/6/Y5V/10V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z B19 A11 VCC11_DUAL 200mA
VDDAN_33_USB_S_5 VDDCR_11_USB_S_1
B20 B11

USB I/O
VDDAN_33_USB_S_6 VDDCR_11_USB_S_2

i
C18 VDDAN_33_USB_S_7 P21 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H23
C20 VDDAN_33_USB_S_8 P20 VSSIO_PCIECLK_2 VSSIO_PCIECLK_15 H26
D18 M21 35mA M22 AA21

G Do
VDDAN_33_USB_S_9 VDDPL_33_SYS VCC3 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16
D19 VDDAN_33_USB_S_10 M24 VSSIO_PCIECLK_4 VSSIO_PCIECLK_17 AA23
B B
D20 VDDAN_33_USB_S_11 VDDPL_11_SYS_S L22 150mA VCC11_DUAL M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23
E19 VDDAN_33_USB_S_12 P22 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19 AD23

PLL
VDDPL_33_USB_S F19 15mA 3VDUAL_SB P24 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AA26
200mA P26 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 AC26
VCC11_DUAL C11 VDDAN_11_USB_S_1 VDDAN_33_HW M_S D6 10mA T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20
D11 VDDAN_11_USB_S_2 T22 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 W 21
VDDXL_33_S L20 20mA T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W 20
V20 VSSIO_PCIECLK_12 VSSIO_PCIECLK_25 AE26
J23 VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 L21
SB950/BGA605/[10HB1-06B950-10R] K20
VSSIO_PCIECLK_27
Part 5 of 5
VCC11_DUAL SB950/BGA605/[10HB1-06B950-10R]

PBC15 PBC31 SPC12 SPC13 SPC14


10u/6/X5R/6.3V/M 1U/6/Y5V/10V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z 0.1U/4/Y5V/16V/Z

VCC3 VCC_SB

PBC32 SPC28
1U/6/Y5V/10V/Z 1U/6/Y5V/10V/Z

A A

3VDUAL_SB

PBC34 PBC12
1U/6/Y5V/10V/Z 0.1U/4/Y5V/16V/Z
Title
ATI SB700 POWER & GND
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 17 of 35
5 4 3 2 1
8 7 6 5 4 3 2 1

EXP_A_RXP[0..15] EXP_A_TXP[0..15]
EXP_A_RXP[0..15] {11} EXP_A_TXP[0..15] {11}
+12V X16_+12V EXP_A_TXP0 C1644 0.1u/4/X7R/16V/K EXP_A_TXP0C
EXP_A_RXN[0..15] EXP_A_TXN[0..15] EXP_A_TXN0 C1645 0.1u/4/X7R/16V/K EXP_A_TXN0C
EXP_A_RXN[0..15] {11} EXP_A_TXN[0..15] {11} EXP_A_TXP1 EXP_A_TXP1C
1 2 C1646 0.1u/4/X7R/16V/K
3 4 EXP_A_TXN1 C1647 0.1u/4/X7R/16V/K EXP_A_TXN1C
Lay 誤 PCIe slot 旁 X16_+12V 5 6 EXP_A_TXP2 C1648 0.1u/4/X7R/16V/K EXP_A_TXP2C
X16_+12V 3GIO_*16 7 8 EXP_A_TXN2 C1649 0.1u/4/X7R/16V/K EXP_A_TXN2C
+12V_ISEN R16M PCIEX16 RN21 0/8P4R/0402/SHT/X EXP_A_TXP3 C1650 0.1u/4/X7R/16V/K EXP_A_TXP3C
A B1 A1 1 2 EXP_A_TXN3 C1651 0.1u/4/X7R/16V/K EXP_A_TXN3C
12V PRSNT1* EXP_A_TXP4 C1652 0.1u/4/X7R/16V/K EXP_A_TXP4C
S B2 12V 12V A2 3 4
0/6/SHT-10/MASK/X
K B3 A3 5 6 EXP_A_TXN4 C1653 0.1u/4/X7R/16V/K EXP_A_TXN4C
R61 0/4/SHT/X B4 RSVD 12V R62 0/4/SHT/X EXP_A_TXP5 C1654 0.1u/4/X7R/16V/K EXP_A_TXP5C
- GND GND A4 7 8
SMBCLK1 B5 A5 RN22 0/8P4R/0402/SHT/X EXP_A_TXN5 C1655 0.1u/4/X7R/16V/K EXP_A_TXN5C
{15,19,34} SMBCLK1 1 SMBDATA1 B6
SMCLK JTAG2
A6 1 2 EXP_A_TXP6 C1656 0.1u/4/X7R/16V/K EXP_A_TXP6C
D {15,19,34} SMBDATA1 D
0 B7
SMDAT JTAG3
A7 3 4 EXP_A_TXN6 C1657 0.1u/4/X7R/16V/K EXP_A_TXN6C
GND JTAG4 EXP_A_TXP7 C1658 0.1u/4/X7R/16V/K EXP_A_TXP7C
VCC3 B8 3.3V JTAG5 A8 5 6
B9 A9 7 8 EXP_A_TXN7 C1659 0.1u/4/X7R/16V/K EXP_A_TXN7C
JTAG1 3.3V VCC3
3VDUAL B10 A10 EXP_A_TXP8 C1660 0.1u/4/X7R/16V/K EXP_A_TXP8C
3.3VAUX 3.3V

l
-PCIE_WAKE B11 A11 R3 10/4 RN23 0/8P4R/4/X EXP_A_TXN8 C1661 0.1u/4/X7R/16V/K EXP_A_TXN8C
{15,19,32,34,35} -PCIE_WAKE W AKE* PW RGD -A_RST {14,21}
KEY EXP_A_TXP9 C1662 0.1u/4/X7R/16V/K EXP_A_TXP9C
VCC3 EXP_A_TXN9 C1663 0.1u/4/X7R/16V/K EXP_A_TXN9C

a
B12 A12 EXP_A_TXP10 C1664 0.1u/4/X7R/16V/K EXP_A_TXP10C
RSVD GND EXP_A_TXN10 C1665 0.1u/4/X7R/16V/K EXP_A_TXN10C
B13 GND REFCLK+ A13 SRCCLK_3GIO_A {13}

i
R2400 EXP_A_TXP0C B14 A14 EXP_A_TXP11 C1666 0.1u/4/X7R/16V/K EXP_A_TXP11C
HSOP0 REFCLK- -SRCCLK_3GIO_A {13}
8.2K/4/1 EXP_A_TXN0C B15 A15 EXP_A_TXN11 C1667 0.1u/4/X7R/16V/K EXP_A_TXN11C
HSON0 GND

t
B16 A16 EXP_A_RXP0 EXP_A_TXP12 C1668 0.1u/4/X7R/16V/K EXP_A_TXP12C
PE0_PRSNT- GND HSIP0 EXP_A_RXN0 EXP_A_TXN12 C1669 0.1u/4/X7R/16V/K EXP_A_TXN12C
{15} PE0_PRSNT- B17 PRSNT2* HSIN0 A17
B18 A18 EXP_A_TXP13 C1670 0.1u/4/X7R/16V/K EXP_A_TXP13C
GND GND EXP_A_TXN13 C1671 0.1u/4/X7R/16V/K EXP_A_TXN13C

n
EXP_A_TXP14 C1672 0.1u/4/X7R/16V/K EXP_A_TXP14C
EXP_A_TXP1C B19 A19 EXP_A_TXN14 C1673 0.1u/4/X7R/16V/K EXP_A_TXN14C
EXP_A_TXN1C HSOP1 RSVD EXP_A_TXP15 EXP_A_TXP15C

e
B20 A20 C1674 0.1u/4/X7R/16V/K
HSON1 GND EXP_A_RXP1 EXP_A_TXN15 C1675 0.1u/4/X7R/16V/K EXP_A_TXN15C
B21 GND HSIP1 A21
-A_RST B22 A22 EXP_A_RXN1
EXP_A_TXP2C GND HSIN1
B23 A23

d
EXP_A_TXN2C HSOP2 GND
B24 HSON2 GND A24
B25 A25 EXP_A_RXP2

i
C1643 GND HSIP2 EXP_A_RXN2
B26 GND HSIN2 A26
100P/4/N/50V/X EXP_A_TXP3C B27 A27

f
EXP_A_TXN3C HSOP3 GND
B28 HSON3 GND A28
B29 A29 EXP_A_RXP3
GND HSIP3 EXP_A_RXN3
B30 RSVD HSIN3 A30

n y
PE0_PRSNT- B31 A31
PRSNT2* GND
B32 GND RSVD A32
C C
EXP_A_TXP4C

o
B33 HSOP4 RSVD A33
EXP_A_TXN4C B34 A34
HSON4 GND EXP_A_RXP4
B35 GND HSIP4 A35
B36 A36 EXP_A_RXN4
EXP_A_TXP5C GND HSIN4
B37 A37

C
EXP_A_TXN5C HSOP5 GND
B38 A38

p
HSON5 GND EXP_A_RXP5
B39 GND HSIP5 A39
B40 A40 EXP_A_RXN5
EXP_A_TXP6C GND HSIN5
B41 HSOP6 GND A41

e o
EXP_A_TXN6C B42 A42
HSON6 GND EXP_A_RXP6
B43 GND HSIP6 A43
EXP_A_RXN6

t
B44 GND HSIN6 A44
EXP_A_TXP7C B45 A45
EXP_A_TXN7C HSOP7 GND
B46 A46

C
HSON7 GND EXP_A_RXP7
B47 A47

y
PE0_PRSNT- GND HSIP7 EXP_A_RXN7
B48 PRSNT2* HSIN7 A48
B49 GND GND A49

b t
EXP_A_TXP8C

o
B50 HSOP8 RSVD A50

a
EXP_A_TXN8C B51 A51
HSON8 GND EXP_A_RXP8
B52 GND HSIP8 A52
B53 A53 EXP_A_RXN8
GND HSIN8

n
EXP_A_TXP9C

g
B54 HSOP9 GND A54
EXP_A_TXN9C B55 A55
HSON9 GND

i
B56 A56 EXP_A_RXP9
GND HSIP9 EXP_A_RXN9
B57 GND HSIN9 A57
EXP_A_TXP10C B58 A58

G Do
EXP_A_TXN10C HSOP10 GND
B59 HSON10 GND A59
B EXP_A_RXP10 B
B60 GND HSIP10 A60
B61 A61 EXP_A_RXN10
EXP_A_TXP11C GND HSIN10
B62 HSOP11 GND A62
EXP_A_TXN11C B63 A63
HSON11 GND EXP_A_RXP11
B64 GND HSIP11 A64
VCC3 B65 A65 EXP_A_RXN11
EXP_A_TXP12C GND HSIN11
B66 HSOP12 GND A66
EXP_A_TXN12C B67 A67
HSON12 GND EXP_A_RXP12
B68 GND HSIP12 A68
1 B69 A69 EXP_A_RXN12
+ EC3 EXP_A_TXP13C GND HSIN12
B70 HSOP13 GND A70
560u/FP/D/6.3V/69/A/11m EXP_A_TXN13C B71 A71
HSON13 GND EXP_A_RXP13
B72 GND HSIP13 A72
B73 A73 EXP_A_RXN13
EXP_A_TXP14C GND HSIN13
B74 HSOP14 GND A74
EXP_A_TXN14C B75 A75
HSON14 GND EXP_A_RXP14
B76 GND HSIP14 A76
B77 A77 EXP_A_RXN14
EXP_A_TXP15C GND HSIN14
B78 HSOP15 GND A78
EXP_A_TXN15C B79 A79
+12V HSON15 GND EXP_A_RXP15
B80 GND HSIP15 A80
PE0_PRSNT- B81 A81 EXP_A_RXN15
PRSNT2* HSIN15
B82 RSVD GND A82

BC834
0.1u/4/X7R/16V/K/X

PCI-E/16X-164P/BK/LONG DOUBLE
A A

+12V VCC3 3VDUAL

1
+ EC172 BC836 BC838 BC839 BC837 BC840 Title
270u/FP/D/16V/8C/A/10m 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K
PCI EXPRESS X 16 ,X1
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 18 of 35
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

3GIO_X1 +12V
PCIEX1_1

l
+12V

B1 12V PRSNT1* A1

a
B2 12V 12V A2
B3 RSVD 12V A3

ti
R63 0/4/SHT/X B4 A4 R64 0/4/SHT/X
SMBCLK1 GND GND
{15,18,34} SMBCLK1 B5 SMCLK JTAG2 A5
SMBDATA1 B6 A6
{15,18,34} SMBDATA1 SMDAT JTAG3
B7 GND JTAG4 A7
VCC3 B8 3.3V JYAG5 A8
B9 A9

n
JTAG1 3.3V VCC3
PCIE_RST- 3VDUAL B10 A10
-PCIE_WAKE 3.3VAUX 3.3V PCIE_RST-
{15,18,32,34,35} -PCIE_WAKE B11 W AKE* PW RGD A11 PCIE_RST- {21,32,35}

e
KEY
C1746 B12 A12
100P/4/N/50V/X RVSD GND
B13 A13

d
GND REFCLK+ PCIE1_CLK {13}
{11} PCIE1_OP B14 HSOP0 REFCLK- A14 -PCIE1_CLK {13}
B15 A15

i
{11} PCIE1_ON HSON0 GND
B16 GND HSIP0 A16 PCIE1_IP {11}
PE1_PRSNT- B17 A17

f
{15} PE1_PRSNT- PRSNT2* HSIN0 PCIE1_IN {11}
B18 GND GND A18
VCC3 R35 8.2K/4/1

n y
PCI-E/1X-36P/BK/OL
C C

o
3GIO_X1 +12V
PE0_PRSNT- +12V PCIEX1_2

B1 A1

C
12V PRSNT1*
B2 A2

p
12V 12V
B3 RSVD 12V A3
R71 0/4/SHT/X B4 A4 R73 0/4/SHT/X
SMBCLK1 GND GND
{15,18,34} SMBCLK1 B5 SMCLK JTAG2 A5

e o
SMBDATA1 B6 A6
{15,18,34} SMBDATA1 SMDAT JTAG3
B7 GND JTAG4 A7

t
VCC3 B8 3.3V JYAG5 A8
B9 JTAG1 3.3V A9 VCC3
B10 A10

C
3VDUAL 3.3VAUX 3.3V
-PCIE_WAKE B11 A11 PCIE_RST-

y
{15,18,32,34,35} -PCIE_WAKE W AKE* PW RGD PCIE_RST- {21,32,35}
KEY

t
B12 RVSD GND A12

b
B13 GND REFCLK+ A13 PCIE2_CLK {13}
{11} PCIE2_OP B14 HSOP0 REFCLK- A14 -PCIE2_CLK {13}

o
{11} PCIE2_ON B15 HSON0 GND A15
+12V

a
3GIO_X1 B16 GND HSIP0 A16 PCIE2_IP {11}
PE0_PRSNT- +12V PCIEX1_3 PCIE_RST- R41 8.2K/4/1 PE2_PRSNT- B17 A17
VCC3 PRSNT2* HSIN0 PCIE2_IN {11}
B18 GND GND A18

g n
B1 12V PRSNT1* A1 {15} PE2_PRSNT-
B2 12V 12V A2

i
B3 A3 C1752
R3199 0/4/SHT/X B4 RSVD 12V
GND GND A4 R3200 0/4/SHT/X 100P/4/N/50V/X PCI-E/1X-36P/BK/OL
SMBCLK1 B5 A5

G Do
{15,18,34} SMBCLK1 SMCLK JTAG2
SMBDATA1 B6 A6
B {15,18,34} SMBDATA1 SMDAT JTAG3 PCIE_RST- B
B7 GND JTAG4 A7
VCC3 B8 3.3V JYAG5 A8
B9 JTAG1 3.3V A9 VCC3
3VDUAL B10 3.3VAUX 3.3V A10
-PCIE_WAKE B11 A11 PCIE_RST- C1753
{15,18,32,34,35} -PCIE_WAKE W AKE* PW RGD PCIE_RST- {21,32,35}
100P/4/N/50V/X
KEY
B12 RVSD GND A12
B13 GND REFCLK+ A13 PCIE3_CLK {13}
{11} PCIE5_OP B14 HSOP0 REFCLK- A14 -PCIE3_CLK {13}
{11} PCIE5_ON B15 HSON0 GND A15
B16 GND HSIP0 A16 PCIE5_IP {11}
R3201 8.2K/4/1 PE3_PRSNT- B17 A17
VCC3 PRSNT2* HSIN0 PCIE5_IN {11}
B18 GND GND A18
{15} PE3_PRSNT-

PCI-E/1X-36P/BK/OL

A A

+12V VCC3 3VDUAL +12V VCC3

1 1
BC841 BC842 BC843 BC844 BC845 BC846 BC847 BC848 + EC173 + EC4
0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 270u/FP/D/16V/8C/A/10m 560u/FP/D/6.3V/69/A/11m Title
PCI_E x4 ,PCI_E x1 SLOT 2,3 ,Switch
Size Document Number Rev
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 19 of 35
8 7 6 5 4 3 2 1
5 4 3 2 1

AD[0..31]
PCI SLOT 1,2 {14} AD[0..31]

VCC3 VCC3 VCC3 VCC3

VCC -12V
PCI SLOT2 +12V VCC VCC -12V
PCI SLOT1 +12V VCC

PCI2 PCI1
B1 -12V TRST A1 B1 -12V TRST A1
D B2 TCK +12V A2 B2 TCK +12V A2 D
B3 GND TMS A3 B3 GND TMS A3
B4 TDO TDI A4 B4 TDO TDI A4
B5 +5V +5V A5 B5 +5V +5V A5
B6 +5V INTA A6 -INTA {14} B6 +5V INTA A6 -INTB {14}

l
{14} -INTB B7 INTB INTC A7 -INTC {14} {14} -INTC B7 INTB INTC A7 -INTD {14}
{14} -INTD B8 INTD +5V A8 {14} -INTA B8 INTD +5V A8
B9 PRSNT1 RESERVED A9 B9 PRSNT1 RESERVED A9

a
B10 RESERVED +5V A10 B10 RESERVED +5V A10
B11 PRSNT2 RESERVED A11 B11 PRSNT2 RESERVED A11

i
B12 GND GND A12 B12 GND GND A12
B13 GND GND A13 B13 GND GND A13

t
B14 RESERVED 3.3V_AUX A14 B14 RESERVED 3.3V_AUX A14
3VDUAL 3VDUAL
B15 GND RST A15 -PPCIRST {14}
B15 GND RST A15 -PPCIRST {14}
{14} PCICLK1 B16 CLK +5V A16 {14} PCICLK2 B16 CLK +5V A16
B17 A17 B17 A17

n
GND GNT -GNT0 {14} GND GNT -GNT1 {14}
{14} -REQ0 B18 REQ GND A18 {14} -REQ1
B18 REQ GND A18
B19 +5V PME A19 -PCIPME {15} B19 +5V PME A19 -PCIPME {15}
AD31 AD30 AD31 AD30

e
B20 AD31 AD30 A20 B20 AD31 AD30 A20
AD29 B21 A21 AD29 B21 A21
AD29 +3.3V AD28 AD29 +3.3V AD28
B22 GND AD28 A22 B22 GND AD28 A22
AD27 B23 A23 AD26 AD27 B23 A23 AD26

d
AD25 AD27 AD26 AD25 AD27 AD26
B24 AD25 GND A24 B24 AD25 GND A24
B25 A25 AD24 B25 A25 AD24

i
+3.3V AD24 AD22 +3.3V AD24 AD23
{14} -C_BE3 B26 C/BE3 IDSEL A26 {14} -C_BE3 B26 C/BE3 IDSEL A26
AD23 B27 A27 AD23 B27 A27

f
AD23 +3.3V AD22 AD23 +3.3V AD22
B28 GND AD22 A28 B28 GND AD22 A28
AD21 B29 A29 AD20 AD21 B29 A29 AD20
AD19 AD21 AD20 AD19 AD21 AD20
B30 AD19 GND A30 B30 AD19 GND A30

n y
B31 A31 AD18 B31 A31 AD18
AD17 +3.3V AD18 AD16 AD17 +3.3V AD18 AD16
B32 AD17 AD16 A32 B32 AD17 AD16 A32
C B33 A33 B33 A33 C
{14} -C_BE2 C/BE2 +3.3V {14} -C_BE2 C/BE2 +3.3V

o
B34 GND FRAME A34 -FRAME {14} B34 GND FRAME A34 -FRAME {14}
{14} -IRDY B35 IRDY GND A35 {14} -IRDY B35 IRDY GND A35
B36 +3.3V TRDY A36 -TRDY {14} B36 +3.3V TRDY A36 -TRDY {14}
B37 DEVSEL GND A37 {14} -DEVSEL B37 DEVSEL GND A37
{14} -DEVSEL
B38 A38 -STOP {14} B38 A38 -STOP {14}

C
-PLOCK GND STOP -PLOCK GND STOP
{14} -PLOCK B39 A39 B39 A39

p
LOCK +3.3V LOCK +3.3V
{14} -PERR B40 PERR SDONE A40 {14} -PERR B40 PERR SDONE A40
B41 +3.3V SBO A41 B41 +3.3V SBO A41
{14} -SERR B42 SERR GND A42 {14} -SERR B42 SERR GND A42

e o
B43 +3.3V PAR A43 PAR {14} B43 +3.3V PAR A43 PAR {14}
B44 A44 AD15 B44 A44 AD15
{14} -C_BE1 C/BE1 AD15 {14} -C_BE1 C/BE1 AD15
AD14 AD14

t
B45 AD14 +3.3V A45 B45 AD14 +3.3V A45
B46 A46 AD13 B46 A46 AD13
AD12 GND AD13 AD11 AD12 GND AD13 AD11
B47 A47 B47 A47

C
AD10 AD12 AD11 AD10 AD12 AD11
B48 A48 B48 A48

y
AD10 GND AD9 AD10 GND AD9
B49 GND AD9 A49 B49 GND AD9 A49

b t
AD8 B52 A52 AD8 B52 A52
AD8 C/BE0 -C_BE0 {14} AD8 C/BE0 -C_BE0 {14}
AD7 B53 A53 AD7 B53 A53
AD7 +3.3V AD6 AD7 +3.3V AD6

o
B54 +3.3V AD6 A54 B54 +3.3V AD6 A54

a
AD5 B55 A55 AD4 AD5 B55 A55 AD4
AD3 AD5 AD4 AD3 AD5 AD4
B56 AD3 GND A56 B56 AD3 GND A56
B57 A57 AD2 B57 A57 AD2
GND AD2 GND AD2

n
AD1 AD0

g
B58 A58 AD1 B58 A58 AD0
AD1 AD0 AD1 AD0
B59 +5V +5V A59 B59 +5V +5V A59

i
-ACK64 B60 A60 -REQ64 -ACK64 B60 A60 -REQ64
ACK64 REQ64 ACK64 REQ64
B61 +5V +5V A61 B61 +5V +5V A61
B62 A62 B62 A62

G Do
+5V +5V +5V +5V
B PCI/120/P/BK/VA PCI/120/P/BK/VA B
-PPCIRST IDSEL[AD22], IDSEL[AD23],
C1745
GNT/REQ[0], GNT/REQ[1],
100P/4/N/50V/X INT[A] INT[B]
PCICLK1 BC861 10P/4/N/50V/X

PCICLK2 BC862 10P/4/N/50V/X

VCC3 VCC
-12V VCC3

BC869 0.1u/4/X7R/16V/K EC11 560u/FP/D/6.3V/69/A/11m -REQ64 R138 8.2K/4


1

-ACK64 R134 8.2K/4


+

BC870 0.1u/4/X7R/16V/K/X BC865 0.1u/4/X7R/16V/K/X


BC874 BC875
BC871 0.1u/4/X7R/16V/K/X BC866 0.1u/4/X7R/16V/K/X 0.1u/4/X7R/16V/K/X 0.1u/4/X7R/16V/K/X
-STOP RN257 1 2 8.2K/8P4R/4
BC872 0.1u/4/X7R/16V/K/X BC867 0.1u/4/X7R/16V/K/X -PLOCK 3 4
-PERR 5 6
BC873 0.1u/4/X7R/16V/K/X BC868 0.1u/4/X7R/16V/K/X -SERR 7 8

BC878 0.1u/4/X7R/16V/K/X BC880 0.1u/4/X7R/16V/K -FRAME RN258 1 2 8.2K/8P4R/4


-IRDY 3 4
BC882 0.1u/4/X7R/16V/K BC881 0.1u/4/X7R/16V/K/X -TRDY 5 6
-DEVSEL 7 8
BC883 0.1u/4/X7R/16V/K
+12V -INTA RN259 1 2 8.2K/8P4R/4
BC884 0.1u/4/X7R/16V/K -INTC 3 4
A A
-INTB 5 6
EC13 560u/FP/D/6.3V/69/A/11m -INTD 7 8
1
+

BC863 BC864 BC877


3VDUAL 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K 0.1u/4/X7R/16V/K/X
-GNT1
{14} -GNT1
C1743 0.1u/4/X7R/16V/K/X -GNT0
{14} -GNT0
C1744 0.1u/4/X7R/16V/K/X -REQ3 RN261 1 2 8.2K/8P4R/4 Title
{14} -REQ3 -REQ2 3 4
C1747 0.1u/4/X7R/16V/K/X
{14} -REQ2
-REQ1 5 6
PCI SLOT 1,2
{14} -REQ1
-REQ0 7 8 Size Document Number Rev
{14} -REQ0
Custom GA-970A-D3P 1.0
Date: Monday, May 06, 2013 Sheet 20 of 35
5 4 3 2 1
8 7 6 5 4 3 2 1

DR177 8.2K/4/1 R108 8.2K/4/1/X USB_SEL R107 8.2K/4/1 VCC3


R19 8.2K/4/1/X A20GATE MB ID loadline Function JP2 RTS1- loadline_75
R7 8.2K/4/X -SIOIDERST {25} RTS1-
VCC3 {25} DSR1-
R22 8.2K/4/1 PCIE_RST- JP3 TXD1 DR184 8.2K/4/1 請分 MB ID
NB請
R15 8.2K/4/1/X -THRMOR222 8.2K/4/1 {25} TXD1 loadline_50
{25} RXD1 VCC
R13 8.2K/4/1 -SB_SPI_CS_ITE JP4 DTR1-
R11 8.2K/4 GP53 {25} DTR1- IO_VCCH
{25} DCD1-

GP66
IT_AVCC IO_VCCH IO_VCCH
R219 8.2K/4/1 GP55 R221 8.2K/4/1/X {25} RI1-
R218 8.2K/4/1 CHARGE_SEL0 GP55 LOW889 HIGHVT2021
3VDUAL CHARGE_SEL1
R220 8.2K/4/1 BC890