1.

0 INTRODUCTION

In a synchronous digital system, the global clock signal is used to define a relative time
reference for the movement of data within that system. Because this function is vital to the
operation of a synchronous system, much attention has been given to the characteristics of these
clock signals and the networks used in their distribution. Most synchronous digital systems
consist of cascaded banks of sequential registers with combinatorial logic between each set of
registers. Synchronous systems use a clock to keep operations in sequence to distinguish this
from previous or next and to determine speed at which machine operates.

Besides that, for the clock must be distributed to all the sequencing elements such as
flip-flops and latches. Furthermore, clock also must be distributing other elements such domino
circuits and memories. For the clock distribution network is different methods are employed to
satisfy the clock conditions. Such techniques involve a tree like structure that has a main “trunk”
supplying the global clock which branches at various points in the circuit based on the loads.
Such clock distribution networks include buffered clock distribution network that distribute
clock to all clocked element. . It is just a wire that possibly an inverter for clock .Then clock
generator is a circuit that produces a timing signal for use in synchronizing a system’s operation.
At its most basic level, a clock generator consists of a resonant circuit and an amplifier. The
resonant circuit is usually a quartz piezo-electric oscillator or MEMS resonator, although simpler
tank circuits and even RC circuits may be used in some cases.
3.0 H-TREES TECHNIQUE

Tree Topology Clock Network Traditionally clock signal is distributed by a tree network
which is characterized by unique paths that deliver the clock signal to every flip flop. Because a
balanced clock tree is simpler to construct and analyze with mathematical models, tree is the
only type of clock distribution supported by most commercial tools. Also unique source to sink
clock path in tree topology enables skew to be intentionally used to improve performance. With
no redundancy in source-sink paths, clock tree introduces less wiring capacitance. Hence tree
topology is a low power solution to distribute clock signal while easing dynamic clock gating.
However, the tree topology sacrifices the clock network robustness. In general, clock trees are
more vulnerable to jitter and process variation induced skew. It is well illustrated in that even an
exact zero skew, clock tree network can have a great deal of skew caused by variability of
interconnects and buffers along paths. Simplest style of clock tree distribution is an H-tree. H-
tree uses a recursive “H” routing pattern and inserts buffers at the regular intervals in the
hierarchy.

H-tree or X-tree clock distribution network consists of a global clock interconnect

which branches out in symmetrical H or X type topology. This branching continues until the
registers are reached. Each branch interconnect is scaled 1/3 to balance the load at those
branches. This type of clock distribution network resolves the issue of buffer delay but produces
power loss in the clock interconnect and thermal power loss in distribution networks as these are
more in the global clock network than on the branches. This may cause over heating in the
nearby circuits thereby affecting their performance if not failing permanently. Figure 2 below
show H-tree clock distribution network for 16 sinks.
 Figure 2 H-tree clock distribution network for 16 sinks

As shown in Figure 2, the path from clock source to all leaves in H-trees are perfectly
balanced which provide zero skew clock deliverance. However skew can still be introduced by
intra-die source of variation as studied in. H-tree is a regular pattern tree which is suitable for
uniform sink and capacitive load distributions. In practice, sink loads and locations are rarely
uniform, hence H-trees are only typically useful for the top level of clock distribution hierarchy.