Jour of Adv Research in Dynamical & Control Systems, Vol.

11, 01-Special Issue, 2019

QCA based Area Efficient B2G & G2B Code

Converters
V. Rama Krishna Reddy*, Assistant Professor, Narasaraopeta Engineering College, Guntur, Andhrapradesh, India.
E-mail: Krishna.venna83@gmail.com
D.V. Bharghav Narayana, UG Scholar, Narasaraopeta Engineering College, Guntur, Andhrapradesh, India.
Ch. Suresh Babu, Assistant Professor, Narasaraopeta Engineering College, Guntur, Andhrapradesh, India.
Abstract--- QCA (Quantum dot-Cellular Automata) is the one of the effective alternative to the currently using
CMOS technology. The demerits of the CMOS technology like high power consumption, more power dissipation,
and speed limitation problems will be solved by this QCA technology. QCA technology makes the devices smaller
in size i.e. nanometres, improves the operational speed i.e. THz with less power consumption as well as dissipation.
It is a nanotechnology and having wide range of applications. In QCA basically the electrons are going to be shifted
in-between the quantum dots as per the energy at quantum junctions. The primary elements of the QCA design are
QCA wire, inverter, and majority voter gates. In this paper binary to gray code converters and gray to binary code
converters are presented with various lengths of data. To simulate the proposed designs QCA Designer tool is used.
We are going to introduce 2, 3, 4, 5-bit binary vs. gray code converters with less number of cells and area using an
efficient xor gate and comparison with existing methods also presented.

I. Introduction
QCA (Quantum Dot Cellular Automata) was introduced to overcome drawbacks of CMOS technology. In
CMOS technology we have power dissipation as main issue, apart from that speed and circuit complexity are other
considerable problems. Power dissipation cannot be completely avoided in CMOS technology. In addition to this
transistor based IC approach is getting extinct. The currently used CMOS technology has channel length which is in
terms of few nanometres(almost equal to zero)and at one point the channel length can't be reduced more. In that case
Moore's Law is not obeyed. Keeping all these issues in mind QCA, a Nanotechnology is proposed that acts as
alternative to CMOS. It's frequency of operation is Terahertz. Thus it is an appropriate method in designing circuits
for general purpose and embedded applications.
QCA cell is shown in Fig.1(a). QCA circuits are implemented with the help of Quantum cells. A cell consists of
4-quantum Dots, 2-electrons[8]. The electrons are arranged diagonally in dots. The position of electrons denotes
Logic"0" (or) Logic"1". There are two polarization states namely positive charge corresponding to logic-1 and
negative charge corresponding to logic-0. By setting one of the polarization states the tunnelling effect takes place
which is shown in Fig.1(b) and signal is transmitted from one location to another through QCA wire. Group of cells
arranged in straight line is called "QCA WIRE" as shown in Fig.2(a) & (b).The QCA wire, Inverter and 3-i/p MV
gate are essential elements in QCA design. Fig.3 (a), Fig.3 (b) shows schematic diagram and symbol of the inverter
respectively[10]. We can obtain an inverter (or a NOT gate) by placing a cell at the corner of another cell. Fig.3(a)
shows that by giving input “0”, we get output as “1” which is the inversion of the input and inverter symbol shows
in fig.3(b).A majority voter gate schematic and symbolic shown in Fig.4(a), 4(b) respectively. Suppose A, B and C
are inputs to the majority voter gate, then mathematical representation of output is given as MV (A,B,C) = (A.B +
B.C + A.C). The three input majority gate will be used as Logic AND gate and Logic OR gate by making one of the
input to fixed Logic. The three input majority voter gate input-out relation is shown in Table.1

Fig.1(a): Basic Cell Structure Fig.1(b): Cell Structure with Tunnel Junctions

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Received: 20 Jan 2019/Accepted: 27 Feb 2019
Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

Fig.2(a): Simple QCAwire Fig.2(b): QCA Cell wire with Clocking

Fig.3(a): Inverter Fig.3(b): Inverter symbol

Fig.4(a): M(A, B, C) = A.B + B.C + A CFig.4(b): Majority Voter Gate Symbol

Table 1: Majority Voter Gate Truth Table

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Received: 20 Jan 2019/Accepted: 27 Feb 2019
Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

Fig.5: AND Gate Fig.6: OR Gate Fig.7: 5-input MV Gate

The majority 5-input gate is shown in Fig.7. Here OUT1 and OUT2 are the two outputs of the MAJ5 gate. Based
on the input combinations they may give majority or minority output values. This paper is describes section-II about
clocking mechanism in QCA, section-III about existing methods, section-IV about proposed designs, section-V
about comparative analysis and section VI is about Conclusion.

II. Clocking Mechanism in QCA

In QCA clocking is main aspect. Clocking helps cells to get synchronized with one another, provides power for
the circuit to run and also controls information flow to get desired output. There are two approaches for clocking in
QCA. First approach is by applying input data array excites from ground state. However, sometimes this transition
may lead to intermediate states. To overcome this issue there is an effective clocking technique [1]. Voltage at the
tunnel junction that gives rise to tunnelling effect between cells moves electrons between the dots. Here Vc
represents the clock voltage which is applied at the tunnelling junction as shown in Fig.8. There are four different
clock signals with 45 degrees of phase shift of one another. The four phases are switch, hold, release and relax and
shown in Fig.9 and Fig.10.

Fig.8: QCA Cell with Clocking Fig. 9: QCA Clocking Zones

Fig.10: Inter Dot Barriers in Clocking Zone

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Received: 20 Jan 2019/Accepted: 27 Feb 2019
Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

III. Existing Method

Binary to Gray code converter is used in cryptography. To provide security information is converted into a
encoded form so that only the sender and receiver knows how to decode it. If the information is in Binary form and
to provide security it is changed into Gray code by encoding technique in transmitting section and in receiving end it
is changed to binary by decoding the message. Thus we need B2G, G2B converters for encoding and decoding of
information. Figure.11 shows the B2G code converter[2] circuit. In this there are 97 QCA cells, occupies 0.12 μm2
total area with 0.5 latency.

Fig.11: Existing Binary to Gray Code Converter

Manisha G. WajeDr.P.K.Dakhole designed a binary to gray converter [6] having 133 cells with overall area of
133μm2 and having a crossover. This circuit provides a latency of 0.75.NehaGuleria designed 4 bit binary to gray
converter[4] with 225 cells with a net area of 0.43μm2.Shifatul Islam, Mohammad Abdullah-al-Shafi and Ali
NewazBahar designed 2 bit binary to gray converter[3] with 41 cells and a net area of 0.05 μm2.Jadav Chandra Das
and Debashis De designed 3 bit binary to gray converter [5]118 cells with net area of 0.45μm2.

IV. Proposed Method

Xor gate is the basic element in the design of B2G, G2B code converters. The QCA structure of an efficient xor
gate [7] is shown in fig.12, it has of 13 QCA cells with 3-inputs and 1-output. This xor gate will be configured as 2-
i/pxor gate by one of the input as constant input as -1.00(logic-0).It occupies the area 0.02μm2 without any
crossings.

Fig.12: Existing X-OR.

Table 2: B2G Code Examples
S:No Binary code Gray code
1 00000 00000
2 00100 00110
3 10000 11000
4 10010 11011
5 11111 10000
6 10101 11111
7 10110 11101
8 10001 11001
9 10011 11010
10 11110 10001

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Received: 20 Jan 2019/Accepted: 27 Feb 2019
Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

Fig.13: Block Diagram of B2G Code Converter

4-bitB2Gconverter basic structure is shown in fig.13 with 4-inputs b3, b2, b1, b0 and 4-outputs g3, g2, g1,
g0.The QCA schematics of 4, 3, 2, 5-bit B2Gconverters are Shown in fig.14 (a), fig.14(b), fig.14(c), fig.14 (d)
respectively. The simulation results of 2,3, 4, 5-bit B2G converters are shown in fig.15(a), fig.15(b), fig.15(c),
fig.15(d) respectively. Some of the 5-bit B2G conversion examples are shown in Table.2.

Fig. 14(a) Fig. 14(b) Fig. 14(c)

Fig. 14(d)

Fig.15: (a) 2-bit B2G

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Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

A 5-bit G2B) code converter is shown in fig.16 with g4,g3,g2,g1,g0 as inputs and b4,b3,b2,b1,b0 as inputs. The
outputs are given as b4=g4, b3=g3⊕ g4, b2=g2⊕ b3, b1=b2⊕ g1, b0=b1⊕ g0.

Fig.16: Block Diagram Gray to Binary Code Converter

The QCA schematics of the 4, 5, 3, 2-bit gray to binary code converters are given in fig.17(a), fig.17 (b),
fig.17(c), fig.17 (d) respectively. And the simulation results of 5, 4, 3, 2-bit gray to binary code converters are given
in fig.18(a), fig.18(b), fig.18(c), fig.18(d) respectively. The summary of proposed binary to gray code converters
shown in Table 4 and gray to binary code Converters shown in Table 3.

Fig.16(b): 3-bit B2G

Fig.16: (c) 4-bit B2G

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Received: 20 Jan 2019/Accepted: 27 Feb 2019
Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

Fig.16: (d) 5-bit B2G

Fig.17 (a) Fig.17 (b)

Fig.17 (c) Fig.17 (d)

Fig.17: Gray to Binary code converter (B2G)

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Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

Fig.18: (a) 5-bit G2B

Fig.18: (b) 4-bit G2B

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Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

Fig.18: (c) 3-bit G2B

Fig.18: (d) 2-bit G2B

Table 3: Summary of G2B converters
S.no No. of bits Net Area (μm2) Total no. of cells
1 5 0.07 51
2 4 0.05 39
3 3 0.04 27
4 2 0.02 15

Table 4: Summary of B2G converters

V. Comparative Analysis
The comparison between the proposed B2G designs and the existing designs [2],[3],[4],[5],[6] are shown in the
Table 5.Our proposed 4-bit B2G code converter design uses less number of cells compared to all existing designs
i.e. 40 QCA cells with minimum net area as 0.08 μm2.

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Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

Table 5: B2GComparison

Table 6: G2B Comparison

The comparison between the proposed gray to binary code design and the existing design [6] is shown in the
Table6.Our proposed 4-bit G2B code converter design uses less number of cells compared to existing designs i.e. 39
QCA cells with minimum net area as0.05 μm2.

Net Area (μm2)

0.5 0.43 0.45
0.4
0.3
0.2 0.14 0.12 0.14 0.11
0.07 0.08 0.05 0.05
0.1
0
Net Area (μm2)

Fig.19: Comparison of Proposed and Existing Designs with Respect to Net Area

No.of Cells
250 225
200
150 118 113 103
97
100 53 51 40 39 41
50
0 No.of Cells

Fig. 20: Comparison of Proposed and Existing Designs with Respect to Number of Cells

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Received: 20 Jan 2019/Accepted: 27 Feb 2019
Jour of Adv Research in Dynamical & Control Systems, Vol. 11, 01-Special Issue, 2019

The comparison between the proposed and existing designs with respect to net area and number of cells is shown
in Fig.19, Fig.20 respectively.

VI. Conclusion
In this paper an efficient single layered B2G converters and G2B code converters are proposed. These proposed
B2G&G2B converters were designed with minimum number of QCA cells, minimum net area of a circuit without
any crossings. Moreover, these B2G, G2B converters are useful for projected security systems. We have designed
all 2, 3, 4, 5-bit B2G converters and G2B code converters and simulated by using QCA Designer tool. All the 2, 3,
4-bit B2G, G2B code converters results are compared with the existing designs and are shown in in fig.19 and
fig.20. Also we have proposed 5-bit B2G& G2B code converters with the cell count 53, 51 respectively and the area
0.14μm2, 0.07μm2 respectively. These type code converters will be expandable to any length of data with optimum
area and minimal cell count.

References
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ISSN 1943-023X 1655

Received: 20 Jan 2019/Accepted: 27 Feb 2019