Logical Effort - Logical effort is defined as the ratio of the input capacitance of a gate to the

input capacitance of an inverter delivering the same output current. Below given figure
represents the NOR-NOR implementation of Boolean expression Y = (T1+T2).(T3+T4).T5.
Having a total of 4 stages. We have introduced 2 inverters at the end to stabilize the delay
occurring in the output waveform.

Input capacitance at each stage can be calculated by below given formula

Cout  g
Cin 
(GH )1/ N
Where,

Cout = output capacitance (pF)

g = logical effort

G = path logical effort = g1.g2.g3…gN

H = path electrical effort = h1.h2.h3…hN

N = number of stages

Capacitance at output = 1000pF

Cout  g (1000) 1
Capacitance at stage-IV – Cin  1/ N
 =189.361pF
(GH ) 5 7 1000 1/ 4
( * *1*1* )
3 3 5
 Cout  g (189.361) 1
Capacitance at stage-III – Cin  1/ N
 = 35.857pF
(GH ) 5 7 1000 1/ 4
( * *1*1* )
3 3 5
Cout  g (35.857)  7 / 3
Capacitance at stage-II – Cin  1/ N
 = 15.8435pF
(GH ) 5 7 1000 1/ 4
( * *1*1* )
3 3 5
Cout  g (15.8435)  5 / 3
Capacitance at stage-I – Cin  1/ N
 = 5.00025Pf ≈ 5Pf
(GH ) 5 7 1000 1/ 4
( * *1*1* )
3 3 5
We can do the sizing of each stage (nMOS & pMOS) by using the input capacitance values
obtained from above calculations.

Stage K Sizing (pMOS) Sizing (nMOS)

126( pMOS )
IV 126x240 = 30240 nm 64x240 = 15360 nm
64(nMOS )
24( pMOS ) 24x240 = 5760 nm 12x240 = 2880 nm
III
12(nMOS )
12( pMOS ) 12 x240 = 2880 nm
II 2 x240 = 480 nm
2(nMOS )
4( pMOS ) 4 x240 = 960 nm
I 1 x240 = 240 nm
1(nMOS )
Schematics-
2-input NOR gate-
3-input NOR gate-

Bit0-
Bit1-

Bit2-

Bit3-
Bit4-

Transient Analysis-
X0 v/s out0-

X1 v/s out1-

X2 v/s out2-

X3 v/s out3-
X4 v/s out4-

Determination of VT for NOR-NOR implementation-

From graph- VT = 790.499Mv

Propagation Delay-
Out1-
tpHL = 9.44067-9.045 = 0.39567ns
tpLH = 6.40723-6.015 = 0.39223 ns
 t pHL  t pLH
tdelay   0.394ns
2

Out2-
tpHL = 12.42412-12.03 = 0.39412 ns
tpLH = 7.399047-7.01 = 0.389047 ns

t pHL  t pLH
tdelay   0.3916ns
2

Out3-
tpHL = 7.42542-7.03 = 0.39542 ns
tpLH = 10.41187-10.01 = 0.40187 ns

t pHL  t pLH
tdelay   0.3986ns
2

Out4-
tpHL = 6.538078-6.015 = 0.52307 ns
tpLH = 3.511302-3.045 = 0.466302 ns

t pHL  t pLH
tdelay   0.4947ns
2