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Journal of

Low Power Electronics


and Applications

Review
CMOS Inverter as Analog Circuit: An Overview
Woorham Bae 1,2
1 Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley,
CA 94720, USA; wrbae@eecs.berkeley.edu
2 Ayar Labs, Santa Clara, CA 95054, USA

Received: 24 June 2019; Accepted: 17 August 2019; Published: 20 August 2019 

Abstract: Since the CMOS technology scaling has focused on improving digital circuit, the design
of conventional analog circuits has become more and more difficult. To overcome this challenge,
there have been a lot of efforts to replace conventional analog circuits with digital implementations.
Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS
inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a
CMOS inverter into an optimum biasing for analog operation. Recently developed applications of
the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output
driver for high-speed link, are introduced and discussed in this paper.

Keywords: analog; analog and mixed signal; amplifier; CMOS; driver; high-speed buffer;
high-speed I/O; Integrated circuit; Inverter

1. Introduction
Since the 1960s, scaling of silicon technologies (Moore’s law) has dominantly driven the
semiconductor industry, as the scaling is actually the almighty knob for all the challenges we
have had; lower power consumption, higher speed, and higher density. However, the main focus of
the scaling has been the improvement of digital circuit, for example high Ion /Ioff ratio, as the computing
capability has been constrained by the power consumption, instead of the speed of the transistor [1,2].
Such digital-driven scaling leads to several issues in analog circuit design. For instance, the intrinsic
gain of transistor has been significantly reduced due to the short-channel effect. Moreover, the threshold
voltage of transistor has not been scaled at the same rate of the supply voltage scaling, in order for
suppressing the leakage current [3]. That means the “normalized” voltage headroom for analog
circuit has been reduced. Therefore, adopting conventional gain-boosting techniques (i.e., cascode)
becomes more and more difficult in modern CMOS technology [4]. What makes things worse is that
the gate-overdrive voltage of analog circuits should be decreased as the voltage headroom reduces,
which increases the sensitivity of analog circuits to the device mismatch [5]. We can observe such
trend in Figure 1, which compares the stacked common-source (CS) amplifier to the non-stacked CS
amplifier [6,7]. Figure 1a,b shows the normalized gain of CS amplifiers with respect to VDD /VTH and
the normalized large-signal bandwidth with respect to the normalized current dissipation, respectively.
The gain of the stacked topology decreases much steeper than that of the non-stacked, which means
that the gain enhancement from the cascode topology becomes less attractive in the modern CMOS
technology where the voltage headroom is reduced. Moreover, the achievable bandwidth of the stacked
amplifier is much less than the non-stacked amplifier even when it dissipates more current, because the
increased self-loading from the stacked transistor degrades the rise/fall time. In addition, [6] revealed
that the input-referred noise becomes even worse in the stacked topology because the transconductance
gm increases due to the reduced gate-overdrive voltage.

J. Low Power Electron. Appl. 2019, 9, 26; doi:10.3390/jlpea9030026 www.mdpi.com/journal/jlpea


J. Low Power Electron. Appl. 2019, 9, 26 2 of 15
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 2 of 15

4 1
2 0.8
0
0.6
-2
0.4
-4
-6 0.2

-8 0
2 2.5 3 3.5 0 0.2 0.4 0.6 0.8 1

Figure 1.
Figure Comparison of
1. Comparison of stacked
stacked over
over non-stacked
non-stacked structure
structure using
using common-source
common-source (CS)
(CS) amplifier
amplifier
topology. (a) Gain degradation as a function of V /V [6], (b) large-signal bandwidth degradation
topology. (a) Gain degradation as a function of VDD/VTH [6], (b) large-signal bandwidth degradation
DD TH
as aa function
as function of
of current
current consumption
consumption [7],
[7], (c)
(c) circuit
circuit diagram
diagram ofof aa CS
CS amplifier.
amplifier.

In summary,
In summary,what whatwe we could
could observe
observe from the CMOS
from the CMOS scaling trend trend
scaling is thatisthethat
scaling
the has focused
scaling has
on improving the digital circuits; hence, the performance of analog
focused on improving the digital circuits; hence, the performance of analog circuits has been circuits has been degraded due to
the short-channel
degraded due to effect and the reduced
the short-channel voltage
effect and headroom.
the reduced The analogheadroom.
voltage circuit designers have come
The analog up
circuit
with the fact that a CMOS inverter, which is the representative of the
designers have come up with the fact that a CMOS inverter, which is the representative of the digitaldigital circuit family, can be the
most powerful
circuit family, can circuit
be thein modern CMOS technologies,
most powerful circuit in modern even in the analog
CMOS domain even
technologies, [8,9]. in
First,
the there
analog is
no stacking; thus, it has not been affected by the reduced voltage
domain [8,9]. First, there is no stacking; thus, it has not been affected by the reduced voltageheadroom. Second, CMOS inverter
utilizes gm Second,
headroom. of PMOSCMOS as wellinverter
as that utilizes
of NMOS gm atofthe
PMOSsameastime.
well When
as thatwe compare
of NMOS atthe
thetwo
same circuits
time.
given in Figure 2, we can find that they have the same load capacitance,
When we compare the two circuits given in Figure 2, we can find that they have the same load including the self-loading.
However, in including
capacitance, case of thethe CMOS inverter, However,
self-loading. the overallingm is the
case sumCMOS
of the of gmNinverter,
and gmPthe ; thus, we can
overall gm isgetthea
higher bandwidth. This aspect becomes much powerful in recent
sum of gmN and gmP; thus, we can get a higher bandwidth. This aspect becomes much powerful in process technologies, where strained
silicon process
recent technique enhances the
technologies, PMOS
where currentsilicon
strained density as much enhances
technique as that of theNMOS PMOS [10–12].
currentIn fact,
densitywhenas
we consider the sizing, the P/N ratio of the inverter for analog intent
much as that of NMOS [10–12]. In fact, when we consider the sizing, the P/N ratio of the inverter foris different to the digital intent.
In orderintent
analog technology where to
is different thethe
strained
digital silicon
intent.technique
In orderis technology
not adopted,where digitalthe
inverter has silicon
strained PMOS
which is generally twice larger than NMOS, because we have
technique is not adopted, digital inverter has PMOS which is generally twice larger than NMOS,to match the strength of PMOS and
NMOS, since we assume that only one of the PMOS and NMOS
because we have to match the strength of PMOS and NMOS, since we assume that only one of the is turned on at a time. However,
in such and
PMOS analog NMOSinverter, the optimum
is turned on at ais time.
at around P/N ratio
However, of unity,
in such where
analog we can the
inverter, achieve the highest
optimum is at
g m per input capacitance [13]. Note that the PMOS and NMOS continuously
around P/N ratio of unity, where we can achieve the highest gm per input capacitance [13]. Note run together in analog
that
mode. That means we were not able to fully utilize the g mP in
the PMOS and NMOS continuously run together in analog mode. That means we were not able toolder technology nodes. In other words,
the strained
fully silicon
utilize the gmP boosts
in older the current density
technology nodes.ofInPMOS other to be matched
words, to thatsilicon
the strained of NMOS,boosts and
thetherefore
current
it makes the analog inverter become more powerful.
density of PMOS to be matched to that of NMOS, and therefore it makes the analog inverter become
moreSome readers may wonder how a CMOS inverter acts like an analog circuit, because it is a
powerful.
representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing”
can be used to distinguish them, which is explained in Figure 3. The blue line shows the input-output
transfer curve of an inverter. Note that the blue lines are the same for both figures. When we see the
big picture (large signal), we can find a digital circuit. However, when we focus on a certain operating
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 3 of 15

J. Low Power Electron. Appl. 2019, 9, 26 3 of 15

point (small signal), we can find an analog circuit. We can also find that the maximum gain is achieved
at the point where the input and output are the same, that is, at the switching threshold. Analog
designers found that such optimum bias point can be achieved with the self-biasing using the resistive
J. Low Power as
feedback, Electron.
shown Appl.
in2019, 9, x 4.
Figure FOR PEER REVIEW 3 of 15

Figure 2. Utilization of gm of PMOS in a CMOS inverter.


Figure 2. Utilization of gm of PMOS in a CMOS inverter.

Some readers may wonder how a CMOS inverter acts like an analog circuit, because it is a
Some readers may wonder how a CMOS inverter acts like an analog circuit, because it is a
representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing”
representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing”
can be used to distinguish them, which is explained in Figure 3. The blue line shows the
can be used to distinguish them, which is explained in Figure 3. The blue line shows the
input-output transfer curve of an inverter. Note that the blue lines are the same for both figures.
input-output transfer curve of an inverter. Note that the blue lines are the same for both figures.
When we see the big picture (large signal), we can find a digital circuit. However, when we focus on
When we see the big picture (large signal), we can find a digital circuit. However, when we focus on
a certain operating point (small signal), we can find an analog circuit. We can also find that the
a certain operating point (small signal), we can find an analog circuit. We can also find that the
maximum gain is achieved at the point where the input and output are the same, that is, at the
maximum gain is achieved at the point where the input and output are the same, that is, at the
switching threshold. Analog designers found that such optimum bias point can be achieved with the
switching threshold. Analog designers found that such optimum bias point can be achieved with the
self-biasing using the resistive feedback, as shown in Figure 4.
self-biasing using the resistive
Figurefeedback,
Figure 2. as shown
2. Utilization of gm ofin
m of Figure
PMOS
PMOS in aa4.CMOS
in CMOS inverter.
inverter.

Some readers may wonder how a CMOS inverter acts like an analog circuit, because it is a
representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing”
can be used to distinguish them, which is explained in Figure 3. The blue line shows the
input-output transfer curve of an inverter. Note that the blue lines are the same for both figures.
When we see the big picture (large signal), we can find a digital circuit. However, when we focus on
a certain operating point (small signal), we can find an analog circuit. We can also find that the
maximum gain is achieved at the point where the input and output are the same, that is, at the
switching threshold. Analog designers found that such optimum bias point can be achieved with the
self-biasing using the resistive feedback, as shown in Figure 4.

Figure 3. Inverter
Figure 3.
3. gain
Invertergain curve
gaincurve and
curveand distinction
anddistinction between
distinctionbetween digital
betweendigital and
digitaland analog.
and analog.
analog.
Figure Inverter

Figure 3. Inverter gain curve and distinction between digital and analog.

Figure 4. CMOS inverter with resistive feedback.


Figure 4. CMOS inverter with resistive feedback.
Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there
has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the
applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 4 of 15

Nowadays,
J. Low Power in order
Electron. Appl. 2019, 9,to26take
advantage of the CMOS inverter in modern process technology, 4 of 15
there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses
on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in
communication receiversreceivers
optical communication [6,14–30],[6,14–30],
high-speed clock andclock
high-speed data buffer [13,31–41],
and data and outputand
buffer [13,31–41], driver for
output
high-speed I/O transmitter [13,40,42–50].
driver for high-speed I/O transmitter [13,40,42–50].

2.2. CMOS
CMOS Inverter
Inverter as as an
an Amplifier
Amplifier
The
Thefirst
firstexample
examplewe wearearegoing
going to to cover
cover isis the
the use
use ofof aa CMOS
CMOS inverter
inverter as as aa high-speed
high-speed amplifier,
amplifier,
which is mostly adopted in optical communication receiver. In optical
which is mostly adopted in optical communication receiver. In optical communication, high-speed communication, high-speed
serial
serialdata datais transmitted
is transmitted by modulating
by modulating the amplitude of light. At
the amplitude of the receiving
light. At the side, a photodetector
receiving side, a
(PD) converts the received light signal to the photocurrent. Due to the
photodetector (PD) converts the received light signal to the photocurrent. Due to the limited limited PD responsibility as well
PD
as and the limited extinction ratio at the transmit side, typically, the amplitude
responsibility as well as and the limited extinction ratio at the transmit side, typically, the amplitude of photo-current signal
ranges from tens ofsignal
of photo-current uA toranges
hundreds from of tens
uA. Inof order
uA totohundreds
be processedof uA.in aInCMOS
orderintegrated circuit (IC),
to be processed in a
the
CMOS integrated circuit (IC), the current-mode signal should be converted to voltage-mode. Thus,isa
current-mode signal should be converted to voltage-mode. Thus, a trans-impedance amplifier
used at the very front-end
trans-impedance amplifierofisan usedoptical receiver.
at the As a result,
very front-end of antheoptical
overallreceiver.
performance of the the
As a result, receiver is
overall
predominantly determined by the trans-impedance amplifier (TIA). Since
performance of the receiver is predominantly determined by the trans-impedance amplifier (TIA). there is an inherent trade-off
between
Since there TIA gain/noise and bandwidth,
is an inherent trade-off compound
betweensemiconductor
TIA gain/noise process andwas traditionallycompound
bandwidth, preferred
to build the optical
semiconductor interface
process was IC due to their
traditionally high-speed
preferred characteristic.
to build the optical However,
interfacesince continuous
IC due to their
advance
high-speed characteristic. However, since continuous advance of CMOS technology has reducedthe
of CMOS technology has reduced the gap, nowadays, CMOS technology is becoming the
mainstream for optical interface ICs.
gap, nowadays, CMOS technology is becoming the mainstream for optical interface ICs.
We
Wecan canseeseeaabrief
briefhistory
historyof ofCMOS
CMOSTIA TIAforforoptical
opticalreceiver
receiverin inFigure
Figure5.5.The
Themost mostprimitive
primitiveTIA TIA
isisaaresistor.
resistor. But there is a strict trade-off between gain and bandwidth, because the gainequals
But there is a strict trade-off between gain and bandwidth, because the gain equalsthe the
resistance R and the bandwidth is 1/2πRC PD . In addition, the signal-to-noise
resistance R and the bandwidth is 1/2πRCPD. In addition, the signal-to-noise (SNR) is another main (SNR) is another main
issue
issueof ofconcern.
concern. The The total
total integrated
integratednoise noisedue
dueto tothe
thethermal
thermalnoise
noiseof ofthe
theresistor
resistorisisgiven
givenas asto:
to:

2 2 = kT kT ,
Vn, out =
Vn,out , (1)
(1)
CCPD
PD

wherekkisisthe
where theBoltzmann
Boltzmannconstant andT Tisisthe
constantand absolute
the temperature.
absolute Then,
temperature. thethe
Then, input-referred noise
input-referred is
noise
obtained by by
is obtained dividing (1) (1)
dividing with thethe
with trans-impedance
trans-impedance gain R as:
gain R as:
kTkT
i2n,inin2=
, in = 2 2
, , (2)
(2)
R RCPDCPD

Figure5.5. Trans-impedance
Figure Trans-impedanceamplifier
amplifierexamples.
examples.
J. Low Power Electron. Appl. 2019, 9, 26 5 of 15

From (2) we can obtain the SNR to:

CPD 2 2
SNR = I R , (3)
kT in
where we can observe that higher gain leads to a better SNR, which implies the trade-off of gain/noise
over the bandwidth. Many circuit designers have tried to find a way to break the trade-off, and
they found that the common-gate (CG) amplifier can break the trade-off. Because the photo-current
directly flows to the load resistor, the trans-impedance gain equals to the resistance. On the other hand,
the input impedance of the CG amplifier is 1/gm , so the pole at the input of CG amplifier is given as to:
gm1
f−3dB = (4)
2πCPD

Note that there is no R term in, which implies that the aforementioned trade-off is now broken,
since CPD is generally much larger than the load capacitance of the CG amplifier. Since the 1/gm can
be reduced by drawing more current by the current source (IB ), we can achieve high gain as well as
high bandwidth at the cost of power consumption. In addition, [51,52] proposed a regulated-cascode
(RGC) TIA, which further improves the gain-bandwidth product of TIA. However, the effectiveness of
such stacked configuration has been degraded due to the aforementioned scaling issue, now many
researchers have ended up with the resistive feedback inverter TIA. The inverter-TIA still have a
similar trade-off as the passive TIA; however, the input resistance of the resistive feedback inverter is
R/(1 + A), where A is the gain of the inverter. That means that the trade-off is relaxed by the factor of
A. Additionally, note that there is no other path that the photo-current can flow; the gain of this TIA
equals R. Readers may consult [28] for a detailed history of TIA evolution.
The resistive-feedback inverter TIA is also able to be combined with inductive peaking technique,
to extend the bandwidth with less gain/power penalty. References [19,25] present the inverter TIA with
series inductive peaking, which is illustrated in Figure 6a. Since an inductor blocks an instantaneous
current flow, it enables sequential charging (or discharging) of the two adjacent capacitances (for
example, PD capacitance and self-load at the input node, or self-load and load capacitances at the
output node), which leads to a faster transient response. On the other hand, [6] added an inductor
in series with the feedback resistor; that is, the inductive feedback as shown in Figure 6b. At a low
frequency, the effect of the inductor is negligible; thus, the TIA simply follows the transfer gain of
the resistive-feedback inverter. Note that such negative feedback increases the bandwidth at the
cost of reduced low-frequency gain. On the other hand, the impedance of the inductor increases as
the frequency increases; hence, after zero frequency, it surpasses that of the feedback resistor. That
means that the total impedance in the feedback path increases, and thus the gain increases. If the
inductive impedance is larger enough than the resistance, the transfer gain of the TIA follows that
of the inverter without resistive feedback. At a very high frequency, the second order pole, which
is introduced by the inductor and the capacitance as well as the intrinsic pole of the inverter, let the
transfer gain decrease rapidly as the frequency increases. As a result, such inductive feedback leads to
a high-frequency peaking, which can be used to compensate the dominant pole by the CPD . Recent
state-of-the-arts works in [15,24,29] have combined the series peaking and the inductive feedback, and
therefore considerable high-bandwidth at a quite impressive energy efficiency is achieved. Moreover,
the authors in [29] saved inductor area by incorporating T-coil inductive peaking.
J. Low Power Electron. Appl. 2019, 9, 26 6 of 15
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 6 of 15

6. (a) Inverter TIA with series peaking, (b) with inductive feedback.
Figure 6. feedback.

The
The application
application of of CMOS
CMOS inverter
inverter as as an
an amplifier
amplifier is is not
not limited
limited to to the
the TIA.
TIA. Optical
Optical receivers
receivers
presented
presentedinin[18,19,21,24–27]
[18,19,21,24–27]extend
extend thethe
usage
usageof the CMOS
of the CMOSinverter to thetopost
inverter thelimiting amplifier
post limiting which
amplifier
follows the TIA. In addition, [16,17,30] present resistive-feedback-inverter-based
which follows the TIA. In addition, [16,17,30] present resistive-feedback-inverter-based low-noise low-noise amplifier
(LNA) and(LNA)
amplifier variableandgain amplifier
variable gain(VGA),
amplifierrespectively. In such applications,
(VGA), respectively. In such aapplications,
normal inverter stage
a normal
and a resistive-feedback
inverter stage are placedstage
stage and a resistive-feedback alternately to retain
are placed the self-bias
alternately (resistive
to retain feedback)
the self-bias as well
(resistive
as high gain
feedback) as (inverter),
well as highas gain
shown in Figureas7.shown
(inverter), Recalling Figure7.3,Recalling
in Figure the small-signal
Figure 3, gain
theofsmall-signal
inverter is
maximized at theiscrossover
gain of inverter maximized voltage.
at theTherefore,
crossover in order to
voltage. maximizeinthe
Therefore, overall
order gain of thethe
to maximize amplifier
overall
chain,
gain ofthe
thecommon-mode
amplifier chain, voltage should be corrected.
the common-mode voltageDue to the
should beconsiderably
corrected. Due large
to gain of the chain,
the considerably
the resistive
large gain offeedback
the chain,itself
the is not enough
resistive to retain
feedback itselfa is
correct bias point.
not enough Suchacommon-mode
to retain variation
correct bias point. Such
leads to some large-signal
common-mode non-idealities,
variation leads to some such as duty-cycle
large-signal distortion.
non-idealities, suchTherefore, a common-mode
as duty-cycle distortion.
feedback
Therefore,isagenerally
common-modeincluded as shown
feedback in the example
is generally includedof Figure 7. The
as shown in DC
the component of the output
example of Figure 7. The
signal is extracted
DC component through
of the output a low-pass filter (LPF)
signal is extracted and then
through compared
a low-pass to the
filter (LPF)reference
and then voltage
compared(i.e.,
crossover voltage).
to the reference The feedback
voltage adjustsvoltage).
(i.e., crossover the input Thecommon
feedback level until the
adjusts the common-mode
input common level voltage at
until
the output becomes the same as the reference voltage.
the common-mode voltage at the output becomes the same as the reference voltage.

Figure 7. Inverter-based multi-stage amplifier with common-mode feedback.


Figure 7. Inverter-based multi-stage amplifier with common-mode feedback.

To sum up, the resistive-feedback inverter has become a mainstream of TIA implementation,
To sum up, the resistive-feedback inverter has become a mainstream of TIA implementation, to
to fully utilize the CMOS process scaling, against the conventional TIA structures. Moreover, there
fully utilize the CMOS process scaling, against the conventional TIA structures. Moreover, there
have been many efforts to extend the application to other high-speed amplifiers. For evidence, taking
have been many efforts to extend the application to other high-speed amplifiers. For evidence,
advantage of the advanced CMOS technology node (14 nm FinFet), [25], where the inverter-based
taking advantage of the advanced CMOS technology node (14 nm FinFet), [25], where the
TIA and post amplifier are adopted, achieves the highest bandwidth optical receiver, which achieves
inverter-based TIA and post amplifier are adopted, achieves the highest bandwidth optical receiver,
64 Gb/s with binary signaling.
which achieves 64 Gb/s with binary signaling.
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 7 of 15

J. Low Power Electron. Appl. 2019, 9, 26 7 of 15


3. High Speed Buffer
In the previous section, we focused on the small-signal behavior of CMOS inverter (with
3. High Speed Buffer
resistive feedback). Here, we will be care of more large-signal-like behavior compared to the
amplifier
In the operation. If the input
previous section, signalon
we focused swing is large enough,
the small-signal behaviorthatofis,CMOS
entering to the(with
inverter noiseresistive
margin
region, theHere,
feedback). amplitude
we will of the signal
be care of moreno longer needs behavior
large-signal-like to be considered
comparedastolong as the gain
the amplifier of the
operation.
“buffer” is larger than unity. However, taking into account the intrinsic
If the input signal swing is large enough, that is, entering to the noise margin region, the amplitude gain of an inverter, the 3 dB
bandwidth
of the signal is notypically
longer needs 5–10×tolower than theas
be considered unity-gain
long as the bandwidth
gain of the(Figure
“buffer” 8).isIflarger
the main signal
than unity.
component
However, is at into
taking between
account the the
3 dBintrinsic
bandwidth gain and
of anthe unity-gain
inverter, the 3bandwidth,
dB bandwidth the signal experiences
is typically 5–10×
distortion
lower than thewhile passingbandwidth
unity-gain through the buffer
(Figure 8). even
If thethough
main signal the amplitude
component is notbetween
is at attenuated.
the 3 dBFor
example, since
bandwidth and the phase
unity-gaindelaybandwidth,
is not a constant
the signaloverexperiences
the frequency, a pattern-dependent
distortion while passing jitter throughwill
be buffer
the introducedeven to the non-return-to-zero
though the amplitude is not (NRZ) datastream
attenuated. even if the
For example, Nyquist
since frequency
the phase delay is
is below
not a
the unity-gain
constant over the bandwidth
frequency,ofa the buffer [53]. Clock
pattern-dependent signal
jitter willisbeanother
introducedgoodtoandthesimpler example, as
non-return-to-zero
there is
(NRZ) only a single
datastream evenfrequency
if the Nyquisttone.frequency
Let us take into account
is below additivebandwidth
the unity-gain white noise. of The amplitude
the buffer [53].
noise is filtered out by the noise margin of inverter; however, the phase
Clock signal is another good and simpler example, as there is only a single frequency tone. Let us take noise propagates through
the account
into inverter.additive
Moreover, if the
white clock
noise. Thefrequency
amplitude is higher
noise isthan the out
filtered 3 dBby bandwidth, the lowoffrequency
the noise margin inverter;
noise hasthea phase
however, largernoise
gainpropagates
than the through
fundamental frequency
the inverter. component.
Moreover, That frequency
if the clock leads to is the jitter
higher
amplification
than [54]. Duty-cycle
the 3 dB bandwidth, distortion
the low frequency is another
noise has important
a larger gainissue, since
than thethe duty-cycle frequency
fundamental is actually
the DC component
component. That leadsofto the signal
the jitter so the duty-cycle
amplification error is distortion
[54]. Duty-cycle amplifiedisafter
another passing through
important issue,a
band-limited
since buffer is
the duty-cycle [42].
actually the DC component of the signal so the duty-cycle error is amplified
after passing through a band-limited buffer [42].

20

0 1 10 10 0 10 00 10 000

-20
Figure 8. Magnitude response of CMOS inverter.
Figure 8. Magnitude response of CMOS inverter.
The above observation implies that the 3 dB bandwidth is more important than the unity-gain
bandwidth whileobservation
The above handling a high-speed
implies thatanalog signal,
the 3 dB in contrary
bandwidth to the
is more digital intent.
important Theunity-gain
than the resistive
feedback is also very useful to extend the 3 dB bandwidth of the inverter. We can obtain a quantitative
bandwidth while handling a high-speed analog signal, in contrary to the digital intent. The resistive
analysis
feedbackhow is the
alsoresistive feedback
very useful to extends
extend the
the bandwidth of the inverter,
3 dB bandwidth of the from the small
inverter. We signal modela
can obtain
shown in Figure 9. Applying KCL to the output node, we obtain:
quantitative analysis how the resistive feedback extends the bandwidth of the inverter, from the
small signal model shown in Figure 9. Applying
vout KCL to thevx output
− vout node, we obtain:
gm vx + + jωCL vout = , (5)
rov vRxF− vout
g m vx + out
+ jωC L vout = , (5)
ro (5) leads to the transfer
where gm is the sum of gmN and gmP . Equation RF function as:
where gm is the sum of gmN and gmP. Equation
vout (5)1leads
− gm RtoF the transfer function as:
= R
, (6)
vx 1 + roF + jωRF CL
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 8 of 15
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 8 of 15

voutvout = 1 −1g−mgRmFRF ,
= R ,
J. Low Power Electron. Appl. 2019, 9, 26 vx vx 1 +1R
+F +F + jω R C
jω RF CFL L
(6)
(6)15
8 of
ro ro
where we
where can achieve the 3 dB bandwidth to:
where we
we can
can achieve
achieve the
the 33 dB
dB bandwidth
bandwidth to:
to:
1 1
ωω
3dBω= =
3 dB =11 ++ +11 . . . (7)
(7)
3 dB ro CLro C LRF CRLF C L (7)
ro C L RF C L

16
16
BW-sim
BW-sim
R RF
12
12 BW-cal
F
vxvx vout BW-cal
vout 8
8

CinCin gmgvmxvx ro ro CLCL 4


4

0
0
0 5 10
0 5 10
RFR(k
F (k) )

(a)
(a) (b)
(b)
Figure 9. (a)
Figure Small
9. (a) signal
Small diagram
signal of of
diagram resistive feedback
resistive inverter,
feedback (b)(b)
inverter, verification of (7).
verification of (7).
Figure 9. (a) Small signal diagram of resistive feedback inverter, (b) verification of (7).
Note
Notethat thethe
that 3 dB3 dBbandwidth
bandwidth of the inverter
of the inverterwithout
without feedback
feedback is 1/r CLo.CThat
is o1/r is, the resistive
L. That is, the resistive
Noteincreases
feedback that the the3 dB3 dBbandwidth
bandwidth of the
by inverter
1/R C . without feedback
Simulated bandwidth is 1/r oCL. That is, the resistive
shown in Figure 9b9bverifies
feedback increases the 3 dB bandwidth by 1/R F LFCL. Simulated bandwidth shown in Figure verifies
feedback increases
(7).(7).Moreover, the
thanks 3todBthebandwidth
negative by 1/R
feedback, FCL. Simulated bandwidth shown in Figure 9b verifies
this circuit is less sensitive to the PVT variations
Moreover, thanks to the negative feedback, this circuit is less sensitive to the PVT variations
(7). Moreover,
compared thethanks
to to normal toCMOS
the negative
inverter. feedback, this circuit is less sensitive to the PVT variations
compared the normal CMOS inverter.
comparedOnOn to
thethethe
other normal
hand, CMOS inverter.
an AC-coupling capacitor is widely
other hand, an AC-coupling capacitor is used
widely at the
used input of the
at the resistive
input of thefeedback
resistive
On for
inverter, the clock
otherbuffer
hand,application
an AC-coupling
[32–39] capacitor
(Figure 10). isThe
widely usedmotivations
primary at the input of of AC
the the coupling
resistive
feedback inverter, for clock buffer application [32–39] (Figure 10). The primary motivations of the
feedback inverter, for clock buffer application [32–39] (Figure 10). The primary motivations of the
forACthecoupling
clock buffer are clock
for the as follows:
buffer are as follows:
AC coupling for the clock buffer are as follows:
1. 1. SinceSinceAC AC coupling
coupling completely
completely blocks
blocks thetheDCDC component
component of of
thetheclock
clocksignal,
signal,thetheduty-cycle
duty-cycle
1. Since AC coupling completely blocks the DC component of the clock signal, the duty-cycle
distortion
distortiondoes not propagate.
does not propagate. Thanks to the self-biasing
Thanks to the cross-over
to the self-biasing to the voltage,
cross-over the duty-cycle
voltage, the
distortion does not propagate. Thanks to the self-biasing to the cross-over voltage, the
is duty-cycle
restored to is the ideal value
restored to theregardless
ideal value of regardless
the input duty-cycle
of the input(Figure 11). (Figure 11).
duty-cycle
duty-cycle is restored to the ideal value regardless of the input duty-cycle (Figure 11).
2. 2. Combined
Combined with
withthe low-pass
the low-pass characteristic
characteristic ofofthetheinverter,
inverter,AC ACcoupling
coupling results
resultsin in
a band-pass
a band-pass
2. Combined with the low-pass characteristic of the inverter, AC coupling results in a band-pass
characteristic. Because a band-pass filter attenuates all out-of-band
characteristic. Because a band-pass filter attenuates all out-of-band noise, it suppresses noise, it suppresses phase
phase
characteristic. Because a band-pass filter attenuates all out-of-band noise, it suppresses phase
noise
noiseand
andjitter from
jitter from thethe
input
inputclock
clock[54].
[54].
noise and jitter from the input clock [54].
3. Because
Because the clock buffer does not have towith
deala with a wide-band signal, the high-frequency
3. Because the
3. the clock
clockbuffer
bufferdoesdoesnotnot
have to deal
have to deal withwide-band
a wide-bandsignal,signal,
the high-frequency cut-off
the high-frequency
cut-off frequency
frequency can be fairlycan be fairly highof(<~1/10 of the clock frequency). Therefore, a small capacitor
cut-off frequency can behigh (<~1/10
fairly high (<~1/10 the clock
of thefrequency). Therefore,
clock frequency). a smallacapacitor
Therefore, can be
small capacitor
can[39].
used be used [39].
can be used [39].

Figure 10. (a) AC-coupled resistive feedback inverter and (b) Miller approximation to calculate
high-pass cut-off frequency.
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 9 of 15

Figure 10. (a) AC-coupled resistive feedback inverter and (b) Miller approximation to calculate
J. Low Power Electron. Appl. 2019, 9, 26 9 of 15
high-pass cut-off frequency.

Duty-cycle
transfer

0.5

0 0.2 0.4 0.6 0.8 1

Figure11.
Figure Dutycycle
11.Duty cycletransfer
transfercurve
curveof
ofAC-coupled
AC-coupledbuffer.
buffer.

The high-pass
The high-pass cut-off
cut-off frequency
frequency of
of the
the AC-coupled
AC-coupled buffer
buffer is
is calculated
calculated as
as follows.
follows. Using
Using Miller
Miller
approximation, the feedback resistance R is translated to the input resistance of R /(1 + A
approximation, the feedback resistance RF is translated to the input resistance of RF/(1 + AF), where
F F F ), where AF
is the DC gain of the inverter. Then, we obtain:
AF is the DC gain of the inverter. Then, we obtain:

jω 1+RA CC


 R 
F
vx
= jω   RF  CC,
F
(8)
vvxin 1 + jω1 +1+AAFF CC
= F , (8)
 RF 
vin
+ jω  is:
where we can find that the high-pass cut-off1frequency  CC
 1 + AF 
1 + AF
ωhp
where we can find that the high-pass cut-off f =
frequency , (9)
R Cis: F C
1+ A
ω without
For reference, the overall transfer function = F
Miller
, approximation is given in [39] as: (9)
hpf
RF CC
vo sgm RF CC
For reference, the overall −
transfer function without Miller
R C approximation , is given in [39] as: (10)
vin gm + r1o + s(CL + CC + Fro C ) + s2 RF CC CL
v sg R C
where CL is the load capacitance
o
≅ − of the buffer. Figure 11 m F C
shows an example of the , simulated duty-cycle
vin 1 RF CC 2 (10)
transfer function of an AC-coupled + + s ( C L + CC +
g m inverter. ) + s RF CC C L
r r
On the other hand, the bandwidtho dependency on theo feedback resistance can also be utilized
to control
where CL the delay
is the of capacitance
load a buffer chain. Conventionally,
of the buffer. Figure a current-starved
11 shows an example inverter of[55]the
or simulated
a variable
capacitive-load inverter [56] have been widely
duty-cycle transfer function of an AC-coupled inverter. used to build a variable delay line. However, basically,
theirOn
mechanism
the other is to reduce
hand, the bandwidth
the bandwidth of CMOS
dependency oninverter to increase
the feedback the delay.
resistance As be
can also a result, such
utilized to
delay cells have a lower bandwidth than an inverter, and therefore, they have
control the delay of a buffer chain. Conventionally, a current-starved inverter [55] or a variable usually become the main
limiting factor ofinverter
capacitive-load the maximum[56] havespeedbeenof a chip.
widely Asused
a remedy, [13,40,41]
to build proposed
a variable a resistive-feedback
delay line. However,
based delay line whose delay is controlled by adjusting the feedback
basically, their mechanism is to reduce the bandwidth of CMOS inverter to increase the resistance. As we observed in (7)
delay. As a
and Figure 9b, the feedback extends the bandwidth of an inverter. That means
result, such delay cells have a lower bandwidth than an inverter, and therefore, they have usually that the resistive-feedback
delay line
become theactually increases
main limiting theofbandwidth
factor the maximum to adjust
speedtheof adelay,
chip. instead of reducing
As a remedy, the proposed
[13,40,41] bandwidth. a
From another qualitative viewpoint of large signal, the resistive feedback decreases
resistive-feedback based delay line whose delay is controlled by adjusting the feedback resistance. the voltage swing;
therefore,
As the output
we observed in (7)rise/fall
and Figuretime 9b,
is reduced. References
the feedback extends [13,40] verified theoflarge-signal
the bandwidth an inverter.effect
That as well,
means
suchthe
that that the resistive feedback
resistive-feedback reduces
delay line ISI considerably
actually increases the compared
bandwidthtotothe conventional
adjust the delay, delay
insteadline,
of
at the cost of increased power consumption due to the short-circuit current
reducing the bandwidth. From another qualitative viewpoint of large signal, the resistive feedback induced by the reduced
voltage swing.
decreases the voltage swing; therefore, the output rise/fall time is reduced. References [13,40]
verified the large-signal effect as well, such that the resistive feedback reduces ISI considerably
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 10 of 15

compared to the conventional delay line, at the cost of increased power consumption due to the
short-circuit current induced by the reduced voltage swing.
J. Low Power Electron. Appl. 2019, 9, 26 10 of 15

4. Output Driver for High-Speed Wireline Communication


4. Output Driver
The last for High-Speed
example is the outputWireline Communication
driver for high-speed I/O link. On the right side of Figure 12, we
can find
The alastconceptual
examplediagramis the outputof a source-series terminatedI/O
driver for high-speed (SST)link.driver,
On the which
rightissidealsoofknown
Figureas12, a
voltage-mode
we driver [35–50].
can find a conceptual Instead
diagram of of relying on a parallel
a source-series terminatedresistance to match
(SST) driver, the driver’s
which output
is also known
impedance with the characteristic impedance of the transmission
as a voltage-mode driver [35–50]. Instead of relying on a parallel resistance to match the driver’s channel, the SST driver adopts
series
outputtermination.
impedance with Suchthe series-terminated
characteristic impedancedata transmission is conceptually
of the transmission channel,enabled with aadopts
the SST driver series
combination
series termination.of a 50-Ω Such resistance and an ideal
series-terminated dataswitch driven by
transmission NRZ data. The
is conceptually main advantage
enabled with a series of
SST driver over the parallel-termination counterpart, which is represented
combination of a 50-Ω resistance and an ideal switch driven by NRZ data. The main advantage of SST by current-mode logic
(CML)
driver overdriver,
theisparallel-termination
its low-power consumption. counterpart, Assuming
which isterminations
represented by at both transmit logic
current-mode and receive
(CML)
sides
driver,(double termination),
is its low-power the series termination
consumption. Assuming flows the signal
terminations current
at both to 100-Ω
transmit andresistance
receive sides(I =
(double termination), the series termination flows the signal current to 100-Ω resistance (I = Vswing /100),
V swing /100), whereas the parallel termination flows to 25 Ω (I = V swing /25). As a result, the parallel
termination
whereas the dissipates 4× higher current
parallel termination flows toto Ω (I = Vaswing
25achieve same /25).
voltage
As a swing.
result, the On parallel
the other hand, the
termination
main downside of SST driver originates to the fact that there is no
dissipates 4× higher current to achieve a same voltage swing. On the other hand, the main downside ideal switch in IC. There are two
types
of SSTof practical
driver SST implementation,
originates to the fact that there N-over-N and P-over-N
is no ideal switch in configurations,
IC. There are two as types
shown ofin Figure
practical
12.
SSTItimplementation,
is well known N-over-N that the N-over-N
and P-over-N works well only foraslow
configurations, shown swing applications,
in Figure 12. It iswhereas
well known the
P-over-N is appropriate for higher swing applications. Note that
that the N-over-N works well only for low swing applications, whereas the P-over-N is appropriate the P-over-N structure is a CMOS
inverter.
for higherBasically, their approach
swing applications. Note is that
the same. Instead structure
the P-over-N of using an is aideal
CMOS 0-Ωinverter.
switch, they utilizetheir
Basically, the
finite
approach resistance of switch
is the same. Insteadtransistor;
of using if an
theideal
turn-on
0-Ω resistance
switch, they equals
utilize to the
50-Ω, a single
finite transistor
resistance can
of switch
work as the
transistor; combination
if the turn-on resistanceof the equals
ideal switch
to 50-Ω,and the resistor.
a single transistorThe 50-Ω as
can work impedance
the combinationis generally
of the
calibrated
ideal switch byand
adjusting the number
the resistor. The 50-Ω ofimpedance
activated driver slices calibrated
is generally and the gate-overdrive
by adjusting the voltage.
number The
of
main challenge here is the non-linear nature of CMOS transistor does
activated driver slices and the gate-overdrive voltage. The main challenge here is the non-linear nature not let the transistors have a
constant
of CMOSresistance
transistorover doesthe notswing
let therange [42]. For
transistors have example,
a constant when the output
resistance overvoltage
the swing increases, the
range [42].
V
For of the pull-down
DS example, when theNMOS (MN1, Mincreases,
output voltage N3) increases the Vand
DS causes
of the the
pull-down NMOS to
NMOS fall(M into
N1 , the
M N3 saturation
) increases
region,
and causes where thethe
NMOS output impedance
to fall into the becomes
saturation very high.where
region, Note that the linearity
the output impedance is a function
becomes of very
VDS,
and
high.the VDSthat
Note rangetheequals
linearitytheisoutput swing.
a function of VDS , and the VDS range equals the output swing.

12.Conceptual
Figure 12.
Figure diagram
Conceptual of source-series
diagram terminated
of source-series (SST) driver(SST)
terminated and practical
driver implementation
and practical
of N-over-N and P-over-N SST configurations.
implementation of N-over-N and P-over-N SST configurations.

To resolve
To resolve this
this issue,
issue, aa series
series resistance is placed
resistance is at the
placed at the output
output of
of the
the SST
SST driver,
driver, as
as shown in
shown in
Figure 13 [37,46–48]. The turn-on resistance of the transistor is reduced here (i.e., 25 Ω) to make
Figure 13 [37,46–48]. The turn-on resistance of the transistor is reduced here (i.e., 25 Ω) to make the the
sum with the series resistance be 50 Ω. The series resistor takes charge of a portion of the output swing,
hence, the VDS of the transistors is reduced. The downside of this approach is the increased transistor
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 11 of 15
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 11 of 15

sum
J. with the series
Low Power Appl.resistance
2019, 9, 26 be 50 Ω. The series resistor takes charge of a portion of the output
sum with Electron.
the series resistance be 50 Ω. The series resistor takes charge of a portion of the output 11 of 15
swing, hence, the VDS of the transistors is reduced. The downside of this approach is the increased
swing, hence, the VDS of the transistors is reduced. The downside of this approach is the increased
transistor size. If 25-Ω resistance is used, the size of transistor is doubled so that both the input
transistor
size. If 25-Ωsize. If 25-Ωisresistance
resistance used, the is used,
size the size isofdoubled
of transistor transistor is doubled
so of
that both the soinput
that capacitance
both the input
capacitance and the output self-capacitance are doubled, each which increases burdens of and the
capacitance
the and the outputare
output self-capacitance self-capacitance
doubled, each are doubled,
of which each of whichofincreases
increases burdens of the
pre-driver stage and degrades the bandwidth of the driver burdens the pre-driver
itself, respectively. Notestage
that and
the
pre-driver
degrades stage and degrades the bandwidth of the Note
driverthatitself, respectively. Noteoperate
that the
transistorsthe bandwidth
should operateofinthethedriver
linearitself,
regionrespectively.
for better linearity, the transistors
where the current should
density is much in
transistors
the linear should
region foroperate
better in the
linearity,linear region
where the for better
current linearity,
density is muchwhere
lowerthe current
than that density
in the is much
saturation
lower than that in the saturation region. Therefore, the device size is generally enormously large.
lower
region.than that in the
Therefore, the saturation
device sizeregion. Therefore,
is generally the device
enormously size is generally enormously large.
large.

VDD
VDD

50=>25
50=>25
25
25
in
in out
out
50=>25
50=>25

Figure 13. SST driver with series resistance.


SST driver
Figure 13. SST driver with series resistance.

Rather than
Rather than puttinga aseries
series resistor, it has been proposed that using a feedback resistor can
Rather thanputting
putting a series resistor, it has
resistor, beenbeen
it has proposed that using
proposed a feedback
that using resistorresistor
a feedback can change
can
change
the gamethe game [13,40,44,50], which is shown in Figure 14. As we studied, the feedback resistor sets
change the[13,40,44,50], which which
game [13,40,44,50], is shown in Figure
is shown 14. As14.
in Figure weAsstudied, the feedback
we studied, the feedbackresistor setssets
resistor the
the biasing
biasing point point
that thatCMOS
the the CMOS
operates operates
in the in the saturation
saturation region. region.
In In the
addition, addition,
DC the DC
output output
impedance
the biasing point that the CMOS operates in the saturation region. In addition, the DC output
impedance
becomes becomes
1/gbecomes 1/gm,1/g
m , instead
instead of 1/g ds. That means we can achieve a high current density of the
impedance 1/gof ds . That
m, instead
means
of 1/g we can achieve a high current density of the
ds. That means we can achieve a high current density of the
saturation
saturation region
region andregion and
a low output a low output
impedance impedance from 1/g as well. In addition, the g is easy to by
be
output from 1/gm asfrom
well.1/g
Inmaddition,
m theaddition,
gm is easy to gbe
m regulated
saturation and a low impedance as well. In the m is easy to be
regulated
using by using a well-known
a well-known constant-g bias circuit [13,57].
regulated by using aconstant-g
well-known m bias circuit mm[13,57].
constant-g bias circuit [13,57].

Figure 14.
Figure Output driver
14. Output driver based
based on
on resistive-feedback
resistive-feedback inverter.
inverter.
Figure 14. Output driver based on resistive-feedback inverter.
Although
Although the
the feedback resistance does
feedback resistance does not
not affect
affect the
the DC
DC output
output impedance, the high-frequency
impedance, the high-frequency
Although
output the feedback resistance does notloss
affect the DC output impedance, theof
high-frequency
output impedance, which affects the return loss of the transmitter, is a function of the
impedance, which affects the return of the transmitter, is a function the feedback
feedback
output impedance,
resistance. The which
output affects is
impedance the return loss
calculated as: of the transmitter, is a function of the feedback
resistance. The output impedance is calculated as:
resistance. The output impedance is calculated as:
11 11 ++sRsR C
F Cin
ZZout ≅ 1 1 ·⋅ 1 + sRFF C1inin , , (11)
Z out ≅ gm + r1o ⋅1 + sRF Cin ( gm ro +11 ) ,
out
(11)
g m + 1 1 + sRF Cin ( 1 ) (11)
g m + r 1 + sRF Cin ( g r + 1)
where Cin is the input capacitance of the driverro[50].
o
We can find roo +the
g mmthat 1 feedback introduces both zero
1 g r
m o + 1
(at RF C ) and pole (at RF C ). As a result, the output impedance becomes ro at a very high frequency.
in in
J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 12 of 15

where Cin is the input capacitance of the driver [50]. We can find that the feedback introduces both
1
J. Low Power Electron. Appl. 2019, 9, 26 g m ro + 1 12 of 15
zero (at ) and pole (at ). As a result, the output impedance becomes ro at a very
RF Cin RF Cin
Therefore,
high frequency. a designer should
Therefore, a carefully
designer chooseshould acarefully
proper Rchoose F such a that guarantees
proper RF suchthe zero
that frequencythe
guarantees is
higher than the Nyquist frequency of the transmit
zero frequency is higher than the Nyquist frequency of the transmit data. data.
On the theother
otherhand,
hand,there
therearearetwo downsides
two downsides of theof resistive-feedback
the resistive-feedback SST driver; low output
SST driver; swing
low output
and power
swing and powerconsumption. Since the
consumption. Sincetransistor should
the transistor operate
should in thein
operate deep
the saturation
deep saturationregionregion
to haveto
high r
have high o , the output impedance deviates
ro, the output impedance deviates from from 1/g m , which is maintained by the constant-g
1/gm, which is maintained by the constant-g m biasing, m

when
biasing, thewhen outputthe swing increases.
output swingItincreases.
also dissipates
It also a higher current
dissipates than that
a higher of the conventional
current than that of SST the
driver due to the
conventional SSTshort-circuit
driver due to current. However, as
the short-circuit the dataHowever,
current. rate increases,
as thethe pre-driver’s
data dynamic
rate increases, the
switching power,
pre-driver’s dynamicwhichswitching
is consumed for driving
power, which high input capacitance,
is consumed for driving dramatically
high input increases. Note
capacitance,
that the dynamic
dramatically powerNote
increases. is proportional
that the dynamic to the switching frequency and
power is proportional capacitance,
to the switching whereasand
frequency the
driver’s current consumption is fixed regardless of
the capacitance, whereas the driver’s current consumption is fixed regardless the data rate (I = V /100Ω).
swing of the data rate (I it
As a result, =
Vsurpasses
swing/100Ω). theAs static poweritconsumption
a result, surpasses theofstatic the output
power driver [42]. Asofa result,
consumption the outputthe pre-driver
driver [42]. power
As a
reduction,
result, thethanks to the small
pre-driver power input capacitance
reduction, of the to
thanks resistive-feedback
the small input SST driver, is able to
capacitance of fully
the
compensate the increased static power.
resistive-feedback SST driver, is able to fully compensate the increased static power.
Another advantage of this driver is a simple slicing implementation because of its inherent
current-driven nature.
current-driven nature.InInthe conventional
the conventional drivers
drivers(including
(including CMLCML and SST), the output
and SST), driver should
the output driver
be slicedbe
should to control
sliced to the control
swing and thethe equalization
swing and thecoefficient;
equalization thus,coefficient;
it increases thethus,complexity
it increasesand the
parasitic.
complexity On andthetheother hand, On
parasitic. in thetheresistive-feedback
other hand, in the SST driver, the slicing
resistive-feedback SSTcan be included
driver, the slicingin can
the
current-mode pre-driver as shown in Figure 15. That is, a simple
be included in the current-mode pre-driver as shown in Figure 15. That is, a simple current current digital-to-analog convertor
(DAC) in the pre-driver
digital-to-analog convertor can(DAC)
replaceinthe theslicing at thecan
pre-driver output
replacestage;
the thus,
slicingit at
significantly
the output reduces the
stage; thus,
design
it complexity
significantly and parasitic
reduces the design effects. It has also
complexity andbeen proven
parasitic that the
effects. current
It has alsoDAC-based
been proven pre-driver
that the
is beneficial
current for pulse-amplitude
DAC-based modulation
pre-driver is beneficial for signaling
pulse-amplitude in [40], modulation
where a fabricated
signaling28-Gb/s
in [40],PAM-4
where
atransmitter
fabricatedchip is presented.
28-Gb/s PAM-4 transmitter chip is presented.

Figure 15. Current-mode pre-driver for resistive-feedback SST driver.


Figure 15. Current-mode pre-driver for resistive-feedback SST driver.
5. Conclusions
5. Conclusions
This paper introduces three state-of-the-art applications of CMOS inverter with resistor feedback,
This paper
by providing introduces
the basic theoriesthree state-of-the-art
of those applications applications of CMOS implementation
and the state-of-the-arts inverter with resistor
results.
feedback,
The focus ofby
thisproviding
paper is not the
justbasic theoriestheofprior
enumerating those
arts,applications and the
but emphasizing thepotential
state-of-the-arts
of CMOS
implementation results.
inverter as an analog The
circuit. Asfocus of this
discussed in thepaper is not just
introduction, CMOS enumerating the prior
inverter becomes more arts, but
powerful
emphasizing
whereas the potentialanalog
the conventional of CMOS inverter
circuits become as less
an analog circuit.
effective As discussed
as technology scales in the introduction,
down. As a result, I
J. Low Power Electron. Appl. 2019, 9, 26 13 of 15

believe that there are a lot of undiscovered usages of the CMOS inverter, which will need thorough
examination in future research.

Funding: This research received no external funding.


Conflicts of Interest: The authors declare no conflict of interest.

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