CAD FOR VLSI PHYSICAL LAB

FOR VII SAM.

B.TECH

Submitted To : Submitted By :
Mr.Mukesh Yadav Mahipal Khoja
Assistant Professor 16ESBCS007

DEPARTMENT OF CSE

SRI BALAJI COLLEGE OF ENGINEERING & TECHNOLOGY

JAIPUR,302013
 TABLE OF CONTENT

Name of Experiment Page

1. Introduction 01
2.Design and study basic gate in CADENCE tools 06

3.Basic Concept of the Placement & Routing 14

4.Auto Place and Route Using SOC Encounter 24

5.Physical Level Design using Synopsys 35

 INTRODUCTION
1.1 Introduction
The intentions for this manual are to serve as an introduction to the Cadence design environment
and describe the methododology used when designing integrated circuits. The department is not
giving courses in Cadence but in integrated circuit design so only the minimum knowledge,
needed to run the laboraties, of Cadence can be gained from this manual. Also this manual
describes the environment currently at the department which is Cadence version 4.45 in
conjunction witch a Design Kit from AMS (Austria Mikro System International AG) which
contains a set of rules and designs for a 0.35 μm CMOS process. For a more thorough
understanding of Cadence the extensive on line manual set is recommended. These are accessed
from any of the tools by pressing the help button. More information about the topics in the first
two chapters can be found in the manuals Design Framework II Help and Cadence Application
Infrastructure User Guide.
The Cadence tool kit consists of several programs for different applications such as schematic
drawing, layout, verification, and simulation. These applications can be used on various
computer platforms. The open architecture also allows for integration of tools from other vendors
or of own design. The integration of all this tools is done by a program called Design Framework
II (DFW).The DFW-application is the cornerstone in the Cadence environment. It provides a
common user interface and a common data base to the tools used. This makes it possible to
switch between different applications without having to convert the data base.
This chapter will give an overview of the user interface supplied by DFW and present some of
the Cadence tools that will be used.

1.2 Cadence User Interface

In Cadence the user interface is graphic and based on windows, forms, and menues.
The main windows of DFW are:
_ Command Interpreter Window (CIW) is controlling the environment. Other tools can be started
from here and it also serves a log window for many applications.
_ Library Manager gives a view of the design libraries and the different constructions that exists
therein.
_ Design Window (DW) shows the current design. It is possible to have several DW opened at
the same time with different, or the same, tools.
Text Window (TW) shows text. It can be a log or report that was asked for, or an editor. The
menus in Cadence are mostly pull-downs, i.e. the menu will appear when the title is clicked with
the left button on the mouse. There are also pop-up menus that appear in the background of the
design window on a middle button press. The forms are used for entering some specific
information that is needed by the function called, the size of a transistor for instance.

1.3 The Design Process

Figure 1.1: An inverter cell with three views: layout, schematic, and symbol.

1.3.1 Libraries and Views

All design data in Cadence are organized in libraries. There are Reference Libraries which
contains basic building blocks usable in the construction and Design Libraries which embodies
the current design. Every library consists of cells and their different views, as in figure 1.1. A cell
is a database object which forms a building block, an inverter for instance. A view represents
some level of abstraction of the cell. It can be a schematic drawing,
1.3.2 Instances and Hierarchy
The main reasons for using hierarchical designs are to save design time and minimize the size of
the data base. Say that a design would need 500 gates of the same type. Then instead of building
it 500 times, it is designed once and then used were it is needed. In this way one cell can be used
(not copied) several times and each such use is called an instance of the cell. In order to be in
stanciated every cell needs a symbol view which acts as a handle to the cell it represents. Only
the symbol is shown when a cell is instanciated. Thus by creating more complex structures by in
stanciating simple instances a hierarchical design is formed. It is possible to move up and down
and work on a selected level in the hierarchy. When a design is opened, the highest level is the
default one.

1.3.3 The Technology File

Since there are different semiconductor processes (with different set of rules and properties),
Cadence has to know the specifications for the one that is to be used. This information is stored
in a set of files called Technology Files which exists on different locations on the system. When a
library is created it is I there fore connected to a specific technology. The technology files
contains information about:
Layer definitions: Conductors, contacts, transistors...
Design rules: minimum size, distance to objects...
Display: Colours and patterns to use on the screen.
Electrical properties: resistance, capacitance...
The technology files are usually supplied by the silicon vendor that is to fabricate the design,
along with some libraries of standard cells and IO pads that can be used by the designer. Such a
collection is called a Design Kit.

1.3.4 The SKILL Programming Language

When a command is performed, from a form or a menu, the system is executing functions
written in the SKILL language. SKILL is developed by Cadence and is based on Lisp. The
Cadence tools are using SKILL for internal communication and for the tool-design
communication. SKILL is also accessible for the designers. Commands can be written in the
CIW window or placed in command files for execution. it can be used for simple tasks like
executing a command or building more complex functions to perform various tasks.

1.3.5 The Design Flow

The abbreviated flow in figure 1.2 shows some of the steps in designing integrated circuits in the
Cadence environment.
 Figure 1.2: The design flow.

The step Create the Design consists of drawing schematic views of all cells and blocks. The
schematic view contains transistor symbols and maybe other components such as resistors and
capacitances, and wires connecting them. From the schematic view the symbol view is created
(almost automatically) so that the cell can be used on a higher level in the hierarchy.

1.4 Schematic and Symbol tools

The step Analyze the design includes functional verification (simulation) of the Design on a
schematic level. The third step, Create Layout, is done in a Layout Editor. Here the final
semiconductor layers are represented by different colours. All the cells and blocks used have the
size they will have on the final chip. The last step is Verification of the design. The layout is
examined for violations against the geometric or electrical rules, and to verify the function of the
physical implementation.
To create the schematic the tool Virtuoso Schematic Composer is used. This editors an
interactive system for building schematics by instantiating some basic components (transistors,
capacitances, etc.) and to connect them to each other. The values (properties) of the components
can be edited to suit the specifications. Text and comments can also be included. The editor will
also create symbols of the cells so that they can be used in other parts of the construction.

1.5 Simulation
The simulation tool is started directly from the schematic editor and all the necessary net lists
describing the design will be created. A simulation is usually performed in a test bench, which is
also a schematic, with the actual design included as an instance. The test bench also includes
signal sources and power supply. Busing parameters for the properties of the components used it
is possible to quickly analyze the design for a vide range of variables.
The simulator is run from with in Affirma Analog Circuit Design Environment which is a tool
that handles the interface between the user and the simulator. The current version of Cadence
used at the department uses the AffirmaSpectre Circuit Simulator. The simulator offers a wide
range of analyses (DC, frequency sweep, transient, noise, etc.) and the results can be presented
graphically and be saved. The results (voltage levels, currents, noise, etc.) can be fed into a
calculator which can present various parameters of the analyzed circuit - delay time, rise time,
slew rate, phase margin, and many other interesting properties. It is also possible to setup
algebraic expressions of in or output signal which can be plotted as a function of some other
variable.

1.6 Layout Tool

The Virtuoso Layout Editor is used for drawing the layout. A layout consists of geometrical
figures in different colours. From the size and color of these figures it’s later possible to generate
the final mask layers which are used in the fabrication of the design. It is possible to include
other cells by instantiating their layout views. To verify that the layout fulfills all electrical and
geometric rules a Design Rule Check (DRC) program is used. This manual will describe Assure
Diva verification which can be called upon directly from the layout editor. This tool will mark
any error in the design and can also extract (i.e. convert to a net list) the layout so it cane
simulated.

1.7 Place and Route

The final stage of the construction of a large design is called place and route. This is the process
when all the different components of the chip is placed on its locations and connected to each
other. Since a design can easily consist of thousands of connection points it would be tedious and
time consuming to do the connections manually. The designer might also want to try various
alternatives in placing the components, output buffers, memory structures, amplifiers, etc. The
place and route tool that will be described later in this manual is named Envisia Silicon
Ensemble. It is a very potent program that that can place and route a very large design while
respecting some design constraints (restrictions on delay and size) at the same time
 Design and study basic gate in
CADENCE tools
2.1 An Overview of VLSI CAD Tools
VLSI designers have a wide variety of CAD tools to choose from, each with their own Strengths
and weaknesses. The leading Electronic Design Automation (EDA) companies include Cadence,
Synopsys, Magma, and Mentor Graphics. Tanner also offers commercial VLSI design tools. The
leading free tools include Electric, Magic, and LASI. This set of laboratories uses the Cadence
and Synopsys tools because they have the largest market share in industry, are capable of
handling everything from simple class projects to state-of-the-art integrated circuits. The full set
of tools is extremely expensive (on the order of $1M per user), but the companies offer academic
programs to make the tools available to universities at a much lower cost. The tools run on Linux
and other flavors of UNIX. Setting up and maintaining the tools involve a substantial effort.
However, Erik Brunvand’s book, Digital VLSI Chip Design with Cadence and Synopsys CAD
Tools, greatly reduces the difficulty of learning to install and use the tools. Once they are setup
correctly, the basic tools are easy to use, as this tutorial demonstrates. Some companies use the
Tanner tools because their list price is much lower and they are easy to use. However, their
academic pricing is comparable with Cadence and Synopsys, giving little incentive for
universities to adopt Tanner. The Electric VLSI Design System is an open-source chip design
program developed by Steve Rubin with support from Sun Microsystems. It is written in Java
and hence runs on virtually any operating system, including Windows, Linux, and Mac. It is easy
to use with older fabrication processes and was used in previous incarnations of this lab. Electric
presently does not read the design rules for state-of-the-art nanometer processes and poorly
integrates with synthesis and place & route. Magic is a free Linux-based layout editor with a
powerful but awkward interface that was once widely used in universities. The Layout System
for Individuals, LASI, developed by David Boyce, is freely available and runs on Windows. It
was last updated in 1999.There are two general strategies for chip design. Custom design
involves specifying however transistor is connected and physically arranged on the chip.
Synthesized design involves describing the function of a digital chip in a hardware description
language such as Virology or VHDL, then using a computer-aided design tool to automatically
generate asset of gates that perform this function, place the gates on the chip, and route the wires
to connect the connect the gates. The majority of commercial designs are synthesized today
because synthesis takes less engineering time. However, custom design gives more insight into
how chips are built and into what to do when things go wrong. Custom design also offers higher
performance, lower power, and smaller chip size. The first two labs emphasize the fundamentals
of custom design, while the next two use logic synthesis
And automatic placement to save time.

2.2 Tool Setup

These labs assume that you have the Cadence and Synopsys tools installed.
Tools generate a bunch of random files. It’s best to keep them in one place. In your home
directory, create some directories by typing:
Midair IC_CAD
Midair IC_CAD/cadence

2.2.1 Getting Started

Before you start the Cadence tools, change into the cadence directory:
Cod ~/IC_CAD/cadence
Each of our tools has a startup script that sets the appropriate paths to the tools and invokes them.
Start Cadence with the NCSU extensions by runningcad-ncsu&a window labeled if will open up.
This is the Integrated Circuit Front and Back End (e.g. schematic and layout) software, part of
Cadence’s Design Framework interface. A “What’s New” and a Library Manager window may
open up too. Scroll through the if window and look at the messages displayed as the tool loads
up. Get in the habit of watching for the messages and recognizing any that are out of the
ordinary. This is very helpful when you encounter problems. All of your designs are stored in a
library. If the Library Browser doesn’t open, choose Tools • Library Manager. You’ll use the
Library Manager to manipulate your libraries. Don’t try to move libraries around or rename them
directly in Linux; there is some funny behavior and you are likely to break them. Familiarize
yourself with the Library Manager. Your cds.lib file includes many libraries from the NCUS
CDK supporting the different MOSIS processes. It also includes libraries from the University of
Utah. The File menu allows you to create new libraries and cells within a library, while the Edit
menu allows you to copy, rename, delete, and change the access permissions. Create a library by
invoking File • New • Library… in the Library Manager. Name the library lab1_xx, where xx are
your initials. Leave the path blank and it will be put in your current working directory
(~/IC_CAD/cadence). Choose the “Attach to existingtech library” and accept the default, Tofu
AMI 0.60u C5N (3M, 2P, high-res). This is technology file for the American Microsystems (now
Orbit Semiconductor) 0.6 μmprocess, containing design rules for layout.

2.2.2 Schematic Entry

Our first step is to create a schematic for a 2-input NAND gate. Each gate or larger component is
called a cell. Cells have multiple views. The schematic view for a cell built with CMOS
transistors will be called cmos_sch. Later, you will build a view called layout specifying how the
cell is physically manufactured. In the Library Manager, choose File • New • Cell View… In
your lab1_xx library, entera cell name of nand2 and a view name of cmos_sch. The tool should
be Composer-Schematic. You may get a window asking you to confirm that cmos_sch should be
associated with this tool. The schematic editor window will open. Your goal is to draw a gate like
the one shown in Figure 1. We are working in a 0.6 μmprocess with λ = 0.3 am. Unfortunately,
the University of Utah technology file is configured on a half-lambda grid, so grid units are 0.15
am. Take care that everything you do is an integer multiple of λ so you don’t come to grief later
on. Our NAND gate will use 12 λ (3.6 am) moms and pros transistors. Choose Add • Instance to
open a Component Browser window. (The menu lists the keyboard shortcut for each command,
such as I for add instance. You’ll want to learn the shortcuts you use most often.) Choose
UofU_Analog_Parts for the library, then selectnmos. The Add Instance dialog will open. Set the
Width to 3.6u (u indicates microns).Click in the schematic editor window to drop the transistor.
You can click a second time to place another transistor. Return to the Component Browser
window and choose pmos.Drop two pros transistors. Then return to the browser and get a god
and a add symbol. When you are in a mode in the editor, you can press ctrl-c or Esc to get out of
it. Other extremely useful commands include Edit • Move, Edit • Copy, Edit • Undo, and Edit
•Delete. Edit • Properties • Object… is also useful to change things like transistor sizes orwire
names. Move the elements around until they are in attractive locations. I like to keep series
transistors one grid unit apart and place pros transistors two grid units above the moms. Look at
the bottom of the schematic editor window to see what mode you are in. Next, use Add • Pin…
to create some pins. In the Add Pin dialog, enter a and b. Make sure the direction is “input.” The
tools are case-sensitive, so use lower case everywhere. Place the pins, being sure that a is the
bottom one. Although pin order doesn’t matter logically, it does matter physically and
electrically, so you will get errors if you reverse the order. Then place an output pin y.

Figure 2.1: nand2 cmos_sch

Now, wire the elements together. Choose Add • Wire (narrow). Click on each component and
draw a wire to where it should connect. It is a good idea to make sure every net (wire) in a design
has a name. Otherwise, you’ll have a tough time tracking down a problem later on one of the
unnamed nets. Every netting your schematic is connected to a named pin or to power or ground
except the net between the two series mom’s transistors. Choose Add • Wire name… Enter mid
or something like that as the name, and click on the wire to name it. Choose Design • Check and
Save to save your schematic. You’ll probably get one warning about a “solder dot on crossover”
at the 4-way junction on the output node. Thesis annoying because such 4-way junctions are
normal and common. Choose Check •Rules Setup… and click on the Physical tab in the dialog.
Change Solder OnCrossOverfrom “warning” to “ignored” and close the dialog. Then Check and
Save again and the warning should be gone. If you have any other warnings, fix them. A
common mistakes wires that look like they might touch but don’t actually connect. Delete the
wire and redraw it. Poke around the menus and familiarize yourself with the other capabilities of
the schematic editor.

2.3 Logic Verification

Cells are commonly described at three levels of abstraction. The register-transfer level (RTL)
description is a Virology or VHDL file specifying the behavior of the cell in terms of registers
and combinational logic. It often serves as the specification of what the chip should do. The
schematic illustrates how the cell is composed from transistors or other cells. The layout shows
how the transistors or cells are physically arranged. Logic verification involves proving that the
cells perform the correct function. One way to do this is to simulate the cell and apply a set of 1’s
and 0’s called test vectors to the inputs, then check that the outputs match expectation. Typically,
logic verification is done first on the RTL to check that the specification is correct. A test bench
written in Verilog or VHDL automates the process of applying and checking all of the vectors.
The same test vectors are then applied to the schematic to check that the schematic matches the
RTL. Later, we will use a layout-versus schematic (LVS) tool to check that the layout matches
the schematic (and, by inference, the RTL).You will begin by simulating an RTL description of
the NAND gate to become familiar with reading RTL and understanding a test bench. In this
tutorial, the RTL and testbench are written in System Virology, which is a 2005 update to the
popular Virology hardware description language. There are many Virology simulators on the
market, including NC-Virology from Cadence, VCS from Synopsys, and Models from Mentor
Graphics. This tutorial describes how-to use NC-Virology because it integrates gracefully with
the other Cadence tools. NCVerilog compiles your Virology into an executable program and runs
it directly, making it much faster than the older interpreted simulators. Make a new directory for
simulation (e.g. nand2sim). Copy nand2.sv, nand2.tv, and test fixture. verilog from the course
directory into your new directory.
mkdir nand2sim
cd nand2sim
cp /courses/e158/10/nand2.sv .
cp /courses/e158/10/nand2.tv .
cp /courses/e158/10/nand2.testfixture testfixture.verilog
nand2.sv is the SystemVerilog RTL file, which includes a behavioral description of anand2
module and a simple self-checking test bench that includes testfixture. verilog. testfixture.verilog
reads in test vectors fromnand2.tv and applies them to pins of the nand2 module. After each
cycle it compares the output of the nand2 module to the expected output, and prints an error if
they do not match. Look over each of these files and understand how they work. First, you will
simulate the nand2 RTL to practice the process and ensure that the testbench works. Later, you
will replace the behavioral nand2 module with one generated from your Electric schematic and
will resimulate to check that your schematic performs the correct function. At the command line,
type sim-nc nand2.sv to invoke the simulator. You should see some messages ending with
ncsim> run Completed 4 tests with 0 errors. Simulation stopped via $stop(1) at time 81 NS +
0You’ll be left at the ncsim command prompt. Type quit to finish the simulation. If the
simulation hadn’t run correctly, it would be helpful to be able to view the results.NC-Verilog has
a graphical user interface called SimVision. The GUI takes a few seconds to load, so you may
prefer to run it only when you need to debug. To rerun the simulation with the GUI, type sim-ncg
nand2.svA Console and Design Browser window will pop up. In the browser, click on the
+symbol beside the test bench to expand, and then click on dut. The three signals, a, b, and y,will
appear in the pane to the right. Select all three, then right-click and choose Send to Waveform
Window. In the Waveform Window, choose Simulation • Run. You’ll seethe waveforms of your
simulation; inspect them to ensure they are correct. The 0 errors message should also appear in
the console. If you needed to change something in your code or test bench or test vectors, or
wanted to add other signals, do so and then Simulation • Re invoke Simulator to recompile
everything and bring you back to the start. Then choose Run again. Make a habit of looking at
the messages in the console window and learning what is normal. Warnings and errors should be
taken seriously; they usually indicate real problems that will catch you later if you don’t fix
them.

2.4 Schematic Simulation

Next, you will verify your schematic by generating a Verilog deck and pasting it into the RTL
Verilog file. While viewing your schematic, click on Tools • Simulation • NCVerilogto open a
window for the Verilog environment. Note the run directory (e.g.nand2_run1), and press the
button in the upper left to initialize the design. Then press then ext button to generate a netlist.
Look in the icfb window for errors and correct them if necessary. You should see that the pmos,
nmos, and nand2 cells were all netlisted. In your Linux terminal window, cd into the directory
that was created. You’ll find quitea few files. The most important are Verilog input files,
testfixture. template, and test fixture.verilog. Each cell is net listed into a different directory
under ihnl. verilog.inpfiles states where they are. Take a look at the net list and other files.
testfixture.template is the top level module that instantiates the device under test and invokes
thetestfixture.verilog. Copy your testfixture.verilog and test vectorsfrom your nand2sim directory
to your nand2_run1 directory using a command suchascp ../nand2sim/testfixture.verilog .cp
../nand2sim/nand2.tv .Back in the Virtuoso Verilog Environment window, you may wish to
choose Setup •Record Signals. Click on the “All” button to record signals at all levels of the
hierarchy.(This isn’t important for the nand with only one level of hierarchy, but will be
helpfullater.)Then choose Setup • Simulation. Change the Simulation Log File to
indicatesimout.tmp –sv. This will print the results in simout.tmp. The –sv flagindicates that the
simulator should accept System Verilog syntax used in the test fixture. verilog. Set the Simulator
mode to “Batch” and click on the Simulate button. You should get a message that the batch
simulation succeeded. This doesn’t mean that it is correct, merely that it run. In the terminal
window, view the simout.tmp file. It will give some statistics about the compilation, and then
should indicate that the 4 tests were completed with0 errors. If the simulation fails, the
simout.tmp file will have clues about the problems. Change the simulator mode to Interactive to
rerun with the GUI. Be patient; the GUI takes several seconds to start and gives no sign of life
until then. Add the waveforms again and run the simulation. You may need to zoom to fit all the
waves. For some reason, SimVision doesn’t print the $display message about the simulation
succeeding with no errors. You will have to read the simout.tmp file at the command line to
verify that the test vectors passed. If you find any logic errors, correct the schematic and re
simulate.
2.5 Symbol
Each schematic can have a corresponding symbol to represent the cell in a higher-level
schematic. You will need to create a symbol for your 2-input NAND gate. When creating your
symbol, it is a good idea to keep everything aligned to the grid; this will make connecting
symbols simpler and cleaner when you need it for another cell. While looking at your nand2
cmos_sch, choose Design • Create Cell view • From Cellview… Choose from cmos_sch to
symbol, and click OK. Cadence will create a generic symbol based on the exports looking
something like Figure 2.

Figure 2.2: nand2 symbol

 .
Figure 2.3: nand2 symbol final version

A schematic is easier to read when familiar symbols are used instead of generic boxes. Modify
the symbol to look like Figure 3. Pay attention to the dimensions of the symbol; the overall
design will look more readable if symbols are of consistent sizes The green body of the NAND is
formed from an open C-shaped polygon, a semicircle, and a small circle. To form the semicircle,
choose Add • Shape • Arc. Experiment with the arc drawing tool. Similarly, Add • Shape • Line
to make the polygon and Add •Shape • Circle to make the output bubble. Move the lines and
terminals around to make it pretty. The Edit • Stretch command may be helpful. Finally, choose
Add • Selection Box… and choose Automatic. This creates a red box around the symbol that will
define where to click to select the symbol when it appears in another schematic.
NOT Gate
Next, design a NOT gate. Name it inv. Draw the cmos_sch and the symbol, as shown
in Figure 5. Make the pMOS width 10 λ and the nMOS width 7 λ.

Figure 2.4: invsch and symbol

 Basic Concept of the Placement &
Routing
3.1 Cell-Based Design Flow

Fig 3.1: Cell-Based Design Flow

3.2 SOC Encounter P&R Flow

 Figure 3.2 SOC Encounter P&R Flow

3.3 IO, P/G Placement

Determine the positions of the PADs
 Functional IO PAD
 Power/Ground PAD
 Corner PAD:- Just for the connection of PAD power rings

Figure 3.3: IO, P/G Placement

3.4 Specify Floorplan

Determine the aspect ratio of the Core and the gap between the PAD and Core
 The Core Utilization is determined in this step
  The final CHIP area is almost determined in this step

Figure 3.4: Specify Floorplan

Determine the related positions of Hard Blocks:- The performance is highly affected

Figure 3.5: Floorplan

Amoeba Placement: - Observe the result of cells and Hard Blocks placement
 Figure 3.6: Amoeba Placement

3.5 Power Planning

Plan the power ring & power stripe:- IR-drop consideration

Figure 3.7 Power Planning

Clock Tree Synthesis

 Figure 3.8: Clock Tree Synthesis

Power Analysis: - IR-drop & electron migration

Figure 3.9: Power Analysis

Power Route:-Connect the power pins of standard cells to the global power lines
 Figure 3.10: Power Route

Add IO Filler

Fill the gap between PADs:- Connect the PAD power rings

Figure 3.11: Add IO Filler

3.6 Routing:-Construct the final interconnections

 Figure 3.12: Routing

Prepare Data in routing

Library

 Physical Library (LEF):- Information of technology, standard cells, Hard

Blocks, and APR
 Timing Library (LIB):-Timing information of the standard cells and Hard
Blocks
 Capacitance Table:-For more accurate RC analysis
 Celtic Library:- For crosstalk analysis
 FireIce/Voltage Storm Library:-For RC extraction and power analysis
 User Data
Gate-Level Netlist (Verilog)
SDC Constraint (*.sdc)
IO Constraint (*.ioc)

3.7 LEF Format – Process Technology

LEF Format – Process Technology: Layer Define

Layer Metal1

TYPE ROUTING;

WIDTH 0.28;

MAXWIDTH 8;

AREA 0.202;

SPACING 0.28;

SPACING 0.6 RANGE 10.0 10000.0;

PITCH 0.66;

DIRECTION VERTICAL;

THICKNESS 0.26;

ANTENNACUMDIFFAREARATIO 5496;

RESISTANCE RPERSQ 1.0e-01;

CAPACITANCE CPERSQDIST 1.11e-04;

EDGECAPACITANCE 9.1e-05;
 END Metal1

Figure 3.13: Layer Define

LEF Format – APR Technology

 Unit
 Site
 Routing Pitch
 Default Direction
 Via Rule

3.8 LEF Format – APR Technology

The placement site gives the placement grid of a family of macros

Figure 3.14: LEF Format

Row Based PR
Figure 3.15: Row Based PR
 Auto Place and Route Using
SOC Encounter
4.1 CHIP-Level Netlist
If your gate-level netlist is generated by “CORE-level synthesis”, you should all the “CHIP-level
module” in it.

Figure 4.1: CHIP-Level Netlist

If your design has a “Hard Block”, you should add an “empty module” for it

 the module name should be the same as the “cell name” of the Hard Block

Figure 4.2 CHIP-Level Netlist

4.2 CHIP-Level Timing Constraint

Figure 4.3: CHIP-Level Timing Constraint

Getting Started

 linux %> ssh -l “user name” cae18.ee.ncu.edu.tw--- Connect to Unix

 unix %> source /APP/cad/cadence/SOC/CIC/soc.csh
 unix %> encounter (Do not run in the background mode !!)

Import Design <Design>

 Design/Design Import
 Verilog Files: your gate-level netlist
 Tot Cell
 LEF Files (*.lef): including all the LEF
 files of cell libraries & hard blocks
 LIB Files (*.lib):
 Max Timing Libraries
 Min Timing Libraries
 Common Model Libraries
 IO Assignment File: *.ioc
 Figure 4.4: Import Design <Design>

Import Design<Timing>
 Capacitance Table File
 Timing Constraint File: *.sdc

Figure 4.5: Import Design<Timing>

Import Design <Power> <IPO/CTS>

 Power Nets
 Ground Nets
  Footprints for In-Place
 Layout Optimization (IPO) and Clock Tree Synthesis (CTS)

Figure 4.6: Import Design <Power> <IPO/CTS>

Import Design <Misc.>

 QX Tech File
 QX Library Directory
 Figure 4.7: Import Design <Misc.> and Floorplan View

4.3 Global Net Connection

 Floorplan/Global Net Connections

Figure 4.8 Global Net Connections

4.4 Specify Floorplan

  Floorplan/Specify Floorplan

Figure 4.9: Specify Floorplan

Specify Scan Chain

encounter %> specifyScanChain ScanChainName
- start {ftname | instPinName}
- start {ftname | instPinName}
encounter %> scantrace
Ex:

Figure 4.10: Scan Chain

Hard Block Placement

 Move/Resize/Reshape floorplan object

Figure 4.11: Hard Block Placement

Edit Block Halo

 Floorplan/Edit Block Halo

 Reserve space without standard cell placement

Figure 4.12: Edit Block Halo

Standard Cell Placement

 Place/Place

Figure 4.13: Standard Cell Placement

4.5 Power Planning – Add Rings
 Floorplan/Custom Power Planning/Add Rings

Figure 4.14: Power Planning – Add Rings

 Floorplan/Custom Power Planning/Add Rings

Figure 4.15: Power Planning – Add Block Rings

Example for Power Rings

Figure4.16: Power Rings

PAD Pins

 Route/SRoute

Figure 4.17: PAD Pins

4.6 Power Planning – Add Stripes
 Floorplan/Custom Power Planning/Add Stripes

Figure 4.18: Power Planning – Floorplan and Add Stripe

Figure 4.19: Power Planning – Add Stripe

 Physical Level Design using Synopsys
Introduction
The very large scale integration of transistors or integrated circuits has occurred since the 1980s.
The process has evolved from the beginning where only one transistor was on a chip, to the point
where there were a small number of devices on the chip such as transistors, resistors, and diodes.
This made it possible to create more than one logic gate and was considered small scale
integration. The next step in the progression towards VLSI was large scale integration in which
there would be several thousand transistors on each chip. This technology has led to very large
scale integration in which millions to hundreds of million transistors are on a single chip such as
a microprocessor. This succession is continuing at Moore’s Law pace and soon there will be
dual-core processors that may reach one billion transistors.
In the early stages of what would eventually become VLSI design, the small number of
transistors allowed human or manual design to occur. As the number of transistors increased and
device dimensions began to shrink, manual design of such systems becomes impractical due to
performance and design time requirements. The amount of evaluation and decision making that
would be required would overwhelm engineers and design teams. Therefore the problem and
focus of this paper is clear: How does one create a complex electronic design consisting of
millions of transistors? The solution is to automate the design process using computer-aided
design (CAD) tools. These tools are necessary for complex designing of VLSI integrated circuits
in which manual design is not possible. CAD tools provide several advantages such as the ability
to evaluate complex conditions in which solving one problem creates other problems. These
tools can also use analytical methods to assess the cost of a decision as well as synthesis methods
to help provide a solution to the problem. Applying CAD tools to the system design process to
propose and analyze solutions to problems allows larger problems to be solved.
The solution of using CAD tools to create complex electronic designs falls under an industry
category: Electronic Design Automation (EDA). The terms can be combined and the process is
then referenced as electronic computer-aided design (ECAD). There are several companies, such
as Cadence® Design Systems, Magma® Design Automation Inc, and Synopsys®, who
specialize in EDA software and CAD tools. Based in Mountain View, California, Synopsys® is a
leading provider of EDA software used to design complex ASICs, FPGAs, and SoCs from
concept to product. The majority of this paper will center on the physical design process and how
the EDA software created by Synopsys® automates parts of the physical design process.

1.1 Design Flow

5.2.1 Overview
It is important to understand where the physical level design process is located in the flow of a
complete system. A generic design flow is shown in Fig 1. This represents the major design
milestones that are involved in the VLSI design flow. From start to finish, the flow defines what
steps and tasks need to be completed and in what order they should be completed. Front-end
design includes most of the steps in the flow prior to physical design. Starting with physical
design and beyond is considered the back-end of the design flow. Therefore, physical design can
be viewed as the bridge between front-end design flow (system specification and functional
design) and back-end design flow, which eventually leads to the fabrication of a design. EDA
software in the form of CAD tools plays a vital role in all stages of the VLSI design flow.
Therefore it is advantageous that the output created at one stage of the flow will be able to
become the input to the next stage. However, the EDA software and tools do not have to be from
the same vendor. If one vendor has a better tool for Functional Verification, but another vendor’s
tool is better for Logic Design, then a set of common input and output standards will allow the
different tools to communicate with each other. The EDA industry has such common standards
so that different tools from different vendors can be used during chip design. Some of these
common standards will be discussed in the physical design flow.

Figure 5.1: Physical Design combined with Layout Verification is part of the final steps in the VLSI
design flow of a system.

The physical design stage of the VLSI design flow is also known as the “place and route” stage.
This is based upon the idea of physically placing the circuits, which form logic gates and
represent a particular design, in such a way that the circuits can be fabricated. This is followed by
connecting the logic with routing (metal). The logic is connected in such a way as to form the
function that was designed prior to physical design. For example, if the output of NAND logic is
connected to the input of INVERTER logic, then the design has been routed to create AND logic.
Each piece of individual logic is placed and connected in a manner that will result in a function
being created that will perform a particular task intended by the system designer. This is a
generic, high level description of the physical design (place/route) stage. Within the physical
design stage, a complete flow is implemented as well. This flow will be described more
specifically, and as stated before, several EDA companies provide software or CAD tools for this
flow. Synopsys® software for the physical design process is called Astro™. The overall goal of
this tool/software is to combine the inputs of a gate-level netlist, standard cell library, along with
timing constraints to create and placed and routed layout. This layout can then be fabricated,
tested, and implemented into the overall system that the chip was designed for.
The first of the main inputs into Astro™ is the gate-level netlist, which can be in the form of
Verilog or VHDL. This netlist is produced during logical synthesis, which takes place prior to the
physical design stage as indicated by Fig 1. Logical synthesis is the combination of the
functional design and logic design stages of the VLSI design flow. The logic synthesis combines
the inputs of RTL code and design constraints to output a final gate-level netlist which can be
interpreted by the physical design tool. The RTL (Register Transfer Level) code is a description
of the architecture or function of the design in terms of data flow between registers [5]. The data
flow between the registers is implemented using combinational logic such as AND, NAND, INV,
etc. The logic synthesis optimizes this combinational logic between the registers based upon the
other input to the logic synthesis tool, which are the design timing constraints. This input
contains timing parameters such as clock speeds and delays that are associated with the inputs
and outputs of the design. These constraints are the result of a system specification for the design
being created The logic synthesis tool is capable of merging the function of a design
implemented through RTL code in the form of Verilog and VHDL as well as the timing
constraints of the design to create an optimized gate-level netlist. The gate-level netlist is then
tested and simulated to verify the logic functionality of the design. Once the design has been
verified, the netlist can then be used by Astro™ to begin the physical design process. This
process is shown in Fig 2 and shows the details behind some of the stages outlined in the generic
VLSI design flow of Fig 1. As described previously, the physical design stage can be seen as the
bridge between front-end design which has just been described and the back-end design flow. A
physical design engineer will assume that the VHDL code and logic synthesized to a target
library has already been completed, and a final gate level netlist has been created. This initial
netlist is also assumed to have been functionally simulated to prove that netlist going into
physical design performs the function given in the system specification. The netlist is considered
“golden” and is the starting/reference point for all stages in the physical design process and
beyond. Meaning that once physical design is complete, the final netlist that is created, which has
all of the components needed (timing/clocks) will be functionally compared to the original netlist
to insure that function has not been changed.
The second of the main inputs into Astro™ is a standard cell library. This is a collection of logic
functions such as OR, AND, XOR, etc. The representation in the library is that of the physical
shapes that will be fabricated.

Figure 5.2: Detailed flow of design steps prior to physical design of system

This layout view or depiction of the logical function contains the drawn mask layers required to
fabricate the design properly. However, the place and route tool does not require such level of
detail during physical design. Only key information such as the location of metal and
input/output pins for a particular logic function is needed. This representation used by Astro™ is
considered to be the abstract version of the layout and the comparison is shown in Fig 3. Every
desired logic function in the standard cell library will have both a layout and abstract view. Most
standard cell libraries will also contain timing information about the function such as cell delay
and input pin capacitance which is used to calculated output loads. This timing information
comes from detailed parasitic analysis of the physical layout of each function at different
process, voltage, and temperature points (PVT). This data is contained within the standard cell
library and is in a format that is usable by Astro™. This allows Astro™ to be able to perform
static timing analysis during portions of the physical design process. It should be noted that the
physical design engineer may or may not be involved in the creating of the standard cell library,
including the layout, abstract, and timing information. However, the physical design engineer is
required to understand what common information is contained within the libraries and how that
information is used during physical design. Other common information about standard cell
libraries is the fact that the height of each cell is constant among the different functions. This
common height will aid in the placement process since they can now be linked together in rows
across the design. This concept will be explained in detail during the placement stage of physical
design.

Figure 5.3: Comparison of layout and abstract views of a logic function. Synopsys

Standard cell libraries can be generated manually or supplied by vendors. There are several
vendors in the EDA industry that supply standard cell libraries based upon a specific process
node and technology such as 0.25um or 0.13um. If generated manually, the cells will need to be
prepared for the physical design process through library preparation which is a separate topic not
discussed in this paper. The physical design engineer assumes that a standard cell library is
available and compatible with Astro™ whether the library was created by a library group or
supplied by a vendor. Other libraries needed during place and route to supplement the design are
input/output (I/O) libraries as well as other custom cells such as RAMs and IP cores that can be
reused.
The third of the main inputs into Astro™ are the design constraints. These constraints are
identical to those which were used during the front-end logic synthesis stage prior to physical
design. These constraints are derived from the system specifications and implementation of the
design being created. Common constraints among most designs include clock speeds for each
clock in the design as well as any input or output delays associated with the input/output signals
of the chip. These same constraints using during logic synthesis are used by Astro™ so that
timing will be considered during each stage of place and route. The constraints are specific for
the given system specification of the design being implemented.
Now that the origin of the three main inputs to Astro™, gate-level netlist, standard cell library,
and design constraints, are realized, what does Astro™ do? An overview of Astro™, since it is a
place and route tool, is to say that it does exactly what was previously stated in the generic VLSI
design flow: the tool places and routes. However, there are some other aspects that need to be
discussed prior to the details of the physical design flow through Astro™. Once this background
information is discussed, the detailed flow can be presented and can be better understood. As
presented previously, a standard cell library is one of the main inputs to Astro™. However, other
libraries are needed as well to make a design complete. The final place and routed layout will
probably contain macro cells such as RAM or IP blocks and pad cells (Input/Output), which
allow signals to enter and exit the chip.
Prior to placement of the standard cells, the placement of all macro, IP blocks, and pad cells
needs to be defined. The tool then places the standard cells automatically based upon the timing
of the design, which is given by the design constraints. Along with the timing, the ability to
connect each standard cell as described in the gate-level netlist is also taken into account so that
overall wire length (RC affect) is reduced. The pins on the standard cells are then physically
connected during the routing stage of the process. This is also based on timing due to the fact that
more timing critical nets such as clocks should have the shortest lengths and non-critical nets can
afford to be longer. This concept is represented by Fig. 4.

Figure 5.4: Visualization of Place and Route. Synopsys

The timing driven placement of cells takes advantage of the common cell height and locates the
standard cells into “placement rows”. Within the rows, cells that are part the timing critical path
based upon the design constraints will be placed closer together so that interconnect delays are
reduced. These placement rows can either be abutted or non-abutted rows. As shown by Fig. 5,
one drawback to non-abutted rows is increase in area due to the gap between standard cell
placement rows. If the rows were abutted, then the cells on the top row would need to be flipped
so that the VDD lines would merge as opposed to VSS shorting with VDD if they are not
flipped. The most common approach is to implement abutted rows to reduce area as well as
increase the metal size of the VDD or VSS connections.
 Figure 5.5: Timing driven placement of standard cells on non-abutted rows. Synopsys

Now that the basic concept of placement has been understood, the background of routing can be
established. In many technologies, there are several levels of aluminum or copper metal that can
be used to provide the connections between all of the cells in the design. When going from one
layer to another, a “via” must be used to make the connection. To prevent metal shorting together
during routing, each metal layer has a preferred direction, either horizontal or vertical. Typically
in routing, the first metal layer is horizontal. As the metal layers increase, the direction alternates
so that any two consecutive metal layers will always be perpendicular to one another. To route
standard cells together, the router uses a grid or routing track to maneuver from point A to point
B. Due to design rules imposed by a fabrication vendor (foundry), the metal routes need to have
a certain minimum width and spacing in order to be manufactured correctly. The routing tracks
are designed to make sure that these width and spacing requirements are achieved. The problem
of routing congestion can then occur if there are more connections to be made than routing tracks
available.
This background information on placement and routing only sketches some of the things that can
be done during the physical design process. There are other problems that need addressed during
the flow in order to complete a design. These problems include what to do in the likely case the
critical paths of the design do not meet the timing requirements of the system or how to connect
all of the register clock pins in the design so that the design is synchronized correctly. The
remainder of the design flow will show how Astro™ can be used to deal with all of these
problems to produce a final place and routed design with all timing constraints achieved.

5.2.2 Design Setup

Before a design can be placed and routed within Astro™, the environment for the design needs to
be created. The goal of the design setup stage in the physical design flow is to prepare the design
for floorplanning. The design setup flow is outlined in Fig 6. As shown in the figure, the first
step is to create a design library. Without a design library, the physical design process using
Astro™ will not work. This library contains all of the logical and physical data that Astro™ will
need. Therefore the design library is also referenced as the design container during physical
design. One of the inputs to the design library which will make the library technology specific is
the technology file. This file must be explicitly defined when creating the design the library. The
technology file contains all of the necessary data for Astro™ based upon a specific process node,
such as 130 or 90nm. This file contains all of the mask layer information as well as via
definitions used for the connection of metal. This is also where a version of the process design
rules used by the tool is maintained. This information such as metal widths and spacing for each
layer can be used by the place and router to aid in simple design rule checking for
manufacturing. Since Astro™ is a graphical user interface (GUI), the layout layers can have
different colors and fill backgrounds associated with each layer. This information is also stored in
the technology file. Other critical data that is contained in the technology file are the resistance
and capacitance values for each layer. This data usually comes in table look-up (TLU) format
and is used by Astro™ to determine the resistance and capacitance of a particular route. It then
can be used to calculate delay introduced by the routing. The units for dimensions such as
time, distance, resistance, capacitance, etc are identified in the technology file, so that Astro™ as
well as the physical design engineer can interpret the data correctly. During the creating of the
design library, this technology is processed into the library and stored within the database. Once
this is done, the design library or container has been created.

Figure 5.6: Design Setup Flow using Astro™. Synopsys

The next step is to attach reference libraries to the design library. These reference libraries, as
discussed previously, contain the standard cells, macro cells, pad cells, and/or reusable IP core
cells that are being implemented into the design.