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Secomd Senaester M"Teeh. Begree Exaxmimwtion, .Fe.:lme/-Iuly 2SI 6

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Tirne: 3 hrs. Max. Marks: trCIO
Note: Answer eny FIVE full

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cJuestions.
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Q
a. Define SOC. Compare SOC, SIP and SOB. (04 Marks)
9r b. Whai is the significance ofl'reusable macros' (lP) rn the designing of SOC? Explain various

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types of,reusable rnacros (IP) used in SOC. (08 &farks)
c. Define the terrn'design nroductivity gan'. Also discuss the eflbct of this ontime to market.
(#E &,Ierks)

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a- What is the importance of using specifications in SOC d"esign? Explain the types of
specification used in detail. (Is Marksi

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b. With the help cf neat diagranr. explain the principle of waterfall ctesign flcw used in SOC.
{18 &farksi
I

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Write notes crn :
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=bi a. ESL Design Flow (08 S{erks}
b.
F0J
Constant Field Scaling (.05 &trarks)
c. Timing Closure Probier:l
w
?a {S6 },'$arks}

aX a- Compare the characteristics between NOR and NAND flash rnemory. With neat diagrarn,
oQ)
Explain the rvorking of NoR Flaslr menlor)/.
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(18 Marks)
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b. Explain the various mapping techniques used in Cache rnemory architectrire. (10 Marks)
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a.
ed

-(tr Discuss the limitatiotts of Bus based architecture used in neiwork on chip (NOC). (10 Marks)
b. Discuss abcut the various routing techniques used in NOC. {10 h{arks)
9i
a-
c-F
a. With tile help of timing diagrarn, explain the riifferent rjata transfer moctes used in tsus based
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NOC. (15 &IarEts)
(h (J b. Explain the worm hole switching in Soc. {05 &,[*rks]
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a. Discuss the challenges associated with the design of'MpSoC. (10 Marks)
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b, What is XTMP model? Explain the steps required to design an XTMP model. (I0 Marks)
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4)= a. What is TIE Language? Wrtte a program in TIE Langllage to adri a new register file and a
+ c.)
i-o)
new instruction to the Xtensa processor. (0S &derks)
o b. Explain the energy aware on-chlp communication system design.
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(trs iVflarks)

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