LAB ASSIGNMENT-4

G.PRUDDVI
13071A0420
BARREL SHIFTER:

Verilog Code for mux2x1:

module mux(a,b,s,q);
input a;
input b;
input s;
output q;
wire q;
assign q=s?b:a;
endmodule
Verilog Code for barrel shifter:
module barrel_shifter(d,s,q);
input [7:0]d;
input [2:0]s;
output [7:0]q;
wire [7:0]q;
wire [7:0]d;
//stage 1 wires
wire s11,s12,s13,s14 ,s15 ,s16 ,s17,s18;
//stage 2 wires
wire s21,s22,s23,s24 ,s25 ,s26 ,s27,s28;
//stage 1 mux
mux a1(d[7],d[0],s[0],s11);
mux a2(d[0],d[1],s[0],s12);
mux a3(d[1],d[2],s[0],s13);
mux a4(d[2],d[3],s[0],s14);
mux a5(d[3],d[4],s[0],s15);
mux a6(d[4],d[5],s[0],s16);
mux a7(d[5],d[6],s[0],s17);
mux a8(d[6],d[7],s[0],s18);

//stage 2 mux
mux a21(s17,s11,s[1],s21);
mux a22(s18,s12,s[1],s22);
mux a23(s11,s13,s[1],s23);
mux a24(s12,s14,s[1],s24);
mux a25(s13,s15,s[1],s25);
mux a26(s14,s16,s[1],s26);
mux a27(s15,s17,s[1],s27);
mux a28(s16,s18,s[1],s28);

//stage 3 mux
mux a31(s25,s21,s[2],q[0]);
mux a32(s26,s22,s[2],q[1]);
mux a33(s27,s23,s[2],q[2]);
mux a34(s28,s24,s[2],q[3]);
mux a35(s21,s25,s[2],q[4]);
mux a36(s22,s26,s[2],q[5]);
mux a37(s23,s27,s[2],q[6]);
mux a38(s24,s28,s[2],q[7]);

endmodule
Theory:

The barrel shifter shown above consists of three stages of 2:1 multiplexers, with one
multiplexer per bit of the input data. When all multiplexer select inputs are inactive
(low), the input data passes straight through the cascade of the multiplexers and the
output data (q7…..q0) is equal to the input data (d7…..d0). When one select line is
enabled via the s[0] the first stage of multiplexers performs a shift-right by one
bit operation, due to their interconnection to the next-higher input. The shifter output
becomes (q7 q0…..q6).

Similarly, the second stage of multiplexers performs a shift-right by two bits when
enabled via thes[1] control signal. The corresponding multiplexer inputs are connected
to their second next-higher input, and higher bits are replaced by the lower bits of
previous stage.The shifter output becomes (q6 q7…..q5).

Finally, the third stage of multiplexers performs a shift-right by four bits, with the
higher four bits equal to the lower bits in the data.The shifter output becomes (q4
q5…..q3).

Due to the cascade of three stages, all three shift operations (by one bit, by two bits,
and by four bits) can be activated independently from each other. For example, when
boths[0] and s[1] are activated, the shifter performs a shift-right by three bits.