EC230 Logic Circuit Design Lab

Experiment No. 1
FAMILIARIZATION OF LOGIC GATES
Aim:
To familiarize logic gates, IC packages and digital IC trainer kit and verify the truth
tables of basic gates and universal gates.
Components and Equipment required:
IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, IC 7486 and digital IC Trainer kit.
Theory:
Digital IC Trainer Kit: The digital IC trainer kit is equipment used to test and set up digital
circuits for doing experiments. Integrated circuits can be fitted in sockets or breadboards
provided in it. The associated circuits can be set up on bread boards. There are built-in voltage
sources and clock signals in it. The frequency of clock can be selected by turning the knob to
different positions. In order to feed monopulses manually, a debouncer switch is also provided.
A set of select -switches are provided to select low and high states for digital inputs. LEDs are
provided to visualize the digital outputs.
Logic gates: In digital electronics, a gate is a logic circuit with one output and one or more
inputs. Logic gates are available as integrated circuits (ICs). Some of the logic gates are
described below:
AND gate: The AND gate performs logical multiplication more commonly known as AND
operation. The AND gate output is in high state only when all the inputs are in high state. 7408
is a digital IC in the TTL family and contains four AND gates. For this reason, it is called quad
two input AND gate. Every AND gate has two inputs in this Dual-in-Line Package. Pin 14 is the
supply pin. For standard TTL devices to work properly, the supply voltage level must be
between +4.75 V and +5.25 V. This is why +5 V is the nominal supply voltage specified for all
devices. Pin 7 is the common ground for the chip. The other pins are inputs and outputs.
OR gate: It performs logical addition. Its output will become high if any of the inputs is in logic
high. 7432 IC is a quad two input OR gate.
NOT gate: It performs a basic logic function called inversion or complementation. The purpose
of the inverter is to change one logic level to opposite level. IC 7404 is a hex-inverter.
NAND gate: A NOT gate following an AND gate is called NOT-AND or NAND gate. Its output
will be low if all the inputs are in high state. 7400 IC is a quad two input NAND gate.
NOR gate: A NOT gate following an OR gate is called NOT-OR or NOR gate. Its output will be
in low state if any of its inputs is in high state. 7402 IC is a quad two input NOR gate.
XOR gate: Its output will be high if and only if one input is in high state. IC 7486 is a quad two
input XOR gate.

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Symbols, Truth tables and DIP Pin outs:

AND Gate:

INPUTS OUTPUT
A B Y = A.B
0 0 0
0 1 0
1 0 0
1 1 1
SYMBOL TRUTH TABLE

IC 7408 QUAD-TWO INPUT AND GATE: PIN OUT

OR Gate:

INPUTS OUTPUT
A B Y = A+B
0 0 0
0 1 1
1 0 1
1 1 1
SYMBOL TRUTH TABLE

IC 7432 QUAD-TWO INPUT OR GATE: PIN OUT

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NOT Gate:

INPUTS OUTPUT
A Y = 𝐴̅
0 1
1 0

SYMBOL TRUTH TABLE

IC 7404 QUAD-TWO INPUT NOT GATE: PIN OUT

NAND Gate:

INPUTS OUTPUT
A B Y = ̅̅̅̅̅
𝐴. 𝐵
0 0 1
0 1 1
1 0 1
1 1 0

SYMBOL TRUTH TABLE

IC 7400 QUAD-TWO INPUT NAND GATE: PIN OUT

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NOR Gate:

INPUTS OUTPUT
A B Y = ̅̅̅̅̅̅̅̅
𝐴+𝐵
0 0 1
0 1 0
1 0 0
1 1 0
SYMBOL TRUTH TABLE

IC 7402 QUAD-TWO INPUT NOR GATE: PIN OUT

XOR Gate:

INPUTS OUTPUT
A B Y = A⊕B
0 0 0
0 1 1
1 0 1
1 1 0

SYMBOL TRUTH TABLE

IC 7486 QUAD-TWO INPUT XOR GATE: PIN OUT

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Procedure:
1. Test all the components and IC packages using a digital IC tester. Also assure whether all
the connection wires are in good condition by testing for the continuity using a
multimeter or a digital IC trainer kit. (Continuity of wires can be tested using a d igital IC
trainer kit by shorting a 5 V supply in the trainer kit to an LED. If wires are in good
condition, LED will glow.)
2. Verify the pin out of IC before feeding the inputs.
3. Verify that the ICs have been perfectly plugged into the breadboard or sockets before
feeding inputs.
4. Set up the circuits and observe the outputs. Enter the input and output states in truth table
corresponding to the input combinations.

Result:
Familiarized logic gate ICs and verified truth tables of logic gates. Also familiarized the
digital IC trainer kit.

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Experiment No. 2
REALIZATION OF FUNCTIONS USING BASIC GATES AND
UNIVERSAL GATES
Aim:
i. To realize logic gates using universal gates.
ii. To realize the functions using basic and universal gates (SOP and POS Forms)
̅ + CD
a. Y1 = AB ̅
̅+B
b. Y2 = (A+B). (A ̅)
Components and Equipment required:
IC 7400, IC 7402, IC 7404, IC 7432 and digital IC Trainer kit.
Theory:
Universal Gates: NAND and NOR gates are called universal gates. Any Boolean expression can
be expressed in SOP or POS form, which can be realized using either NAND or NOR gates only.
NAND gate: A NOT gate following an AND gate is called NOT-AND or NAND gate. Its output
will be low if all the inputs are in high state. 7400 IC is a quad two input NAND gate.
NOR gate: A NOT gate following an OR gate is called NOT-OR or NOR gate. Its output will be
in low state if any of its inputs is in high state. 7402 IC is a quad two input NOR gate.
Realization of logic gates using NAND gates.
i. NOT gate using NAND gate
̅A = ̅̅̅̅̅
𝐴. 𝐴

ii. AND gate using NAND gate

A B = ̿̿̿̿
𝐴𝐵

iii. OR gate using NAND gate

A+ B= 𝐴 + 𝐵 = ̅̅̅̅
̿̿̿̿̿̿̿̿ 𝐴̅𝐵̅

iv. XOR gate using NAND gate

Y=𝐴̅ B+A𝐵̅
= A ̅𝐴+𝐴̅ B+A 𝐵̅+𝐵̅ B
= A(𝐴̅+𝐵̅) + B(𝐴̅+𝐵̅)
̅̅̅̅̅
= A(𝐴. ̅̅̅̅̅
𝐵)+B(𝐴. 𝐵)
̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
̅̅̅̅̅
= A(𝐴. 𝐵 ) + B(𝐴. ̅̅̅̅̅
𝐵)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ ) ̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅
=. A. (𝐴𝐵 B. (𝐴𝐵)

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Realization of logic gates using NOR gates.

i. NOT gate using NOR gate
𝐴̅ = ̅̅̅̅̅̅̅̅
𝐴+𝐴
ii. AND gate using NOR gate

𝐴𝐵 = ̅̅̅̅̅̅̅̅
A B = ̿̿̿̿ 𝐴̅ + 𝐵̅
iii. OR gate using NOR gate
̿̿̿̿̿̿̿̿
A+ B= 𝐴 +𝐵
iv. XOR gate using NOR gate
Y=𝐴̅ B+A𝐵̅
= A ̅𝐴+𝐴̅ B+A 𝐵̅+𝐵̅ B
= A(𝐴̅+𝐵̅) + B(𝐴̅+𝐵̅)
= (A+B) (𝐴̅+𝐵̅)
̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
= (A + B) (𝐴̅ + 𝐵̅ )
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅
̅ + 𝐵̅ )
= (A + B) + (𝐴

Circuit Diagram and Design:

Realization of logic gates using NAND gate
i. NOT gate using NAND gate

INPUT OUTPUT
7400 A Y = 𝐴̅
0 1
1 0

ii. AND gate using NAND gate

INPUTS OUTPUT
7400 7400 A B Y = A.B
0 0 0
0 1 0
1 0 0
1 1 1

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iii. OR gate using NAND gate

7400 INPUT
OUTPUT
S
Y=
7400 A B
A+B
0 0 0
7400 0 1 1
1 0 1
1 1 1

iv. XOR gate using NAND gate

INPUTS OUTPUT

A B Y = A⊕B
0 0 0
0 1 1
1 0 1
1 1 0

Realization of logic gates using NOR gate

i. NOT gate using NOR gate

INPUTS OUTPUT
A Y = 𝐴̅
0 1
1 0

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ii. AND gate using NOR gate

INPUTS OUTPUT
A B Y = A.B
0 0 0
0 1 0
1 0 0
1 1 1

iii. OR gate using NOR gate

INPUT
OUTPUT
S
Y=
A B
A+B
0 0 0
0 1 1
1 0 1
1 1 1

iv. XOR gate using NOR gate

INPUTS OUTPUT
Y=
A B
A⊕B
0 0 0
0 1 1
1 0 1
1 1 0

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Realization of Functions:
Y1 = A𝐵̅ + C𝐷
̅ Truth Table
̅+
Y1 = A𝑩
A B C D
̅
C𝑫
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

Y1 = A𝐵̅ + C𝐷
̅ using basic gates

̅ + CD
Y1 = AB ̅ using NAND gates

̅+ CD
Y1 = AB ̅

= ̿̿̿̿̿̿̿̿̿̿̿̿
AB̅ + CD ̅

= ̅̅̅̅̅̅̅̅̅
̅̅̅̅
AB̅ . ̅̅̅̅
CD̅

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̅ + CD
Y1 = AB ̅ using NOR gate
̅+ CD
Y1 = AB ̅

= ̿̿̿̿̿̿̿̿̿̿̿̿
AB̅ + CD ̅

= ̅̅̅̅̅̅̅̅̅
̅̅̅̅
AB̅ . ̅̅̅̅
CD̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ + B). (C̅ + 𝐷)
= (A
= ̅̅̅̅̅̅̅̅̅̅̅
̅ + B) + (C
(A ̅̅̅̅̅̅̅̅̅̅
̅ + 𝐷)
̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
= ̅̅̅̅̅̅̅̅̅̅̅
̅ + B) + ̅̅̅̅̅̅̅̅̅̅
(A (C̅ + 𝐷)

̅+B
Y2 = (A+B). (A ̅)

INPUTS OUTPUT

A B ̅+B
Y2 = (A+B). (A ̅)

0 0 0
0 1 1
1 0 1
1 1 0
Truth Table

̅+B
Y2 = (A+B). (A ̅) using NAND gate

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̅+B
Y2 = (A+B). (A ̅) using NOR gate

Procedure:
1. Test all the components and IC packages using multimeter and digital IC tester.
2. Verify the truth tables of the circuit by feeding the input bit combinations.

Result:
̅ + CD
Realized logic gates using universal gates and realized the functions Y1 = AB ̅ and
̅ +B
Y2 = (A+B). (A ̅) using basic and universal gates.

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Experiment No. 3
HALF ADDER AND FULL ADDER USING BASIC GATES AND
UNIVERSAL GATES
Aim:
To design and setup half adder and full adder circuit using basic gates and universal
gates.
Components and Equipment required:
IC 7400, IC 7402, IC 7408, IC 7432, IC 7486 and digital IC Trainer kit.
Theory:
A Binary adder is a circuit which is able to add together two binary numbers. The half
adder adds two binary digits an addend and an augend to produce a sum and carry. The sum can
be implemented by using an Exclusive OR gate and an AND gate can be used for carry
generation.
The Boolean expression for the sum and carry are
Sum S = AB
Carry C = A.B
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. The full adder adds an addend, an augend and carry input generated by the
previous stage addition. It has two outputs, sum and carry. Full adder circuit can be implemented
using AND, OR and EX-OR gates. Full adder circuit can also be implemented with the help of
two half adder circuits. The first half adder is used to add two inputs and generate sum and carry
output. Then second half adder combines the sum and carry input and generate final sum and
carry out.
The sum and carry can be expressed as
Sum S = A  B  Ci
Carry C = (A B) Ci + AB = AB+ BCi + ACi

Circuit Diagram and Design:

Half Adder
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0

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1 1 0 1

Truth Table

Boolean Expression: S=A ̅B + AB

̅=A B
C = AB

Circuit Diagram:
Half adder using Basic Gates

Half adder using NAND Gate

Half adder using NOR Gate

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Full Adder
Inputs Outputs
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Truth Table

Realization using K map;

Sum

̅ B Ci
S=A ̅ +AB ̅ +A
̅ Ci ̅B̅ Ci+ A B Ci

̅ (A
= Ci ̅B+AB ̅B
̅) + Ci (A ̅ + A B)

̅̅̅̅̅̅̅
̅ (AB) + Ci (AB)
= Ci

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= ABCi

Carry

Co = AB + B Ci + A Ci

̅ B Ci (avoiding horizontal grouping)

̅ Ci + A
= AB + A B

̅ B)
̅+A
= AB + Ci (A B

= AB + Ci (AB)

Boolean Expressions: S = A B Ci
Co = AB+ Ci (A B)

Full Adder using Basic Gates:

Full Adder using NAND Gate:

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Co = AB+ Ci (A B)
= ̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
AB + Ci (AB)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ . Ci
AB (AB)

Full Adder using NOR Gate:

Co = AB+ Ci (A B)
= ̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
AB + Ci (AB)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅
AB . Ci (AB)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= (A̅ + B ̅̅̅̅̅̅̅̅
̅̅̅ + (A
̅ ). (Ci B))
= ̅̅̅̅̅̅̅̅̅̅̅
̅ + B
(A ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅
̅̅̅ + (A
̅ ) + (Ci B))
̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= ̅̅̅̅̅̅̅̅̅̅̅
̅ + B
(A ̅ ) + (Ci ̅̅̅̅̅̅̅̅
̅̅̅ + (A B))

Procedure:

1. Test all the components and IC packages using multimeter and digital IC tester.
2. Setup the half adder circuit and feed the input combinations.

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3. Observe the output corresponding to the input bit combinations and enter it in truth table.
4. Repeat the above steps for full adder

Result:
Designed and setup half adder and full adder circuit using basic gates and universal gates
and verified the output using truth table.

Experiment No. 4
HALF SUBTRACTOR AND FULL SUBTRACTOR USING BASIC GATES
AND UNIVERSAL GATES
Aim:
To design and setup half subtractor and full subtractor circuit using basic gates and
universal gates.
Components and Equipment required:
IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, IC 7486 and digital IC Trainer kit.
Theory:
Half Subtractor:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be applied
using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.

Full Subtractor:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow output of the half subtractor
and the second term is the inverted difference output of first X-OR.

Circuit Diagram and Design:

Half Subtractor

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Inputs Outputs
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Truth Table

Boolean Expression: D=A ̅B + AB

̅=A B
̅B
Br = A

Circuit Diagram:
Half subtractor using Basic Gates

Half subtractor using NAND Gate

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̅B = B (A
Br = A ̅+B
̅)
̅̅̅̅)
= B. (AB
̿̿̿̿̿̿̿̿̿
= B. ̅̅̅̅)
(AB

Half subtractor using NOR Gate

̅B = A
Br = A ̅ (A+B)
= ̿̿̿̿̿̿̿̿̿̿̿̿̿
̅ (A + B)
A
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
=A + ̅̅̅̅̅̅̅̅̅̅
(A + B)
Full Subtractor
Inputs Outputs
A B bi D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Truth Table
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Simplification
̅ + A𝐵̅ 𝑏𝑖
D = 𝐴̅𝐵̅ bi + 𝐴̅B𝑏𝑖 ̅ + ABbi
̅ (𝐴̅B + A𝐵̅)
= bi (𝐴̅𝐵̅ + AB ) + 𝑏𝑖
= bi(𝐴̅̅̅̅̅̅ ̅ (A B)
𝐵) + 𝑏𝑖
=A B C

Br = ABbi + A̅ B bi̅+ A̅ B bi + A̅ B
̅ bi
=A ̅ ) + bi (A B+ A̅ B
̅B (bi +bi ̅)
=A̅B + bi(AB
̅̅̅̅̅̅)

Boolean Expression: D = A B bi
̅B+ bi ̅̅̅̅̅̅̅̅̅
Br = A (𝐴 𝐵)

Full subtractor using Basic Gates:

Full subtractor using NAND Gate:

Br = A̅B + bi(AB̅̅̅̅̅̅)
̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
̅ B + bi(AB
=A ̅̅̅̅̅̅)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅
̅ B. ̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅)
=A bi(AB

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Full subtractor using NOR Gate:

Br = A̅B + bi(AB̅̅̅̅̅̅)
=A̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(A + B) + ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
+ ̅̅̅̅̅̅̅̅̅̅ (AB) + ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
((AB) + bi)
̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
=A (A + B) + ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
+ ̅̅̅̅̅̅̅̅̅̅ (AB) + ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
((AB) + bi)
Procedure:

1. Verify whether all the components and wires are in good condition
2. Setup the half subtractor and feed the input bit combinations
3. Observe the output corresponding to input combination and enter it in the truth table
4. Repeat the above steps for a full subtractor circuit.

Result:
Designed and setup a half subtractor and full subtractor using basic gates and universal
gates.

Experiment No. 5
4 BIT ADDER/SUBTRACTOR AND BCD ADDER USING IC 7483
Aim:
To design and setup a 4-bit binary adder, 4-bit binary adder/subtractor and a BCD adder
using IC 7483.
Components and Equipment required:
IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, IC 7486 and digital IC Trainer kit.
Theory:
IC7483 is a TTL IC with 4 full adders in it. This IC is used for arithmetic and logic
operations namely addition, subtraction, complimentary etc.
4-bit binary adder: A3, A2, A1, A0 and B3, B2, B1, B0 are inputs and Cout S3,S2, S1,S0 is the
output. Carry in pin is grounded. This is also called ‘nibble adder’.
4 bit adder/subtractor: To add nibbles, SUB is made 0. To subtract B3B2B1B0 from A3A2A1A0
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SUB input should be made 1. XOR gates function as controlled inverters. When SUB = 1,
B3B2B1B0 is complimented. Now A3,A2A1A0 complimented version of B3B2B1B0 and 1 at Cin
pin added together. Cout is ignored. Thus the 2’s compliment of subtrahend is added with
minuend. If minuend is less than subtrahend. Obtained output will be 2’s compliment of
difference single digit BCD adder.
BCD Adder: In the BCD addition, if sum exceeds 4, 6 must add to result to convert it in to BCD
number. For this two 7483 are required. One for binary addition and other for addition of 6. A
combinational circuit is setup so that its output C makes A3A2A1A0 = 0110 when S3S2S1S0 >
1001 or Cout =1.

Circuit and Design:

Pin out diagram of IC 7483

Pin out diagram of 7410: 3 input NAND gate

4-Bit Binary Adder

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4-Bit Binary adder/subtractor

Single Digit BCD Adder

S3 S2 S1 S0 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0

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1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Truth Table
Karnaugh Map Simplification

C is 1 when S3S2S1S0 > 1001.

In addition to this, if C1 =1, C should be 1.
Combining above two conditions C =1, when S3S2S1S0 > 1001 or C1 =1.
Hence the expression for C = Cout + S3S2 + S1S3
Circuit Diagram

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Procedure
1. Test all components.
2. Setup the circuits one by one
3. Verify its output
Result
Designed and setup a 4-bit binary adder, 4-bit binary adder/subtractor and a BCD adder
using IC 7483 and obtained the output.

Experiment No. 6

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BINARY TO GRAY AND GRAY TO BINARY CONVERTERS

Aim:
To design and setup a Binary to Gray converter and Gray to Binary converter.
Components and Equipment required:
IC 7486 and digital IC Trainer kit.
Theory:
To convert a binary number to corresponding Gray code, the following rules are applied:
1. The MSB in the Gray code is the same as the corresponding bit in a Binary number.
2. Going from left to right, add each adjacent pair of Binary digits to get the next Gray code
digit. Disregard carries.
As the first step to design a Binary to Gray code converter, set up a truth table with Binary
numbers B3 B2 B1 B0 and corresponding Gray code numbers as G3 G2 G1 G0. Set up a circuit
realizing the simplified logic expressions obtained using K maps for Gs as the functions of Bs.
To convert from Gray code to Binary, the following rules are applied.
1. The most significant digit in the binary number is the same as the corresponding digit in
the Gray code.
2. Add each Binary digit generated to the Gray code digit in the next adjacent position.
Disregard carries.
To design the Gray to Binary code converter, set up the truth table and get simplified expressions
using Karnaugh maps for each Binary bits as a function of Gray code bits. Each Gray code
number differs from the preceding number by a single bit.
Circuit and Design:
Binary Gray
Binary to Gray Code B3 B2 B1 B0 G3 G2 G1 G0
Converter: 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Truth Table:

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Realization using Karnaugh Map:

K-Map for G0:

G0 = ̅̅̅
B1 B0 + B1̅̅̅
B0 = B0B1
K-Map for G1:

G1 = ̅̅̅
B1 B2 + B1̅̅̅
B2 = B1B2

K-Map for G2:

G2 = ̅̅̅
B2 B3 + B2̅̅̅
B3 = B2B3

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K-Map for G3:

G3 = B3
Boolean Expressions:
G0 = B0  B1
G1 = B1  B2
G2 = B2  B3
G3 = B3

Circuit Diagram:

Binary to Gray Code Converter using Ex-OR Gates

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Gray to Binary Code

Converter: Gray Binary
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

Truth Table:
Realization using Karnaugh Map:
K-Map for B0:

̅̅̅̅ 𝐺1
𝐵0 = 𝐺3 𝐺2 ̅̅̅̅ 𝐺0
̅̅̅̅ + 𝐺3̅̅̅̅ 𝐺2 𝐺1
̅̅̅̅ 𝐺0 + 𝐺3 𝐺2 𝐺1
̅̅̅̅ 𝐺0 + 𝐺3
̅̅̅̅ 𝐺2
̅̅̅̅ 𝐺1
̅̅̅̅ 𝐺0
+ 𝐺3 𝐺2 𝐺1 𝐺0 + 𝐺3 𝐺2 𝐺1 𝐺0 + 𝐺3 𝐺2 𝐺1 ̅̅̅̅
̅̅̅̅ ̅̅̅̅ 𝐺0 + ̅̅̅̅
𝐺3 ̅̅̅̅
𝐺2 𝐺1 ̅̅̅̅
𝐺0

= ̅̅̅̅
𝐺1 ̅̅̅̅
𝐺0 (G3 ̅̅̅̅
𝐺2 + ̅̅̅̅
𝐺3 G2) + 𝐺1 𝐺0 (G3 ̅̅̅̅
𝐺2 + ̅̅̅̅
𝐺3 G2)
̅̅̅̅ ̅̅̅̅ ̅̅̅̅ ̅̅̅̅
+ 𝐺1 𝐺0(G3 G2 + 𝐺3 𝐺2) + 𝐺1 𝐺0 (G3 G2 +𝐺3 ̅̅̅̅ ̅̅̅̅
𝐺2)

̅̅̅̅ 𝐺0
= 𝐺1 ̅̅̅̅𝐺0 ̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ (G3G2) + 𝐺1𝐺0 (G3G2) + 𝐺1 (𝐺3𝐺2)+ 𝐺1𝐺0̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅
(𝐺3𝐺2)

= ̅̅̅̅̅̅̅̅̅̅̅̅
(𝐺0𝐺1) (G3G2) + (G0G1) ̅̅̅̅̅̅̅̅̅̅̅̅
(𝐺3𝐺2)

= G0  G1  G2  G3

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K-Map for B1:

B1 = G3 𝐺2̅̅̅̅ 𝐺1
̅̅̅̅ + 𝐺3
̅̅̅̅ G2̅̅̅̅ ̅̅̅̅ 𝐺2
𝐺1+ G3 G2 G1+ 𝐺3 ̅̅̅̅ G1
= 𝐺1 (G3 𝐺2 + 𝐺3 G2) + G1 (G3 G2 +𝐺3 ̅̅̅̅
̅̅̅̅ ̅̅̅̅ ̅̅̅̅ ̅̅̅̅ 𝐺2)
̅̅̅̅
= 𝐺1 (G3G2) + G1 (𝐺3𝐺2) ̅̅̅̅̅̅̅̅̅̅̅̅
= G3  G2  G1
K-Map for B2:

B2 = 𝐺2G3 + G2𝐺3 = G2  G3

K-Map for B3:

B3 = G3

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Boolean Expressions:
B0 = G0  G1  G2  G3
B1 = G3  G2  G1
B2 = G2  G3
B3 = G3

Circuit Diagram:

Gray to Binary Code Converter using Ex-OR Gates

Procedure:
1. Test all the components and IC packages using multimeter and digital IC tester.
2. Verify the truth tables of the circuit by feeding the input bit combinations.

Result:
Designed and setup a Binary to Gray converter and Gray to Binary converter and
verified the truth tables.

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Experiment No. 7
STUDY OF FLIP FLOPS
Aim:
Study of Flip Flops: S-R, D, T, JK and Master Slave JK FF using NAND gates.
Components and Equipment required:
IC 7400, IC 7410, breadboard and digital IC Trainer kit.
Theory:
Flip-flop is the basic building block of a computer memory system. A flip-flop is setup
by connecting two inverters back to back. Its output will remain in the same state until it is
forced to change it by same means. This property is used to save a binary in a flip flop.
Clocked SR Flip-flop: S and R stands for set and reset. This flip flop activates during positive
level on the clock input. Qn present state and Qn+1 next state when the inputs are applied. When
S=K=0 clock =1, output remains the same. When S=1 and R=0 and clock =1, Q becomes 1.
When S=R=1 is forbidden case.
D Flip flop: It is obtained by shorting S and R inputs of SR flip flops. This flip flop is called as
latch flip flop. It has only one input referred to D input or data input. The input data is
transferred to output when a clock pulse is applied.
JK Flip flop: The indeterminate output of SR flip flop when S=R=1 is avoided in JK. Output
toggles on this state. It has a limitation problem called race around condition. When clock is ON
and because of the presence of feedback path and small propagation delay of circuit compared to
the clock period. When J=K=1, output toggles its state many times. When clock input is
withdrawn, output of the flipflop will be uncertain.
Master Slave JK flip flop: The race around problem of JK flip flop is rectified in this. It is
created by cascaded two JK flip flops. The clock fed to first stage is inverted and fed to the
second stage. This ensures that the slave follows master and determinates the racing problem.
T flip flops: T stands for toggle. The output toggles when a clock pulse is applied. The output of
the flip flop changes state for an input pulse. T flip flop is derived from a master slave JK flip
flop by shorting J and K inputs. Converting ordinary JK flip flop to T flip flop is avoided due to
race around problem.

Circuit Diagram:
Clocked SR Flip Flop: Logic Symbol and circuit

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Truth Table
Input Output
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 X

JK Flip Flop
Logic symbol and circuit

Truth table

Input Output
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 ̅̅̅̅
𝐐𝐧

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D Flip Flop:
Logic Symbol and Circuit

Truth Table

Input Output
D Qn+1
0 Qn
1 1

T- Flop flop
Logic symbol and circuit

T FF

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Truth table
Input Output
T Qn+1
0 Qn
1 ̅̅̅̅
𝐐𝐧

Master Slave JK Flip Flop

Logic symbol and truth table
Input Output
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 ̅̅̅̅
𝐐𝐧

Circuit diagram

Procedure:
1. Test all the components and IC packages using multimeter and digital IC tester.
2. Set up the flip flops using gates and verify their truth tables.
Result:
Designed and set up various flip-flops such as SR, D, JK, T and Master-Slave JK using
gates and also its outputs are verified using truth table.

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Experiment No. 8
SYNCHRONOUS COUNTER: 4-BIT UP AND 4-BIT DOWN COUNTER
Aim:
To design and set up a synchronous 4-bit up counter and a 4-bit down counter.
Components and Equipment required:
IC 7408, IC 7476 and digital IC Trainer kit.
Theory:
Circuits for counting events are frequently used in computers and other digital systems.
Since a counter circuit must remember its past states, it has to possess memory. The number of
flip flops used and how they are connected determine the number of states and the sequence of
the states that the counter goes through in each complete cycle.
Counters can be classified into two broad categories according to the way they are clocked:
a) Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse,
and then each successive flip -flop is clocked by the Q or 𝑄̅ output of the previous flip -flop.
b) Synchronous Counters - all memory elements are simultaneously triggered by the same
clock.
Synchronous Counters:
In synchronous counters, the clock inputs of all the flip-flops are connected together and
are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in
parallel). The most important advantage of synchronous counters is that there is no cumulative
time delay because all flip-flops are triggered in parallel. Thus, the maximum operating
frequency for this counter will be significantly higher than for the corresponding ripple counter.
4 bit Synchronous UP Counter:
The 4 bit up counter shown is designed by using JK flip flop. External clock pulse is
connected to all the flip flops in parallel. For designing the counters JK flip flop is preferred.
The significance of using JK flip flop is that it can toggle its state if both the inputs are high,
depending on the clock pulse.
The inputs of first flip flop are connected to HIGH (logic 1), which makes the flip flop to
toggle, for every clock pulse entered into it. So the synchronous counter will work with single
clock signal and changes its state with each pulse. The output of first JK flip flop (QA) is
connected to the input of second flip flop. The AND gates (which are connected externally)
drives the inputs of other two flip flops. The inputs of these AND gates, are supplied from
previous stage flip flop outputs.
AND gates are used at the input side of FF2 and FF3. The output of the AND gate will
be high only when the QA, QB outputs are high. Similarly, the flip flop FF3 will toggle for the
fourth clock pulse when QA, QB and QC are high. The QD output will not toggle till the 8th clock
pulse and will again remain high until 16th clock pulse. After the 16th clock pulse, the Q outputs
of all flip flops will return to 0.

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4 bit Synchronous DOWN Counter:

Down counter counts the numbers in decreasing order. This is similar to an up counter
but it should decrease its count. So inputs of JK flip- flop are connected to the inverted Q (𝑄̅ ) .
The 4 bit down counter is designed by using JK flip flop. The same external clock pulse is
connected to all the flip flops. As the counter has to count down the sequence, initially all the
inputs will be in high state as they have to count down the sequence. It will start with 1111 and
ends with 0000. In the down counter it should be remembered that, preceding flip flop will
toggles only if front flip flop produces low logic at its output.
Circuit Diagram and Design:

Pin out of IC 7476

Excitation table of JK Flip-Flop:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

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4-bit Synchronous UP counter:

Truth Table
Present State Next State FF D FF C FF B FF A
QD QC QB QA QD+ QC+ QB+ QA+ JD KD JC KC JB KB JA KA

0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X

0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1

0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X

0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1

0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X

0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1

1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X

1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1
1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X
1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1

1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X
1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1

1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X

1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1

K-Map Realization
JA KA

JA = 1 KA = 1

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JB KB

JB = QA KB = QA

JC KC

JC = QAQB KC = QA QB

JD KD

JD = QAQBQC KD = QAQBQC

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Circuit Diagram:

4-bit Synchronous DOWN counter:

Truth Table
Present State Next State FF D FF C FF B FF A
QD QC QB QA QD+ QC+ QB+ QA+ JD KD JC KC JB KB JA KA

1 1 1 1 1 1 1 0 X 0 X 0 X 0 X 1
1 1 1 0 1 1 0 1 X 0 X 0 X 1 1 X

1 1 0 1 1 1 0 0 X 0 X 0 0 X X 1
1 1 0 0 1 0 1 1 X 0 X 1 1 X 1 X

1 0 1 1 1 0 1 0 X 0 0 X X 0 X 1
1 0 1 0 1 0 0 1 X 0 0 X X 1 1 X
1 0 0 1 1 0 0 0 X 0 0 X 0 X X 1
1 0 0 0 0 1 1 1 X 1 1 X 1 X 1 X

0 1 1 1 0 1 1 0 0 X X 0 X 0 X 1
0 1 1 0 0 1 0 1 0 X X 0 X 1 1 X

0 1 0 1 0 1 0 0 0 X X 0 0 X X 1
0 1 0 0 0 0 1 1 0 X X 1 1 X 1 X

0 0 1 1 0 0 1 0 0 X 0 X X 0 X 1

0 0 1 0 0 0 0 1 0 X 0 X X 1 1 X
0 0 0 1 0 0 0 0 0 X 0 X 0 X X 1

0 0 0 0 1 1 1 1 1 X 1 X 1 X 1 X

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K-Map Realization
JA KA

JA = 1 KA = 1

JB KB

JB = ̅̅̅̅
𝐐𝐀 KB = ̅̅̅̅
𝐐𝐀

JC KC

JC = ̅̅̅̅
𝐐𝐀 ̅̅̅̅
𝐐𝐁 KC = ̅̅̅̅
𝐐𝐀 ̅̅̅̅
𝐐𝐁

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JD KD

JD = ̅̅̅̅
𝐐𝐀 ̅̅̅̅
𝐐𝐁 ̅̅̅̅
𝐐𝐂 KD = ̅̅̅̅
𝐐𝐀 ̅̅̅̅
𝐐𝐁 ̅̅̅̅
𝐐𝐂

Circuit Diagram:

Procedure:
1. Test all the components and IC packages using the digital IC tester.
2. Setup the circuits and verify the counter states.
Result:
Designed and set up a synchronous 4-bit up counter and a 4-bit down counter and
obtained its output and verified the counter states using truth table.

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Experiment No. 9
SYNCHRONOUS COUNTER: MOD N COUNTERS
Aim:
To design and setup a mode 5 up counter and a self-starting counter for the sequence
0,2,4,5,0,2,4,5,…….
Components and Equipment required:
IC 7476, IC 7408, IC 7432, and digital IC Trainer kit.
Theory:
A mod N counter is a counter that has N states. Its output frequency is f/N. A counter
which is reset at the fifth clock pulse is called Mod 5 counter or Divide by 5 counter. A Mod-n
Synchronous counter can be implemented using appropriate number of J-K flip-flops connected
together with their clocks triggered simultaneously. A synchronous counter which counts a
truncated sequence of n unique states can be similarly implemented. The Modulus number
represents the unique number of states which the counter counts in a sequence. The Modulus
number determines the number of flip-flops required based on the relation n = 2mwhere m is the
number of flip-flops

Circuit Diagram and Design:

Mod 5 UP counter
Truth Table
Present State Next State FF 2 FF 1 FF 0
Q3 Q2 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 0 X 1 0 X 0 X

K-Map Realization:

̅̅̅̅𝟐
J0 = 𝐐 K0 = 1

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J1 = Q0 K1 = Q0

J2 = Q0Q1 K2 = 1

Circuit diagram

Mod 5 up counter

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Self-starting counter for the sequence 0,2,4,5,0,2,4,5,…….

Truth Table
Present State Next State FF C FF B FF A
Q3 Q2 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0

0 0 0 0 1 0 0 X 1 X 0 X
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0 X X 1
0 0 1 0 0 0 0 X 0 X X 1
0 1 1 0 0 0 0 X X 1 X 1
1 1 0 0 0 0 X 1 X 1 0 X
1 1 1 0 0 0 X 1 X 1 X 1

K-Map Realization:

̅̅̅̅𝟏
J0 = Q2 𝐐 K0 = 1

̅̅̅̅𝟎 ̅̅̅̅
J1 = 𝐐 𝐐𝟐 K1 = 1

̅̅̅̅𝟎 Q1
J2 = 𝐐 K2 = Q0 + Q1

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Circuit Diagram:

Self-starting counter for the sequence 0,2,4,5,0,2,4,5,…….

Procedure:
1. Test all the components and IC packages using the digital IC tester.
2. Setup the circuits and verify the counter states.

Result:
Designed and set up a mode 5 up counter and a self-starting counter for the sequence
0,2,4,5,0,2,4,5,……. and verified the counter states.

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Experiment No. 10
SYNCHRONOUS COUNTER: 3 BIT UP/DOWN COUNTER
Aim:
To design and implement a 3 bit synchronous up/down counter.
Components and Equipment required:
IC 7476, IC 7432, IC 7408, IC 7404 and digital IC Trainer kit.
Theory:
An up/down counter is one that is capable of progressing in increasing order or
decreasing order through a certain sequence. An up/down counter is also called bidirectional
counter. Usually up/down operation of the counter is controlled by up/down or mode signal.
When this signal is high counter goes through down sequence and when up/down signal is low
counter follows up sequence.
Circuit Diagram and Design:
3-bit Synchronous UP/DOWN counter:
Truth Table
Present State Next State FF C FF B FF A
Mode QC QB QA QC+ QB+ QA+ JC KC JB KB JA KA

0 0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 1 0 1 0 0 X 1 X X 1

0 0 1 0 0 1 1 0 X X 0 1 X

0 0 1 1 1 0 0 1 X X 1 X 1

0 1 0 0 1 0 1 X 0 0 X 1 X

0 1 0 1 1 1 0 X 0 1 X X 1

0 1 1 0 1 1 1 X 0 X 0 1 X

0 1 1 1 0 0 0 X 1 X 1 X 1
1 1 1 1 1 1 0 X 0 X 0 X 1

1 1 1 0 1 0 1 X 0 X 1 1 X

1 1 0 1 1 0 0 X 0 0 X X 1
1 1 0 0 0 1 1 X 1 1 X 1 X

1 0 1 1 0 1 0 0 X X 0 X 1
1 0 1 0 0 0 1 0 X X 1 1 X

1 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 1 1 1 1 X 1 X 1 X

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K-Map Realization
JA KA

JA = 1 KA = 1

JB KB

JB = M ̅̅̅̅ ̅ QA
𝐐𝐀 + 𝐌 KB = M ̅̅̅̅ ̅ QA
𝐐𝐀 + 𝐌

JC KC

JC = M ̅̅̅̅
𝐐𝐀 ̅̅̅̅ ̅ QA QB
𝐐𝐁 + 𝐌 KC = M ̅̅̅̅
𝐐𝐀 ̅̅̅̅ ̅ QA QB
𝐐𝐁 + 𝐌

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Circuit Diagram:

Procedure:
3. Test all the components and IC packages using the digital IC tester.
4. Setup the circuits and verify the counter states.
Result:
Designed and set up a synchronous 3-bit up/down counter and verified the counter states
using truth table.

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Experiment No. 11
SHIFT REGISTERS
Aim:
To design and setup various shift registers:
i. Serial In - Serial Out (SISO)
ii. Serial In - Parallel Out (SIPO)
iii. Parallel In - Serial Out (PISO)
iv. Parallel In - Parallel Out (PIPO)
v. Right shift register using IC 7495
vi. Left shift register using IC 7495

Components and Equipment required:

IC 7474, IC 7408, IC 7432, IC 7495 and digital IC Trainer kit.
Theory:
Shift registers are a type of sequential logic circuit, mainly for storage of digital data.
They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
the input of the next flip-flop. Most of the registers possess no characteristic internal sequence of
states. All the flip-flops are driven by a common clock, and all are set or reset simultaneously.
The data can be entered to the shift register either in serial or parallel. Similarly, the output can
be taken from it either in serial or in parallel. Since there are two ways to shift data into a
register and similarly two ways to shift data out of register, four basic types of shift registers can
be constructed. They are Serial In - Serial Out (SISO), Serial In - Parallel Out (SIPO), Parallel In
Serial Out (PISO) and Parallel In - Parallel Out (PIPO).

Circuit Diagram:

Pin Out of 7474: D Flip-flop

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Pin out Diagram of IC 7495

Serial In Serial Out (SISO):

CLK Serial in Serial out
1 1 X
2 0 X
3 0 X
4 1 1
5 X 0
6 X 0
7 X 1
8 X X
Truth Table
Circuit Diagram:

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Serial In Parallel Out (SIPO):

OUTPUT
CLK DATA
Q0 Q1 Q2 Q3
0 - X X X X
1 1 1 X X X
2 0 0 1 X X
3 0 0 0 1 X
4 1 1 0 0 1
Truth Table
Circuit Diagram:

Parallel In Parallel Out (PIPO):

DATA INPUT OUTPUT

CLK P0 P1 P2 P3 Q0 Q1 Q2 Q3
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
Truth Table
Circuit diagram:

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Parallel In Serial Out (PISO):

CLK ̅̅̅̅̅̅̅
𝑳𝒐𝒂𝒅 Q3 Q2 Q1 Q0 Output
/shift
0 0 1 0 0 1 1
1 1 0 0 0 0 0
2 1 0 0 0 0 0
3 1 0 0 0 0 1
Truth Table

Circuit Diagram:

Right shift register using IC 7495 Left shift register using IC 7495

Procedure:

1. Setup the circuit one by one. Clear all flip-flops.

2. Feed the inputs and clock and verify the output using truth table.

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Result:
Designed and setup the following shift registers and obtained the output.
1. Serial In - Serial Out (SISO)
2. Serial In - Parallel Out (SIPO)
3. Parallel In - Serial Out (PISO)
4. Parallel In - Parallel Out (PIPO)
5. Right shift register using IC 7495
6. Left shift register using IC 7495

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Experiment No. 12
RING COUNTER AND JOHNSON COUNTER
Aim:
To design and setup four bit Ring Counter and Johnson Counter using FF & 7495.

Components and Equipment required:

IC 7474, IC 7495 and digital IC Trainer kit.
Theory:
Shift counters give a specific set of counter states. It is obtained by shifting a specific
array of binary inputs. Ring counter and Johnson counter are the two important shift registers.
Ring Counter: It is a shift counter shifting the sequence in a cyclic nature. A ring counter is
constructed using JK flip flop by connecting Q and Q ̅ outputs from one flip-flop to J and K
inputs of next flip flop respectively. The output of the final flip flop is connected to input of the
first flip flop. To start the counter, the flip flops should be initialized using preset and clear
inputs. For each clock pulse the number gets shifted like in a ring. Ring counter is called a
divide by N counter where N is the number of flip flops. Ring counter divides the flip flop by N.
Ring counters are used for switching devices or lamps in a particular order, rotate a stepper
motor etc.
Johnson Counter: A ring counter can be converted to a Johnson counter by connecting Q ̅ and Q
outputs of the last flip flop to the J and K inputs of the first flip flops respectively. The mod
number of counter is double of that of the ring counter. Johnson counter is also called twisted
ring counter or divide by 2N counter.

Circuit Diagram:

Pin out of IC 7474

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Ring Counter using D Flip Flop:

Clk QA QB QC QD
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 0 0 1 0
8 0 0 0 1
9 1 0 0 0

Truth Table
Circuit Diagram

Timing Diagram

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Johnson Counter using D Flip Flop:

Clk QA QB QC QD
1 0 0 0 0
2 1 0 0 0
3 1 1 0 0
4 1 1 1 0
5 1 1 1 1
6 0 1 1 1
7 0 0 1 1
8 0 0 0 1
9 1 0 0 0

Truth Table
Circuit Diagram

Timing Diagram

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Ring Counter using IC 7495:

Johnson Counter using IC 7495:

Procedure:
1. Setup the Ring counter using D-Flip flop IC7474. Apply clock pulses and observe the
outputs. Repeat experiment to shift order binary pattern.
2. Setup Johnson counter. Clear all Q output by connecting clear pins to logic 0. After
clearing deactivate clear pins. Apply clock pulses and verify its operations.
3. Setup Johnson counter using IC7495 and verified its output.

Result:
Designed and setup 4 bit ring counter and Johnson counter using IC7474 and 7495.
Obtained its output and verified the truth table.

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Experiment No. 13
COUNTER IC’S
Aim:
To setup and realize counter IC’s 7490, 7492, 7493 and verify their truth tables.
Components and Equipment required:
IC 7490, IC 7492, IC 7493 and digital IC Trainer kit.
Theory:
The 7493: This 14 pin DIP TTL MSI circuit is a 4 bit binary counter that can be used in either a
mode-8 or a mode-16 configuration. If the clock is applied at input A and Q is connected to input
B it functions as a mode-16, 4 bit, binary ripple counter. Internally, there is one mode-2 counter
and a mode-8 counter that can be connected in cascade. The outputs are QD, QC, QB and QA. If
clock is applied at input B, the output will appear at QD, QC and QB and it will behave as a
mode-8 counter. In this case, flip flop QA is not used. A high level at both reset inputs R0(1) and
R0(2), will make all the flip flops reset.
The 7490: This TTL MSI decade counter has a mode-2 counter and a mode-5 counter in it. The
flip flop A forms a mode 2 counter and flip flops B, C and D form a mod-5 counter. If the clock
is applied at input A and QA is connected to input B, we get a binary decade counter. If clock is
at B, then mod-5 counter outputs are QD, QC and QB.
The 7492: This is a divide by 12 counter very similar to 7490. Flip flops B, C and D are
connected in the 3 x 2 configuration. If the input is applied at pin 1 and outputs are taken from
QB, QC and QD it will function as a mod 6 counter. If QA (pin 12) is connected to B input (pin 1)
this counter functions as a 2 x 3 x 2 or mod-12 counter.

Circuit Diagrams:

DIP Pin Out of 7490:

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Internal Block Diagram of 7490:

Internal Diagram of 7490:

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Truth Table of Decade Counter:

CLK QD QB QC QA

1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1

Decade counter using 7490

DIP Pin Out of 7493

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Internal Block Diagram of 7493:

Internal Diagram of 7493:

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Truth Table of 4 bit Binary counter:

CLK QD QB QC QA

1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1 0 1 0
12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1

4 bit Binary counter using 7493 (mod-16 counter):

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DIP Pin Out of 7492

Internal Block Diagram of 7492

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Internal diagram of 7492:

Truth Table of mod-12 counter

CLK QD QB QC QA

1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 1 0 0 0
8 1 0 0 1
9 1 0 1 0
10 1 0 1 1
11 1 1 0 0
12 1 1 0 1

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Divide by 12 counter using 7492:

RESET/COUNT Function Table for 7490

RESET/COUNT Function Table for 7492 and 7493

Procedure:
1. Test all components, connecting wires and IC packages using multimeter and digital IC tester.
2. Verify the working of the counters and their truth tables.

Result:
Studied the counter ICs 7490, 7492 and 7493 and the outputs are verified using truth
tables.

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Experiment No. 14
MULTIPLEXERS AND DE-MULTIPLEXERS USING GATES AND ICs
Aim:
To study multiplexers and de-Multiplexers using Gates and ICs (74150, 74154).
Components and Equipment required:
IC 7404, IC 7432, IC 7411, IC 74150, IC 74154 and digital IC Trainer kit.
Theory:
4:1 Multiplexer using gates: Multiplexer is a combinational circuit which selects one of inputs
and route it to output. A MUX has data input lines, data select lines and output. According to the
2 bit binary code on data selected inputs, corresponding data input line will be selected and
routed to output. If S1 S0 is 00, D0 will be selected, if S1 S0 is 01, D1 will be selected and so on.
The Boolean expression is given by,
Y = D0 S̅1 ̅̅̅
S0 + D1 S̅1 S0 + D2 S1 ̅̅̅
S0 + D3S1S0
1:4 Demultiplexer using gates: Demux does the reverse operation of multiplexers. The data on
a line is directly given to anyone of the output line according to the binary code on data select
lines. When the inputs S1S0 is 00, logic state on data line will be available on D0 output and so
on.
16:1 Multiplexer using IC 74150: It is a 16:1 MUX in 24 pin DIP. It has 16 data inputs D0
through D15 and four data select inputs, S0, S1, S2, S3 . The output is compliment of input data.
Strobe input is active low. If S3, S2, S1, S0 is 0000, output will be ̅D̅̅0̅, if S3, S2, S1, S0 is 0001,
output will be ̅̅̅
D1 and so on.
1:16 Demultiplexer using IC 74154: Demux using IC74154 is a 1:16 demux in 24 pin DIP. It
has a data input D and 16 outputs Y0 through Y15 and an active low strobe input. The data select
inputs ABCD decides the output pin at which the data should be available. For example, if
ABCD = 0001, the data input will be available at Y1 output.

Circuit Diagram and Design:

7411 Pin Out

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4:1 Multiplexer using gates

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Logic Symbol Truth Table

Boolean Expression: Y = D0 S̅1 ̅̅̅

S0 + D1 S̅1 S0 + D2 S1 ̅̅̅
S0 + D3S1S0
Circuit Diagram

1:4 Demultiplexer using gates

S1 S0 Y0 Y1 Y2 Y3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D

Logic Symbol Truth Table

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Circuit Diagram

16:1 Multiplexer using IC 74150

Data Select Output

Strobe
A B C D Y
0 0 0 0 0 ̅̅̅̅0
D
0 0 0 0 1 ̅̅̅
D1
0 0 0 1 0 ̅̅̅̅2
D
0 0 0 1 1 ̅̅̅̅3
D
0 0 1 0 0 ̅̅̅̅4
D
0 0 1 0 1 ̅̅̅̅5
D
0 0 1 1 0 ̅̅̅̅6
D
0 0 1 1 1 ̅̅̅̅7
D
0 1 0 0 0 ̅̅̅̅8
D
0 1 0 0 1 ̅̅̅9
D
0 1 0 1 0 ̅̅̅̅̅
D10
0 1 0 1 1 ̅̅̅̅̅
D11
0 1 1 0 0 ̅̅̅̅̅
D12
0 1 1 0 1 ̅̅̅̅̅
D13
0 1 1 1 0 ̅̅̅̅̅
D14
0 1 1 1 1 ̅̅̅̅̅
D15
1 X X X X 1
Truth Table

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Pin Out of 74150 16:1 MUX using 74150

1:16 Demultiplexer using IC 74154
Data Select Output
Strobe Data
A B C D Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1 1 X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Pin Out of 74154 1:16 DEMUX using 74154

Procedure
1. Test all ICs and wires. Setup circuit 4:1 Mux circuit using gates as shown in the figure.
2. Feed all combinations of select lines one by one, observe the logic state at a
corresponding output and verify its functions using truth tables.
3. Repeat for 1:4 Demux circuit.
4. Setup the circuit of 16:1 mux using 74150 and 1:16 demux using 74154 IC as shown in
figure and verify the truth table.

Result
Studied multiplexers and de-Multiplexers using Gates. Also familiarized the 16:1
multiplexer IC 74150 and 1:16 Demultiplexer IC 74154.

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Experiment No. 15
COMBINATIONAL CIRCUITS USING MUX & DEMUX
Aim:
i) ̅B
To realize the function Y = A ̅ C̅D
̅+A ̅B̅ CD
̅+A̅BCD + ABC̅D ̅ + ABCD̅ using 16:1
Multiplexer IC 74150.
ii) To realize the function Y = A ̅B ̅ CD + A̅BCD + AB
̅ C̅D
̅ + AB
̅ CD using 1:16 De-
Multiplexer IC 74154.
Components and Equipment required:
IC 74150, IC 74154, IC 7420 and digital IC Trainer kit.
Theory:
̅B
Y=A ̅C̅D
̅+A̅B̅CD̅+A ̅BCD + ABC̅D
̅ + ABCD
̅ using 16:1 Multiplexer IC 74150:
̅B
The expression Y=A ̅C̅D ̅B
̅+A ̅CD
̅+A̅BCD + ABC̅D ̅ + ABCD̅ , denotes Σm( 0,2,7,12,14).
So connect D0 , D2 , D7, D12 , D14 to ground and give Vcc to all other data inputs. We get a high
value of output for 0000,0010,0111,1100,1110.

Y=A ̅B
̅CD + A ̅BCD + AB ̅C̅D
̅ + AB
̅CD using 1:16 De-Multiplexer IC 74154:
The given expression 𝐴𝐵 ̅̅̅̅𝐶𝐷 + 𝐴̅𝐵𝐶𝐷 + 𝐴𝐵̅ 𝐶̅ 𝐷
̅ + 𝐴𝐵̅ 𝐶𝐷 is also expressed as
f(A,B,C,D)=∑m(3,7,8,11). Outputs of 74154 are active low. Minterms of the function are
3,7,8,11. If the binary numbers corresponding to these numbers are applied at the select inputs,
corresponding data output will be 0. The outputs Y3, Y7, Y8 and Y11 must be inverted and ORed
to obtain Y. When active low inputs are fed to NAND gate input, it is equivalent to OR
operation.

Circuit Diagram:

Pin Out Diagram of 7420 IC

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̅𝐁
Y=𝐀 ̅ 𝐂̅𝐃
̅ +𝐀
̅𝐁̅ 𝐂𝐃 ̅ 𝐁𝐂𝐃 + 𝐀𝐁𝐂̅𝐃
̅ +𝐀 ̅ + 𝐀𝐁𝐂𝐃
̅ using 16:1 Multiplexer IC 74150:

Inputs Output
A B C D Y
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

Truth Table Y = Σm( 0,2,7,12,14) Realization using 74150

̅𝐁
Y=𝐀 ̅ 𝐂𝐃 + 𝐀 ̅ 𝐂̅𝐃
̅ 𝐁𝐂𝐃 + 𝐀𝐁 ̅ + 𝐀𝐁
̅ 𝐂𝐃 using 1:16 De-Multiplexer IC 74154:

Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

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Truth Table Y = ∑m(3,7,8,11) Realization using 74154

Procedure:
1. Test the ICs and connecting wires.
2. Set up the circuit as shown in figure and verify its truth table.
Result:
i) Realized the function Y = A ̅B̅C̅D
̅+A ̅B̅CD̅+A̅ BCD + ABC̅D
̅ + ABCD
̅ using 16:1
Multiplexer IC 74150 and verified the output.
ii) Realized the function Y = A ̅B̅CD + A ̅ BCD + AB
̅C̅D
̅ + AB
̅CD using 1:16 De-
Multiplexer IC 74154 and verified the output.

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