Transactionson Power Delivery, Vol. 7 No.
1,Janua~y1992
A REALTIME DIGITAL SIMULATOR FOR TESTING RELAYS
P.G. McLaren, Senior Member R. Kuffel, R. Wierckx, J. Giesbrecht, Member, L. Arendt
Department of Electrical and Computer Engineering
University of Manitoba
Winnipeg. Manitoba, Canada R3T 2N2
Keywords. Parallel processing. Digital Signal Processor, Simulation, Relays.
ABSTRACT
This paper describes the shvchue and performance of a real
time digital simulator (RTDS) for testing relays. The RTDS uses
parallel processing architecture based on a state of the art
Digital Signal Processor (DSP) to run power system simulations
in real time with a time step of 50-1OOps. Physical devices such
as relays, energy monitors for MOV's or Power System
Stabilisers (PSS) can be fed with the appropriate signals from
the RTDS and the output from the physical device can be fed
back into the simulation. Examples are given of tests on a
commercial distance relay.
I"
Relay test facilities have evolved along with the capability
of the relays they have been designed to test. Devices such as
induction disk or balanced beam relays responding to rms values
of their input signals could legitimately be tested on heavy
current test benches using power frequency signals transformed
down from the mains. Operating times of lOOms or more meant
that fault transients were of little significance. As induction
cup, moving coil and electronic relays became available with
"instantaneous" operating times it became necessary to
accurately model at least the exponential component of fault
waveforms. Heavy current air cored coils along with point on
wave switches became the recognised test apparatus. With the
advent of "BlocWspike" [ 11 and "Sampling" [2] electronic
relays engineers began to appreciate that speed of operation and
speed of maloperation went hand in hand. System expansion
and interconnection nonetheless required faster operating times
to ensure stability. Test procedures which could adequately
represent the fault "noise" signal components both on the relay
input signals (travelling waves, transducer distortion) and
electromagnetic interference from the relay environment had to
be taken into account. The system model used to produce the
test waveforms became more complex and analogue T N A s of
increasing complexity and cost were employed 131. There were
only a few of the latter, mostly in the hands of the relay
manufacturers and research institutions. A more satisfactory
solution has now emerged with the availability of digital fault
recordings or digital waveforms from an off-line EMTP
(Electromagnetic transient program) study. The digital
waveforms are played back in real time at the relay under test via
programmable D/A's (Digital to Analogue converters) or
microcomputers and conditioning amplifiers. The EMTP
solution allows more detail of the power system to be included
but the real time aspect of the test procedure is lost The ability
to alter a parameter in the primary system and rerun the case can
also be a very time consuming process. In addition there are
A paper recommended and approved
9 1 SM 319-4 PWRD
by the IEEE Power System Relaying Committee of the
IEEE Power Engineering Society for presentation at
the IEEE/PES 1991 Summer Meeting, San Diego,
California, July 28 - August 1, 1991. Manuscript
submitted February 1, 1991; made available for
printing April 16, 1991.
o885-8977/91/$3.ooQ1992 IEEE
207
Manitoba HVDC Research Centre
400-1619 Pembina Highway
Winnipeg. Manitoba, Canada R3T 2G5
storage limits for the output waveforms from the EMTP which
typically limit the study to a duration of 0.5s of fault
waveforms. It is possible to build up a sequence of fault
waveforms and to allow some interaction of the relay and
breaker with the solution process if a data bank of fault studies
is built up and a process controller used to decide the sequence of
waveforms [4].
The need to increase the transmission capability of existing
and new electrical networks is forcing the relay engineer to
examine the performance of present and future relays in greater
detail than has been the case in the past. Shunt and series
compensation, hybrid ac-dc systems and back to back converter
stations are examples of relatively new system elements which
create new problems for the relay engineer. The performance of
back up relays, power swing blocking features, adaptive features
such as recognising the opening of the remote end breaker, etc.,
require simulation runs which can interact with the relays and
controllers to examine these features. Either the off-line
simulations must incorporate models of the relays and
controllers or a sufficiently detailed real time simulator must be
available which can interact with the relays and controllers.
The former solution raises questions about the validity of the
relay simulation and until recently the latter solution has not
been available.
The Manitoba HVDC Research Centre has now developed a
fully digital real time simulator capable of modelling power
systems of sufficient complexity for testing relays. This has
been achieved by using parallel processing techniques coupled
with the latest DSP (Digital Signal Processor) technology.
This paper briefly describes the simulator hardware, how a
-
case is entered using an input graphics package running under X
Windows, and examples of test signals used to test a distance
relay.
Whereas analogue simulators use scaled down models of
system elements, a digital simulator models these same
elements by solving the mathematical equations which describe
the element behaviour. To run an electromagnetic transient
study a time step of approximately 50ps is required. A system
such as that shown in Fig. 4 would require hundreds of millions
of floating point operations per second (MFLOPS) to solve all
the necessary equations at least once in a single time step. The
most powerful computer workstations available today can run at
only a few MFLOPS on an intermittent basis. It is clear that a
special purpose device is required which uses parallel processing
techniques running on processing elements capable of very
high speed floating point arithmetic.
The RTDS is made up of several standard 19" racks. Each
rack contains 18 processing element cards (PE's), one inter-rack
communication card (IRC) and one workstation interface card
(WIC) [5]. The system used for the relay tests, Figure 4, required
two such racks, Any one rack can directly communicate with
four other racks. Due to the natural sparsity of power systems
208

this is not a significant restriction. Since there are only three
types of card, and programmable VLSI devices are used to
construct the cards, the cost of the RTDS is much less than for
an analogue simulator of similar capability. In addition the
same card may be used to run code representing a synchronous
machine in one study [6] or a transmission line in another
study. This is a versatility which an analogue simulator cannot
match.
Figure 1 shows the layout of the arrangement for testing a
relay. The RTDS for this study occupies two 19" racks in the
simulator cubicle. Typically a 4 rack RTDS would allow a fairly
complex test system to be assembled. Figure 2 is a photograph
of the test apparatus and this should be compared to the extent
of an analogue TNA to perform the same study [3]. The largest
items are the 6 current and 6 voltage conditioning amplifiers.

Each PE card is equipped with a processor capable of up to 13

MFLOPS. It also has hardware to allow interfacing to external
signals. Two analogue channels can be selected to monitor
variables being computed on that card and these channels can be
voltagdcurrent
scaled on-line to suit the external device. (The signals to drive amplification
the conditioning amplifiers feeding the relay were obtained relay under test
from these channels.) There is also a circular buffer with 6144
data locations which can be used to capture a designated part of
the variables for subsequent display or processing on the host
workstation. An input channel can also accept a logic signal
such as the closing of the test relay contacts to trigger breaker
opening. h
user interface simulator
The IRC card transfers data generated on its rack to other
connected racks which need this information €or the next time
step. Transfer of information takes place at 500 Mhz.

The WIC deals with the communication between the RTDS

and the host computer network over an ethernet communication
link. The data transfer rate is 10 Mhz. The WIC is not involved
in the real time simulation but deals with the downloading of the Figure 1- Closed Loop Testing of a Physical Relay
case prior to the run and running on-line diagnostics to ensure
each PE is operating correctly.

RTDS and conditioning amplifiers Close up of RTDS

Figure 2 -Photograph of test set up


Figure 3 - Screen dump from host workstation during system data entry.
Simulator soft ware
The user interface to the RTDS is via the host workstation
on which various high level software routines are available to
set up, run and analyze a case. Figure 3 is a "screen dump" from
the host workstation of a system being assembled for another
study using the input graphics routine called "DRAFT". The
screen is divided into a right 'menu'or component selection area
containing Icons representing all of the system elements which
have been coded for the real time simulator, and an area on the
left where the system is being assembled. With the aid of a
mouse any desired component can be selected and dragged into
the left area to be connected at the desired location. There are
many more Icons available than are shown on the screen and
again the complete menu can be examined by using the mouse in
the right hand window to scroll up and down, left and right.
When a particular Icon is incorporated in the circuit diagram the
user is prompted on the screen to supply the necessary data for
the item in question. Although only a portion of the entire
circuit is visible on the screen, one can move around the whole
circuit by scrolling with the mouse.
Once the circuit diagram is complete, the information is
translated into a data file for use by the compiler. The compiler
combines this information with information derived from
another input program describing the system dynamics, eg.
209
timing and type of fault, prefault load flow,etc., and produces
the code which must be executed by the PE and IRC cards on each
rack. The compiler uses diakoptic techniques to separate
thepower system model into decoupled blocks which can be
executed on the available RTDC racks. It performs the software
equivalent of "patching" in an analogue computer and indicates
to the user which card has been allocated which model. This
allows the user to identify where he should connect say an
oscilloscope to observe a particular variable behaviour.
The machine code run by individual processors is hand
assembled and stored in a library of routines. These sets of
instructions representing the various models are stored on the
host workstation and are accessed by the compiler as required.
The user of the RTDS need never be exposed to this low level
software.
Results
When the compiler has completed its task the case is run up
to ~e prefault steady state under the control of the turbine
governor. This takes several minutes due to the time constants
involved. Once the steady state is established the fault is
applied from the keyboard when the user is satisfied that the
conditioning amplifiers have been switched on, recording
apparatus trigger primed, etc. In the series of tests to be
210

-
Figure 4 System diagram.

described the breaker is triggered by the closing of the test relay the result for a close up reverse fault. The relay has tripped in
contacts. The breaker model has a pre-insertion resistor which Zone 3 aftex the zone three timer has expired. This timer was
comes in at the first current zero after the relay trip and current deliberately set at a low value (4Oms) since there are no other
interruption takes place at the following current zero. In order relays on the system to clear the fault in a time scale which will
to keep the model system in synchronism, the breaker is keep the system stable. The zone 1 and zone 2 elements did not
reclosed after looms with the fault removed. While this would pick up showing correct action of the memory polarisation.
not be the procedure followed in practice it avoids the necessity Finally Figure 10 (a) shows the machine rotor A@ signal for a
of closing down the case and restarting under governor control.
The system has no power system stabiliser and the power reclose time of lOOms and 2OOms. Figure 1O(b) shows the Am
swings continue for some time after the reclose. On the other signal and the phase "a" current on a different time scale for the
hand this allows the relay to be tested under power swing lOOms reclose case.
conditions. The time between successive faults on the same
case was dictated by the time it took the power swings to die DSA 601 DIGITIZING SIGNAL ANALYZER
out. date: 3O-JAN-91 tim: 14: 32 53

Figure 4 is a one-line diagram of the power system used in Voltage Scale 375 kV/div
the tests. One source is ideal with an equivalent source 3oomv
impedance and the other is a full turbo alternator model with
governor and AVR. The pre-fault load flow is 263.73 M W at
unity p.f. from the alternator. Data for the test system is given
in the appendix. The test relay is a 3 zone distance relay
employing an analogue phase comparator. The protected line is
lOOkm long and the zone 1 setting was chosen to be 2 7 m
primary ohms corresponding to 80 km. Zone 2 was set at 120%
of zone 1 and zone 3 at 150%of zone 2 in the forward direction 50mV
and 25% of zone 1 in the reverse direction. All three zones have Idiv
circular mho characteristics.

The scaling of output variables had to ensure that the

conditioning amplifiers could handle the levels. The present
current amplifiers can only reach 20A rms and the fault currents d: $
were therefore kept below this level. There was no problem
with the voltage amplifiers. The present study does not use CT
and CVT models although the code is available to run such -
models.
Currentscale 8kAldiv
The following figures show waveforms recorded on a digital
storage oscilloscope and subsequently downloaded to an X-Y
plotter. Only a few of the test waveforms are shown to illustrate
the capability of the RTDS. -19.8ma i0mddiv 00.2-
ti- i B 0 . 0 ~ ~ Cursor
t2- 22.5Bmo TYW
Figure 5 shows the complete screen plot containing voltage At- 22.40mr Verticel
and current variables at the relay location for a three phase short i/At- 44.64Hz
circuit at 50 kms along the line. The two cursors indicate the
fault initiation and the relay trip signal which in this case axe
22.4 ms apart Figure 6 shows a line to line fault at the same
location. The time scale is longer and the first part of the
reclose waveforms can be seen. The relay trip time is 21.6 ms.
Figure 7 shows the waveforms for a l i e to ground fault on phase Figure 5 -Voltage and current waveforms for a three-phase fault.
"a" with no offset in the faulted phase current and Figure 8(a) is
the corresponding case with maximum offset. Figure 8(b)
shows the maximum offset case when the fault resistance is 5Q
and there is an increase in the relay trip time. Figure 9 shows
 21 1

Voltage Scale 375 kV/div Voltage Scale 375 kV/div

-0:: ::
I

I t

I_Lt-li
I I
I I i
I
-19.Bms lOms(div 80.2mS
Relay Trip

Figure 8(a) -Waveforms for U3 fault, max. offset

-39.6~18 20ms(div 160.4~1~

1
r 1 I

---- -
Figure 6 -Waveforms for an ab line to line fault
1 Voltage Scale 375 kV/div---- T - -7 - -1

Figure 8(b) -Waveforms for U3 fault, R, = 5R

Voltage Scale 375 kvldiv

i I ' I

Figure 7 -Waveform for U3 fault, no offset

1
i
-19.ems lOns/div 80.2111s
Figure 9 - Waveforms for close-up reverse fault
212
University of Manitoba in xunning the tests and recording the
test waveforms.
r f 1

Macpherson, R.H., Warrington, A.R. Van C., and

McConnell, A.J., "Electronic protective relays", Trans.
Am. Inst. El=. Eng., 1948, 67 Pt. II, pp. 1702-1708.

McLaren, P.G., "Static sampling distance relays", Proc.

IEE. 1968, 115 (3). pp. 418-424.
Nimmersj6, Gunw. Hillstrb, Birger. Wemer-Erichsen,
I t . I Odd, Rockefeller, George D., "A digitally-controlled,
-3.96s 2ddiv 16.04s real-time, d o g power-system simulator for closed-loop
protective relaying testing", IEEE Trans. on Power
Figure lqa) -Am for 100 and 200 ms reclose intervals Delivery, Vol, 3, No. 1, Jan. 1988, p. 138.

Esztergalyos. Jules, Nordstrom, Jerry, Short, Thomas H.,

and Martin,Ken. "Digital Model Power System". IEEE
"Computer Applications in Power", Vol. 3. No. 3. July
1990, pp. 19-24.

Rosendahl, G.K., Wierckx, R.P.. Maguire, T.L.,

Woodford, D.A., "A Parallel Machine for Real-Time Power
System Simulations". Canadian Conference on Electrical
and Computer Enginming, Montreal, September 1989.

Brandt, D., Wachal, R., Valiquette, R., Wiercks. R.,

-99Oms
1 I .
500ma/div 4.018,
I "Closed loop testing of a joint var controller using a
digital real-time simulator", IEEE PES Winter Power
I Meeting, New York, February 1991. Paper 91WM 240-2-
PWRS.
Figure 1O(b)--A@ 1. for 100 ms reclose interval
"Dynamic Models for Steam and Hydro Turbines in Power
Systems Studies", IEEE PAS-92. Nov/Dec. 1973. p. 1904.
The sample results shown above illustrate the capability of APPENDM
the RTDS to run real time simulations for testing relays. The
size and versatility of the RTDS should be clear from Figure 3
and the fact that it has already been used to test two completely
w
different power system devices [6]. The RTDS is small enough General:
to be taken to a substation to test relays and it will shortly be Base MVA = 590 MVA
used in this capacity at the Dorsey converter station of Base Voltage (high side) = 230 kV
Manitoba Hydro to check the performance of the existing relays Therefore Base Impedance = 89.66i2
on a series compensated line. The RTDS can also be interfaced
to existing analogue simulators to greatly enhance their Transmission Lines:
capability and it is likely to be used in this way with present day
HVDC analogue simulatoxs.
- Modelling 2 x 100 lan lines
- Travellii wave models
Transducer models and MOV's have now been coded for use - Flat line configuration
with the RTDS and the algorithms give excellent representation - Lines are not transposed
of the non-linear effects without the need to iterate. These same - Positive Sequence Characteristic impedance = 259.64R
algorithms have been incorporated in EMTDC and greatly - Zen, Sequence Characteristic impedance = 744.13i2
increase the speed of solution in off-line studies. The "DRAFT"
input routine asks whether the data is for use with EMTDC or the Generator:
RTDS and any case can be checked by running off-line 590 MVA
simulation with EMTDC. 22 kV
Xd" = 0.215 PU ~d,," = 0.032 sec.
Faster processors with more onboard EPROM will allow Xa' = 0.280 pu TQ = 4.2 sec.
smaller time steps to be used and an increased number of racks xd=2.11 pu
will allow larger systems to be modelled. X,,"= 0.215 pu Tq/ = 0.062 sec.
x, = 2.02 pu
ACKNOWLEDGEMENTS R. = 0.0046 pu
& = 0.155 pu
The authors wish to acknowledge the financial support
given by Manitoba Hydro. They also wish to acknowledge the Exciter:
advice
_ _ - and
- technical assistance eiven bv Mr. T. Goldsborouah IEEEStandard STlA
of Manitoba Hydro and the asskame 6 f Mr. E. Dirks of &e ."
Ka = 100.0 (cain)
r

Exciter Time constant T. = 0.02 sec.
Transducer Time Constant TR= 0.02 sec.
Turbine:
Based IEEE Standard [I- (tandem Compounddouble
reheat)
&&r G. MeLann w u born in Perth, Scotland in 1936. He
received his bachelor's degree from the University of St.
Andrews in 1958 with first class honours in Electrical
Engineering. He then worked for A.E.I. for 3 years in their
power systems development department in Manchester, England
before returning to St. Andrews to take up a University
Lectureship in power systems and machines. During his 6 years
at St. Andrews he completed his doctorate in power system
protection as a part time research student. He then spent 1 year
at Heriott Watt University in Edinburgh before joining the staff
of the Engineering Laboratoq in Cambridge in 1968. His main
research interests are power system protection, condition
monitoring of large electrical motors, surges in electrical
machines and systems, and superconductors.
In July 1988 he moved to the University of Manitoba to
become the NSERC Industrial Research Chair in Power Systems
and is now a registered engineer in the province of Manitoba.
He is also a Senior Member of the IEEE and a Chartered Engineer
in Europe (Eurhg.).
Jt. Kuffel was born on December 15. 1961 in Manchester,
England. He studied electrical engineering at the University of
Manitoba in %peg, Canada receiving his BSc. in 1984 and
his MSc. in 1986. His industrial experience includes one year
with Brown Boveri (BBC) at their analog simulator Facility in
Turgi, Switzerland. Mr. Kuffel then returned to Winnipeg and
spent two and a half years with Teshmont Consultants Inc.
213
Presently he ie employed by the Manitoba HVDC Research
Centre where he works as a member of the analog simulation
team responsible for utilizing and maintaining the ABB HVDC
simulator situated at the Centre. He is also actively involved in
the development of the real time digital simulator and its
associated software.
E W l e r a graduated from the University of Manitoba with a
B.Sc. (EE) in 1983 and a MSc. (EE) in 1985 and is currently
enrolled in the Ph.D. program. Since 1985 he has been
employed by the Manitoba HVDC Research Centre as
Simulation Engineer.
W.J.s) Giesbreck (M') received his B.Sc. (EE)
degree at the University of Manitoba in 1969. and M.Sc. (EE)
and Ph.D. degrees from the University of Waterloo in 1977 and
1981 respectively.
His industrial experience includes 7 years at GE Canada
designing HVdc computer controls and digitally controlled
exciters. Dr.Giesbrecht is presently employed at the Manitoba
HVDC Research Centre in Winnipeg. His research interests
include applications of microcomputers to power systems and
power system controls.
Lawrence H. A r u was born December 12, 1962 in
Winnipeg, Manitoba. He received his B.Sc. (EE) degree from
the University of Manitoba in 1984. His industrial experience
include four and a half years designing intelligent industrial
monitoring and controls devices. Mr. Arendt is currently with
the Manitoba HVDC Research Centre in Winnipeg. His
responsibilities include designing hardware and writing
software for the Centre's real-time digital simulator.