NIDHI PATEL

Telephone: 669-333-2694 E-mail: nidhipatel.ee@gmail.com Linkedin : https://www.linkedin.com/in/nidhipatel18

OBJECTIVE
Actively looking for full time position or internship in the field of ASIC Design, PCB Design.

EDUCATION
Northwestern Polytechnic University (3.6/4 GPA) August 2014 – April 2016
Masters in Electrical Engineering ( VLSI Design)
Gujarat Technological University (7.6/10 CGPA)
Bachelors of Electronics and Communication Engineering July 2009 - May 2013

TECHNICAL SKILLS
Operating system: LINUX, Windows family, IOS
Tools: Synopsys VCS, Cadence NC- verilog, keil, MATLAB, KiCAD
Machine level language: X-86, ARM, MIPS
Programming language: VHDL, Verilog, JAVA

SPECIALITIES
VHDL and Verilog Programing, High level -Logic synthesis, in-depth knowledge of CMOS circuits, Oscilloscope, PCB Design.

WORK EXPERIENCE
 ELECTRICAL ENGINEER INTERN YzOak (August, 2016 - Present)
CAD and PCB Designing.
 TRAINEE ENGINEER JAILAXMI INDUSTRIES (JANUARY-APRIL, 2014)
Asist Sr. engineer in production department. Maintaining operating procedure for manufacturing.
 INTERN PATEL CONSTRUCTION AND SUPPLIER (JULY-NOVEMBER, 2013)
Make a bridge of understanding regarding product between clients and supplier. Make client aware about
products.
Maintain database of client, products.
PROJECT DETAILS

 HEALTH METER DESIGN (Intra university project competition: 2nd rank) (Spring 2016, MSEE)
Role: Team leader, Circuit design, testing of circuit
Design of Health meter that counts pulse rate and measures body temperature.
Software used: TINA (Toolkit for Interactive Network Analysis), Circuit sandbox
Components used: Arduino kit, LM386, MCP9700, low pass filter, HS-08 Bluetooth

 DESIGN OF MULTI LEVEL CARRY LOOK AHEAD CARRY ADDER (Fall 2015, MSEE)
Verilog modules of 8, 16 & 32 bits of Ripple Carry Adder & Look Ahead Carry Adder were made in Verilog.
Simulation: using Synopsys VCS tool in UNIX environment & compared by various constraints such as power, area & slack.
Done Static Timing Analysis (STA) of every module

 RESEARCH PROJECT OF DRAM (1T1C CELL) (Spring 2015, MSEE)

Done research work on DRAM Memory cell - 1T1C versions, Layout, READ/WRITE Operations, Cell Stability.
 DESIGN OF ACLR FILTER (Fall 2014, MSEE)
Design of ACLR filter using Bartlett-Hanning window method
Software simulation in MATLAB to verify system performance, to study gain/phase responses, noise margin, gain/phase
crossover frequencies, system output response and stability analysis.
 Role: System response analysis, algorithm modifications to improve noise margin and system stability.
 VENTILATOR USING STEPPER MOTOR CONTROLLER (May 2013, BEEC)
Built automatically controlled ventilator with help of electronic components and software program
Components Used: (x51) Controller, Transistor (BC547 NPN), Digital Array (IC ULN2003), 7- segment LCD, Pressure Sensors
Role: Identification of components, circuit building, system performance study and enhancement.
 4x7 SEGMENT DISPLAY CONTROL (November 2012, BEEC)
Four 7-segement displays were controlled using 89C52 controller to display time and date
Components Used: Atmel 89C52 Controller, Capacitors (33pf, 10µf), Resisters (10k & 330Ὡ)
Connection: port 2.0 - p2.6 was used in digital clock to display time
Role: Component selection, Interfacing and circuit design, Machine language code development for micro controller

COURSE WORK
System analysis and simulation Advance digital IC design
Microelectronics circuit design and analysis Advance UNIX/LINUX programming
Digital design and HDL VLSI design (place and route)
Computer architecture Applied specific integrated circuit design
Network engineering and management Design verification with system verilog

REFERENCES
Mohan Landgu Rohit Yadav Vrunda Desai
Lead Integration Engineer Analytics Consultant Purchase Analyst
Finesse Inc Slalom Consulting Netflix