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IRFB3207
IRFS3207
IRFSL3207
Applications
HEXFET® Power MOSFET
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply D
VDSS 75V
3.6m:
l High Speed Power Switching
l Hard Switched and High Frequency Circuits RDS(on) typ.
Benefits G
max. 4.5m:
l Worldwide Best RDS(on) in TO-220
S ID 180A
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case k ––– 0.45
RθCS Case-to-Sink, Flat Greased Surface , TO-220 0.50 ––– °C/W
RθJA Junction-to-Ambient, TO-220 k ––– 62
RθJA 2
Junction-to-Ambient (PCB Mount) , D Pak jk ––– 40
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03/06/06
IRF/B/S/SL3207
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 75A, VGS = 0V g
trr Reverse Recovery Time ––– 42 63 ns TJ = 25°C VR = 64V,
––– 49 74 TJ = 125°C IF = 75A
Qrr Reverse Recovery Charge ––– 65 98 nC TJ = 25°C di/dt = 100A/µs g
––– 92 140 TJ = 125°C
IRRM Reverse Recovery Current ––– 2.6 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Package limitation current is 75A as Coss while VDS is rising from 0 to 80% VDSS.
Repetitive rating; pulse width limited by max. junction Coss eff. (ER) is a fixed capacitance that gives the same energy as
temperature. Coss while VDS is rising from 0 to 80% VDSS.
Limited by TJmax, starting TJ = 25°C, L = 0.33mH When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use mended footprint and soldering techniques refer to application note #AN-994.
above this value. Rθ is measured at TJ approximately 90°C
ISD ≤ 75A, di/dt ≤ 500A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
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IRF/B/S/SL3207
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
ID, Drain-to-Source Current (A)
100
10
4.5V
2.0
100.0 (Normalized)
TJ = 25°C
1.5
10.0
1.0
VDS = 50V
≤ 60µs PULSE WIDTH
1.0
0.5
4.0 5.0 6.0 7.0 8.0 9.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
12000 20
VGS = 0V, f = 1 MHZ
ID= 75A VDS = 60V
Ciss = Cgs + Cgd, Cds SHORTED
VGS, Gate-to-Source Voltage (V)
8000 Ciss
12
6000
8
4000
4
2000
Coss
Crss
0
0
0 40 80 120 160 200 240 280
1 10 100
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRF/B/S/SL3207
1000.0 10000
OPERATION IN THIS AREA
LIMITED BY R DS (on)
TJ = 175°C 1000
100.0
100 100µsec
10.0
10
TJ = 25°C
1.0
1 1msec
Tc = 25°C
Tj = 175°C 10msec
VGS = 0V Single Pulse DC
0.1 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS , Drain-toSource Voltage (V)
150
ID , Drain Current (A)
90
100
80
50
0
70
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
TC , Case Temperature (°C)
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.0 4000
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 12A
2.5
16A
3000 BOTTOM 75A
2.0
Energy (µJ)
1.5 2000
1.0
1000
0.5
0.0 0
20 30 40 50 60 70 80 25 50 75 100 125 150 175
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRF/B/S/SL3207
1
D = 0.50
Thermal Response ( ZthJC )
0.1
0.20
0.10
0.05 R1 R2
R1 R2 Ri (°C/W) τi (sec)
0.01 0.02 τJ τC
τJ τ 0.2151 0.001175
0.01 τ1 τ2
τ1 τ2 0.2350 0.017994
Ci= τi/Ri
Ci= i/Ri
0.001
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1
0.05
10 0.10
1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
800 ID = 75A Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neitherTjmax nor Iav (max)
is exceeded.
600
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
400 during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
200 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
0 ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
25 50 75 100 125 150 175
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Starting TJ , Junction Temperature (°C) Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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IRF/B/S/SL3207
5.0 16
ID = 1.0A
VGS(th) Gate threshold Voltage (V)
4.5 14
ID = 1.0mA
ID = 250µA
4.0 12
IRRM - (A)
3.5 10
3.0 8
2.5 6 IF = 30A
VR = 64V
2.0 4 TJ = 125°C
TJ = 25°C
1.5 2
-75 -50 -25 0 25 50 75 100 125 150 175 100 200 300 400 500 600 700 800 900 1000
Fig 16. Threshold Voltage Vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt
16 400
14
300
12 QRR - (nC)
IRRM - (A)
10
200
8
6 IF = 45A IF = 30A
100
VR = 64V VR = 64V
4 TJ = 125°C TJ = 125°C
TJ = 25°C TJ = 25°C
2 0
100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt
400
300
QRR - (nC)
200
IF = 45A
100
VR = 64V
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
VGS=10V*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
-
+
Recovery
Current
Body Diode Forward
Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Ripple ≤ 5% ISD
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
LD
VDS VDS
90%
+
VDD -
D.U.T 10%
VGS VGS
Pulse Width < 1µs
Duty Factor < 0.1% td(on) tr td(off) tf
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT Vgs(th)
0
1K
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRF/B/S/SL3207
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TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
4.10 (.161) 1.50 (.059)
3.90 (.153) 0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
30.40 (1.197)
NOTES : MAX.
1. COMFORMS TO EIA-418. 26.40 (1.039) 4
2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)
3. DIMENSION MEASURED @ HUB.
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/06
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/