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I. MIFARE TAG
Step:
- Initial & Enable: USART, SPI, MFRC
- Send WUPA command. Wait until there a tag in antenna area.
- Send Anticollision command to get 4 bytes NUID
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2. Memory organnization
The 1024 x 8 bit EEPROM memory is organized in 16 sectors of 4 blocks. Oneblock contains
16 bytes.
Manafucturer block
Data blocks
- All sectors contain 3 blocks of 16 bytes for storing data.
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- The MF0ICU1 accepts the WUPA command only in Idle and halt state the response is
the 2 byte ATQA.
SELECT:
HALT:
- The Halt command is used to set the MF0ICU1 Ics into a different wait state (halt
instead of idle).
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II. MFRC
Idle:
- Places the MFRC in Idle mode. The Idle command also terminates itself.
Mem:
- Transfer 25 bytes from the FIFO buffer to the internal buffer.
- To Read out the 25 bytes from internal buffer the Mem command must be started with
an empty FIFO buffer. In this case, 25 bytes are transferrd from internal Buffer to FIFO.
- This command automatically terminates when finished and Idle command becomes
active.
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Generate RandomId:
- This command generates a 10-bytes random number which ins initally stored in the
internal Buffer. This then overwrites the current 10 bytes in the internal 25-byte buffer.
- This command automatically terminates when finished and the MFRC522 return to Idle
mode.
CalcCRC:
- The FIFO buffer content ins transferred to the CRC coprocessor and the CRC
calculation is started.
- The CRC calculation’s result is stored in CRCResultReg register.
- The CRC calculation is not stopped when the FIFO buffer is empty during the data
stream. The next byte written to the FIFO buffer is added to the calculation.
- The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0]. The
value is loaded in to the CRC coprocessor when the command starts.
- This command must be terminates by writing a command to the CommandReg[3:0].
Transmit:
- The FIFO buffer content is imediately transmitted after starting this command.
- Before transmitting the FIFO buffer content, all relevant registers must be set for data
transmission.
- This command automatically terminates when the FIFO buffer is empty. It can be
termanated by another command written to the CommandReg[3:0].
NoCmdChange:
- This command does not influence any running command in the CommandReg register.
Receive:
- The MFRC522 activates the receiver path and waits for a data stream to be received. The
correct settings must be chosen before starting this command.
- This command auto terminated when the data stream ends. This is indacated either by
the end of frame pattern or by the length byte depending on the selected frame type and
speed.
- Remark: if the RxModeReg[2] set to 1. The receive command will not automatically
terminate. It must be terminated by starting another command.
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Transceive:
- This command continously repeats the transmission of data from the FIFO buffer and
the reception of data from RF field. The first action is transmit and after transmission the
comamnd is changed to receive a data stream.
- Each transmit process must be started by setting the BitFramingReg[7] to 1.
- This command must be cleared by writing any command to the CommandReg register
MFAuthent:
SoftReset
- This command performs a reset of the device. The configuration data of the internal
buffer remain unchanged. All registers are set to the reset values.
- This command automatically terminates when finished.
- Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to
9.6 kBd.
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III. CODE
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6. MFRC Initial
Description:
- Get MFRC to be ready for reading any Tag
Input: None
Output: None
Step:
- Transfer Disable
- Reset MFRC522
- Create a Auto-Timer with 25ms count up.
- Enable 100% ASK
- Enable:
o Transmitter can only be started if an RF field is generated
o MFIN Pin active high.
o Preset value for CRC calculate to 6363h
- Output signal on pin TX1/TX2 delivers the 13.56Mhz enegy carrier modulated
by the transmission data.
Infromation:
- Timer:
𝑇𝑃𝑟𝑒𝑠𝑐𝑎𝑙𝑒𝑟(3390) .𝑇𝑅𝑒𝑙𝑜𝑎𝑑𝑉𝑎𝑙(48)
25ms =
6.78𝑀𝐻𝑧
[7]: = 1 => Auto Timer : Start automatically at the end of the transmission in
all communication mode at all speeds.
= 0 => Indicates the the timers is not influenced by the protocol.
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TxControlReg: control the logical behavior of the antenna driver pins TX1/TX2
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7. Send Data
Description:
- Send data from FIFO Buffer to Tag.
Input:
Output:
Step:
- Initial:
o Enable TX/RX/Idle/LoArlett/Err/Timer Interrupts.
o Set signal on pin IRQ is inverted to Status1Reg[4].
o Clear all interrupt requests.
o Clear FIFO pointer.
o Set MFRC to Idle.
- Write data into FIFO Buffer
- Set MFRC to Transceive mode.
- Send data.
- Wait until Timeout or There’s interrupt request from Rx/Idle/Err
- Stop send data
- Check Timeout.
- Check Errors (BufferOvfl / CollErr/ CRCErr/ ProtocolErr)
- Check there’s a Tag by check interrupt request from(TxIrq/LoAlert/ Err).
- Get bits number of receive data.
- Get result data from FIFO Buffer
- Return.
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Information:
ComIEnReg: Interrupt Request Enable bits
[7]: = 1 => Signal on pin IRQ is inverted to the Status1Reg register’s IRQ bit
= 0 => Equal.
[6:0]: = 1 => Allows the …. Interrupt Request to be propagated to pin IRQ.
[7]: = 1 => Indicates that all bits in this register are set.
= 0 => Indicates that all bits in this register are cleared.
[6]: = 1 when last bit of the transmitted was sent out.
[5]: = 1 when receiver has detected the end of a valid data stream
[4]: = 1 when a command terminates.
If an unknown command is started, the CommandReg value changes to
idle state and this bit is set.
The MCU starting the Idle command does not set this bit.
[2]: = 1 when FIFOLength > WaterLevel
[1]: = 1 when any error bit in the ErrorReg is set.
[0]: = 1 when the timer overflow from 65535 back to 0
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[7]: = 1 => Immediately clear the internal FIFO buffer’s read and write pointer
and BufferOvfl bit.
[6:0]: Indicates the number if bytes stored in the FIFO buffer
Writing to FIFODataReg register increments and Reading decrement this
value.
[7]: = 1 => Starts the transmission of data. Only valid in Transceive Command.
[2:0]: Number of bits of last byte will be transmitted. 000b indicates that all bits
of the last byte will be transmitted.
ErrorReg: Error bits showing the errir status of the last command executed.
[4]: = 1 when MFRC write data to FIFO Buffer eventhough it is already full
[3]: = 1 when a bit-collision is detected.
Cleared automatically at reicever start-up phase.
Only valid during the bitwise anticollision at 106kBd.
[2]: = 1 when CRC calculation is failed.
Automatically cleared during receiver start-up phase.
[0]: = 1 when SOF is incorrect
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[2:0]: Indicates the number of valid bits in last received byte. If this value is 0,
whole byte is valid.
8. Wake Up
Input:
- An byte array to store ATQA response
Output:
- Status
Step:
- Set number of bits of the last byte will be transmitted to 7
- Send WUPA command to Tag
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9. Anti Collision
Input:
- A bytes array to store received 4 bytes NUID.
Output:
- Status
Step:
- Set number of bits of last byte will be transmitted to 8.
- Send AntiCollision Command
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Information:
DivIrqReg: Interrupt request bits
11. HALT
Description:
- The Halt command is used to set the MF0ICU1 Ics into a different wait state
(halt instead of idle).
Input: None
Output: None
Step:
- Send HALT command to Tag
[7]: = 1 => Clean Temperture error if the temp is below the alarm limit of 125oC.
[3]: Indicate that the MIFARE crypto1 unit is swithed in and therefore all data
communication with the card is encrypted.
Can only be set to 1 by a succsessful execution of the MFAuthent command.
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IV. SOURCE
- MFRC522 datasheet
- MifareUltra/OneS50 datasheet
- https://labitat.dk/wiki/RFID_RC522-AN
- http://calc.gmss.ru/Mifare1k/
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