Data Converter

Fundamentals

Mixed Signal IC Design : EC9041

David Johns and Ken Martin

University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)
 Introduction
• Two main types of converters
Nyquist-Rate Converters
• Generate output having a one-to-one relationship with a
single input value.
• Rarely sample at Nyquist-rate because of need for anti-
aliasing and reconstruction filters.
• Typically 3 to 20 times input signal’s bandwidth.
Oversampling Converters
• Operate much faster than Nyquist-rate (20 to 512 times
faster)
• Shape quantization noise out of bandwidth of interest, post
signal processing filters out quantization noise.

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 Ideal D/A Converter

V out
B in D/A

V ref

• B in defined to be an N -bit digital signal (or word)

–1 –2 –N
B in = b 1 2 + b2 2 …
+ + bN 2 (1)

• b i equals 1 or 0 (i.e., bi is a binary digit)

• b 1 is MSB while b N is LSB
• Assume B in is positive — unipolar conversion

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 Ideal D/A Converter
• Output voltage related to digital input and reference
voltage by
–1 –2 –N
V out = V ref ( b 1 2 + b2 2 + … + bN 2 )
= V ref B in
(2)
–N
• Max V out is V ref ( 1 – 2 )
• Multiplying DAC realized by allowing V ref to be another
input signal
• Ideal DAC has well-defined values (not same for A/D )

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 Ideal DAC Converter
V out
------------
V ref
1 2-bit DAC
3/4

1/2 V LSB 1
---------------- = --- = 1 LSB
V ref 4
1/4

0
00 01 10 11 (100) B in

V ref 1
• V LSB ≡ --------
N
- and 1 LSB = -----N-
2 2
 Example
• An 8-bit D/A converter has V ref = 5 V .
• What is the output voltage when B in = 10110100 ?
–1 –3 –4 –6
B in = 2 +2 +2 +2 = 0.703125 (3)

V out = V ref B in = 3.516 V (4)

• Find V LSB .
V LSB = 5 ⁄ 256 = 19.5 mV (5)
 Ideal A/D Converter

B out
V in A/D

V ref

–1 –2 –N
V ref ( b 1 2 + b2 2 + … + b N 2 ) = V in ± V x (6)

where
1 1
– --- V LSB ≤ V x < --- V LSB (7)
2 2
 Ideal A/D Converter
V LSB
B out ---------------- = 1/4 = 1 LSB
V ref

11

10

01
V in
00 -----------
0 1/4 1/2 3/4 1 V ref
V 01 ⁄ V ref V 11 ⁄ V ref

• A range of valid input values produces same digital output

word — quantization error.
• No quantization error in D/A converter case.

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 Ideal A/D Converter
• Transitions offset by 0.5V LSB so midpoint are same as D/A
case
Quantizer Overload
• Quantization error limited to ± V LSB ⁄ 2 otherwise
quantizer is said to be “overloaded”.
• Overloading occurs when input signal is beyond one V LSB
of the two last transition voltages.
• In 2-bit example, input should be greater than – 1 ⁄ 8 V ref
and less than 7 ⁄ 8 V ref

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 Quantization Noise
B V
1
V in A/D D/A
+
– V
Quantization
Q noise

VQ
V in
1
--- V LSB
V1 2
t
(Time)
1
– --- V LSB
t 2 T
(Time)

V Q = V 1 – V in or V 1 = V in + V Q (8)

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 Quantization Noise
VQ

V in V1
V in V1

V1 = V in + V Q

Quantizer Model

• Above model is exact

— approx made when assumptions made about V Q
• Often assume V Q is white, uniformily distributed number
between ± V LSB ⁄ 2

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 Quantization Noise
• Average of quantization noise is zero.
• Power of quantization noise can be shown to equal
V LSB
V Q ( rms ) = ----------- (9)
12
• Each extra bit results in noise power decrease of 3dB
• Noise power is independent of sampling frequency
• If assume input signal is a sinusoid of peak amplitude of
V ref ⁄ 2

 V in ( rms )  V ref ⁄ ( 2 2 ) 
SNR = 20 log ------------------ = 20 log  -------------------------------
 V Q ( rms )  V ⁄ ( 12 )
LSB
SNR = 6.02N + 1.76 dB

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 Quantization Noise
60 10-bit
SNR
50 Best possible SNR
(dB)
40

30

20
( V pp = V ref )
10

0 V in ( dB )
–60 –50 –40 –30 –20 –10 0

• SNR reaches max when input signal is max

• (might improve SNR if oversampling used)

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 Example
• A 100-mV pp sinusoidal signal is applied to an ideal 12-bit
A/D converter for which V ref = 5 V .
• Find the SNR of the digitized output signal.
•
• First, find max SNR if full-scale sinusoidal waveform of
± 2.5 V applied
SNR max = 6.02 × 12 + 1.76 = 74 dB (10)

• Since input is only ± 100-mV it is 28 dB below full scale,

so SNR of digitized output is
SNR = 74 – 28 = 46 dB (11)

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 Signed Codes
• Often need converters for both positive and negative
signals — signed codes
Sign Magnitude
• Neg numbers simply invert MSB
1’s Complement
• Neg numbers invert all bits
Offset Binary
• Assign 000... to most negative number and count up
2’s Complement
• Invert MSB of offset binary case or ...
• Neg numbers are 1 LSB larger than 1’s complement

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 Signed Codes
Normalized Sign 1’s Offset 2’s
Number number magnitude complement binary complement
+3 +3/4 011 011 111 011
+2 +2/4 010 010 110 010
+1 +1/4 001 001 101 001
+0 +0 000 000 100 000
(–0) (–0) (100) (111)
–1 –1/4 101 110 011 111
–2 –2/4 110 101 010 110
–3 –3/4 111 100 001 101
–4 –4/4 000 100

• 2’s complement most common when doing signal

processing

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 2’s Complement
111 011
000 110 100 010
3 3
-4 2 -4 2

001 -3 1 101 101 -3 1 001

-2 0 -2 0
-1 -1
010 100 110 000
011 111

Offset Binary 2’s Complement

• Each have wrap-around behaviour

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 2’s Complement Benefits
• Addition of both positive numbers is done with simple
addition (nothing extra needed)
• Subtraction of A – B done by complementing bits of B and
adding LSB into carry-in of adder
• Can go above max as long as final result is within range
(no overflow hardware needed)
Example
• 2+3+(-4) = 1
010 + 011 + 100 = 101 + 100 = 001
• Final result of 1 correct though temp result of -3 obtained

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 Performance Limitations
• For D/A measure, use output voltage levels
• For A/D measure, use transition points (easier than
midpoints)
V LSB
B out ---------------- = 1/4 = 1 LSB
V ref

11

10

01
V in
00 -----------
0 1/4 1/2 3/4 1 V ref
V 01 ⁄ V ref V 11 ⁄ V ref

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 Offset and Gain Error

V out
------------
V ref
Ideal
1

3/4
Gain error
1/2

1/4
Offset error
0
00 01 10 11 (100) B in

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 Offset and Gain Error
V out
• D/A converter — units of LSB: E off ( D ⁄ A ) = -----------
V LSB
0…0
• A/D converter — deviation of V 0…01 from 1 ⁄ 2 LSB
V 0…01 1
E off ( A ⁄ D ) = --------------- – --- LSB (12)
V LSB 2
• With gain error, set offset error to zero
 V out V out  N
E gain ( D ⁄ A ) =  ----------- – -----------  – ( 2 – 1) (13)
 V LSB 1…1
V LSB
0…0


 V 1…1 V 0…01 N
E gain ( A ⁄ D ) = ------------- – --------------- – ( 2 – 2 ) (14)
 V LSB V LSB 

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 Resolution and Accuracy
Resolution
• Number of distinct analog levels — n N -bit resolution can
N
resolve 2 distinct analog levels.
Absolute Accuracy
• Difference between the expected and actual transfer
responses — includes offset, gain and linearity errors
Relative Accuracy
• After offset and gain errors removed — also called
maximum integral nonlinearity error
• A 12-bit accuracy implies that the converter’s error is less
12
than the full-scale value divided by 2

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 Resolution and Accuracy
• A converter may have 12-bit resolution with only 10-bit
accuracy
• Another converter may have 10-bit resolution with 12-bit
accuracy.
• Accuracy greater than resolution means converter’s
transfer response is very precisely controlled — better
than the number of bits of resolution.
Example
• A two bit D/A (resolution 2-bits) with output levels at 0.0,
1/4, 2/4, 3/4 is ideal (infinite bit accuracy since no errors)

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 Integral Nonlinearity (INL) Error

V out Integral nonlinearity error (best-fit)

------------
V ref

3/4

Integral nonlinearity error (endpoint)

1/2

1/4

0
00 01 10 11 (100) B in

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 INL Error
• After both offset and gain errors removed, integral
nonlinearity (INL) error is deviation from a straight line.
• Can use endpoint or best fit straight lines — endpoint
more conservative
• INL plotted for each digital word

INL max INL

0.5LSB

0
00 01 10 11 (100) B in

• Maximum INL also referred to as relative accuracy

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 Differential Nonlinearity (DNL) Error
• Ideally, each step is 1 LSB away from adjacent level
• DNL defined as variation in step sizes from 1 LSB
(once gain and offset errors removed)
• Example — Max DNL = 0.5 LSB has at least one step size
which is either 0.5 LSB or 1.5 LSB
• As in INL error, DNL plotted for each digital word and
max is maximum magnitude.

DNL max DNL

0.5LSB

0
00 01 10 11 (100) B in

step size between 00 and 01 is 1.5 LSB

step size between 10 and 11 is 0.7 LSB

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 Monotonicity
Monotonic D/A Converters
• Where output alway increases as input increases
— no negative slope in transfer-response
• Important for some control loop applications
• If max DNL < 1 LSB, converter is monotonic
• Can be monotonic and have DNL > 1 LSB
• If max INL < 0.5 LSB, converter is monotonic
Missing Code A/D Converters
• Similar to monotonic but for A/D converter
• Increasing analog input skips some digital codes
• If max DNL < 1 LSB or max INL < 0.5 LSB, no missing
codes

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 Converter Speed
A/D Conversion Time and Sampling Rate
• Conversion time — time for a single measurement
• Sampling rate — max sampling rate (typically inverse of
conversion time)
• Note that converter might have latency due to pipelining
D/A Settling Time and Sampling Rate
• Settling time — time for converter to settle to within a
specified resolution (typically 0.5 LSB)
• Sampling rate — max rate (typically inverse of settling
time)

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 Sampling-Time Uncertainty
• Error due to variations in sampling time
V ref
• Consider full-scale sine wave: V in = --------- sin ( 2πf in t )
2
• Rate of change is max at zero crossing
• If sampling time has variation ∆t , then to keep ∆V less
than 1 LSB, require that
V LSB 1
∆t < ------------------- = --------------- (15)
πf in V ref N
2 πf in
• Example — 250 MHz sinusoidal signal must keep
∆t < 5 ps for 8-bit accuracy
• Same 5ps for 16-bit accuracy and 1 MHz sinusoid

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 Dynamic Range
• Ratio of rms value of max amplitude input sinusoid to rms
output noise plus distortion
• Can be expressed as N, effective number of bits
SNR = 6.02N + 1.76 dB (16)
• Often a function of freq of input signal (lower SNR as freq
increases)
— more realistic than only using INL and DNL
• Note, distortion of some converters not a function of input
signal level
• Other converters (such as oversampling), distortion
decreases as signal level decreases (similar to other analog
circuits)

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 Example
• 3-bit D/A converter, V ref = 4 V , with following values
{ 0.011 : 0.507 : 1.002 : 1.501 : 1.996 : 2.495 : 2.996 : 3.491 }
3
• 1 LSB — V ref ⁄ 2 = 0.5 V
• Offset voltage is 11 mV resulting in
0.011
E off ( D ⁄ A ) = ------------- = 0.022 LSB (17)
0.5
• Gain error
3.491 – 0.011
E gain ( D ⁄ A ) =  --------------------------------- – ( 2 – 1 ) = – 0.04 LSB
3
(18)
 0.5 
• For INL and DNL errors, first remove both offset and gain
errors

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 • Offset error removed by subtracting 0.022 LSB
• Gain error removed by subtracting off scaled values of
gain error. Example — new value for 1.002 (scaled to 1
LSB) given by
1.002  2
------------- – 0.022 + --- ( 0.04 ) = 1.993 (19)
0.5  7
• Offset-free, gain-free, scaled values are
{ 0.0 : 0.998 : 1.993 : 2.997 : 3.993 : 4.997 : 6.004 : 7.0 } (20)
• INL errors — Since now in units of LSBs, given by
difference between values and ideal values
{ 0 : – 0.002 : – 0.007 : – 0.003 : – 0.007 : – 0.003 : 0.004 : 0 } (21)
• DNL errors — difference between adjacent values and 1
LSB
{ – 0.002 : – 0.005 : 0.004 : – 0.004 : 0.004 : 0.007 : – 0.004 } (22)

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 Example
• A full-scale sinusoidal is applied to a 12-bit A/D
• If fundamental has a normalized power of 1 W and
remaining power is 0.5 µW , what is the effective number
of bits for the converter?
SNR = 6.02N eff + 1.76 (23)

• In this case, SNR given by

1
SNR = 10 log  -----------------------
-  = 63 dB (24)
 – 6
0.5 × 10
resulting in
63 – 1.76
N eff = ---------------------- = 10.2 effective bits (25)
6.02

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Nyquist-Rate D/A Converters

David Johns and Ken Martin

University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)
 D/A Converter Basics.
B in D/A V out
V ref
• B in is a digital signal (or word),
–1 –2 –N
B in = b 1 2 + b2 2 + … + bN 2 (1)

• b i equals a “1” or a “0” (i.e. a binary digit).

• V ref — an analog reference; V out — output .
–1 –2 –N
V out = V ref ( b 1 2 + b2 2 + … + bN 2 ) (2)

N
• Define V LSB to be LSB signal change, V LSB ≡ V ref ⁄ 2
 D/A Converter Basics
N
• For errors, define “units” of LSB 1 LSB = 1 ⁄ 2
• A multiplying D/A allows V ref to be a varying input —
V out proportional to multiplication of V ref and B in .
• For ideal D/A , output signal is a well defined value — no
quantization error!
V out
---------
V ref
1

3/4

1/2
V LSB
1/4
---------- = 1/4 = 1 LSB
V ref
0
00 01 10 11 (100) B in
 D/A Resistor-String (Hamadé, JSSC, Dec. 1978)
V ref
b3 • Guaranteed monotonic

b3 b2 • Integrated with better than 10-bits

absolute accuracy.
b3
• Delay through the switch network
b3 b2 b1 V out major speed limitation
N • Resistors might be realized using
2 b3
polysilicon
Resistors
b3 b2
• If n-channel only used, can be laid
b3 out small
b3 b2 b1 • Requires 2N resistors

3-bit
 D/A Resistor-String — Digital Decoding
V ref

• Higher speed implementation

(less resistance thru transistors)
• Large cap load on buffer input
3 to 1 of 8 decoder b1
• Can pipeline digital decoding for
N b2 faster speed
2
Resistors b3 • Requires 2N resistors

V out

3-bit
 Folded-resistor-string D/A
• (Abrial, JSSC, Dec. 1988)
V ref
word lines • Less capacitance load
over the single bus
approach
2 to 1 of 4 decoder

b1 • Requires 2N resistors

b2

bit lines

V out

2 to 1 of 4 decoder

b3 b4 4-bit
 Binary-Weighted Resistor D/A’s.
RF

b1 b2 b3 b4 V out

2R 4R 8R 16R

– V ref 4-bit

b1 b2 b3
V out = – R F V ref – ------- – ------- – ------- – …
 (3)
 2R 4R 8R 
• Only N resistors
• Resistor and current ratios are on the order of 2N
• No guarantee of monotonicity.
• Prone to glitches (more later).
 Reduced Spread Binary Resistor D/A
RF

V out
b b b b
1 2 3 4

2R 4R 2R 4R 4R

1
3R V A = --- ( – V )
4 ref
– V ref R
4-bit

• Reduced resistor spread

• Keep repeating this procedure —> R-2R ladder
 R-2R Based D/A Converters
R 1 R' 1 R 2 R' 2 R 3 R' 3 R 4 R' 4
R R R 2R
V ref

2R 2R 2R 2R
V V V V
ref ref ref ref
----------- ----------- ----------- -----------
2R 4R 8R 16R

R' 4 = 2R
R 4 = 2R || 2R = R
R' 3 = R + R 4 = 2R
R 3 = 2R || R' 3 = R
(4)
• Small size, good matching (only R and 2R)
 R-2R Based Resistor Ladders
• Example D/A converter
RF

b1 b2 b3 b4 V out
2R I 2R Ir 2R I 2R
Ir ---r --- ---r
R 2 R 4 R 8 2R

– V ref
Ir Ir ⁄ 2 Ir ⁄ 4 Ir ⁄ 8 4-bit

• Currents through the switches are scaled

• Should scale switch sizes for good accuracy
• No node voltage changes except for output —> fast
 R-2R Based Resistor Ladders
• Slower circuit having equal current through switches

Rf
R 2R 2R

R R R

Vo

b4 b3 b2 b1

I I I I

4-bit
-5V

• Node voltages change — slower circuit

• No need to scale switch sizes (smaller size)
 Glitches
• Different delays for switching the different currents
• MSB change often worst case

I1 Rf

t V out
I2 τ1 τ2
t I1 I2
I1 + I2
t

• Glitches can be minimized by limiting the bandwidth but

that slows down circuit
• Use thermometer code to reduce glitches
 Charge-Redistribution SC D/A’s
• Programmable SC gain amplifier.
16C φ1

φ2
8C 4C 2C C V out
φ1
b1 b2 b3 b4
φ1 ( φ2 )
φ2 C2
V ref 4-bit
φ2 ( φ1 )

• Sign bit realized by interchanging input phases

• Carefully clock-waveforms required to minimize voltage
dependency of clock-feed-through.
• Digital codes should be changed when input side of
capacitors are connected to ground. Requires extra digital
complexity.
 Thermometer D/A Converters
Binary Thermometer Code
Decimal b1 b2 b3 d1 d2 d3 d4 d5 d6 d7
0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0 1
2 0 1 0 0 0 0 0 0 1 1
3 0 1 1 0 0 0 0 1 1 1
4 1 0 0 0 0 0 1 1 1 1
5 1 0 1 0 0 1 1 1 1 1
6 1 1 0 0 1 1 1 1 1 1
7 1 1 1 1 1 1 1 1 1 1
b1 b2 b3

Binary-to-thermometer code conversion

Rf
d1 d2 d3 d4 d5 d6 d7

V out
d1 d2 d3 d4 d5 d6 d7

R R R R R R R

–V
ref
 Thermometer Code D/A Converter
01

C 2N C
01 02
Vref - Vout
02 +
01
C
Top Capacitors are
Connected to Ground 02 C2
C

• 2 N unit sized caps

Bottom Capacitors are
Connected to Vref
• Guaranteed monotonic
C
• Much lower glitching
• Low DNL
C
 Current-Mode D/A’s

Vout
• Thermometer-code
• High-speed, output feeds
directly to resistor
• Important that delay to all
the switches are equal.
• Overlapped clocks much
better than having non-
Column Decoder
Col. Vout overlapped clocks.
di di
di
Row Decoder

Row I - Src
Array

Bias
 Current-Steered D/A [Colles, 88]
• Operates as cascode current sources.
• For max speed, keep voltage swing at source of Q1 small
(just turned off)
• Switching feed-through from the digital input enhances
switching speed.
Q Q
V – 4 3
ref
+

d d
V 1 2
bias
Q Q
1 2
V V
V bias bias
ref

R
ref

V out
50 Ω
 Segmented D/A
• Schoeff, 79; Saul, 85; Grebene, 84
R/2
• Combine
- thermometer and
Vout
+ binary
• Accuracy needed
for LSB reduced
• Glitches reduced
2R 2R 2R 2R • Very popular
Vref R R R R
+
-

Vref

2R 2R 2R 2R 2R

2 MSB’s 4 Bit Binary LSB - Segment

 Dynamically-Matched Current Sources
• Schouwenaar, 88
• Each current source is

0 0 1
Shift Register
0 0 0
I ref calibrated with a
single reference
• 64 used so D/A can
continue operating

I d1 I d2 I d3 I d4 I d5 I 64 • Achieved 92 dB
SNDR, and 20 mW
with 3V.
• Used for audio
Switch Network
application
To D/A

• Dynamic technique with current switching for realizing

very well-matched current sources
• Up to 16 bit accuracy
 Dynamically-Matched Current Sources
• Current source 0.9I
I ref I out I out added so a low gm
I ref device used (W/L
S2 S2 equal to 10/75)
I d1 I d1
• Re-calibrate before
S1
leakage causes
Cgs Cgs
0.9Iref
0.5LSB error
0.9Iref
Q1 Q1
S1

Calibration Regular Usage

• Minimize clock-feedthrough and charge-injection by

having capacitance Cgs and bias voltage V GS large
• Implies voltage error causes less current deviation.
Nyquist-Rate A/D Converters

David Johns and Ken Martin

University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)
 A/D Converter Basics
V in A/D
B out
V ref
–1 –2 –N
V ref ( b 1 2
+ b 2 2 + … + b N 2 ) = V in ± x
1 1
where  – --- V LSB < x < --- V LSB (1)
 2 2 
• Range of valid input values produce the same output
signal — quantization error.
V LSB
B out ---------- = 1/4 = 1 LSB
V ref
11

10

01
V in
00 -------
-
0 1/4 1/2 3/4 1 V ref
 Analog to Digital Converters
Low-to-Medium Medium Speed, High Speed,
Speed, Medium Accuracy Low-to-Medium
High Accuracy Accuracy
Integrating Successive Flash
approximation
Oversampling Algorithmic Two-step
(not Nyquist-rate)
Interpolating
Folding
Pipelined
Time-interleaved
 Integrating Converters
S
2 S
 1
 S 2
C1

–V S Comparator b
in 1 R 1
1 V
x b
Control 2
V
ref Counter b
logic 3

(Vin is held constant during conversion.) b

N

Clock

1 B
f = ----------- out
clk T
clk

• Low offset and gain errors for low-speed applications

• Small amount of circuitry
• Conversion speed is 2N+1 times 1/Tclk
 Integrating Converters
Vx
– V in3
Phase (I) Phase (II)
(Constant slope)

– V in2

– V in1

Time
T1

T 2 (Three values for three inputs)

• Count at end of T2 is digital output

• Does not depend on RC time-constant
 Integrating Converters
0

H(f) –20 dB/decade slope

–10
(dB)

–20

–30
Frequency (Hz)
10 60 100 120 180 240 300 (Log scale)

• Notches the input frequencies which are multiples of 1/T1

 Successive-Approximation Converters
Start
Signed input

Sample V in, V D/A = 0, i = 1

• Makes use of binary search algorithm
• /Requires N steps for N-bit converter
V in >V D/A
No
• Successively “tunes” a signal until
within 1 LSB of input
Yes

bi = 1 bi = 0
• Medium speed
• Moderate accuracy
V D/A →V +V ⁄2 D/A ref
i+1
V D/A → V – (V ⁄ 2 )
D/A ref
i+1

i →i+1

No
i ≥N
Yes

Stop
 DAC Based Successive-Approximation
V in
Successive-approximation register
S/H (SAR) and control logic

b b B
1 2 b out
N
D/A converter
V D/A V ref

• Adjust V D/A until within 1 LSB of V in

• Start with MSB and continue until LSB found
• D/A mainly determines overall accuracy
• Input S/H required
 Charge Redistribution A/D
s
Vx ≅ 0 2

SAR
16C 8C 4C 2C C C
b b b b b
1 2 3 4 5
s 3
1. Sample mode

s s
1 V = –V 2
V
in
V
ref
x in
16C 8C 4C 2C C C
b b b b b SAR
1 2 3 4 5
s 3

s
1
V ref V V 2. Hold mode
V x = – V in + ----------- s in ref
2
2
SAR
16C 8C 4C 2C C C
b b b b b
1 2 3 4 5
s 3

3. Bit cycling
s
1
V V
in ref
 Charge Redistribution A/D
• McCreary, 75
• Combines S/H, D/A converter, and difference circuit
• Sample mode: Caps charged to V in , compar reset.
• Hold mode: Caps switched to gnd so V x = – V in
• Bit cycling: Cap switched to V ref . If V x < 0 cap left
connected to V ref and bit=1. Otherwise, cap back to gnd
and bit=0. Repeat N times
• Cap bottom plates connected to V ref side to minimize
parasitic capacitance at V x . Parasitic cap does not cause
conversion errors but it attenuates V x .
 Algorithmic (or Cyclic) A/D Converter
Start
Signed input
• Operates similar to successive-
approx converter
Sample V = Vin, i = 1
• Successive-approx halves ref voltage
each cycle
No
V>0
• Algorithmic doubles error each cycle
Yes (leaving ref voltage unchanged)
bi = 1 bi = 0

V → 2(V – Vref /4) V → 2(V + Vref /4)

i →i+1

No
i>N

Yes

Stop
 Ratio-Independent Algorithmic Converter
Out

Vin
S/H Cmp Shift register

Vref /4
X2 S/H
Gain amp –Vref /4

• McCharles, 77; Li, 84

• Small amount of circuitry — reuse cyclically in time
• Requires a high-precision multiply by 2 gain stage
 Ratio-Independent Algorithmic Converter
Q1

C2 C2
C1 C1
Verr Verr
Cmp Cmp
Q1 Q1

1. Sample remainder and cancel input-offset voltage. 2. Transfer charge Q1 from C1 to C2.
Q1

C2 C2
C1 C1
Verr Verr
Cmp Cmp
Q2
Q1+Q2 Vout = 2 Verr
3. Sample input signal with C1 again
after storing charge Q1 on C2. 4. Combine Q1 and Q2 on C1, and connect C1 to output.

• Does not rely on cap matching

• Sample input twice using C1; hold first charge in C2 and
re-combine with first charge on C1
 Flash (or Parallel) Converters
• Peetz, 86; Yoshii, 87; Hotta, 87; and Gendai, 91
Vref

Vin • High-speed
R
----
2 Over range
• Large size and power hungry
R

• 2N comparators
V r7

R V r6
• Speed bottleneck usually large cap
R V r5 load at input
(2N–1) to N N digital
R V r4 encoder outputs
• Thermometer code out of comps
R V r3
• Nands used for simpler decoding
R
V r2
and/or bubble error correction
R
V r1
• Use comp offset cancellation
R⁄2 Comparators
 Issues in Designing Flash A/D Converters
• Input Capacitive Loading — use interpolating arch.
• Resistor-String Bowing — Due to Iin of bipolar comps —
force center tap (or more) to be correct.
• Signal and/or Clock Delay — Small arrival diff in clock
or input cause errors. (250MHz 8-bit A/D needs 5ps
matching for 1LSB) — route clock and Vin together with
the delays matched [Gendai, 1991]. Match capacitive
loads
• Substrate and Power-Supply Noise — V ref = 2 V and 8-
bit, 7.8 mV of noise causes 1 LSB error — shield clocks
and use on-chip supply cap bypass
• Flashback — Glitch at input due to going from track to
latch mode — use preamps in comparators and match
input impedances
 Flash Converters — Bubble Errors
• Thermometer code should be 1111110000
• Bubble error (noise, metastability)— 1111110100
• Usually occurs near transition point but can cause gross
errors depending on encoder
V
in …
…
…
…

V (2N–1) to N N digital
ri
encoder outputs

[Steyaert, 93]
…
…
…

• Can allow errors in lower 2 LSB but have MSBs encoder

look at every 4th comp [Gendai, 91]
 Reduced Auto-Zeroing
• Tsukamoto et al, ISSCC/96
• Spalding et al, ISSCC/96
• Reduce the auto-zero portion of conversion
— auto zero when not performing conversion
— add one more comparator and ripple up auto-zero
Advantages
• Lower power — less current drawn from ref string
• More speed — more time for conversion
Disadvantage
• 1/f noise not rejected as much
 Two-Step A/D Converters
V
in
V
4-bit 4-bit 1 V
q 4-bit
Vin MSB 16 LSB
D/A
A/D A/D
Gain amp

First 4 bits Lower 4 bits

(b , b , b , b ) (b , b , b , b )
1 2 3 4 5 6 7 8

• High-speed, medium accuracy (but 1 sample latency)

• Less area and power than flash
• Only 32 comparators in above 8-bit two-step
• Gain amp likely sets speed limit
• Without digital error correction, many blocks need at least
8-bit accuracy
 Digital Error Correction
S/H2
(8-bit accurate) V
in
Gain amp
4-bit 4-bit
V
1 V
q
Vin S/H1 MSB D/A 8 S/H3
A/D
(8-bit accurate) (5-bit accurate)
(8-bit accurate)
(4-bit accurate)
5 bits
Digital delay

Error 5-bit
D correction LSB
4 bits
A/D

(5-bit accurate)

8 bits

• Relaxes requirements on input A/D

• Requires a 5-bit 2nd stage since Vq increased
• Example, see [Petschacher, 1990].
 Interpolating A/D Converters
V
ref
= 1V • Goodenough, 1989
V (Overflow) • Steyaert, 1993
V in 4
latch
16
R
latch
15
• Kusumoto, 1993
R 14
R latch
R 13 • Use input amps to
latch
V
3 R 12 amplify input around
latch
0.75 V
R 11 reference voltages
R
latch
b1
R latch
10
Digital • Latch thresholds less
R 9 b2 critical
V R
latch
logic
2 latch
8
b3
0.5 V R 7 • Less cap on input (faster
V 2c
R
latch
6
b4 than flash)
V 2b latch
R
V 2a R 5
R
latch • Match delays to latches
V 4
1 latch
0.25 V R 3 • Often combined with
latch
R
Input
amplifiers
R 2 folding architecture
latch
R 1
latch
R Latch
comparators
 Interpolating Converters
5.0 V2
V 2b
V 2c

V1
(Volts) Latch threshold

V 2a

0 V in
0 0.25 0.5 0.75 1.0
(Volts)

I I I I
1 2a 2b 2

3 3 3 3
9 3 3 9

current interpolation
(Relative width sizing shown)
(All lengths same)
 Folding A/D Converters
b
2-bit 1
MSB A/D
converter b Folding block responses
2
• Reduce number of
V ref = 1 V
1
V1 latches using folding
(Volts) Threshold
V
Folding 1
block Latch
0
• Save power and area
0 4-
-----
8-
-----
12
------
1 1 V
in
 4 8 12 16  (Volts)
V r =  -----
-, ------, ------, ------ 
 16 16 16 16  V2
16 16 16
• Similar concept to 2-step
V Threshold
in V
Folding
block
2 Latch
Digital
b
3 • Folding rate of 4 shown
logic
b 3
------ 7-
----- 11
------ 15
------
V
in
for 4 bit converter
 3 7 11 15  4 16 16 16 16
V r =  -----
-, ------, ------, ------  V3
 16 16 16 16 
Threshold
V
Folding 3 Latch
block
2- 6- 10 14 V
 2 6 10 14 
-----
16
-----
16
------
16
------
16
in
V =  -----
-, ------, ------, ------ 
r
 16 16 16 16  V4
Threshold
V
Folding 4 Latch
block

1 5 9- 13 V
 1 5 9 13 
------
16
------
16
----- ------
16
in
V r =  ------, ------, ------, ------  16
 16 16 16 16 
 Folding Circuit
V
CC
R R
1 1

V Q1 V
a b Q2

V out

V V V V
r1 r2 r3 r4

I I I I
b b b b
V
in
VEE
(a)
V out

V –V
CC BE

V –V –I R
CC BE b 1 V in
V r1 V r2 V r3 Vr4

(b)
 Folding with Interpolation
b
2-bit 1
MSB A/D
converter b Folding-block responses
2
V = 1V V1
ref 1
V (Volts) Threshold • Folding usually used
V 1
4
R
Latch
0 V
in
with interpolation
0 4- 8- 12 1
----- ----- ------
R
V2
16 16 16 (Volts)
• Reduces input cap (
V V Threshold
in 2
Folding
block Latch
Digital
b3
V
• Without interp, same
logic in input cap as flash
3 7- 11 15
b4 ------ ----- ------ ------
 3 7 11 15  16 16 16 16
V r =  ------, ------, ------, ------  R V3
 16 16 16 16  Threshold • [van Valburg, 1992]
V Latch
3 V
R 2 6- 10
in • [van de Grift, 1987]
------ ----- ------ 14
------
16 16 16 16
V4
Threshold
• [Colleran, 1993]
V
Folding 4
block Latch
V4 V
V in
4 1 5- 9- 13
------ ----- ----- ------
16 16 16 16
 1 5 9 13 
V r =  -----
-, ------, ------, ------ 
 16 16 16 16 
 Pipelined A/D Converters
b 1

QN
DN
b
N – 1-bit shift register
2

QN-1 QN-1
DN-2 DN-2

b N–1

Q1 Q1 Q1
D1 D1 D1 b N

Vin 1-bit 1-bit 1-bit 1-bit

DAPRX DAPRX DAPRX DAPRX

(DAPRX - digital approximator)

Analog pipeline

bi

Vi–1 S/H Cmp

–Vref/4
2 Vi
Vref/4
 Time-Interleaved A/D Converters [Black, 80]
f1

S/H N-bit A/D

f2

f0
S/H N-bit A/D
Digital
V output
in f3 Dig.
S/H mux

S/H N-bit A/D

f4

S/H N-bit A/D

• Use parallel A/Ds and multiplex them

• Tone occurs at fs/N for N converters if mismatched
• Input S/H critical, others not — perhaps different tech for input S/H
Nyquist-Rate D/A Converters

David Johns and Ken Martin

University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)
 D/A Converter Basics.
B in D/A V out
V ref
• B in is a digital signal (or word),
–1 –2 –N
B in = b 1 2 + b2 2 + … + bN 2 (1)

• b i equals a “1” or a “0” (i.e. a binary digit).

• V ref — an analog reference; V out — output .
–1 –2 –N
V out = V ref ( b 1 2 + b2 2 + … + bN 2 ) (2)

N
• Define V LSB to be LSB signal change, V LSB ≡ V ref ⁄ 2
 D/A Converter Basics
N
• For errors, define “units” of LSB 1 LSB = 1 ⁄ 2
• A multiplying D/A allows V ref to be a varying input —
V out proportional to multiplication of V ref and B in .
• For ideal D/A , output signal is a well defined value — no
quantization error!
V out
---------
V ref
1

3/4

1/2
V LSB
1/4
---------- = 1/4 = 1 LSB
V ref
0
00 01 10 11 (100) B in
 D/A Resistor-String (Hamadé, JSSC, Dec. 1978)
V ref
b3 • Guaranteed monotonic

b3 b2 • Integrated with better than 10-bits

absolute accuracy.
b3
• Delay through the switch network
b3 b2 b1 V out major speed limitation
N • Resistors might be realized using
2 b3
polysilicon
Resistors
b3 b2
• If n-channel only used, can be laid
b3 out small
b3 b2 b1 • Requires 2N resistors

3-bit
 D/A Resistor-String — Digital Decoding
V ref

• Higher speed implementation

(less resistance thru transistors)
• Large cap load on buffer input
3 to 1 of 8 decoder b1
• Can pipeline digital decoding for
N b2 faster speed
2
Resistors b3 • Requires 2N resistors

V out

3-bit
 Folded-resistor-string D/A
• (Abrial, JSSC, Dec. 1988)
V ref
word lines • Less capacitance load
over the single bus
approach
2 to 1 of 4 decoder

b1 • Requires 2N resistors

b2

bit lines

V out

2 to 1 of 4 decoder

b3 b4 4-bit
 Binary-Weighted Resistor D/A’s.
RF

b1 b2 b3 b4 V out

2R 4R 8R 16R

– V ref 4-bit

b1 b2 b3
V out = – R F V ref – ------- – ------- – ------- – …
 (3)
 2R 4R 8R 
• Only N resistors
• Resistor and current ratios are on the order of 2N
• No guarantee of monotonicity.
• Prone to glitches (more later).
 Reduced Spread Binary Resistor D/A
RF

V out
b b b b
1 2 3 4

2R 4R 2R 4R 4R

1
3R V A = --- ( – V )
4 ref
– V ref R
4-bit

• Reduced resistor spread

• Keep repeating this procedure —> R-2R ladder
 R-2R Based D/A Converters
R 1 R' 1 R 2 R' 2 R 3 R' 3 R 4 R' 4
R R R 2R
V ref

2R 2R 2R 2R
V V V V
ref ref ref ref
----------- ----------- ----------- -----------
2R 4R 8R 16R

R' 4 = 2R
R 4 = 2R || 2R = R
R' 3 = R + R 4 = 2R
R 3 = 2R || R' 3 = R
(4)
• Small size, good matching (only R and 2R)
 R-2R Based Resistor Ladders
• Example D/A converter
RF

b1 b2 b3 b4 V out
2R I 2R Ir 2R I 2R
Ir ---r --- ---r
R 2 R 4 R 8 2R

– V ref
Ir Ir ⁄ 2 Ir ⁄ 4 Ir ⁄ 8 4-bit

• Currents through the switches are scaled

• Should scale switch sizes for good accuracy
• No node voltage changes except for output —> fast
 R-2R Based Resistor Ladders
• Slower circuit having equal current through switches

Rf
R 2R 2R

R R R

Vo

b4 b3 b2 b1

I I I I

4-bit
-5V

• Node voltages change — slower circuit

• No need to scale switch sizes (smaller size)
 Glitches
• Different delays for switching the different currents
• MSB change often worst case

I1 Rf

t V out
I2 τ1 τ2
t I1 I2
I1 + I2
t

• Glitches can be minimized by limiting the bandwidth but

that slows down circuit
• Use thermometer code to reduce glitches
 Charge-Redistribution SC D/A’s
• Programmable SC gain amplifier.
16C φ1

φ2
8C 4C 2C C V out
φ1
b1 b2 b3 b4
φ1 ( φ2 )
φ2 C2
V ref 4-bit
φ2 ( φ1 )

• Sign bit realized by interchanging input phases

• Carefully clock-waveforms required to minimize voltage
dependency of clock-feed-through.
• Digital codes should be changed when input side of
capacitors are connected to ground. Requires extra digital
complexity.
 Thermometer D/A Converters
Binary Thermometer Code
Decimal b1 b2 b3 d1 d2 d3 d4 d5 d6 d7
0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0 1
2 0 1 0 0 0 0 0 0 1 1
3 0 1 1 0 0 0 0 1 1 1
4 1 0 0 0 0 0 1 1 1 1
5 1 0 1 0 0 1 1 1 1 1
6 1 1 0 0 1 1 1 1 1 1
7 1 1 1 1 1 1 1 1 1 1
b1 b2 b3

Binary-to-thermometer code conversion

Rf
d1 d2 d3 d4 d5 d6 d7

V out
d1 d2 d3 d4 d5 d6 d7

R R R R R R R

–V
ref
 Thermometer Code D/A Converter
01

C 2N C
01 02
Vref - Vout
02 +
01
C
Top Capacitors are
Connected to Ground 02 C2
C

• 2 N unit sized caps

Bottom Capacitors are
Connected to Vref
• Guaranteed monotonic
C
• Much lower glitching
• Low DNL
C
 Current-Mode D/A’s

Vout
• Thermometer-code
• High-speed, output feeds
directly to resistor
• Important that delay to all
the switches are equal.
• Overlapped clocks much
better than having non-
Column Decoder
Col. Vout overlapped clocks.
di di
di
Row Decoder

Row I - Src
Array

Bias
 Current-Steered D/A [Colles, 88]
• Operates as cascode current sources.
• For max speed, keep voltage swing at source of Q1 small
(just turned off)
• Switching feed-through from the digital input enhances
switching speed.
Q Q
V – 4 3
ref
+

d d
V 1 2
bias
Q Q
1 2
V V
V bias bias
ref

R
ref

V out
50 Ω
 Segmented D/A
• Schoeff, 79; Saul, 85; Grebene, 84
R/2
• Combine
- thermometer and
Vout
+ binary
• Accuracy needed
for LSB reduced
• Glitches reduced
2R 2R 2R 2R • Very popular
Vref R R R R
+
-

Vref

2R 2R 2R 2R 2R

2 MSB’s 4 Bit Binary LSB - Segment

 Dynamically-Matched Current Sources
• Schouwenaar, 88
• Each current source is

0 0 1
Shift Register
0 0 0
I ref calibrated with a
single reference
• 64 used so D/A can
continue operating

I d1 I d2 I d3 I d4 I d5 I 64 • Achieved 92 dB
SNDR, and 20 mW
with 3V.
• Used for audio
Switch Network
application
To D/A

• Dynamic technique with current switching for realizing

very well-matched current sources
• Up to 16 bit accuracy
 Dynamically-Matched Current Sources
• Current source 0.9I
I ref I out I out added so a low gm
I ref device used (W/L
S2 S2 equal to 10/75)
I d1 I d1
• Re-calibrate before
S1
leakage causes
Cgs Cgs
0.9Iref
0.5LSB error
0.9Iref
Q1 Q1
S1

Calibration Regular Usage

• Minimize clock-feedthrough and charge-injection by

having capacitance Cgs and bias voltage V GS large
• Implies voltage error causes less current deviation.