DIGITAL CONTROL SYSTEM FOR HIGH PRECISION POWER SUPPLIES OF

THE NEW BRAZILIAN SYNCHROTRON SOURCE

Gabriel O. Brunheira, Jakson P. Bonaldo, João Nilton H. da Rosa, Cleber Rodrigues, José A. Pomilio
School of Electrical and Computer Engineering
University of Campinas
Campinas, São Paulo, Brazil
jbonaldo@gmail.com, antenor@dsce.fee.unicamp.br

Brazilian Synchrotron Light Laboratory – LNLS

Power Electronic Group – ELP
Rua Giuseppe Máximo Scolfaro, 10.000
Zip Code 13083-970, P.O. Box 6192 – Campinas – SP - Brazil
gabriel.brunheira@lnls.br, joao.rosa@lnls.br, clero@lnls.br

Abstract – This paper proposes an architecture of
digital current regulator intended to be used to control
the power supplies of the new Brazilian synchrotron light
source, called Sirius. It is based on a high-precision
Digital to Analog Converter and a modern System on
Chip device, which has the capability of performing real-
time control tasks together with managing and interface
tasks. Despite this system will be used to control many
kinds of power supplies, it was validated in a 100 W
power supply, which was previously developed to be used
in the present Synchrotron Light Source.
Keywords - Digital Control, High Precision Current
Source, DC-DC converter
I. INTRODUCTION
The Brazilian Synchrotron Light Laboratory (LNLS),
located in Campinas-SP, has built and operated the first
Synchrotron Light Source in the southern hemisphere and the
only one in Latin America [1]. Now it is building a second
one, called Sirius, which will be a third generation
synchrotron source, with 3GeV energy and very higher
brilliance, as well the lowest emittance among not only those
in operation, but also in design process [2, 3]. Due to the
small size of the electron beam, its orbit must be much more
stable, as well the current sources which feed the magnets.
The number of these power supplies (PS) will also be much
greater than in the current light source, probably more than
one thousand units. Thus the use of a digital regulation
system is strongly indicated, mainly due to the following
advantages [4, 5, 6]:
• Lower susceptibility to noise, thermal variations and
components aging;
• Easier parameter adjusts and higher malleability;
• Unique controller hardware for all PS's;
• More diagnosis functionalities;
• Allows implementation of more complex control
strategies.
Therefore, it has been decided to apply digital control in
all current source families that will be used in Sirius, using,
when possible, the same hardware, i.e., the same control and
processing board. This strategy was chosen by other particle
accelerators with good results [7]. This system will be called
Universal Digital Controller (UDC).
Usually, the current sources used at LNLS present a
precision better than 0.01% in relation to their output range
[8, 9, 10] (in this case precision can be understood as a
general expression which encompasses resolution, short and
long time stability, linearity, etc. This represents an
additional difficult for the design of current digital
regulators, because their performance is affected by
quantization and mathematical noise, accuracy of analog-to-
digital converters (ADC) and the resolution of the pulse
width modulator (PWM) [11, 12]. Moreover, some models of
power supplies will have a high bandwidth, up to 2kHz, what
means an additional difficult once the available time for
processing will be shorter, the reference values must be
updated at this frequency and, mainly, the switching
frequency must be enough higher than this value.
Many strategies have been proposed in order to obtain
PWM with high resolution, as delay line, dithering, dual
clock, etc, and each one has its advantages and disadvantages
[13]. This work used a Digital Signal Processor (DSP) which
has internally a high resolution PWM (HRPWM) based on a
delay line. This off-the-shell solution was suitable for this
project because of its low cost, size and reliability. Moreover,
it saved developments costs and can be combined in the
future with other solutions, like dithering, in order to increase
PWM resolution even more.
This work will discuss the main components of a digital
regulation system, as well its characterization and modeling.
The proposed system validation was performed with a
bipolar current source with rated output of 10A/10V. This PS
model is already used at LNLS but with analog regulation.
For the tests this analog circuit was exchanged by the digital
one.
Section II will show the basic modeling of the system in
the analog domain. Section III brings considerations about
the digital implementation of the regulator, discussing the
main performance indicators of the signal acquisition and the
digital PWM behavior. Experimental results are shown in
section IV and section V presents the conclusions.
 II. SYSTEM MODELING The transfer function which relates the output current with
the equivalent duty cycle d is given by:
Figure 1 shows the power stage of the PS, which is based
on a 4-quadrant (4Q) converter [11, 14], Figure 2 shows its GP s
I
VDC GL s (6)
linearized model.

The transfer function given by (7) is a first order Padé

approximation of the delay effect caused by the digital PWM
[15]. Ts corresponds to one sample period.

(7)

The current transducer gain is given by (8), once the

measured current is normalized in relation to the maximum
value that it can take on, considering transient situations:
Fig. 1. The power stage of the PS used for tests

(8)
ADCFSR

In order to attenuate the superposition of harmonic

components close to Nyquist frequency it is necessary to use
an anti-aliasing filter as (9):

GAL s (9)
Fig. 2. Linear model of the PS

In order to obtain the transfer function of this circuit, it III. CONSIDERATIONS ABOUT DIGITAL
was applied the Thevenin theorem in both sides of the load, IMPLEMENTATION
resulting in the simplified model of Figure 3. The Thevenin
impedance and voltages are given by (1), (2) and (3). A. General Description
The System on Chip (SoC) F28M35H52C1 (Texas
Instruments®) is used to implement the digital controller. It
contains two processing cores: one is a microcontroller ARM
Cortex-M3, which will perform man-machine tasks and the
communication with the control network of Sirius. The
second core is a floating point DSP of C2000 family running
with a 150 MHz system clock, which is used to execute the
Fig. 3. Simplified linear model of the PS control algorithm and signal processing, as well to drive the
power circuit using its HRPWM.
Data acquisition is performed by an external analog-to-
·R ·C
·R ·C ·C·L ·L· C C ·R ·C
·V (1) digital converter AD7634 (Analog Devices®), and the
samples are transferred to the C2000 core using a serial
·R ·C peripheral interface (SPI). The resolution of this ADC is 18
·V (2) bits and its signal-to-noise relation (SNR) is 101 dB. It was
·R ·C ·C·L ·L· C C ·R ·C
used evaluation boards from the manufacturers to implement
·R ·C ·L ·L
(3) both the ADC and the digital regulator.
·R ·C ·C·L ·L· C C ·R ·C
B. Digital PI With Dynamic Saturation
Equation (4) shows the transfer function of the output In a conventional implementation of a PI controller, the
current Io(s) in relation to voltages Vin1 and Vin2, obtained integrator can saturate when a significant variation is applied
from the previous one and the circuit in Figure 3: to reference. The controller saturation can last a long time,
what makes the power stage also provide a saturated output,
(4) obviously different from that request by reference.
In order to avoid this problem, a PI controller with
dynamic saturation of integral part has been applied, as
The differential voltage VINV =Vin1-Vin2 can be written as a showed in [15]. Figure 4 shows the block diagram of the
function of the duty cycle δ and the input voltage VDC: implemented PI structure, where:
- Maximum output value of PI controller
VINV s VDC · d s (5) - Dynamic limit for the integrator at instant
k
 But even with the two conditions above satisfied, LCO
can still happen due to the non-linear characteristic of the
quantization process on the control loop. So, the two actions
can be used at least to attenuate the amplitude and effect of
LCO.

D. The ADC
The effective number of bits of the ADC (ENOBADC) can
be calculated by:

.
(13)
.

Fig. 4. PI Controller with dynamic saturation of integrator [15]
The integrator limit LI(k) is calculated at each k iteration
of the controller as:
| | | | (10)
This technique allows the calculation of a new limit LI for
the integrator at each iteration. Thus the limitation of the
integral part happens in a soft and gradual way, what limits
transients and overshoots usually caused by this saturation.
C. Attenuation Of Oscillations Caused By Limit Cycle
Due to the limitations of the ADC resolution and, mainly,
the digital PWM, which introduce quantization noise in the
control loop, oscillations can appear in the controlled
variable [15, 16]. Thus, the regulation quality of the output
current can be diminished, causing errors in steady state and
increasing ripple. Depending on the control technique and
the coefficients used, these oscillations caused by limit cycle,
called Limit Cycle Oscillation (LCO) can compromise the
stability and reliability of the system. In conventional
systems this effect can be disregarded, but in high precision
ones it can be noted and its effects are significant.
A necessary condition but not enough to prevent the LCO
is that the increment of one PWM quantized level, i.e., 1
LSB of the duty cycle, results in a increment of the variable
sampled by the ADC (in this case, the output current IO(t))
smaller than the quantization level of the ADC itself, in the
steady-state [15, 16]. This can be expressed as:
SINADADC is the Signal-to-Noise-and-Distortion Rate of
the ADC. This ratio could be interpreted, in some sense, as
the relation between the input full-scale range and the
minimum distinguishable input variation, expressed in bits of
resolution. Thus this value could be considered for the
calculation of the effective quantization level, which would
be expressed as:
(14)
Where:
- ADC input full scale range
The measured SINADADC from the AD7634 provided by
the manufacturer is 101 dB, and the input range was
configured to ±10 V.
For the PS of this work, the output current can assume
values between -10A and +10A. The transducer and the
signal conditioning circuit has unitary gain, then the ADC
input signal amplitude (in Volts) is equal to the real current
amplitude (in Amperes) and it can be considered the own
current signal. For this reason, there is no loss of resolution
due to signal scaling in this case.
Therefore, the effective quantization level of the ADC is
218.8 µA.
E. Digital PWM
The number of effective bits of the Digital PWM
( ) is determined by:

(11) (15)

Where:
where is the fraction of PWM duty cycle related to 1 FCLK - Modulator clock frequency
LSB, is the steady-state gain of the transfer function Fs - Desired modulation frequency
between the duty-cycle d(s) and the output current (i.e.,
· 0 ), and is the quantization level of the The used DSP presents 150 and the PWM
ADC, expressed in the sampled variable units (in this case, modulating frequency was chosen 50 . Then, the
Ampere). number of effective bits would be 11. Due to this
The addition of an integral part ( ) in the control loop
number be lower than the ADC resolution, one of the
contributes to LCO reduction [16]. The acting of this integral previous conditions to prevent LCO would not be respect.
part must be enough slow, generating duty cycle increases But the chosen DSP has a special peripheral, the
lower than the less significant bit (LSB) of the PWM. Then, HRPWM, which allow the division of the lowest step of the
it must be assured that: conventional PWM in lower steps of 150 ps, as showed in
Figure 5.
0 K I DIG 1 (12)
 Bode Diagram
100
Hol uncompensated
50 Hol compensated

Magnitude (dB)
0

-50

-100

-150

Fig. 5. High Resolution PWM 360

270

Phase (deg)
180
The HRPWM resolution can be calculated substituting the 90
system clock period 1 by the lowest increment (150 ps):
0

-90
1 2 3 4 5 6
F · · 10 10 10 10 10 10
N HRPWM
floor (16) Frequency (Hz)

Fig. 7. Frequency response of the system

Thus the effective bit number of the HRPWM is
17, and the output current increment due to 1
LSB of the digital PWM can be calculated by (17) which Applying the discretization of the analog PI controller, the
results in 114.4 µA. conversion of parameter to the digital domain is given by:

· ·0 (17) (19)
N HRPWM

It can be observed that the condition (12) is satisfied to

IV. CURRENT CONTROLLER DESIGN prevent or minimize LCO.

Table I shows the main parameters of the power circuit

and the digital controller used in the design. Equations (6) to V. EXPERIMENTAL RESULTS
(9) were used to calculate the current controller, which is a
proportional-integral kind. Figure 6 shows the block diagram The power circuit was implemented using MOSFET’s
of the control loop of the converter output current. The open IRFB4310 (100V/140A) which are driven by the integrated
loop transfer function is given by: circuit (IC) IR2112.
The following figures show the dynamic response of the
HOL GAL s · · · (18) system to several current steps. It can be observed in Figure 8
and 9 that for a higher the current step, a longer response
Table I – PS and UDC Parameters time occurs. The reason is that this time depends basically of
Parameter Value Parameter Value the DC link voltage (15V) and the load inductance (25mH).
15 V 25 mH But the value of the output current is also important because
100 µH 50 kHz the voltage drop on the load resistance limits the voltage
470 ηF 100 kHz
available to the inductance. If a faster response is necessary
3.3 µF 30 kHz
4.7 Ω 20 V the DC link voltage must be increased. There is no action to
1Ω N 17 be made by the controller to overcome this limit, but the PI
HRPWM
gains must be high to reach the maximum or minimum duty
cycle as fast as possible.

1
IFSR
Fig. 6. Block diagram of the current control loop

With the parameters of Table 1, the PI parameters were

calculated using the analog PI controller design approach
[15], in order to get the cut-off frequency of the closed loop
system of 1500 Hz and the phase margin of 70o. The
resulting parameters were 70 and 95000. Figure
7 shows the system response before and after the
compensation. Fig. 8. Current step from 6A to 3A (1A/div; 1ms/div)
 Fig. 9 – Current step from 1A to 2A (1A/div; 1ms/div)
However, the usual operation of this PS requires just small
steps. In this case, other factors as the system delay and the
finite PI gains are the major reason for the response time
limitation. Figure 10 shows the output current for a 0.2A
step, where the time response is lower than 1ms.
Fig. 10. Current step from 1A to 1.2A (0.2A/div; 0.5ms/div)
Figure 11 shows the output current when a sinusoidal
reference with the amplitude of 1A and 100Hz is applied.
The designed controller, due to its high gain, is able to follow
a small signal as this one. On the contrary the controller
would go quickly to the saturation, causing a deformed
waveform in the output. This effect increases with the
increasing of the reference frequency.
Fig. 11. Output current following a 100Hz/1Vpp sinusoidal
reference (Green trace: reference; blue trace: current)
Figure 12 shows the result for a long term stability test
during almost 17 hours, for an output current of 5A. It can be
observed that, after the warm-up time and the room
temperature stabilization, the average variation (do not taking
into account the fast instabilities) was less than 60µA, what
means less than 3ppm of the output range.
Fig. 12. Long term stability test of output current for 5A (blue
trace: current; green trace: temperature)
VI. CONCLUSION
This work showed the implementation of a digital
regulation system, the UDC, for high precision current
sources. The main components of the regulator, as the
HRPWM, the ADC and the processing system F28M35 were
validated with a 100W bipolar PS.
The obtained results showed that the goal of a high precise
regulation was reached just using a conventional PI
controller. But other more modern control techniques can be
still used just changing the DSP firmware, what can improve
the system performance. This is one of the main advantages
of using digital control.
The final goal is to extend the concept of this regulation
system for all topologies of PS that will be used in Sirius. For
this reason, dedicated boards are been built right now for
both the ADC and the digital regulator, in order to be used in
place of the evaluation boards employed until this moment.
Soon, new tests must be performed and new results obtained.
ACKNOWLEDGEMENT
Authors would like to thanks Fundação de Amparo a
Pesquisa do Estado de São Paulo - FAPESP.
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