A 2.

4GHz CMOS VCO Design

Hong Qi, Zhao Yuhao
School of Electric Science and Technology
Anhui University
Hefei, China
hongqi@ahu.edu.cn

Abstract—A single resistor was used between the drain node of  ∆ω 1 

 2 FkT   ω 0 
2
   (1)
f3
the bias transistor and the source node of the differential L ( ∆ ω ) = 10 log  ⋅ 1+    ⋅ 1 + 

 P sig   2 Q ∆ ω   
 
∆ω 
transistors. The wide-band nature of resistance can suppress the  

2nd harmonic as well as other even harmonics leaking from the

LC tank across the full period of oscillation. A fully integrated
2.4GHz all PMOS LC VCO was implemented in a 0.35µm
CMOS process. The simulation results show the achieved phase
noise of -121dBc/Hz@600kHz.

Keywords-CMOS; voltage-controlled oscillator;radio frequenc;

Varactor

I. INTRODUCTION
The rapid growth of high speed wireless LAN market is
driving the development of high performance RF integrated
systems in low-cost technologies. Of all RF blocks, VCOs are Fig 1. The schematic of the LC VCO with the new filtering resistor

essential components of such wireless systems. The VCO’s

main performance include Frequency-Voltage curve, phase
noise, etc. For CMOS process’s limiting, phase noise is a key
target. A lot of papers has reported the improvement about
phase noise in structure, progress, theory, etc. [1]-[6] This
paper introduce a new topology structure that one single resist
was used at the drain node of the bias transistor. The
wide-band nature of resistance can suppress the second
harmonic as well as other even harmonics leaking from LC
tank across the full period of oscillation.
II. VCO DESIGN
Fig 1 shows the standard LC VCO design with wide-band
harmonic filtering resistor.
As published by Lesson 1966[2], the phase noise of an
LC-VCO can be described as:
According to the equation, we can see that the
fundamental parameters that affect phase noise at offset
frequency △f are Q (lorded quality factor of the LC tank), Psig
(Power loss), ω0 (oscillation frequency), F (excess noise
factor), △f1/3(corner frequency of device’s flicker noise).[7]
To the negative resistor CMOS LC oscillator with bias
transistor, the main phase noise is the flicker noise will be
up-converted to 1/f3 noise and device’s thermal noise will be
up-converted to 1/f2 noise. Low-frequency noise in bias
transistor will be up-converted to phase noise through the
switching action of the cross-coupled transistor. The
high-frequency bias noise is usually grounded by the large
junction capacitances of the bias transistor. In this sense
PMOS device is preferred to bias the circuit than NMOS
device since PMOS device has low corner frequency of
flicker noise, which means less low frequency noise. And
upside bias structure is selected can suppress the substrate

1-4244-1312-5/07/$25.00 © 2007 IEEE 669

noise for PMOS is connected to the upside so PMOS is placed
in n-well but not substrate. And large device size is used since
the flicker noise is related to the device size through
kf
i 21 = ∆f
f fC oxWL
When we change the amplitude of the oscillation, the
frequency will also change. The nonlinear nature of the
cross-coupled transistors will generate harmonic distortion at
the VCO tank output nodes in response to a increased voltage
swing. See Fig 2.
Fig 2. Transient in voltage-limited region
General the amplitude increase with the current increasing.
But for the supply voltage’s limit, the amplitude of the VCO
will not increase with the current when amplitude is near to
the supply voltage. We can get equation:
 I ⋅R current− limited
Vm =  B eq
 Vlimit voltage− limited
The distortion wave reflects the resistor’s balance in LC
tank. Second and third harmonics of the fundamental current
will flow into the low impedance side of the LC tank and the
oscillation frequency adjusts to compensate the imbalance of
active power in the LC tank. This is the basic process of
AM-PM in the LC VCO. The cross-coupled transistor plays a
fundamental role in the AM-PM conversion. And the AM-PM
conversion factor can be adjusted by the device sizing of the
two switching transistors. At the same bias current, reducing
W/L radio of MOS device would increases the gate overdrive
voltage Vgs-Vth, thus increasing the linear range of the
cross-coupled pair and reducing the AM-PM conversion
1-4244-1312-5/07/$25.00 © 2007 IEEE
factor for a given signal swing. On the other hand, reducing
device sizes means more low frequency flicker noise would
be up-converted into phase noise. So the optimum device
sizing is a tradeoff between AM-PM conversion factor and
switching device’s flicker noise.
(2)
The tune-range is decided by PN varactors, inductor and
parasitic capacity [6]
C P + C v ,max
FTR = (4)
C P + C v ,min
from the equation we can see that FTR is inverse to the
parasitic capacity Cp.
III. THE FILTERING RESISTOR’S FUNCTION
At RF and microwave frequencies, the out-put
impendence of the bias transistor is nearly zero due to the
large junction capacitance of the PMOS devices. Basically,
this ground node will affect overall quality factor of the LC
tank. Across a single period of oscillation, the two switching
transistors will change their operate points back and forth. At
zero differential oscillation voltage, both switching transistors
are in saturation, and the low impendence node is isolated
from the LC tank. As the differential oscillation voltage
swings, one transistor enter into triode region and the other
transistor was droved deeper into saturation. The channel
resistance RDS of the transistor in triode region reduces rapidly
with the oscillation voltage, thus the LC tank is loaded
directly by the “ground” and its quality factor was degraded
(3)
heavily. The followed equation formulizes the relationship
between the load QL and the unload QU for LC tank as a
function of the loading resistance RL
QU R L
QL = (5)
QU ω 0 L + R L
As shown in Fig3, even harmonics flow in a common way,
through the switching transistors to the “ground”. If one serial
resistor is used, due to the wide-band nature of resistor, it can
suppress not only second harmonic but also all the other
harmonics. As a proof of concept, Fig4 show the frequency
spectrum at the common source node with filtering resistor,
but the thermal noise of the resistor will be up-converted into
670
1/f2 noise by the switching transistors. From the Fig6, we can see the phase noise at 10 KHz
improved with the resistance’s increasing. It is because the
filtering resistor suppresses the even harmonics from the LC
tank as well as the low frequency bias noise. If continue
increase the resistance, the phase noise will degrade for the
thermal noise contribution overwhelms the phase noise
reduction by the harmonic filtering. In this design R=74Ω
is selected.

Fig 3. Frequency spectrum at the common source node without filtering

resistor

Fig 6. Phase noise at both 10 KHz and 600 KHz versus resistance

IV. SIMULATION RESULTS

Fig 4. Frequency spectrum at the common source node with filtering resistor According to the filtering technology, a 2.4GHz VCO is
designed with Mentor Eldo RF and chartered 0.35 process.
And the level of this noise is proportional to the resistance.
Fig7 is phase noise curve at 2.4GHz. It shows phase noise is
From Fig5, we can see that before 10 KHz the low-frequency
-121.1 at 600KHz. Fig8 is transient analyses of VCO. We can
noise contribute most to phase noise, and after 10 KHz the
see from it that the VCO need about 28ns from beginning to
thermal noise contribute most. So there is a tradeoff between
stable. Fig9 is tuning range, which shows the range is from
the harmonic filtering and its thermal noise contribution. Fig6
2.189GHz to 2.488GHz, and get to 12.46%.
shows simulated phase noise at both 10 KHz and 600 KHz
offset frequencies as a function of the resistance.

Fig 7. Phase noise at 2.4GHz

Fig 5. Phase noise curve Table 1 shows some papers’ phase noise performance,
which use FOM [6]

1-4244-1312-5/07/$25.00 © 2007 IEEE 671

 f   p 
FOM = L{∆f }− 20log 0  + 10log  (6)
 ∆f  1mW 

Fig 8. Transient analyses of VCO Fig 9. The frequency tuning curve

Table 1. Phase noise performance compare with other papers

paper process f0/GHz Nphase/(dBc/Hz) VDD/V I/mA FOM

[5]
Hegazi BiCMOS 1.0 -152@3MHz 2.5 3.65 -194.86
This paper 0.35µmCMOS 2.4 -121@600KHz 3.3 12 -177.15
Bunch[9] 0.35µmCMOS 2.5 -117@600KHz 3 12 -173.85
[10]
Liu 0.35µmCMOS 6.0 -98.4@1MHz 1.5 12 -161.41
[6]Jonghae Kim, Jean-Olivier Plouchart, Noan Zamder, Melanie Sherony, Yue
ACKNOWLEDGMENT
Tan, Meeyoung Yoon,Robert Trzcinski, Mohamed Talbi, John Safran, Asit
An all PMOS LC VCO with wideband harmonic filtering Ray, Lawrence Wangner. A Power-Optimized widely-tunable 5-GHz
resistor is designed at 2.4GHz. Its tuning range get to Monolithic VCO in a digital SOI CMOS Technology on High Resistivity
300MHz fits 80MHz of WLAN. So it can be used in WLAN. Substrate. ISLPED’03, 2003, Seoul, Korea.
This paper also can be a referenced paper for CMOS negative [7] Thomas H. Lee. The Design of CMOS Radio-Frequency Integrated
resistance LC VCO. Circuits. Publishing House of Electronics Industry, Beijing, 2004.
[8]Jan Craninckx, Michiel S. J. Steyaert. A 1.8-GHz Low-Phase-Noise
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February 1998. Frequency Integrated Circuits Symposium, 2001,5:49—52.

[2] D. B. Lesson. A Simple model of feedback Oscillator noise Spectrum. [10] Liu T P.A 6.5 GHz monolithic CMOS voltage—controlled oscillators.

Proceeding of the IEEE. ISSCC Tech Dig, 1999, 2:404—405

[3] J. J. Rael and A. A. Abidi, “Physical processes of phase noise in

differential LC oscillators,” in Proc. IEEE Custom Integrated Circuits
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[5] Emad Hagazi, Henrik Sjǒland, Abidi.A Filtering Technique to low LC
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