IE1204 Digital Design F11: Programmable Logic, VHDL For Sequential Circuits

IE1204 Digital Design
F11: Programmable Logic,

VHDL for Sequential Circuits
Masoumeh (Azin) Ebrahimi (masebr@kth.se)
Elena Dubrova (dubrova@kth.se)

KTH / ICT / ES
This lecture
• BV pp. 98-118, 418-426, 507-519
IE1204 Digital Design, Autumn2016 2

Programmable Logic Devices
• Programmable logic devices (PLDs)

were introduced in the 1970s
• They are based on a structure with an
AND-OR array that makes it easy to
implement a sum-of-products
expression

Structure of a PLD
x1 x2 xn
Input buffers
and
inverters
x1 x1 xn xn
P1
AND plane OR plane

Pk
f1 fm

Programmable Logic Array (PLA)
x1 x2 x3
• Both AND and OR
arrays are
OR
programmable P1 plane
f1=x1x2+x1x3+x1x2x3 P2
f2=x1x2+x1x2x3+x1x3 P3
P4
AND
plane
f1 f2

Programmable Array Logic (PAL)
x1 x2 x3
• Only the AND array is
programmable
P1
f1=x1x2x3+x1x2x3 f1
P2
f2=x1x2+x1x2x3
P3
f2
P4
AND plane

Combinatorial and register outputs
• In earlier PLDs there were

– combinatorial outputs
– register outputs (outputs with a flip-flop)
• For each circuit the number of combinational
and register outputs was fixed
• To increase flexibility, macrocells were
introduced
– one can choose if an output is
combinatorial or has a flip-flop
Macrocells in a PLD
x1 x2 x3
Select
P1 Enable
P2 f1
P3
P4 f2 f1
Flip-flop
D Q
A programmable
multiplexer can be
Clock used to select the
type of output
To AND plane

Programming of PLDs

Complex PLD's (CPLD)
• PLDs were quite small (PALCE 22V10

had 10 flip-flops)
• To program larger functions, structures
consisting of several PLD-like blocks
were developed called Complex PLD
(CPLD)

CPLD Structure
I/O block
I/O block
PAL-like PAL-like
block block
Interconnection wires
I/O block
I/O block
PAL-like PAL-like
block block

Programming of CPLDs via the
JTAG interface
• Modern CPLDs (and FPGAs) can be
programmed by downloading circuit
description (programming information)
via a cable
• Download usually uses a standard port
called JTAG port (Joint Test Action
Group)

Programming via the JTAG port
You can program the
chips when they are
soldered to the circuit
board - using the
(a) CPLD in a Quad Flat Pack (QFP) package
programmer you can
To computer
select which chip you
want to program
through the JTAG port
Printed
circuit board
(b) JTAG programming

Field Programmable Gate Arrays
• CPLDs are based on the AND-OR array

• It is difficult to make really large
functions using CPLDs
• FPGAs use a different concept based
on logic blocks

Structure of an FPGA

Look-up-tables (LUT)
A LUT with n inputs can
Programmable 0/1 realize all
1
cells combinational functions
with up to n inputs.
0/1 0 The usual size of LUT
1
in an FPGA is n = 4
f
0/1 0
1
0/1 0
x2
x1
Two-input LUT

Example: XOR gate
Programmed
values 0 1
x1 x2 f
1 0
1
1 1 0
f
1 0 1 1 1
0
0 1 1
0 0
0 0 0 x2
x1
Two-input LUT

Logic Block in a FPGA
• A logic block in an FPGA often consists of a

LUT, a flip-flop and a multiplexer to select
register output
Select
Out
Flip-flop
In1
In2 LUT D Q
In3
Clock

Programming the LUT's and the
connection matrix in an FPGA
x3 f
• Blue cross: switch
is programmed
• Black cross: switch
is not programmed x1
x1 0 x2 0
0 f1 1 f2
0 0
f=f1+f2 x2 x2
1
x3
0
f=x1x2+x2x3
f1 0
1 f
1
f2
1

DE2 University Board
• DE2 Board
– Cyclone II EP2C35
FPGA (Datorteknik-
course)
– 4 Mbytes of flash
memory
– 512 Kbytes of static
RAM
– 8 Mbytes of SDRAM
– Several I/O-Devices
– 50 MHz oscillator

Cyclone II
Logic Element

Cyclone II Family
(3) Total Number of 18x18 Multipliers DE2

Stratix III Family
DE3 Board

Multiple processors can be
implemented on an FPGA
• Nios II is a so-called 'soft-
processor' (32-bit) that Nios II
can be implemented on
Altera’s FPGAs
• Today's FPGAs are so
Nios II
large that multiple
processors can fit on a
single FPGA chip
Very powerful multiprocessor
systems can be created on an
FPGA!
ASICs
• An ASIC (Application Specific Integrated

Circuit) is a circuit which is manufactured at a
semiconductor factory
• In a full custom integrated circuit, the entire
circuit is customized
• In an ASIC, some design steps have already
been made to reduce design time and cost
• There are several types of ASICs:
– Gate array ASICs
– Standard cell ASIC
ASICs: Gate Array
• In a gate array ASIC, gates (or transistors) are

already on silicon

ASICs: Gate Array
f1
• We only need
to create the
x1
links between
the inputs and
outputs of x2
gates
x3

ASICs: Standard Cells
• A standard cell can for example be AND, OR, Invert,

XOR, XNOR, buffer, or a storage function as flipflop
or latch.

Comparison
FPGA, Gate Array, Standard Cell
Initial Cost Cost per part Performance Fabrication

Time
FPGA Low High Low Short
Gate Array
(ASIC)
Standard Cell High Low High Long
(ASIC)

Design Trade-Offs
Design Time
Full Custom
Standard Cell
Gate Array
Programmable
Logic
Microprocessor
Performance

VHDL: Sequential circuits

Quick question
• Which logic gate is represented by the

following VHDL code?

Quick question
• Which logic gate is represented by the

following VHDL code?

Moore-machine processes
• For a Moore machine, we create three

processes
– Next state decoder
– Output decoder
– State register
State
NEXT STATE STATE REGISTER OUTPUT

Input DECODER DECODER Output
signals signals
Clk
Bottle dispenser
• Bottle dispenser consists of several

parts
– COIN RECEIVER
– DROP BOTTLE
– COIN RETURN
• Machine accepts only the following
coins: 1 Euro, 50 Cent, 10 Cent
• The vending machine only returns 10
Cent coins

Bottle dispenser vending machine
in VHDL
• We use bottle dispenser vending machine as
an example
• We describe its system controller in VHDL
COIN_PRESENT DROP
GT_1_EURO DROP_READY DROP BOTTLE
COIN EQ_1_EURO
SYSTEM
RECEIVER LT_1_EURO CONTROL
DEC_ACC RETURN_10_CENT
CLR_ACC CHANGER_READY COIN RETURN

Signal Properties
• DROP_READY is active for one clock cycle after the

bottle has been ejected
• CHANGER_READY is active for one clock cycle after a
10 Cent coin is ejected
• Because of the mechanical properties, the following
signals are active and inactive for several clock cycles:
– COIN_PRESENT (active for several clock cycles after the coin
drop)
– DROP_READY (active for several clock periods after bottle
drop)
– CHANGER_READY (inactive for several clock periods after coin
return)

Flow diagram of control system
Reset • Coin
– 10 Cent, 50 Cent, 1 Euro
• Coin return
No Coin
registered? – 10 Cent
• Bottle Price
Yes
– 1 Euro
Total <1 €
Total?
Total = 1 € Total> € 1
Eject Return
bottle 10 Cent
Reset Decrease
sum sum

State diagram (Moore)
COIN_PRESENT
(a)
(a) Wait for coin
COIN_PRESENT
(b) Register coin
COIN_PRESENT
(b) (c) Coin is registered (3 cases)
COIN_PRESENT (d) Drop bottle
LT_I_EURO
(c) (e) Reset sum
EQ_I_EURO GT_I_EURO (f) Return 10 Cent
DROP CHANGER (g) Decrease sum with 10 Cent
READY READY
(d) (f) RETURN_10_CENT
DROP
DROP READY CHANGER_READY • Upon entry into the state,

signal becomes active
(e) (g)
• When exiting the state,
CLR_ACC DEC_ACC signal becomes inactive

State diagram
COIN_PRESENT
(a) • State assignment
COIN_PRESENT with no claim for
COIN_PRESENT optimality (Ad hoc)
(b) – (a) next to (b)
– (b) next to (c)
COIN_PRESENT
LT_I_EURO – (d) next to (e)
(c) – (f) next to (g)
EQ_I_EURO GT_I_EURO
• For all these cases,
DROP CHANGER only one variable
READY READY
(d) (f) changes
DROP RETURN_10_CENT
AB
DROP READY CHANGER_READY 00 01 11 10
0 a - d f
(e) (g) C 1 b c e g
CLR_ACC DEC_ACC
(”-” = don’t care)
State diagram
COIN_PRESENT
(a)
000 • The state diagram
COIN_PRESENT contains all information
(b)
COIN_PRESENT required to generate an
001 implementation
COIN_PRESENT
LT_I_EURO (c) • Assumption: D flip-flops
011
GT_I_EURO
are used as state
EQ_I_EURO
register
DROP CHANGER
READY (d) (f) READY • 7 states: 3 flip-flops are
DROP 110 100 RETURN_10_CENT
needed
DROP READY CHANGER_READY
The state variable order is
(e) (g)
101
ABC, i.e. state (c) is
111
CLR_ACC DEC_ACC
A = 0, B = 1,C = 1

Unused state?!
COIN_PRESENT
(a)
• If fall into the unused
000 (h)
COIN_PRESENT 010
state (h) we are stuck!!
Possible ways out:
COIN_PRESENT
(b) • going to (c) and
001
continue.
COIN_PRESENT
LT_I_EURO (c) • going to (d) and
011 offering soft drinks!!
EQ_I_EURO GT_I_EURO
• going to (e) and
DROP CHANGER
READY READY resetting any
(d) (f)
100 previous payment.
DROP 110 RETURN_10_CENT
• Which option do you
prefer for your design?!
(e) (g)
111 101 • Which option leads to a
CLR_ACC DEC_ACC
simpler design?

Construction of next-state and
output decoders (Moore machine)
Input- Combinational Combinational Output-
Flip-flops
signals circuit circuit signals
Clk
COIN_PRESENT DA A
D
LT_I_EURO DROP
EQ_I_EURO RETURN_I0_CENT
GT_I_EURO DB B
DROP_READY Next D Output
CHANGER_READY State Decoder CLR_ACC
A
Decoder DEC_ACC
DC C
B D
C
Clk
At next step, we develop the logic for the next state (DA, DB, DC) and outputs
Construction of next-state and
output decoders
Next state Output
Input-signals decoder Flip-flops decoder Output-signals
(Combination (Combination
al circuit) al circuit)
Clk
? ?
COIN_PRESENT DA A
D
LT_I_EURO DROP
GT_I_EURO DB B
A
Decoder DEC_ACC
DC C
B D
C
Clk
At next step, we develop the logic for the next state (DA, DB, DC) and outputs
Decoder: Next state - DA
COIN_PRESENT
(a) DA AB
000
00 01 11 10
COIN_PRESENT
COIN_PRESENT 0 0 - 1 1
(b) C
001 1 0 (=) + (>) 0 0
COIN_PRESENT
LT_I_EURO (c) (=) : EQ_1_EURO
011 (>) : GT_1_EURO
EQ_I_EURO GT_I_EURO
DROP CHANGER
READY (d) (f) READY

(e) (g)
111 101 D A = AB( =) + AB( >) + A C
CLR_ACC DEC_ACC
45
Variable-Entered Mapping (VEM)
• Variable-Entered Mapping can help to draw and

minimize Karnaugh diagrams with many variables.
– In this example there are several variables as:
Coin_Present, Drop_Ready, Changer_Ready, GT, LT, EQ.
• Instead of opening an "extra dimension" we write a
variable into the Karnaugh map
• You must be extra careful when drawing circuits so
that you do not forget a variable combination!
DA AB
00 01 11 10
0 0 - 1 1
C
1 0 (=) + (>) 0 0

Decoder: Next state - DB
COIN_PRESENT
(a) DB AB
000
00 01 11 10
COIN_PRESENT
COIN_PRESENT 0 0 - 1 0
(b) C
001 1 CP (=) 0 1
COIN_PRESENT
LT_I_EURO (c) (=) : EQ_1_EURO
011 CP : COIN_PRESENT
EQ_I_EURO GT_I_EURO
DROP CHANGER
READY (d) (f) READY

(e) (g)
111 101 DB = AB( =) + BC + BC(CP ) + ABC
CLR_ACC DEC_ACC

Decoder: Next state- DC
COIN_PRESENT
(a) DC AB
000
00 01 11 10
COIN_PRESENT
COIN_PRESENT 0 CP - DR CR
(b) C
001 1 1 0 0 1
COIN_PRESENT
LT_I_EURO (c) CP : COIN_PRESENT
011 DR: DROP_READY
EQ_I_EURO GT_I_EURO
CR: CHANGER_READY
DROP CHANGER
READY (d) (f) READY

(e) (g)
D C = AC(CP) + BC(DR)
111 101
+ A B(CR) + BC
CLR_ACC DEC_ACC
Decoder: Output signals
COIN_PRESENT
(a) • Output decoder is
000
COIN_PRESENT trivial, since its value
COIN_PRESENT is directly dependent
(b)
001 on the current state
COIN_PRESENT
LT_I_EURO (c)
011
EQ_I_EURO GT_I_EURO
DROP = AB C
DROP CHANGER
READY READY
CLR_ACC =ABC
(d) (f)
DROP 110 100 RETURN_10_CENT RETURN_10_ CENT = A BC
DROP READY CHANGER_READY DEC_ACC = A BC
(e) (g)
111 101
CLR_ACC DEC_ACC
Implementation
COIN_PRESENT DA A
D
LT_I_EURO DROP
GT_I_EURO DB B
A
Decoder DEC_ACC
DC C
B D
C
Clk
Now you can design ”Next State Decoder” and ”Output Decoder” by knowing
the logic function of Da, Db, Dc, and logic funtion of outputs ”Drop”,
”Return_10_Cent”, ”CLR_ACC”, and ”DEC_ACC”.

Vending Machine in VHDL:
Entity
ENTITY Vending_Machine IS
• Entity describes the system
PORT (
as a 'black box' -- Inputs
• Entity describes the interface coin_present : IN std_logic;
to the outside world gt_1_euro : IN std_logic;
eq_1_euro : IN std_logic;
• All inputs and outputs are lt_1_euro : IN std_logic;
described drop_ready : IN std_logic;
• Apart from the input and changer_ready : IN std_logic;
reset_n : IN std_logic;
output signals, block diagram
clk : IN std_logic;
needs signals for -- Outputs
– Clock dec_acc : OUT std_logic;
– Reset (active low) clr_acc : OUT std_logic;
drop : OUT std_logic;
return_10_cent : OUT std_logic);
END Vending_Machine;

Architecture
• The architecture describes the function
of the machine
• We define
– internal signals for the current and next
states
– three processes for next-state decoder,
output decoder and state register

Processes in VHDL
• A architecture in VHDL can contain

multiple processes
• Processes are executed in parallel
• A process is written as a sequential
program

Internal signals
• Moore machine contains internal signals

for
– Current state
– Next state
• These signals are declared in the
architecture description

Internal Signals
• We need to create a type for internal signals
• Since we describe the states, we use an enumerated
type with the values a, b, c, d, e, f, g
• We declare one variable for the current state
(current_state) and one for the next state
(next_state)
ARCHITECTURE Moore_FSM OF Vending_Machine IS

TYPE state_type IS (a, b, c, d, e, f, g);
SIGNAL current_state, next_state: state_type;
BEGIN -- Moore_FSM
…

Internal Signals
• If we do not specify a state assignment, synthesis tool will select it
• We can force a certain encoding using attributes (NOTE: Attributes
are dependent on synthesis tool and thus are not portable!)
ARCHITECTURE Moore_FSM OF Vending_Machine IS

TYPE state_type IS (a, b, c, d, e, f, g);
-- We can use state encoding according to BV 8.4.6
-- to enforce a particular encoding (for Quartus)
ATTRIBUTE enum_encoding : string;
ATTRIBUTE enum_encoding OF state_type : TYPE IS "000
001 011 110 111 100 101";
SIGNAL current_state, next_state : state_type;
BEGIN -- Moore_FSM
…

Process for Next-State Decoder
Next state Output
Clk
• Next-State-Decoder is described as a
process
• Sensitivity list contains all the inputs that
'activate' the process
NEXTSTATE : PROCESS (current_state, coin_present,
gt_1_euro, eq_1_euro, lt_1_euro, drop_ready,
changer_ready) –- Sensitivity List
BEGIN -- PROCESS NEXT_STATE
…

Process for Next-State-Decoder
Next state Output
Clk
• We now use a CASE statement to describe the transitions to the

next state from each state conditions
COIN_PRESENT
CASE current_state IS (a)
000
WHEN a => IF coin_present = '1' THEN COIN_PRESENT
next_state <= b; COIN_PRESENT

(b)
001
ELSE COIN_PRESENT
LT_I_EURO (c)
next_state <= a; 011
EQ_I_EURO GT_I_EURO
END IF;
DROP CHANGER
WHEN b => IF coin_present = '0' THEN READY
(d) (f) READY
110 100 RETURN_10_CENT
next_state <= c; DROP

ELSE
(e) (g)
next_state <= b; 111 101
CLR_ACC DEC_ACC
END IF;

• We can simplify the description by specifying a default value for
the next state
…
next_state <= current_state;
CASE current_state IS
WHEN a => IF coin_present = '1' THEN
next_state <= b;
END IF;
WHEN b => IF coin_present = '0' THEN
next_state <= c;
END IF;
…
It is important to we specify all options for next_state signal. Otherwise we
may implicitly set next_state <= next_state which generates a loop.

• We terminate the CASE statement with a WHEN OTHERS
statement. Here we specify that we should go to the state a if
we end up in an unspecified state
…
WHEN g => next_state <= c;
WHEN OTHERS => next_state <= a;
END CASE;
END PROCESS NEXTSTATE;

Process for Output-Decoder
Next state Output
Clk
• Output decoder is described as a

separate process
• Sensitivity list contains only the current
state because the outputs are directly
dependent on it

Process for Output-Decoder
OUTPUT : PROCESS (current_state)
BEGIN -- PROCESS OUTPUT
drop <= '0';
clr_acc <= '0';
dec_acc <= '0';
return_10_cent <= '0';
CASE current_state IS
WHEN d => drop <= '1';
WHEN e => clr_acc <= '1';
WHEN f => return_10_cent <= '1';
WHEN g => dec_acc <= '1';
WHEN OTHERS => NULL;
END CASE;
END PROCESS OUTPUT;
Process for State register
Next state Output
Clk
• State register is modeled as a synchronous process

with asynchronous reset (active low)
CLOCK : PROCESS (clk, reset_n)
BEGIN -- PROCESS CLOCK
IF reset_n = '0' THEN -- asynchronous reset (active low)
current_state <= a;
ELSIF clk‘EVENT AND clk = '1' THEN -- rising clock edge
current_state <= next_state;
END IF;
END PROCESS CLOCK;

Quick question
• Which state machine is represented by this VHDL code?

Mealy machine
State
NEXT STATE OUTPUT

STATE REGISTER
DECODER DECODER
Input Output
signals signals
Clk
• In a Mealy machine, output signals depend

on both the current state and inputs

Mealy machine in VHDL
• A Mealy machine can be modeled in the

same way as the Moore machine
• The difference is that output decoder is
also dependent on the input signals
• Process which models outputs needs to
have input signals in the sensitivity list
as well!

More on VHDL
• The sample code for bottle dispenser

available on the course website
• Look at the study of "VHDL synthesis"
on the course website
• Both Brown/Vranesic- and Hemert-book
includes code samples

Summary
• PLD, PAL, CPLD

• FPGA
• ASIC – gate array and standard cell
• Modeling sequential circuits with VHDL
• Next lecture: BV pp. 584-640

IE1204 Digital Design F11: Programmable Logic, VHDL For Sequential Circuits

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IE1204 Digital Design

F11: Programmable Logic,

Elena Dubrova (dubrova@kth.se)

• BV pp. 98-118, 418-426, 507-519

IE1204 Digital Design, Autumn2016 2

• Programmable logic devices (PLDs)

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AND plane OR plane

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• In earlier PLDs there were

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• PLDs were quite small (PALCE 22V10

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(b) JTAG programming

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• CPLDs are based on the AND-OR array

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• A logic block in an FPGA often consists of a

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(3) Total Number of 18x18 Multipliers DE2

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• An ASIC (Application Specific Integrated

• In a gate array ASIC, gates (or transistors) are

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• A standard cell can for example be AND, OR, Invert,

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Initial Cost Cost per part Performance Fabrication

FPGA Low High Low Short

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• Which logic gate is represented by the

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• Which logic gate is represented by the

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• For a Moore machine, we create three

NEXT STATE STATE REGISTER OUTPUT

• Bottle dispenser consists of several

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• DROP_READY is active for one clock cycle after the

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DROP READY CHANGER_READY • Upon entry into the state,

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DROP 110 100 RETURN_10_CENT

DROP READY CHANGER_READY

• Variable-Entered Mapping can help to draw and