Advances

in CMOS
Fabrica2on Technology
Different Process Technologies

•  NWELL
Here an NWELL is created in a p-sunstrate. p-MOSFETs are built in the
NWELL and n-MOSFETs in the p substrate

•  PWELL
Prior to the n-well process p-well process was popular. In this case a PWELL is
created in the substrate and n-MOSFETs are built in the PWELL

•  Twin Tub/ WELL

In this case both a p-well and an n-well are created for the n-MOSFET's and
p-MOSFETs respec2vely in the twin well or twin tub technology.
Both transistors can be op2mized separately

•  SoI – Silicon on Insulator

As the name suggests transistors are fabricated on an insulator (SiO2 or sapphire) . Insula2ng
substrate eliminates capacitance between the source/drain and body, resul2ng in higher speed devices
and low leakage currents.
Advanced CMOS Process Techniques

•  Shallow trench isola2on – Use of SiO2 trenches for noise isola2on

•  n+ and p+-doped polysilicon gates – For low threshold voltages
•  Source-drain extensions LDD - Lightly doped Drain structure used to
reduce hot-electron effects, in smaller geometry designs.
•  Self-aligned silicide (spacers)
•  Non-uniform channel doping (short-channel effects)
Process enhancements

•  Up to eight metal levels in modern processes

•  Copper for metal levels 2 and higher
•  Stacked contacts and vias
•  Chemical Mechanical Polishing for technologies with several metal levels
•  For analog applica2ons some processes offer:
!  Capacitors
!  Resistors
!  Bipolar transistors (BiCMOS)
Process enhancements- SoI

•  SOI is gaining lot of currency in high speed UDSM processes.

–  Reduced parasi2cs: Substrate capacitor
•  Enhances speed 25-30% or
•  Lower power ~50% or
•  Mix of both above.
–  Reduced substrate cross talk & MOS Strip, R,L,C losses at high freq
•  Beaer RF capability of CMOS. Upto 10GHz.
•  Two types of SOI
–  SIMOX: Oxygen Implant/Anneal process
–  BESOI: Bond/Etch back process
–  Both use Silicon as substrate and thin layer of SiO2 as isola2on between
Substrate and Thin so-called epitaxial layer.
Process enhancements- SoI

•  Process
1. Take 2 monolithic silicon wafers
2. Oxidize wafer A
3. Implant hydrogen to a depth of epitaxy
4. Bond the wafer B with reversed wafer A
5. Split OR SmartCut ® wafer A
6. Annealing and Polishing of bonded wafers.
7. Remaining wafer A split, becomes new wafer
for new SOI wafer crea2on.
•  Advantage
–  This SOI crea2on technique relies on standard
microelectronics manufacturing equipment.
Process enhancements- SoI
Process enhancements- FinFET

•  Innova2ve design of the MOSFET that evolved with shrinking sizes and
higher levels of integra2on
•  Typically built on SOI substrate on which silicon is etched into "fin"-like shaped
body of the transistor; the gate is wrapped around and over the "fin"
which also acts as a transistor's channel.
*Fin comes from the structure i.e. looks like fins of a FISH

*First developed by Chenming Hu and his colleagues

FIN FET Advantages

Power Much lower power consump2on allows high

integra2on levels. Early adopters reported 150%
improvements.
Opera2ng Voltage FinFETs operate at a lower voltage as a result of
their lower threshold voltage.
Feature Size Possible to pass through the 20nm barrier
previously thought as an end point.

Sta2c leakage Typically reduced by 90%

current!
Opera2ng Speed In excess of 30% faster than the non-FinFET
versions.