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STUDY OF 8086/8088

INTRODUCTION

Assembly Language is a low level programming language for a computer


system. It is specific to a certain computer system. Hence it is machine dependent in nature.
The 8086 was Intel’s first 16-bit microprocessor. Its design is based on the 8080. The
memory in 8086 based microcomputer is organized as bytes. The 8086 always access a 16-bit
word to or from memory.

A word instruction accessing a word starting with ac even address can


perform its function with one memory access. A word instruction starting at an odd address
must perform two memory accesses to two consecutive memory even addresses, discarding
the unwanted bytes of each. For byte access starting at odd address N, the byte at the previous
even address N-1 is also accessed but discarded. Similarly for byte access starting at even
address N, the byte with add address N+1 is also accessed but discarded.

Assembler is an intermediate program, which converts Assembly


Language into machine-readable language. Design specifications for an assembler are:
a. Identify the necessary information to perform a task.
b. Select a suitable data structure to hold the information.
c. Determine the processing necessary to maintain the information in the data
structure.
d. Determine the processing necessary to perform the task.
8086 ARCHITECTURE:
The architecture of 8086 microprocessor is divided internally into two separate units. They
are

1. Execution Unit (EU)


2. Bus Interface Unit (BIU)

These two units function independently

EXECUTION UNIT:
The execution unit executes instructions that have already been fetched by BIU. A 16-
bit arithmetic and logical unit (ALU) in EU maintain the fuctions of micreprocessor, control
flags and manipulates the general registers. These are the AX, BX, CX, DX, SP, BP, SI and
DI and flag register.
The 16-bit general registers are
i) AX Register |AH|AL|
ii) BX Register |BH|BL|
iii) CX Register |CH|CL|
iv) DX Register |DH|DL|

These general registers can be accessed as a 8 bit register by dividing high byte register and
low byte register. Other than general register no other register can be accessed as 8 bit
registers.

AX Register
The AX register is known as the primary accumulator and it is used for all
input\output operations, some string operations and some arithmetic operations
For example: Multiplication, Division.

BX Register:
The BX register is known as base register.
This is the only general-purpose register whose contents can be used for addressing 8086
memory

CX Register:
The CX register is known as the counter register. This register required to control the
number of times a loop is repeated in the program and contains the value by which bits are
shifted left or right. The instruction loop starts automatically decrement CX by 1 without
affecting flags. If C=0 the 8086 execute next instruction or branches to label start.

DX Register:
DX register is a data register. This register is used for some input\output operations,
this register used to multiply and divide large values.

Pointer Register:
The pointer registers are
a) Stack Pointer Register
b) Base Pointer Register
This register permits the system to access data in the stack segment.
a) Stack Pointer Register:
The stack pointer permits implementation of a stack in memory used for temporary
storage of address and sometimes data. This register is associated with stack segment
register for addressing the stack.
b) Base Pointer Register:
The base pointer facilitates referencing of “Parameters” (data and address passed via
stack).

Index Register:
Index registers are mainly used for extending address of locations and also used in
addition and subtraction.
The two index registers are
a) Source Index
b) Destination Index.
c) The instruction that process data strings use the SI and DI index registers
together with the DS and ES, respectively inorder to distinguish between
the source and destination address.

Flag Registers:

Out of 16 bit nine bits contains the flag register that activates and indicates the flag
registers that activates and indicates the current status of the machine and execute the results
of programs. The flag registers is also involved in comparing the data and arithmetic
operations to change the status of the flag. The flag bits are as follows.

AF (Auxillary carry Flag)


AF is set if there is a carry from the low nibble into the high nibble or a borrow from
the high nibble into the low nibble of the low order 8 bits of a 16 bit number. This flag is used
by BCD arithmetic instructions.

CF (Carry Flag)
This is set if there is a carry from addition or a borrow from subtration.

OF (Overflow Flag)
It is set if there is an arithmetic overflow that is if the size of the result exceeds the
capacity of the destination location.

SF (Sign Flag)
The flag is used to intimate result of arithmetic operation (0=plus, 1=minus)

PF (Parity Flag)
This is set if the result has even parity, PF is zero for odd parity of the result.

ZF (Zero Flag)
Is set to 1 if the result is zero and 0 if the result is nonzero. The three control bits in
the flag register that can be set or cleared by the programmer.

DF (Direction Flag)
This flag is used to correct the interrupts in program.

TF (Trap Flag)
The flag permits operations of CPU in single step mode. The dos DEBUG program
steps the trap flag so at a time can step through the execution of instruction and effects on
register and memory.

BUS INTERFACE UNIT:


The Bus Interface unit fetches instruction, reads operands and write results. The BIU
contains segment registers and instruction pointers, instruction queue and address calculates
for fetching and queuing of instructions. The BIU’s instruction queue is First In First Out
(FIFO). BIU prefetches 6 bytes of instruction code from a memory at a time. This prefetches
in speeds up the program execution. This machanism is known as pipelining. The BIU will
first complete fetching and the services the execution unit. The Instruction queue allows BIU
of contiguous supply of instruction to the execution unit.
The BIU also has four 16 bit segment registers
1. Code Segment (CS)
2. Data Segment (DS)
3. Stack segment (SS)
4. Extra Segment (ES)
The 8086’s 1 megabyte memory is divided into segments of up to 64K bytes each.

Code Segment:
The code segment register contains the initials addresses of code segment.
This address plus the offset value in the instruction pointer (IP) to indicate the instructions of
the program to be fetched for execution.

Stack Segment:
The stack contains the initial address of the stack segment and finds the
specific location by adding offset value with address of the segment. The programmer can
use the BP instead of SP for addressing the stack.

Data Segment:
The DS register points to the current data segment, operands for most
instructions are fetched from this segment. The address plus offset value in instruction pointer
gives specific location in the data segment.

Extra Segment:
ES register points to the extra segment in which data is stored. Some string
operations use the extra segment register for memory address.

Conclusion:
Thus, we have studied in detail about the structure of 8086/8088
microprocessor.

8086 INSTRUCTION SET &


ADDRESSING MODE

ARITHMETIC INSTRUCTIONS:

Addition:
ADD:
It is used to add the content of the register with other register or memory variable.
Eg: ADD AX,BX ;AX=AX+BX
ADC:
An addition with carry instruction adds the bit in the carry flag(C) to the operand
data.
Eg: ADC AX,TEMP ;AX=AX+TEMP+carry
INC:
The increment instruction increments the value in a register or a memory location
by 1,accepts segment register;
Subtraction:
SUB:
It is used to subtract the content of a register or memory location from the content
of another register or memory location.
Eg: SUB AX,BX ;AX=AX-BX
SBB:
The subtraction with borrow instruction is similar to the sub instruction except
for the fact the the carry flag which holds the borrow also gets subtracted.
Eg: SBB AX,BX ;AX=AX-BX-carry

Multiplication and Division:


MUL and IMUL:
Multiplication is performed on byte, word which can be signed integers (IMUL)
or unsigned integers (MUL). The product after a multiplication is always a double
with product.

DIV and IDIV:


Multiplication is performed on byte, word which can be signed integers (IMUL)
or unsigned integers (MUL). The product after a multiplication is always a double
with product.

LOGICAL OPERATIONS:
AND:
It is used to AND two bits A&B and produce the result as shown in the truth
table.
Eg: AND CX,DX ;CX is ANDED with DX and the result is
;moved to CX
OR:
The OR operation performs logical addition and is often called the inclusive OR
function.
Eg: OR SI,DX ;SI is often with DX and the result moves to SI
XOR:
The exclusive OR instruction(XOR) differs from inclusive OR.
Eg: XOR SI,BX ;SI is XOR ed with BX and the result is stored ;in
SI

DATA TRANSFER INSTRUCTION:


MOV:(Move)
MOV instruction copies the content of the source operand into the destination
operand. The source moves changes with MOV instruction.
Eg: MOV AX,BX

LEA(Load Effective Address):


The LEA instruction loads a 16 bit register with the offset address of the data
specified by the operand.
E.g. LEA AX, NUMB ; AX is loaded with the address
of NUMB

PUSH & POP:


The PUSH & POP instructions are important instructions that store and retrieve
data from the LIFO (Last In First Out) stack memory. The microprocessor has four
forms of the PUSH & POP instructions. They are: register, memory, segment register
and flag.

PUSH:
It transfers two bytes of data to the stack from the register or from a memory
location.
E.g.: PUSH AX ; 6 bit register
PUSH BX ;16 bit addressing mode stack
PUSH F ; Copies the flag register to stack
POP:
The POP instruction performs the inverse of a PUSH instruction. The POP
instruction removes data from the stack and places it into the target 16-bit register,
segment register, or a 16 bit memory location.
E.g. POP DI ; 16 bit register
POP [SI] ; 16 bit memory address
POP F ; Load the flag register from stack

String Data Transfers:


Direction flag:
The direction flag(D) selects autoincrement(D=0) or autodecrement(D=1)
operation for the DI and SI registers during string operation.
CLD:
CLD instruction selects auto increment mode (D=0).
STD:
STD selects the auto decrement mode (D=1).

LODS:
The LODS instruction loads AL, AX with data stored at the data segment offset
address indexed by the SI register. After loading AL/AX the contents of SI are
incremented if D=0 or decremented if D=1.
E.g. LODSD ; AL=DS: [SI]; SI=SI+1
LODSW ; AX=DS: [SI]; SI=SI+2
STOS:
The STOS instruction stores AL, AX at the extra segment memory location
addressed by the DI register.
E.g. STOSB ; ES: [DI] =AL; DI=DI+1
STOSW ; ES: [DI] =AX; DI=DI+2
REP:
The repeat prefix (REP) is added to any string data transfer instruction except the
LODS instruction. The REP prefix decrements CX by 1 each time till CX becomes 0.
E.g. MOV CX, 10
REP STOSB
The above command copies the content of AL to extra segment addressed by
DI for 10 times.
MOVS:
It transfers data from one memory location to another. This is the only memory
to memory transfer allowed in the 8086. It transfers a byte (or) word from data
segment location addressed by SI to Extra Segment location addressed by DI.
E.g. MOVSB ; A byte transferred from location
addressed by SI to location by DI.
MOVSW ; A word transferred.

MISCELLANEOUS DATA TRANSFER INSTRUCTIONS:


XCHG:
This command exchanges the content of a register with the content of any other
register or memory location.
E.g. XCHG AX, [DI] ; The content of AX and the memory
location addressed are exchanged.
LAHF:
The LAHF instruction transfers the right most 8 bits of the flag register into the
AH register.

SAHF:
The SAHF instruction transfers the AH register into the rightmost 8 bits of flag
register.

SHIFT INSTRUCTIONS

SHL/SAL
Shift bits of word or byte left, put zero(s) in LSB(s).

SHR
Shift bits of word or byte right, put zero(s) in MSB(s).

SAR
Shift bit of word or byte right, copy old MSB into new MSB.
ROTATE INSTRUCTIONS:

ROL
Rotate bits of byte or word left, MSB to LSB and to CF.

RCL
Rotate bits of byte or word left, MSB to CF and CF to LSB.

RCR
Rotate bits of byte or word right, LSB to CF and CF to MSB.

UNCONDITIONAL TRANSFER INSTRUCTIONS

CALL
Call a procedure (subprogram), save return address on stack.

RET
Return from procedure to calling program.

JMP
Goto specified address to get next instruction.

CONDITIONAL TRANSFER INSTRUCTIONS

JA/JNBE
Jump if above or Jump if not below or equal.

JAE/JNB
Jump if above or equal or Jump if not below.

JB/JNAE
Jump of below or Jump if not above or equal.

JBE/JNA
Jump if below or equal or Jump if not above.

JC
Jump if carry flag CF = 1.

JNC
Jump if no carry (CF = 0).

JNO
Jump if no overflow (Overflow flag OF = 0).

JNS
Jump if no sign (Sign flag SF = 0).

JO
Jump if overflow flag OF = 1.

JP/JPE
Jump if parity or Jump if parity even (PF = 1).
JS
Jump if sign (SF = 1).

ITERATION CONTROL INSTRUCTIONS

LOOP
Loop through a sequence of instructions until CX = 0.

LOOPE/LOOPZ
Loop through a sequence of instructions while ZF = 1 and CX ≠ 0.

LOOPNE/LOOPNZ
Loop through a sequence of instructions while ZF = 0 and CX ≠ 0.

JCXZ
Jump to specified address if CX = 0.

INTERRUPT INSTRUCTIONS

INT
Interrupt program execution, call service procedure.

INTO
Interrupt program execution if OF = 1.

IRET
Return from interrupt service procedure to main program.

NO OPERATION INSTRUCTION

NOP
No action except fetch and decode.

8086 ADDRESSING MODES:

The 8086 has 12 addressing modes. These modes can be classified into five
groups.
1. Register and immediate modes
2. Memory addressing modes
3. Port addressing mode
4. Relative addressing mode
5. Implied addressing mode

Register and Immediate Modes:


In register mode, source operands, destination operands, or both may be
contained in registers. For example: MOV AX, BX moves 16-bit contents of BX into AX.
In immediate mode the operand is specified in the instruction itself. In an 8-bit
microprocessor, the operand is paced in memory immediately after the operation-code byte.
An immediate-mode instruction having an 8-bit operand is a 2-byte instruction. One with a
16-bit operand is a 3-byte instruction.

Memory Addressing Modes:


The EU has direct access to all registers and data for register and immediate
modes. The EU cannot directly access the memory operands. It must use the BIU inorder to
access memory operands. For eg: When the EU needs a memory operand it sends an offset
value to the BIU. This offset is added to the contents of a segment register after shifting it 4
times to the left generating a 20-bit physical address.

The various memory addressing modes are


 Memory Direct Addressing
 Register Indirect Addressing

 Based Addressing
 Indexed Addressing
 Based Indexed Addressing
 String Addressing

Memory Direct Addressing:


In This mode, the effective address is taken directly from the displacement
field of the instruction . No register are involved.

Register Indirect Addressing:


In this mode the instruction specifies a register in the CPU whose contents
give the address of the operand in memory. In other words, the selected register contains the
address of the operand rather than the operand itself. Before using a register indirect mode
instruction the programmer must ensure that the memory address of the operand is placed in
the proccesor register with a previous instruction. A reference to the register is then
equivalent to specifying a memory address.

Based Addressing:
In this mode, the effective address is the sum of a displacement value (signed
8-bit or unsigned 16-bit) and the contents of register BX or BP. The based addressing mode
with BP is a very convenient way to access stack data.

Indexed Addressing:
In this mode, the effective address is calculated from the sum of a
displacement value and the content of register SI or DI.

Based Indexed Addressing:


In this mode, the effective address is computed from the sum of a base register
(BX or BP), an index register (SJ or DI) and a displacement.

String Addressing:
This mode uses index registers. SI is assumed to point to the first byte or word
of the source string, and DI is assumed to point to the first byte or word of the destination
when a string instruction is executed. The SI or DI is automatically incremented or
decremented to point to the next byte or word depending on DF.

Port Addressing:
Two I\O port addressing modes can be used the direct port and indirect port
modes.
In direct port mode, the port number is an 8-bit immediate operand to access 256
ports.
In indirect port modes, the port number is taken from DX allowing 64k bytes
or 32k words of ports.
Relative Addressing Mode:
Instructions using this mode specify the operand as a signed 8 bit displacement
relative to PC. An example in JNC START. This instruction means that if carry=0, the PC is
loaded with current PC contents plus the 8 bit signed value of START; otherwise the next
instruction is executed.

Implied Addressing Mode:


In this mode the operand is specified implicitly in the definition of the
instruction. Instructions of this type are 1-byte instructions. For example, the instruction
“complement accumulator” is an implied-mode instruction because the operand in the
accumulator register is implied in the definition of the instruction.

Conclusion:
Thus, we have studied in detail about the instruction set and addressing mode.

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