Oec 9600 Blocks Diagram

SERIES9600
™
CARD RACK IMAGE SYSTEM INTERCONNECT
LEFT DISPLAY RIGHT DISPLAY TECHNIQUE PROCESSOR PCB ASSEMBLY REFER TO 875410* OR 877971**
X-RAY TUBE
SCH. #876735* or 877742** 875538
ANALOG INTERFACE PCB
LOADS & RUNS DOS & SCH. # 876738
LEFT X-RAY ON RIGHT APPLICATION SOFTWARE IMAGE FUNCTIONS
CONTROL PANEL CONTROL PANEL COLLIMATOR
SWITCH DIGITAL TO ANALOG CONVERSION INTERFACE PCB
SERIAL COMMUNICATIONS TO
ANALOG TO DIGITAL CONVERSION SCH. #874750
MONITOR CART AND
PIO CONTROL AND STATUS
CONTROL PANEL PROCESSOR
INTERFACE TP TO SYSTEM MOTOR DRIVERS
SOLID STATE DISK DRIVE & I.I. FIELD SELECTION
CAMERA AND IMAGE
CONTROLLER FOR FLOPPY DRIVE
COLLIMATOR CONTROLS INTENSIFIER
CONTROL PANEL &
CONTROL PANEL POWER SUPPLY
ASSEMBLY PROCESSOR PCB
SCH. #875601 A/D DATA
877000
COMPUTER BUS
INTERFACES CONTROL SWITCHES CAMERA ROTATION
DRIVES LEDS AND DISPLAY SERIAL COMMUNICATIONS CCD
CAMERA GAIN
SERIAL COMMUNICATIONS TO TP CAMERA
FAST STOP FAST STOP MOTHERBOARD VIDEO LEVEL INDICATOR
SWITCH SWITCH SCH. #875539
POWER & SIGNAL
INTERCONNECT & DISTRIBUTION
MRESET*
XRAY SWITCH INTERCONNECT X-RAY DISABLE
XRAY LAMP VIDEO STABLE
CABLE TO / FROM FLUORO
SERIAL COMM. +24V TO AC TO WORKSTATION STORE
EMERGENCY OFF HANDSWITCH CAMERA & II STATOR SERIAL COMM.
AC CAMERA VIDEO
POWER
AC
AC
FOOTSWITCH POWER/MOTOR
STATOR
RELAY PCB
TRANSFORMER
SCH. # 875997
PS 1 STATOR RELAYS
PROVIDES 40VAC
POWER/SIGNAL AC +15-15 +5 STATOR SENSE
INTERFACE PCB LIFT RELAYS
BATTERIES PRE-CHARGE II POWER RELAY
SCH. # 876001* AC & +24V
CIRCUITRY EMERGENCY OFF INTERFACE
K1, K2, C2, C3, R1 OR 877998** +24 VOLT INTERLOCK RELAY
AUTO START RELAY
INTERFACES AC & DC POWER,
CONTROL SIGNALS, AND PS 2
SERIAL COMMUNICATIONS AC +24
B+ VOLTAGE
DARLINGTON
DRIVERS DRIVE SIGNALS
Q1, Q2
POWER/SIGNAL
DISTRIBUTION PCB C-ARM
ELEVATION SCH. #875968 ELEVATION
MOTOR &
ROTATION RELAYS
& LIMIT SWITCHES SWITCH INTERFACING ROTATION
SWITCHES
FILTER AC
CIRCUIT
L1, C1
X-RAY
GENERATOR REGULATOR PCB ROTATION L-ARM MOTOR
BATTERY
DRIVER PCB SCH. #877458 MOTOR POWER PCB
CHARGER PCB
SCH. # 877461 & LIMIT SWITCHES SCH. #876378
SCH. # 876643*
KV CONTROL & SENSE or 877995**
MA CONTROL & SENSE REFER TO
FILAMENT REGULATOR (MA) FAULT PAL & CIRCUITRY CHARGES BATTERIES
HIGH VOLTAGE DARLINGTON DRIVERS (KV)
SATURATION FAULT DETECTOR
PRECHARGE OUTPUT
MAINFRAME INTERCONNECT DIAGRAM
875500*
9600 C-Arm
TANK OR
HV STEP-UP XFMR 877972** For Reference Only Page 1 of 2
HV RECTIFIER
FILAMENT STEP-DOWN XFMR CARM_BLK.DS4 12/3/96
KV & MA SENSING
GENERATOR
CONTROLLER *=Use for system serial numbers 69-0001 to 69-1000
HIGH VOLTAGE CABLES ASSEMBLY 9600 C-Arm Block Diagram
TO X-RAY TUBE 875392 **=Use for system serial numbers 69-1001 and up
CARD RACK IMAGE SYSTEM
TECHNIQUE PROCESSOR PCB INTERCONNECT X-RAY TUBE
ASSEMBLY CONTROL PANEL
SCH. 877742 REFER TO 878377
ANALOG INTERFACE PCB 878381 ASSEMBLY
LOADS & RUNS DOS & SCH. # 876738 IMAGE FUNCTION 877000
APPLICATION SOFTWARE PCB
COLLIMATOR
SERIAL COMMUNICATIONS TO DIGITAL TO ANALOG CONVERSION SCH. #878398
MONITOR CART AND ANALOG TO DIGITAL CONVERSION MOTOR DRIVERS
CONTROL PANEL PROCESSOR PIO CONTROL AND STATUS I.I. FIELD SELECTION
INTERFACE TP TO SYSTEM CAMERA AND
SOLID STATE DISK DRIVE CONTROL PANEL
COLLIMATOR CONTROLS IMAGE
WITH APPLICATIONS PROCESSOR PCB
SOFTWARE ON SRAM CARD INTENSIFIER SCH. #878486
&
POWER SUPPLY INTERPRETS CP SWITCHES
DRIVES LEDS
A/D DATA
DRIVES DISPLAYS
COMPUTER BUS SERIAL COMMUNICATIONS
TO TECHNIQUE PROC.
SERIAL COMMUNICATIONS CCD
CAMERA LEFT & RIGHT
DISPLAYS
MOTHERBOARD
SCH. #878396
POWER & SIGNAL
INTERCONNECT & DISTRIBUTION CONTROL PANEL LEFT & RIGHT
CAMERA
VIDEO STATOR PROCESSOR I/O PCB CONTROL PANELS
TRANSFORMER SCH. #878489
PROVIDES 40VAC CABLING
CONNECTIONS
INTERCONNECT CABLE X-RAY DISABLE FOR CPP PCB
TO / FROM WORKSTATION VIDEO STABLE
FLUORO AC +24V TO AC TO
STORE FOOTSWITCH HANDSWITCH CAMERA & II STATOR
SERIAL COMM.
CAMERA VIDEO SIGNALS
AC
X-RAY ON
POWER/MOTOR SWITCH
AC POWER
POWER/SIGNAL RELAY PCB & SWITCH
INTERFACE PCB SCH. # 875997 INTERFACE
BATTERIES PRE-CHARGE AC,+24V COLUMN I/O PCB
CIRCUITRY SCH. # 877998 STATOR RELAYS SCH. #878492
STATOR SENSE FAST STOP
K1, K2, C2, C3, R1
LIFT RELAYS
CABLING
SWITCHES
INTERFACES AC & DC POWER, II POWER RELAY
AC CONTROL SIGNALS, AND EMERGENCY OFF INTERFACE CONNECTIONS
SERIAL COMMUNICATIONS +24 VOLT INTERLOCK RELAY FOR CPP PCB
B+ VOLTAGE BATTERY AUTO START RELAY AND SWITCHES
DARLINGTON CHARGER PCB
DRIVERS SCH. # 877995
Q1, Q2 DRIVE SIGNALS
SIGNALS
CHARGES BATTERIES
PRECHARGE OUTPUT POWER C-ARM
ELEVATION
AC AC &
FILTER ROTATION
CIRCUIT SWITCHES
L1, C1 ELEVATION L-ARM MOTOR
X-RAY PS 2
GENERATOR REGULATOR PCB PS 1 MOTOR POWER PCB
DRIVER PCB +15-15 +5 +24 & LIMIT SWITCHES SCH. #876378
SCH. #877458
SCH. # 877461
KV CONTROL & SENSE
MA CONTROL & SENSE
FILAMENT REGULATOR (MA) FAULT PAL & CIRCUITRY
HIGH VOLTAGE DARLINGTON DRIVERS (KV)
SATURATION FAULT DETECTOR
9600 C-Arm
TANK
ROTATION For Reference Only Page 2 of 2
HV STEP-UP XFMR REFER TO MAINFRAME MOTOR
HV RECTIFIER INTERCONNECT DIAGRAM #878376 & LIMIT SWITCHES
FILAMENT STEP-DOWN XFMR CARM_BLK.DS4 12/3/96
KV & MA SENSING
GENERATOR
Use for system serial numbers
CONTROLLER
HIGH VOLTAGE CABLES ASSEMBLY
69-2001 and up
and 62-001 and up
9600 C-Arm Block Diagram
TO X-RAY TUBE 875392
PART OF GENERATOR
CONTROLLER ASY. PRI.I 1.6 VOLT TRIP POINT AT TP1 FAULT PAL OUTPUT TRUTH TABLE
DRAWING #875392
P2 TP1(1A8) U2 PINS
(1A7) FAULT
3 2 17 14 13
2 7 MOTHERBOARD
U1 L H
OVERVOLTAGE L SCH. #875539 OR #878396
+5 CR3 3
CURRENT LOOP GENERATOR DRIVER PCB
SATURATION L H H
R12 ANALOG INTERFACE PCB
SCH. #877461 OVERLOAD H L H SCH. # 876738
R11
VOLTAGE DROP B+
FROM Q1 P3 P2
4 R25 R37 R36 TP17
Q1 R14
10K 10K +12 2 U2 17 OVERLOAD 11
U36
9 12 31 17 3 14
L1
U46
P1 TP7 P3 U27
(1B7)
CR27 8V REFERENCE FAULT SATURATIONTP16 (1A5)
(2A7)
PIO
12 12 SATDET 3- PAL
TP3 4 16 7 14 FAULT 13 7 14 4
VR1 (1A6) 7
2 +U14 FAULT_1 U36 (1A6) U36 33 U46 16 15 (2B7)
(1B8) Q2 Q9 CR23 A2J3
(1A7)
4 (1A6) R18 U7 (2A2) (1A6) (1A5) (2A7)
2 13 FAULT 15 5 13 6 U46 14 17
C1
VOLTAGE DROP 100K HV (2A3) U36 18 5 U36 32
P2 DRIVE 14 DRVON
FROM Q2
PAL U11 8 (2A7)
9
R19 10K (1B7)
9 TP1 TP2 TP21 TP22
B A Disables HV DRA & HV DRB
+5V when Fault is detected
3- TP24 TP25 TP23

CR20 7 OVER VOLTAGE FAULT +5V +12V +15V
2 +U32
J1 P4 (2D8)
(2D7)
C TAP1 5
D TAP2 4
R100 (2D6)
3 U33 SECTAP 26 45 11 U3 U7
+ MUX ADC
AC
(1D6) (1D5)
IN 28 14
TP23 TP24 TP22 TP5

+15V VR1 +12V -15V VR2 -12V +5V GND
(1B4) (1B4)
HIGH VOLTAGE
TRANSFORMER
T1
X-RAY REGULATOR PCB
HIGH VOLTAGE TANK SCH. # 877458
9600 C-ARM
For Reference Only Page 1 of 1
96FAULTS.DS4 12/4/96
GENERATOR KV CIRCUIT FAULTS

FUNCTIONAL DIAGRAM
9600 Digital Mobile C-Arm - Generator Block Diagrams, Test Points, and Signal Waveforms
Test Conditions
OVERLOAD FAULT
TRIP POINT = 1.6 VOLTS In the manual fluoro mode, use
a technique of 50 kV and 1 mA
for the majority of this lab.
Other kV settings will be useful for

PRI.I
observing a change in DC voltages.
Note these unique kV settings on
this worksheet for future reference.
100 mV dc
100 us
The waveforms represent
normal X-ray on conditions
at 50 KV @ 1 ma.
OVER VOLTAGE FAULT
TRIP POINT = 30 VPP (140 KVP)
3
2
P2
TP1
PRI I U1
2 7
R11 3
R12 TAP1
U2 A2J3
2 12
17
5
THESE COMPONENTS ARE COVERED
BY THE BATTERY CHARGER PCB U14
7 14
13
200 mV dc
TP5 100 us
P3
U11 R35 GND

R36
9
8
U7 TP3 U33
SATDET U32
7
27
TP17 3
OVLD CR20
TP16SATF 14
9
OEC-DIASONICS,INC.
54 P4 X-RAY REGULATOR
00-873616- ( )
SATURATION FAULT
TRIP POINT = 8 VOLTS
FAULT PAL OUTPUT TRUTH TABLE

SATDET
TP17 2 V dc
FAULT PAL U2 U7
OUTPUTS
TP16 50 us
PIN 9
OVERVOLTAGE H 9600 GENERATOR
SATURATION H H DRVON Page 1 of 1
2 V dc 96FLT_SS.DS4 8-21-96
OVERLOAD H H 50 us
9600 GENERATOR FAULTS

WORKSHEET
9600 Mobile Digital C-Arm - Generator Block Diagrams, Test Points, and Waveforms
SEE SERVICE MANUAL U30

FOR SWITCH & LED (1C5)
DIAGNOSTIC UTILITIES U36
75 75 MRESET* 12 13 14 6 57
U43 (1B7)
(1B8)
LATCH
P1 CONNECTS TO THE LEFT CONTROL PANEL TP2

P2 CONNECTS TO THE RIGHT CONTROL PANEL +5V TP 3
TECHNIQUE 80C188
P1 & P2 PROCESSOR
PCB
SCH.# 876735
MICROPROCESSOR
U13 U12 U11&16
U6 (2D5) (2C5) (23D) U2 U4
(1C7) KEYPAD KEYPAD A8-14 D A8-14 D
(1C3) (1C1) 24 EMEROFF_HI 4
COLUMN ROW LED A0-7 EPROM A0-7 SEE 24V INTERLOCK PWR/MTR
VFD INPUT OUTPUT LATCHES 25 EMEROFF_LO 3 BLOCK DIAGRAM RELAY PCB
BUFFER SRAM SCH. #875997
LATCH LATCH (1-16) X-RAY_ON
27 X-RAY_LAMP 9
U1
15 SEE X-RAY ON BLOCK DIAGRAM
U7
A0-7 A0-7 (1B2) P1 FOR DETAIL OF X-RAY ON SIGNAL
AD 0-7 U9 RESET* PAL
(1B3) CHIP
CONTROLS & SELECTS
A0-7
DISPLAY U3 X-RAY_LAMP SIGNAL TO WORKSTATION POWER
8 J1-5 INTERCONNECT CABLE
INTERFACE PANEL
(1B2)
MEMORY AND ADDRESSING SEE WORKSTATION
AD O-15 CR1
CONTROL AND
(1B5) P2
COMMUNICATIONS
BLOCK DIAGRAM FOR A
CONTROL CONTINUATION OF THE
16 SECURITY INTERCONNECT CABLE SIGNALS
PANEL TO OPTO ISOLATORS U50 & 51
+5V PROCESSOR 84 X-RAY_SWITCH ON ANALOG INTERFACE PCB
+12V TP8
PCB
P9 P1 J6
TP11 TP 1, 3, SCH. #875601 P4 P10
LS1 (SEE X-RAY ON BLOCK DIAGRAM
(1B3) TP5 12, 13
1 MRESET* 18 17 1 1 FOR DETAILS OF TH ESE CIRCUITS)
28 U14 X-RAY_SWITCH
Q2 U5 1
16 6 5 4 36 EMEROFF_HI 10 9 14 14
(1B3) (1C4) 3 +5V 9 SECURITY FROM HANDSWITCH
TP4 (1D4) EMEROFF_LO 12 11 15 15
U15
Y1 67 80C196 7 13 16 16 X-RAY_SWITCH
WATCHDOG X-RAY_SWITCH 14 2
(1D5) 10MHZ
DS1 BLINKS TIMER FROM FOOTSWITCH
SWITCHES SECURITY 2 1 18 18 10 SECURITY
ON AND OFF
TO INDICATE 23 150MS
VCC X-RAY_LAMP 16 15 17 17
THAT THE P7
MICROPROCESSOR DS1
IS EXECUTING CODE (1A3) +5V TP2 17 18 5 4
5 +12
SEE PAGE 2 FOR +12 VR2 +15
Q1 19 SEE SYSTEM POWER BLOCK DIAGRAM
COMMUNICATION CHASSIS GND 19 19 19 19 -12 -15 5
VR1 FOR DETAILS OF POWER DISTRIBUTION
(1A3) CIRCUITRY
MICROPROCESSOR (1B7)
P8
POWER/SIGNAL
P6 1 3 1 3 P7 1 5 2 4 3 P5 INTERFACE PCB
SCH. #876001 MAINFRAME
MOTHERBOARD
SCH. #875539
FAST STOP
SWITCHES
REFERENCE TO
9600 C-ARM INTERCONNECT DIAGRAM
875500
9600 C-ARM
CPP_TP_1.DS4 6/4/96
USE THIS DIAGRAM

CONTROL PANEL PROCESSOR/
ON SYSTEM SERIAL NUMBERS TECHNIQUE PROCESSOR
XRAY SWITCH 69-0001 TO 69-1000 BLOCK DIAGRAM
U5
P4 P10
(1C4) E3 P9 P1 J5 P2 BUFFER
TP10 2 1 TP3 TP12
80C196 9 10 TECH_TXD_HI 6
11 10 TECH_TXD_HI 7 12 12 TECH_TXD_HI 103 103 TXD_A 20 TP2
TXD_TECH 3 17
RXD 17 U10 9 TECH_TXD_LO 12 TECH_TXD_LO U2 TXD
11 +5V TP 3
TP9 2 1 5 TP4 TP14
(1B7) 14 TECH_RTS_HI 13 14 TECH_RTS_HI 14
RTS_TECH 13 13 TECH_RTS_HI RTS_A 25
CTS
44 13
U10 15 TECH_RTS_LO 16 TECH_RTS_LO U2 15 104 104 5 15 RTS
E2 15
13 U37
TP1 (4A4) TP10 A
TP6 14 TECH_RXD_HI 3 4 TECH_RXD_HI 10 MICROPROCESSOR
15 RXD_A 2
TXD 18 U8 11 RXD_TECH 10 10 TECH_RXD_HI 101 101 18 2
U38
3 19
TECH_RXD_LO 1 2 TECH_RXD_LO 9 U1 RXD
U30
13 (1B7) TP2
TP7 (4A5) TP11 (1C5)
6 TECH_CTS_HI 7 8 TECH_CTS_HI 14
39 7 13 CTS_TECH 11 11 TECH_CTS_HI 102 102 CTS_A 4 4 5 27
RTS U8 TECH_CTS_LO 15 U1 16 U38 CTS BUFFERED
TECH_CTS_LO 5 6
5 ADDRESS BUS
+5V MAINFRAME
MICROPROCESSOR U39
TP8 MOTHERBOARD
CONTROL (4A7) BUFFERED
SCH. #875539
PANEL TP16 DATA BUS
PROCESSOR POWER/SIGNAL
TP 1, 3, PCB INTERFACE PCB IFBTX RXD_D 19 20 44
70 70 RXD 80C188
12, 13 SCH. #876001 U5
SCH. #875601
TP13 (4B3)
RS422 D
SERIAL IFBRX 72 72 TXD_D 18 1 43 TXD
COMMUNICATION
RS-232
DRIVER/ SERIAL
21 22 RECEIVER SWITCHES 1 & 2 OF SW1 COMMUNICATIONS
P3
MUST BE ON TO ENABLE CONTROLLER
S1 SERIAL COMMUNICATIONS
(3B8)
1 8 2 U35 18 TECHNIQUE
2 7 4 (3B6) 16 PROCESSOR
PCB
BUFFER SCH.# 876735
TXD = TRANSMIT DATA

RTS = REQUEST TO SEND
RXD = RECEIVE DATA
CTS = CLEAR TO SEND
U17 U16 IMAGE
P2 FUNCTIONS
(1D8)
PCB
1 9 SCH.#874750
RX
2 19 TX
MICROCONTROLLER 9600 C-ARM

CPP_TP_1.DS4 6/4/96
USE THIS DIAGRAM C-ARM COMMUNICATIONS

ON SYSTEM SERIAL NUMBERS
69-0001 TO 69-1000 BLOCK DIAGRAM
TXD = TRANSMIT DATA

RXD = RECEIVE DATA
CTS = CLEAR TO SEND
TP2
+5V TP 3 U27 P1
(1B5)
U39 U52
(1B3) SD0-7
(4A7) P14 P3
P2 J5 P2 P10 TP11
TP17 (1C7) 9
8 20 19 RXD_B 105 105 MFRXD 20 8 13 MFRXD 28 28 MFRXD 30
RXD 8 U16 10 TXDA 386
MOTHERBOARD
(1B4)
TP18
23 3 4 CTS_B 106 106 MFCTS 21 3 12 MFCTS 26 26 MFCTS 5 29
CTS 6 U16 4 OP0
B TP9 TP12
1 18 TXD_B MFTXD 22 9 MFTXD (1C7) 21 21 MFTXD 11 31
7 107 107 15 13 U15
TXD RXDA
TP19
21 2 5 RTS_B MFRTS 23 2 14 MFRTS 18 18 MFRTS 3 7
RTS 108 108 1 U15 IP0
(1B4)
TECHNIQUE
SERIAL RS-232 MAINFRAME J1 ON INTERCONNECT TP 2&16 TP 7
PROCESSOR DUAL UART
COMMUNICATIONS DRIVER/RECEIVER MOTHERBOARD POWER CABLE +5V TP 1-4
PCB
CONTROLLER SCH. #875539 PANEL
SCH.# 876735 AT COMM PCB
SCH. #872125
1 TP 1&6 TP 9
+12V -12V
1 LEMO CONNECTOR PINS SHOWN AUX INTERFACE PCB

SCH. #876502
C-ARM WORKSTATI0N
REFERENCE TO
REFERENCE TO
9600 WORKSTATION INTERCONNECT DIAGRAM
9600 C-ARM
MAINRAME INTERCONNECT DIAGRAM #876158 For Reference Only Page 3 of 3
#875500
CPP_TP_1.DS4 6/4/96
USE THIS DIAGRAM

WORKSTATION / C-ARM
69-0001 TO 69-1000 COMMUNICATIONS BLOCK DIAGRAM
SEE SERVICE MANUAL U30

FOR SWITCH & LED (1C5)
DIAGNOSTIC UTILITIES U36
75 75 MRESET* 12 13 14 (1B7)6 57
U43
(1B8)
LATCH
P1 CONNECTS TO THE LEFT CONTROL PANEL

+5V
P2 CONNECTS TO THE RIGHT CONTROL PANEL TP6
TECHNIQUE 80C188
P1 & P2 PROCESSOR TP 3, 7,
PCB 8, 9
SCH.# 877742
MICROPROCESSOR
U13 U12 U11&16
U6 (2D5) (2C5) (23D) U2 U4
(1C7) KEYPAD KEYPAD A8-14 D A8-14 D
(1C3) (1C1) 24 EMEROFF_HI 4
COLUMN ROW LED A0-7 EPROM A0-7 SEE 24V INTERLOCK PWR/MTR
VFD INPUT OUTPUT LATCHES 25 EMEROFF_LO 3 BLOCK DIAGRAM RELAY PCB
BUFFER SRAM SCH. #875997
LATCH LATCH (1-16) X-RAY_ON
27 X-RAY_LAMP 9
U1
15 SEE X-RAY ON BLOCK DIAGRAM
U7
A0-7 A0-7 (1B2) P1 FOR DETAIL OF X-RAY ON SIGNAL
AD 0-7 U9 RESET* PAL
(1B3) CHIP
CONTROLS & SELECTS
A0-7
DISPLAY U3 X-RAY_LAMP SIGNAL TO WORKSTATION POWER
8 J1-5 INTERCONNECT CABLE
INTERFACE PANEL
(1B2)
MEMORY AND ADDRESSING SEE WORKSTATION
AD O-15 CR1
CONTROL AND
(1B5) P2
COMMUNICATIONS
BLOCK DIAGRAM FOR A
CONTROL CONTINUATION OF THE
16 SECURITY INTERCONNECT CABLE SIGNALS
PANEL TO OPTO ISOLATORS U50 & 51
+5V PROCESSOR 84 X-RAY_SWITCH ON ANALOG INTERFACE PCB
+12V TP8
PCB
P9 P1 J6
TP11 TP 1, 3, SCH. #875601 P4 P10
LS1 (SEE X-RAY ON BLOCK DIAGRAM
(1B3) TP5 12, 13
1 MRESET* 18 17 1 1 FOR DETAILS OF TH ESE CIRCUITS)
28 U14
Q2 U5 1 X-RAY_SWITCH
16 6 5 4 36 EMEROFF_HI 10 9 14 14
(1B3) (1C4) 3 +5V FROM HANDSWITCH
TP4 9 SECURITY
U15 (1D4) EMEROFF_LO 12 11 15 15
Y1 67 80C196 7 13 16 16 X-RAY_SWITCH
WATCHDOG X-RAY_SWITCH 14 2
DS1 BLINKS (1D5) 10MHZ
TIMER 2 1 18 18 10 SECURITY FROM FOOTSWITCH
ON AND OFF SWITCHES SECURITY
TO INDICATE 23 150MS
VCC X-RAY_LAMP 16 15 17 17
THAT THE P7
MICROPROCESSOR DS1
IS EXECUTING CODE (1A3) +5V TP2 17 18 4
5 5 +12
SEE PAGE 2 FOR +12 VR2 +15 SEE SYSTEM POWER BLOCK DIAGRAM
Q1 19 19
COMMUNICATION CHASSIS GND 19 19 19 -12 -15 5
FOR DETAILS OF POWER DISTRIBUTION
(1A3) VR1
CIRCUITRY
MICROPROCESSOR (1B7)
P8
POWER/SIGNAL
P6 1 3 1 3 P7 1 5 2 4 3 P5 INTERFACE PCB
SCH. #877998 MAINFRAME
MOTHERBOARD
SCH. #875539
FAST STOP
SWITCHES
REFERENCE TO
9600 C-ARM INTERCONNECT DIAGRAM
877972 9600 C-ARM
CPP_TP_2.DS4 6/4/96
USE THIS DIAGRAM CONTROL PANEL PROCESSOR/

XRAY SWITCH
69-1001 TO 69-2000
TECHNIQUE PROCESSOR
BLOCK DIAGRAM
P4 P10
U5 E3 P9 P1 J5 P2 BUFFER
(1C4) TP10 2 1 TP3 TP12 TP32
9 10 TECH_TXD_HI 6 +5V
11 10 TECH_TXD_HI 7 TXD_TECH 12 12 TECH_TXD_HI 103 103 TXD_A 20 TP6
17 5 15 TXD
RXD U10 9 TECH_TXD_LO 11 12 TECH_TXD_LO U2
TP9 2 1 5 TP4 TP13 TP33 TP 3, 7,
80C196 (1B7) 14 TECH_RTS_HI 13 14 TECH_RTS_HI 14 TECH_RTS_HI RTS_A 8, 9
44 13 15 RTS_TECH 13 13 104 104 3 17 25
U10 15 TECH_RTS_LO 16 TECH_RTS_LO U2 RTS
(CTS) E2 15
13 U37
TP6 TP1 TP10 (4A4) TP30 A
14 TECH_RXD_HI 3 4 TECH_RXD_HI 10 MICROPROCESSOR
18 15 11 RXD_TECH 10 10 TECH_RXD_HI 101 101 RXD_A 2 18 1 14 19
TXD U8 2 TECH_RXD_LO 9 U1 RXD
TECH_RXD_LO 1
13 (1B7) U30
TP2 TP11 TP31 (1C5)
TP7 6 TECH_CTS_HI 7 8 TECH_CTS_HI 14
39 7 13 CTS_TECH 11 11 TECH_CTS_HI 102 102 CTS_A 4 2 COM 15 27
(RTS) U8 TECH_CTS_LO 15 U1 16 CTS BUFFERED
TECH_CTS_LO 5 6 SEL
5 ADDRESS BUS
MICROPROCESSOR MAINFRAME 21 U38 U39
MOTHERBOARD 1 (4A7)
+5V CONTROL 20 (4B5) BUFFERED
SCH. #875539
TP8 PANEL TP18 DATA BUS
PROCESSOR POWER/SIGNAL 20 5 18
TP 1, 3, PCB INTERFACE PCB IFBTX RXD_C 19
70 70 80C188
12, 13 SCH. #877998 U5
SCH. #875601 TP38
TP20 (4B3) 2 19 36
RS422 U53 RXD
IFBRX 72 72 TXD_C 18 1 23
SERIAL TP40 C
(4C5) 10 37
COMMUNICATION 7 TXD
RS-232
DRIVER/ 8 PORT
21 22 RECEIVER SEL SERIAL
P3
COMMUNICATIONS
2 S1 CONTROLLER
(3B8)
1 8 2 U35 18 TECHNIQUE
2 7 4 (3B6) 16 PROCESSOR
PCB
BUFFER SCH.# 877742
1 THESE 2 SIGNALS, COM_MODE_0 & COM_MODE_1
TXD = TRANSMIT DATA
GO TO U53 & U38 TO SELECT SERIAL COMMUNICATIONS
FOR C-ARM OR UROVIEW
RXD = RECEIVE DATA
CTS = CLEAR TO SEND
2 SWITCHES 1 & 2 OF SW1 MUST BE ON TO IMAGE
ENABLE SERIAL COMMUNICATIONS U17 U16 FUNCTIONS
P2 (1D8) PCB
SCH.#874750
1 9
RX
2 19 TX
MICROCONTROLLER 9600 C-ARM
CPP_TP_2.DS4 6/4/96
USE THIS DIAGRAM C-ARM COMMUNICATIONS

69-1001 TO 69-2000
BLOCK DIAGRAM
TXD = TRANSMIT DATA

RXD = RECEIVE DATA
CTS = CLEAR TO SEND
+5V
TP6 U27 P1
COM U52 TP 3, 7, (1B5)

U39
SELECT (1B3) 8, 9 SD0-7
(4A7) P14 P3
TP34 P2 J5 TP11
P2 P10
3 TP14 (1C7) 9 386
8 16 U38 20 19 RXD_B 105 105 MFRXD 20 8 13 MFRXD 28 28 MFRXD 30
RXD 8 U16 10 TXDA MOTHERBOARD
(4B5)
TP35
TP15 (1B4)
23 17 4 3 4 CTS_B MFCTS 21 3 12 MFCTS 26 26 MFCTS 5 29
CTS 106 106 6 U16 4 OP0
B TP16 TP12
TP36 1 18 TXD_B MFTXD 22 9 15 MFTXD (1C7) 21 21 MFTXD 11 31
7 107 107 13 U15
TXD RXDA
TP37 TP17
RTS 108 108 1 U15 IP0
(1B4)
RS-232 TECHNIQUE
SERIAL MAINFRAME J1 ON INTERCONNECT TP 2&16 TP 7 DUAL UART
DRIVER/RECEIVER PROCESSOR
COMMUNICATIONS MOTHERBOARD POWER CABLE +5V TP 1-4
PCB
SCH. #872125
1 TP 1&6 TP 9
+12V -12V
1 LEMO CONNECTOR PINS SHOWN

AUX INTERFACE PCB
SCH. #876502
C-ARM WORKSTATI0N
REFERENCE TO REFERENCE TO
MAINRAME INTERCONNECT DIAGRAM
#877972
9600 WORKSTATION INTERCONNECT DIAGRAM 9600 C-ARM
#877970
CPP_TP_2.DS4 6/4/96
USE THIS DIAGRAM

WORKSTATION / C-ARM
69-1001 AND UP COMMUNICATIONS BLOCK DIAGRAM
J5 P2
J1 U30
SEE SERVICE MANUAL (1C5)
FOR SWITCH & LED TO MRESET* 12 U36
90 75 75 13 14 6 57
DIAGNOSTIC UTILITIES IMAGE FUNCTION PCB U43 (1B7)
P2-90
(1B8)
LATCH
TP2
+5V TP 3
TECHNIQUE 80C188
P1 CONNECTS TO THE LEFT CONTROL PANEL
PROCESSOR
P2 CONNECTS TO THE RIGHT CONTROL PANEL
PCB
P1 & P2 SCH.# 877742
POWER/SIGNAL MICROPROCESSOR
INTERFACE PCB
J2 P5 SCH. #877998
P4 P10 P9 P5
U13
(1C7) PWR/MTR
CONTROL 18 17 MRESET* 1 1
RELAY PCB
PANEL P2
VFD SCH. #875997
PROCESSOR
BUFFER 10 9 EMEROFF_HI 14 18 24 EMEROFF_HI 4
PCB
SCH. #878486 SEE 24V INTERLOCK
12 11 EMEROFF_LO 15 15 25 EMEROFF_LO 3 BLOCK DIAGRAM
U5&6 27 X-RAY_LAMP* 9 X-RAY_ON
(2D3) U1
CR1 15
16 15 X-RAY_LAMP* 17 16
LED SEE X-RAY ON
14 (1B5) P1 BLOCK DIAGRAMFOR DETAILS
U9 U10 LATCHES 14 13 X-RAY_SWITCH 16
A8-14 D A8-14 D (1-16) OF X-RAY ON SIGNAL
(1C3) (1C1) CONTROLS & 2 1 SECURITY 18 17
A0-7 EPROM A0-7 DISPLAY
SRAM U7 INTERFACE X-RAY_LAMP*
(2C5) SIGNAL TO POWER INTERCONNECT
KEYPAD 8 WORKSTATION J1-5 PANEL CABLE
U8 ROW
A0-7 A0-7 (1B2) OUTPUT
AD 0-7 U12 LATCH SEE WORKSTATION CONTROL AND
(1B3) RESET* PAL CHIP COMMUNICATIONS BLOCK DIAGRAM FOR A
SELECTS J1 P4
CONTINUATION OF THE
A0-7 J6 INTERCONNECT CABLE SIGNALS
U1 U14
(2D5) +5V
(1B2) 16 SECURITY
MEMORY AND ADDRESSING KEYPAD R1 TO OPTO ISOLATORS U50 & 51
AD O-15 P10 84 X-RAY_SWITCH ON ANALOG INTERFACE PCB
COLUMN
INPUT
LATCH 5
1 X-RAY_SWITCH
CR1
4 SECURITY 9 SECURITY FROM HANDSWITCH
+5V P3 J3
TP3 CR2 2 X-RAY_SWITCH
2 X-RAY_SWITCH XRAY SWITCH
10 SECURITY FROM FOOTSWITCH
TP6 TP 1, 9, 1
TP5 7, 4 +5V (SEE X-RAY ON BLOCK DIAGRAM
1 MRESET* 31 31 9 9 P7 FOR DETAILS OF TH ESE CIRCUITS)
U11 U3
16 6 5 4 36 3 X-RAY_LAMP
(1C4) 3 +5V +12 3
TP8 U2 (1D4) VR2 +15
SEE SYSTEM POWER BLOCK DIAGRAM
Y1 67 80C196 7 P8 -12 -15 6 FOR DETAILS OF POWER DISTRIBUTION
WATCHDOG S2 VR1
(1D5) 10MHZ +12V
DS1 BLINKS TIMER EMEROFF_LO 3 (1B7) P5
ON AND OFF
TO INDICATE 23 150MS 20 20 LS1 1
THAT THE
VCC (1B3)
28 FAST STOP
MICROPROCESSOR DS1 Q2 3 SWITCHES MAINFRAME
IS EXECUTING CODE (1A3) (1B3) MOTHERBOARD
SEE PAGE 2 FOR EMEROFF_HI 1 SCH. #878396
Q1 19
COMMUNICATION CONTROL PANEL
(1A3)
MICROPROCESSOR
CIRCUITRY PROCESSOR I/O PCB COLUMN I/O PCB P9 S1 9600 C-ARM
SCH. #878489 SCH. #878492
CPP_TP_3.DS4 6/4/96
USE THIS DIAGRAM
69-2001 AND HIGHER &
REFERENCE TO
9600 C-ARM INTERCONNECT DIAGRAM 62-0001 AND HIGHER TECHNIQUE PROCESSOR
878376 BLOCK DIAGRAM
U11 E3 J1 P4 P3 J3 P4 P10
P9 P5 J5 P2 BUFFER
(1C4) TP12 2 1 TP3 TP12 TP32
TECH_TXD_HI +5V
11 10 TECH_TXD_HI 3 3 5 5 9 10 6 12 TXD_A
TXD_TECH 12 103 103 20 TP6
RXD
17 U4 9 TECH_TXD_LO 4 U2 7 TXD_TECH 5 15 TXD
4 6 6 11 12 TECH_TXD_LO
TP11 2 1 5 TP4 TP13 TP33 TP 3, 7,
80C196 (1B7) TECH_RTS_HI
14 TECH_RTS_HI 1 1 7 7 13 14 14 RTS_A 8, 9
44 13 U2 15 RTS_TECH 13 13 RTS_TECH 104 104 3 17 25
(CTS) U4 15 TECH_RTS_LO 21 21 TECH_RTS_LO RTS
E2 8 8 15 16
13 U37
TP1 TP10 TP30 A
TP13 14 TECH_RXD_HI 11 11 2 2 3 4 TECH_RXD_HI (4A4) MICROPROCESSOR
10 2
18 15 11 RXD_TECH 10 10 RXD_TECH RXD_A 1 14 19
TXD U15 U1 101 101 18
TECH_RXD_LO 30 30 1 1 1 2 TECH_RXD_LO RXD
9
13 U30
(1B7) TP2 TP11 TP31 (1C5)
TP10 6 TECH_CTS_HI 14 14 4 4 7 8 TECH_CTS_HI 14 4
39 7 U15 13 CTS_TECH 11 11 CTS_TECH 102 102 CTS_A 2 COM 15 27
(RTS) U1 16
TECH_CTS_LO 13 13 3 3 5 6 TECH_CTS_LO 15 SEL CTS BUFFERED
5 ADDRESS BUS
MICROPROCESSOR MAINFRAME 21 U38
MOTHERBOARD U39
1
+5V SCH. #878396 20 (4B5) (4A7) BUFFERED
TP3 CONTROL CONTROL DATA BUS
PANEL PANEL TP18 20 5 18
TP 1, 4, PROCESSOR PROCESSOR COLUMN I/O POWER/SIGNAL IFBTX RXD_C
70 70 19 80C188
7, 9 PCB I/O PCB PCB INTERFACE PCB
U5
SCH. #878486 SCH. #878489 SCH. #878492 SCH. #877998 TP38
TP20 (4B3) 2 19 36
U53 RXD
IFBRX 72 72 TXD_C 18 1 23 TP40 C
(4C5) 10 37
7 TXD
RS-232
DRIVER/ 8 PORT
71 73 RECEIVER SEL SERIAL
J1
COMMUNICATIONS
P2 71 73
CONTROLLER
2 S1
IMAGE
FUNCTIONS U17 (3B8)
PCB U16 1 8 2 U35 18 TECHNIQUE
TXD = TRANSMIT DATA (1D8) TP6
RTS = REQUEST TO SEND SCH.#878398 2 7 4 (3B6) 16 PROCESSOR
RXD = RECEIVE DATA 19 PCB
CTS = CLEAR TO SEND TX SCH.# 877742
TP5 BUFFER
9
RX
MICROCONTROLLER
1
THESE 2 SIGNALS, COM_MODE_0 & COM_MODE_1
GO TO U53 & U38 TO SELECT SERIAL COMMUNICATIONS
FOR C-ARM OR UROVIEW
2 SWITCHES 1 & 2 OF SW1 MUST BE ON TO

ENABLE SERIAL COMMUNICATIONS
9600 C-ARM
USE THIS DIAGRAM CPP_TP_3.DS4 6/4/96
69-2001 AND HIGHER & C-ARM COMMUNICATIONS
62-0001 AND HIGHER BLOCK DIAGRAM
TXD = TRANSMIT DATA

RXD = RECEIVE DATA
CTS = CLEAR TO SEND
+5V
TP6 U27 P1
COM U52 TP 3, 7, (1B5)

U39
SELECT (1B3) 8, 9 SD0-7
(4A7) P14 P3
TP34 P2 J5 TP11
P2 P10
3 TP14 (1C7) 9
8 16 U38 20 19 RXD_B 105 105 MFRXD 20 8 13 MFRXD 28 28 MFRXD 30
RXD 8 U16 10 TXDA 386
TP35
(4B5) MOTHERBOARD
TP15 (1B4)
23 17 4 3 4 CTS_B MFCTS 21 3 12 MFCTS 26 26 MFCTS 5 29
CTS 106 106 6 U16 4 OP0
B TP16 TP12
TP36 1 18 TXD_B MFTXD 22 9 15 MFTXD (1C7) 21 21 MFTXD 11 31
7 107 107 13 U15
TXD RXDA
TP37 TP17
RTS 108 108 1 U15 IP0
(1B4)
RS-232 TECHNIQUE
SERIAL MAINFRAME J1 ON INTERCONNECT TP 2&16 TP 7
DRIVER/RECEIVER PROCESSOR DUAL UART
COMMUNICATIONS MOTHERBOARD POWER CABLE +5V
PCB TP 1-4
SCH. #872125
1 TP 1&6 TP 9
+12V -12V
1 LEMO CONNECTOR PINS SHOWN

AUX INTERFACE PCB
SCH. #876502
C-ARM WORKSTATI0N
MAINRAME INTERCONNECT DIAGRAM
#878376
9600 WORKSTATION INTERCONNECT DIAGRAM
#877970
9600 C-ARM
USE THIS DIAGRAM
ON SYSTEM SERIAL NUMBERS CPP_TP_3.DS4 6/4/96
62-0001 AND HIGHER WORKSTATION / C-ARM
COMMUNICATIONS BLOCK DIAGRAM
TEST POINTS IN PARENTHESES
INDICATE NEWER PCB
SCH. # 878486
TP1
TP1
RXD_TECH
2VDC
.5ms
RXD
TP 10 TP3
(TP 12)
.2ms
2VDC 10MHZ.
POWER/SIGNAL INTERFACE PCB CLOCK
SCH. # 877998 TP4
ASM. # 878000 TP5
RESET*
TP3 TP4
TXD_TECH TP6
TXD
TP 6
2VDC TP3 (TP 13) TP7
.5ms
TP2 .2ms
2VDC CONTROL PANEL PROCESSOR PCB
SCH. # 875601
TP1
ASM. # 875603
TP9
TP10
MRESET* RTS
TP 11
2VDC
CTS_TECH 1S
TP11
CTS_TECH at TP2 CTS
MRESET*
and
RTS_TECH at TP4 RESET*
TP 5 TP12
RTS_TECH 2VDC 2VDC
1S 1S
DS1
TP13
RTS at TP 7 (TP 10)
and
CTS at TP 9 (TP 11)
2VDC
5S
10 MHZ.
CLOCK
TP 4
2VDC 9600 C-ARM

20MS COMMUNICATION SIGNALS For Reference Only Page 1 of 3
POWER SIGNAL INTERFACE PCB CP_TP_SS.DS4 4/23/96
AND
CONTROL PANEL PROCESSOR
TECHNIQUE PROCESSOR
SIGNAL SHEET
TEST POINTS IN COMMUNICATION SIGNALS

PARENTHESES
TECHNIQUE PROCESSOR TO CONTROL PANEL PROCESSOR
INDICATE OLDER PCB AND
SCH. #876735 TECHNIQUE PROCESSOR TO IMAGE FUNCTIONS PCP
TXD_A
TP 12
1VDC
.1ms
TXD_A
TP 32 P1 P2
(TP 12)
TP9
1VDC
.100ms
TP3
RTS_A / TP13
RTS_A at TP 13
7.3728MHZ. CLOCK TP31 and
TP11 CTS_A at TP 11
12 TP33 TP30 CTS_A / TP11
TP12
TP32 TP13 500ms
TP10 1VDC
RTS_A
TP 33
U36
(TP 14)
500ms
1VDC
TECHNIQUE PROCESSOR PCB RXD_A

SCH. # 877742 TP 10
ASM.# 877744 1VDC
500ms
RXD_A
TP 30
(TP 10)
TP20
500ms TP6 MSD LSD TP18
TP8
1VDC +5V
TP7
U2 U1 S2
RESET U36 PIN 12
7.3728MHZ.
CLOCK
CTS_A
TP 31
(TP 11)
500ms
1VDC
9600 C-ARM
CP_TP_SS.DS4 4/23/96

TP20 - TXD_C TP18 - RXD_C TECHNIQUE PROCESSOR
.2ms 5VDC .2ms 5VDC SIGNAL SHEET
TEST POINTS IN
PARENTHESES
COMMUNICATION SIGNALS INDICATE OLDER PCB
TECHNIQUE PROCESSOR TO WORKSTATION
SCH. #876735
RXD_B
TP 14
(TP 17)
RXD_B .2ms
TP 34 P1 P2 5VDC
.2ms TP14
2VDC TP16
TP9
TP17
TP3 TP15
7.3728MHZ. CLOCK
12
U36
TXD_B TXD_B
TP 36 TP 16
.2ms (TP 9)
2VDC .2ms
5VDC
TECHNIQUE PROCESSOR PCB

SCH. # 877742
ASM.# 877744
TP34
TP35
TP36
TP37
TP6 MSD LSD
TP8 +5V
TP7
RTS_B U2 U1 S2 CTS _B
RTS_B at TP 37 RESET
and CTS_B at TP 15 (TP 18)
CTS_B at TP 35 and
RTS_B at TP 17 (TP 19)
CTS_B 10VDC
10 S
2VDC 10S RTS_B
9600 C-ARM
CP_TP_SS.DS4 4/23/96

TECHNIQUE PROCESSOR
SIGNAL SHEET
(3B5) DIAGNOSTIC REFER TO THE SERVICE MANUAL FOR A LISTING
ADDRESS MEMORY
14.7456 MH Y3 (1D5)
DECODING GALS (SHEET 2 OF SCH.)
LEDS
U1 & U2 0 0 1 1
OF THE CODES DISPLAYED ON THE BOOT/DIAGNOSTIC LEDS
U44-CPU (1A6) U14-BOOTPROM

RESET U23-28 BOOT CODE FOR
ADDRESS S1 2 RESET TO PIOS ON ANALOG INTERFACE PCB
S2 WATCHDOG U45-I/O D(1D7) MICROPROCESSOR (3B8)
LATCHES 1. COM SEL
(1D3) TIMER 24
1.2 SEC (1B2-1D2) U46-BUS (1B6) U16-19-SRAM 2. COM SEL
U34 (1D4) MICROPROCESSOR 3. FDD OSC
MRESET* TO IMAGE FUNCTION PCB AND
U47-MEMORY (1A7) MEMORY 4. FDD OSC 3
U50 CONTROL PANEL PROCESSOR PCB
30 9600
BIDIRECTIONAL
A U15-OPTION PROM BUFFER ALL ON
16 TRANSCEIVER
4 2 1 57 CODE FOR SOLID U35
STATE DRIVE
2
U36 (1B3) (3B7) E1
RESET U20-EEPROM JUMPERS
6 CAL DATA 9600
EVENT DATA NOT USED
12 13 14 80C188 SERIAL NUMBER (3B7)
MRESET* MICRO
18 PROCESSOR
3
REAL U30
TIME (1C5) SOLID STATE
CLOCK DISK DRIVE
U29 U13 (3B5)
(1B4)
SERIAL
COMMUNICATIONS BI-DIRECTION
CONTROLLER TRANSCEIVER
U39 U49 (3B4)
REAL TIME CLOCK
INTERRUPT (4B7)
CONTROLLER
SOLID STATE DRIVE
U51
SEE CONTOL PANEL PROCESSOR/ FLOPPY DISK CONTROLLER
(1C6)
TECHNIQUE PROCESSOR U48 (NOT USED)
COMMUNICATIONS BLOCK DIAGRAM
FOR COMMUNICATION DETAILS
BUFFER
U40 (5C3)
L R
SEQUENCER AMUXSEL 0-3
DUAL PORT BUFFER RAM
RAM A U11(5D3) U41 (5D2)
U31
TECHNIQUE PROCESSOR PCB (5D7) D ADDRESSING

COUNTERS
SCH. #876735 OR #877742 U42, 22, 3, SAMPLE
12,21,32
( 5B6-5C4)
ASSY. # 877744 ASSY. #876737
+5V
TP6 +5V A
RESET* PAL
TP 3, 7, U4
8, 9 TP3 TP2 A/D_D0-7
P1 P2 P1 (Serial Numbers 69-0001 to 69-2000)

J2 J5 P5 (Serial Numbers 69-2001 and higher &
62-0001 and higher)
TO CONTROL PANEL
9600 C-ARM
P2 TO POWER PANEL/ For Reference Only Page 1 of 2
-15
MAINFRAME MOTHERBOARD
-12
VR1 INTERCONNECT CABLE
P3 TP_AIBK2.DS4 6/4/96
+15 +12 (CARD RACK BACKPLANE) TO IMAGE SYSTEM
VR2
SCH. #875539 OR #878396 P4
HIGH VOLTAGE/SIGNAL CABLE
TECHNIQUE PROCESSOR/
2
TO P3 ON
X-RAY REGULATOR PCB
ANALOG INTERFACE
2 2 2
2 2 BLOCK DIAGRAM
1 1 MAINFRAME MOTHERBOARD 1 1 1 1
REFER TO THE FOLLOWING
(CARD RACK BACKPLANE) 4 FUNCTIONAL SCHEMATICS FOR
SCH. #875539 OR #878396 DETAILS OF THE CIRCUITRY USING THE PIOS.
U22
J3 J6
X-RAY ON / DISABLE
P1 P2 9
IMAGE PATH (SHEET 2)
ABS LOOP These transistors switch the following relays:
TARGET (not used) U38 Q3 - "Stator Run" - K1 on Power/Motor Relay PCB

D/A SECTION
X-RAY ON / DISABLE Q4 - "Pre-charge" - K1 on Generator Controller Asy.
D/A MA CAL (not used)
PRE-CHARGE Q5 - "Contact" - K2 on Generator Controller Asy.
CONV. TP19 STATOR RELAY / STATOR SENSE
U31 U33
25 KVPCONT 6 7 IMAGE INTENSIFIER CONTROLS Q6 - "II On" - K7 on Power/Motor Relay PCB
(P4) THE "S" NUMBERS ARE CHIP INPUT
-10 VOLT -10V (1B6) TP18 7 Q7 - "Stator Start" - K2 on Power/Motor Relay PCB
TP33 REFERENCE NUMBERS. SOFTWARE U27
REFERENCE FOR 23 MACONT 2 1 MONITORS THESE INPUTS AS CHANNELS 0-15.
D/A CONVERTERS (P4) Q8 - not used
U33 THESE CAN BE SEEN IN THE STATUS MODE, X-RAY ON / DISABLE
VR1,U30, Q14 EVENT HISTORY, AND MAY BE SEEN AS A:D STATOR RELAY / STATOR SENSE Q10 - not used
(2D1) 5 CHANNEL ERRORS DURING BOOT-UP. REFER GENERATOR INTERLOCK
SPARE
TP10 TO THE C-ARM SOFTWARE SECTION OF THE GENERATOR KV CIRCUIT FAULTS
U28 SERVICE MANUAL FOR DETAILS. BATTERY CHARGER
D/A 6 FILCNTRL 2 1 (P4)
CONV. TP13
U18 25 CAM_GAIN 6 7 (P3)
(1B6) U29 5 THE OUTPUTS OF U31 AND U18 ARE CURRENT SOURCES.
AMUXSEL 0-3
U33, 28, 29 ARE CURRENT TO VOLTAGE CONVERTERS.
CAM_BLK (not used)
6 THERE ARE 16 A/D CHANNELS, BUT ONLY 10 ARE BEING USED.

8 HVDRVB THE RANGE OF THE VOLTAGE INPUTS IS 0-10 VOLTS.
(P4)
U40 11 FILDRVA
CTC SECTION U12-CTC
(1A5)
(P4) REFER TO THE FOLLOWING FUNCTIONAL SCHEMATICS
U15-FF 3 40KHZ (P4) FOR DETAILS OF THE SIGNAL CIRCUITRY:
U16 7
U17-PAL KVPMEAS (KVP MEASURED)
6 HVDRVA (P4) KVP BLOCK
U42
(1A5-8) 11 FILDRVB A0 A3
(1A5) (P4)
MASNS (MA MEASURED)
CH0 A/D SECTION MA BLOCK
(P4) KVPMEAS
S1
6 FILSNS (FILAMENT B+ VOLTAGE SENSE)
TP28 (P4) CH1 MAMEAS
3 VIDEOSTABLE S2 MA BLOCK
U22
(P2) (P4) CH2
A TP27 FILSNS 16 A/D A/D_D0-7
S3 SAMPLE & VLI (VIDEO LEVEL INDICATOR)
40 STORE CHANNEL CONV.
PIO (P2) (P3) CH3 VLI HOLD ABS LOOP
S4 ANALOG U7
(2D7) U8
B J2 MUX
(P3) CH4 HOUSTEMP (1D5) HOUSETEMP ( X-RAY TUBE HOUSING TEMPERATURE)
RESET S5 U3 (1D5) STATOR RELAY / STATOR SENSE
ON SOLDER SIDE OF PCB
REFER TO NOTE CH6 (1D6)
2 USED ONLY DURING CALIBRATION (P3) CAMROT
ON PAGE 1 S7 CAMROT (CAMERA ROTATION)
C J1 CH8 SECTAP CCD CAMERA MOTOR DRIVE IRIS/ROTATION MOTORS
(P4)
S9
(P4) CH9 LINE_SNS SAMPLE* SECTAPV (SECONDARY TAP VOLTAGE)
TO IMAGE S10 GENERATOR KV CIRCUIT FAULTS
U38 A U26 FUNCTION PCB CH10
(P3) (P4) CHGR_I
U36 S11 LINE_SNS (LINE VOLTAGE SENSE)
PIO Q3-8 & 10 (P4) CH11 200V_SNS BATTERY CHARGER
(2D7) (2B2) S12
BUFFER (P2&P4)
B CHGR_I (BATTERY CHARGER CURRENT)
9 BATTERY CHARGER
PIO SECTION U43
U45
4 U50, 51, & 52 THE FOLLOWING SIGNALS TO THE OPTOCOUPLERS ORIGINATE FROM THE 200V_SNS (BATTERY B+ AND BATTERY CHARGER VOLTAGE SENSE)
OPTOCOUPLERS 8 8 CONTROL PANEL X-RAY SWITCH, FOOTSWITCH, AND HANDSWITCH: BATTERY CHARGER
C (2C5)
(2C8) XRAY SWITCH, SECURITY, FLUORO ONLY, BOOST, & L/R (SAVE). PRE-CHARGE
U27 A (P4)
LINE DRIVERS
PIO
(P4)
9600 C-ARM
(2B7)
Page 2 of 2
B INTERLOCK KEEP-ALIVE CPUINTLK
(P2) ANALOG INTERFACE PCB For Reference Only
Q1, Q2, K1,CR1, CR2 (2B4)
+5V +12V +15V TP 1, 2, SCH. #876738 TP_AIBK2.DS4 6/4/96
BUFFER DS1 TP25 TP23 21, 22
TP24
C U46 (2B7) (P4) TECHNIQUE PROCESSOR/
U19, U24 STATOR SENSE (P2) ANALOG INTERFACE
(2A8-7)
BLOCK DIAGRAM
2 DURING BOOT, THE TECHNIQUE PROCESSOR INITIATES THE 10mS KEEP ALIVE PULSES.
RELAY K1 ENERGIZES, ILLUMINATING DS1. THIS IS THE START OF THE INTERLOCK CIRCUIT. GENERATOR DRIVER PCB
THE CONTROL PANEL DISPLAYS 18 ARROWS AT THIS TIME (SEE NOTE 3) SCH. #877461
ANALOG INTERFACE PCB DATA BUS +24V TO K1 CONTROL PANEL
TO/FROM FIL SELECT RELAY +24V TO K1 & K2
SCH. #876738 +15V +24 V TO K2 PROCESSOR PCB
TECHNIQUE SEE MA BLOCK PRECHARGE RELAYS
SEE KV BLOCK SEE PRE CHARGE BLOCK SCH. #875601
PROCESSOR DIAGRAM DIAGRAM
DIAGRAM S2
K1
P7-3 EMEROF_LO
1 7 2 N.C.
25
PULSE DETECTOR P7-1
2 U27 P4 -3
DS1 Q1 & Q2
(2B7) A2J4-3
2 LOW (1D8) 4
(2B1)
6 PIO P6-3
(2A5) P2-1
U45 INTLK X-RAY REGULATOR PCB
13 7 11
(2A4) /244 SCH. #877458 S1
P6-1 EMEROF_HI
(2C5) BATTERY CHARGER PCB N.C.
CPU INTERLOCK
SCH. #876643
Q1
TP1 TP2 TP21 TP22 OR #877995
+5V R5 REFERENCE TO MAINFRAME
J3-3 4
A1J3-3 INTERCONNECT DIAGRAM,
1
(1A8) +24V SCH. #875500 OR #877972
(2B8) R16
(1C8) TP5
TP24 TP25 TP23
4 GND
+5V +12V +15V
P2-107 P2-35 P3-16 P2-1 P4-12 P4-10
J6-107 J6-35 P4-10 P1-1 P10-11 P10-9

INTLK
MOTHER BOARD P1-15 P9-15
SCH. #875539
EMERGENCY_OFF_B P1-14 P9-14
CB1
2 AMP
120V_PH1_SWITCHED (1C5) P5-1
P2-19 P2-25 P2-24
CB7
+24V TO CCD CAMERA 3 PS2
3 AMP
5
P5 P5-4
(1C6) LF2 +24VDC
P1-2 P1-3 P1-4 TP1
EMERGENCY_OFF_A 1
(1D7) P7-7 P6-20
+24V_IN
P2-6
TP4
(1B7) +24V_INTERLOCK P7-1 P6-19 CB5
TP3 PS1
5 AMP
P7-12 P6-10 P2-4
+15V +15V
(1C8) K4
(1C6) (1A5)
11 CB5
10 11 13 5 AMP
7
6 9 6 P7-6 P6-24 120VAC_PH1
C7 6 5 POWER SIGNAL
CR11 4 5 (1A5) USE THIS DIAGRAM ON
4 8 INTERFACE PCB
+ 8
3
2 SYSTEM SERIAL NUMBERS
SCH. #876001
1
4 69-0001 TO 69-2000
12V 1 4 OR #877998
CR10 12V P12-4
16 K8 CR9 12 K9
CR4 12V TO 8 CR7
(1C7) (1D7) K3 12V
R17 1 ALL RELAYS SHOWN IN THE DE-ENERGIZED CONDITION
MOMENTARY 1
R13 K10 KEY_PWR (+12VDC)
CLOSURE
TO LATCH K9 R9 (1B7) P1-14 120VAC 9600 C-ARM
SEE THE FOLLOWING DIAGRAMS: For Reference Only Page 1 of 2
TP2 E5
POWER MOTOR RELAY PCB 1
GND 1 2 SYSTEM POWER SYSTEM POWER
SCH. 875997 (1C6) INTRLK.DS4 6/4/96
KEYPOWER C-ARM POWER
CONTROL PANEL DISPLAY GENERATOR INTERLOCK

1 WITH E5 INSTALLED, AC IS PROVIDED TO THE ROTATION AND ELEVATION M OTORS VIA K3. (SEE LIFT & ROTATION MOTOR BLOCK) 3 BLOCK DIAGRAM
THE 24V INTERLOCK CIRCUIT WILL NOT COMPLETE AND THE CONTROL PANEL WILL DISPLAY 18 ARROWS (SEE NOTE 3)
2 DURING BOOT, THE TECHNIQUE PROCESSOR INITIATES THE 10mS KEEP ALIVE PULSES.
RELAY K1 ENERGIZES, ILLUMINATING DS1. THIS IS THE START OF THE INTERLOCK CIRCUIT. GENERATOR DRIVER PCB
THE CONTROL PANEL DISPLAYS 18 ARROWS AT THIS TIME (SEE NOTE 3) SCH. #877461
ANALOG INTERFACE PCB DATA BUS +24V TO K1 COLUMN I/O PCB
SCH. #876738 TO/FROM FIL SELECT RELAY +24V TO K1 & K2
+15V +24 V TO K2 SCH. #878492
TECHNIQUE SEE MA BLOCK PRECHARGE RELAYS
SEE KV BLOCK SEE PRE CHARGE BLOCK
PROCESSOR DIAGRAM DIAGRAM
DIAGRAM S2
K1
P8-3 EMEROF_LO
1 7 2 N.C.
25
PULSE DETECTOR P8-1
2 U27 P4 -3
DS1 Q1 & Q2
(2B7) A2J4-3
2 LOW (1D8) 4
(2B1)
6 PIO P9-3
(2A5) P2-1
U45 INTLK X-RAY REGULATOR PCB
13 7 11
(2A4) /244 SCH. #877458 S1
P9-1 EMEROF_HI
(2C5) BATTERY CHARGER PCB N.C.
CPU INTERLOCK
SCH. #877995
Q1
TP1 TP2 TP21 TP22
+5V R5 REFERENCE TO MAINFRAME
J3-3 4
A1J3-3 INTERCONNECT DIAGRAM,
1
(1A8) +24V #878376
(2B8) R16
(1C8) TP5
TP24 TP25 TP23
4 GND
+5V +12V +15V
P2-107 P2-35 P3-16 P2-1 P4-12 P4-10
J6-107 J6-35 P4-30 P1-1 P10-11 P10-9

INTLK
MOTHER BOARD P5-15 P9-15
SCH. #878396
EMERGENCY_OFF_B P5-18 P9-14
CB1
2 AMP
120V_PH1_SWITCHED (1C5) P5-1
P2-19 P2-25 P2-24
CB7
+24V TO CCD CAMERA 3 PS2
3 AMP
5
P5 P5-4
(1C6) LF2 +24VDC
P1-2 P1-3 P1-4 TP1
EMERGENCY_OFF_A 1
(1D7) P7-7 P6-20
+24V_IN
P2-6
TP4
(1B7) +24V_INTERLOCK P7-1 P6-19 CB5
TP3 PS1
5 AMP
P7-12 P6-10 P2-4
+15V +15V
(1C8) K4
(1C6) (1A5)
11 CB5
10 11 13 5 AMP
7
6 9 6 P7-6 P6-24 120VAC_PH1
C7 6 5 POWER SIGNAL
CR11 4 5 (1A5) USE THIS DIAGRAM ON
4 8 INTERFACE PCB
+ 8
3
SCH. #877998
1
4 69-2001 AND HIGHER AND
1
CR10 12V 12V 4 P12-4 62-0001 AND HIGHER
16 K8 CR9 12 K9
CR4 12V TO 8 CR7
(1C7) (1D7) K3 12V
R17 1 ALL RELAYS SHOWN IN THE DE-ENERGIZED CONDITION
MOMENTARY 1
R13 K10 KEY_PWR (+12VDC)
CLOSURE
TO LATCH K9 R9 (1B7) P1-14 120VAC 9600 C-ARM
SEE THE FOLLOWING DIAGRAMS: For Reference Only Page 2 of 2
TP2 E5
POWER MOTOR RELAY PCB 1
GND 1 2 SYSTEM POWER SYSTEM POWER
SCH. 875997 (1C6) INTRLK.DS4 6/4/96
KEYPOWER C-ARM POWER
CONTROL PANEL DISPLAY GENERATOR INTERLOCK

1 WITH E5 INSTALLED, AC IS PROVIDED TO THE ROTATION AND ELEVATION M OTORS VIA K3. (SEE LIFT & ROTATION MOTOR BLOCK) 3 BLOCK DIAGRAM
THE 24V INTERLOCK CIRCUIT WILL NOT COMPLETE AND THE CONTROL PANEL WILL DISPLAY 18 ARROWS (SEE NOTE 3)
9600 Mobile Digital C-Arm - Workstation Block Diagrams, Test Points, and Waveforms
1N 1Q 1P 1K 1H Phase shift without Camera
1 V dc 1 V dc 1 V dc 1 V dc 1 V dc
10 us 10 us 10 us 100 ns 10 ns
1F TTL Low without Camera
1O
TTL Low = 60 Hz
1S 1R 1M TTL High = 50 Hz
15 10
(See Note 2 on Sheet 1) U39
2 7
1T
U40
TTL High = Camera Sync Present 2
TTL Low = No Camera Sync Present
Stays
Low 13 U41
U28
2 6
1 V dc
20 us
1 V dc 1 V dc 1 V dc U29 U36
2 ms 10 us 5 us
19
C89 1E
7 9 4
U43
VCO
1L 1J 1I
TP33
With Camera Sync Present Camera Sync Present
TTL High = Genlock Enabled TTL Low
Without Camera Sync Present Camera Sync Not Present
TTL Low = Genlock Disabled 60Hz = 25.8MHz; 50Hz = 25.6MHz
14 13
U44
+5VA 3
TP26
5 TP23
TP30
U6 +5VR TP38 DS1
AGND
DGND
TP25 +5V 9
TP27 U32 U38 U45 1 V dc
TP19 TP28 5
-12V TP24 +12V DS2 20 us
-5V
1 V dc 1G
20 ns With Camera
2.5 VDC (Approximately)
Without Camera
0 VDC (Approximately)
VIDEO SWITCHING PCB
1A TTL High without Camera 1B TTL Low without Camera 1C TTL Low without Camera 1D TTL Low without Camera
Waveforms aquired
with and without Camera
sync as noted.
9600 C-ARM
Stays GEN_LOK1.DS4 6/19/96

Low
9600 WORKSTATION "GEN-LOCK"

1 V dc 1 V dc 1 V dc 1 V dc
20 us
BLOCK DIAGRAM / WORKSHEET
10 us 5 us 10 us
BEGINNING OF INTERLOCK
TP1
GND
U27-25
2 V dc
10 ms 7 6 2 1
19 1 K1 GND
12
TP21
7
20 2
P1
Q1 DS1
CR8
TP4 TP1 TP8
P7
6
1
U27-11
Q2
TP2
K7
TP9
2 V dc
10 ms
CR11
CR10
TP3
TP4 R17
P2
K8
+24V INTERLOCK TO BATTERY CHARGER PCB
C7
CR9
R13
CR4 U27-11 1R16
K9
4
U27-25 U27
INTERLOCK COMPLETE SIGNAL 11
CR7 2 V dc
10 ms
K4
K10
25
TP3
E5
R9
U27-25
7
10 V dc
10 ms INTERLOCK HOLDIN SIGNAL
13
U45
MOMENTARY CLOSURE OF K8 LATCHES K9
K8-6
( RISING EDGE = 15V VIA FAST STOP SWITCHES
FALLING EDGE = K9 LATCHED )
CPU INTERLOCK FROM ANALOG SUPPORT PCB

TP3
15V = INTERLOCK OK TP3
10 V dc
10 ms
ASSY 00-875999- ( )
POWER/MOTOR RELAY PCB

K8-6
10 V dc
10 ms GND
TP22
P1
TP2
GND
TP4
10 V dc
100 ms
9600 C-ARM
K8-6
GINTLKSS.DS4 6/4/96
10 V dc
9600 GENERATOR INTERLOCK
100 ms
SIGNAL SHEET
MOMENTARY
CLOSURE OF K8
1vpp = 10kv (2B6) TP12 1v = 10kvp 1v = 20kvp
High Charge Mode
TP10 POSITIVE PEAK TP9
R46
KV SENSE 3 1 DETECTOR KVP MEASURED See Battery Charger
3 U20 1
U16 U22, U26, U18 (2B5) CR6
2 Block Diagram
(2B7)
U3 (2B4) (2B4)
MUX 19 KVPMEAS 7 NEGATIVE PEAK TP13 (1C8)
(2B7) 6 - U16 R49 2+ 7 mA SERVO
DETECTOR U19
P3 U25, U26, U18 1v = 10kvp COMPENSATION
3
- To mA Block Diagram
P2 NETWORKS U17
(1D6) (2B6) (Enable mA Error Amp)
46 27
(2C4)
(.075V/KVP) PWM
KVPCONT (2C7)
2 - (2C7) 2 + TP2
U31 TP19 6 R25 1 5 PWM COMP
47 28 KVP CONTROL 7
D:A 25 - U20 3 + U23 U12
6 7 E2 3 U34
- (2C5)
(1B4)
U33 (KVEREN) TP15
(1B6) U7 19 U17
(2D6)
PAL 15 RAMP
-10V REF GEN DRV ST*
(2C6) 5kHZ.
VR1, U30, Q14 Q6
TP33 (1D2) 8 PWM _COMP
HV DRV A 29 10 13 U8, U28, Q4 HV DRV B TP23 TP24

2 TP22 TP5
(2D5)
HV DRV B 28 9 12 VARIABLE +15V VR1 +12V -15V VR2 -12V +5V GND
3 X-RAY REGULATOR PCB
U8, U29, Q5 HV DRV A
DUTY (1B4) (1B4)
U17 FIXED (1B7) CYCLE SCH. #877458
(2C5)
PAL DUTY
U42 CYCLE
6 A2J3 7 8 7 P4
12 Darlington Drivers
K2
8 1 +
13 Q1 B+
P3 7 8
(1A6) U40
+15V (1C7) P1 C1
F1 B1 CB1
(1C8) T1 3
C2 &C3 -
2A R1 K1 30A
Q8 BATTERY
TP1 TP2 TP21 TP22 (1C6)
HV DRV B E1 PACKS KV SENSE
2 BATTERY F1 1:10000
(1C8)
(1C7) F2 C2E1 CHARGER
B2 Tank
TP24 TP25 TP23 Q7 TP5 9 876643 3A
+5V +12V +15V K2 3 2A
E2 2
-15V (1C6)
8
+15V C1 HV
L1
(1B8) TRANSFORMER
TP6
(1C8) (1B7)
ANALOG INTERFACE PCB Q6 Q2 B+
SCH. #876738 HV DRV A
P2 C1
F5 B1
Q5 T3 3
(1C7) 2A See Precharge
MOTHERBOARD (1B8) 1
SCH. #875539 OR #878396 (1B6)
E1
Block Diagram 9600 C-ARM
-15V 2
C2E1 2 See Battery Charger
F4 B2 Block Diagram KV_BLK.DS4 12/4/96
9
2A See Generator Interlock
GENERATOR DRIVER PCB (1B6) E2 3 Block Diagram KV BLOCK DIAGRAM
SCH. #877461 8
U19-7 MA SERVO
U20 -7 KVP CONTROL
Test Conditions -3.75 VOLTS AT 50 KVP HI = 8.5V MA SERVO ON
PPD .075V / KV
In the manual fluoro ( X-RAYS ON )
HV DRV A TP12
mode, use a technique
2 V dc LO = 0V MA SERVO OFF
of 50 kV and 1 mA for 10 V dc
100 us ( X-RAYS OFF )
the majority of this lab. 100 us
Other kV settings will KVPSNS
be useful for observing
a change in DC voltages. 1 V dc
100 us NPD TP9 KVP MEASURE
Note these unique HV DRV B TP13 2.5 VOLTS AT 50KVP
kV settings on this 2 V dc 1 VOLT = 20 KVP
worksheet for future 10 V dc 100 us ( X-RAYS ON )
100 us
reference.
U17
U12 R25
A1J3
A2J3
78 U19
CR6 U18 KVPM
U16 U20 17 27
2 KVPSNS 36 3 TP9
17 R46 TP15 RAMP
TP10 36 U22
R48 U23
P3 1 1 V dc
R52 U26 2 50 us
R49 3
U7-19 KVEREN (KV SERVO ENABLE) R54 U25 TP12
PPD U34-2 KV CORR.
HI =X-RAY ON U17 PINS 6-7 OPEN
U28 E2 U34
LO = X-RAY OFF U17 PINS 6-7 SHORTED
Q4 27
U7 NPD 3
HV DRV A 2 19 U8 TP13
3 U29 TP15
HV DRV B RAMP
PWM Q5 Q6
TP2
X-RAY REGULATOR U34-7 COMP. OUT
00-873616- ( )
GOES LOW WHEN
HV DRV B RAMP EXCEEDS
KV CORR. VOLTAGE.
HV DRV A E2 KV SERVO DISABLE
U23-1 KV CORRECTION
INSTALLING E2
OVERRIDES KVEREN
X-RAYS OFF = 0 VOLTS 2 V dc
FROM PAL U7
X-RAYS ON = -2.2V TYP. 50 us
TP2 PWM_COMP
FLIP FLOP OUTPUT
U12-5 GOES LOW
HV DRV B WHEN U34-7 COMP.
OUT GOES LOW
2 V dc 2 V dc
100 us 100 us
9600 C-ARM
HV DRV A Page 1 of 2
For Reference Only
2 V dc 2 V dc
100 us 100 us KV_LABSS.DS4 5/17/96
KV GENERATION
SIGNAL SHEET
Test Conditions
In the manual fluoro mode, use a

technique of 50 kV and 1 mA for
100 V dc the majority of this lab. Other kV
100 us settings will be useful for observing
a change in DC voltages. Note these
unique kV settings on this worksheet
for future reference.
5 V dc
100 us
Q5 Q6 Q7 Q8 P1
F1
T1
F2 3
2 5 V dc
100 us
8
9
100 V dc
F4 100 us
GENERATOR DRIVER
R20
P2
00-873613- ( )
3
2
T3
K2 F5 8
9
R29
P3 TP6 TP5
78
TP 5
HVDR B
2 V dc
100 us
9600 C-ARM
TP 6 For Reference Only Page 2 of 2
HVDR A
2 V dc KV_LABSS.DS4 5/17/96
100 us
KV GENERATION
SIGNAL SHEET
9600 Mobile Digital C-Arm - Generator Block Diagrams, Test Points, and Signal Waveforms
ANALOG P4 15 MA SENSE
INTERFACE PCB
SCH. #876738 CURRENT TO VOLTAGE CONVERTER LOW PASS FILTER
U3 P2 P3 TP7 SCALING AMP 8mA/Volt Fluoro

TP6 TP11
MUX 6 7
40mA/Volt Film
21 FILSNS 50 31 3 1 5 3 U31 1
U31 + U30 + U30 7
20 1 2 (1D7) (1D6) (1D6) (1D4)
U6 K1
(1D6) (1D8) SCALING (not used) U21
48 30 MA MEASURED MA MEASURED
350mV/mA - fluoro U13 Closes above 30kV FROM 100 TURN WINDING
U31 70mV/mA - film (1D7) AROUND ANODE SOCKET
(1B4) TP18
6 7 XRAY REGULATOR PCB
D:A + = More heat
MA ERROR - = Less heat
U33 SCH. #877458
2 1 53 TP4
23 TP8 (1C7)
R27 6- R82 6 TANK
1 -
(1B6) 3 34 mA CONTROL 2 - U15 8 7 7 FILREG
-10V REF 5 +U15 U27
GEN VR1 (1D7)
TP21 (1D7) + (1C6)
U18
TP33
(1D2) 32 FIL B CONTROL 5 FILAMENT TRANSFORMER
D:A 3 TP10 (1A7)
4 E1
kVP Measured 10 11
6 2 1 4.1V 51 U10 (1C7)
U5
PAL From kV Sense
2 +
(1B6)
U28
(1B5) 23 FILDRVA 4 3 9 16 U7 3 XL XS
5 12 Circuits TP9 7 TP18 1 FIL B+ SENSE
FILDRVB 3
See KV Block 3 - U19 KV
U27
U17
22 6 13 Diagram U13 P3
mA SERVO (1D7) PAL (1C6) NOTE: THE XL AND XS
PAL (1A5) 14 (2B4) FILFDBK 6 CONNECTIONS PASS
U40 Opens when THRU THE X-RAY
14 11
X-rays on REGULATOR PCB
15 11 BEFORE CONNECTING
TO THE TANK
U42 TP23 TP24 TP22 TP5
(1A6) 3 5 +5V GND
(1A5) +15V VR1 +12V -15V VR2 -12V
U11 U11 (1B4) (1B4)
(1B6)
TP1 TP2 TP21 TP22 4 6
11 5 4 P3 3 P3
If E1 jumper is installed, no mA correction
voltage will be applied to TP4
TP24 TP25 TP23 P3
+5V +12V +15V 3
161V = Fluoro 6
GENERATOR DRIVER PCB 176V = .3mm Film 161V prep
P1 SCH. #877461 FILAMENT 184V = .6mm Film 141V prep
REGULATED R8 (1D8)
6 B+ REGULATOR
MOTHERBOARD
VOLTAGE Q10, Q1, Q2 FILAMENT VOLTAGE
SCH. #875539 OR #878396
F3 (1D7) Q4
6 (1C5)
(1D4)
TP4
C2 &C3 P2 K1 10
(1D5) (1D4)
(1D6) 9
TP3 L3
C13
T2
4 FIL DR A 9600 C-ARM
K2 P3
+ TP2 (1D6)
5 FIL DR B Q3 For Reference Only Page 1 of 1
MA_BLK.DS4 6/6/96
11 .6mm MODE High above 100 mAs
CB1 Q11
- K1 R1 (1D4)
BATTERY MA BLOCK DIAGRAM
PACKS P3
TP21 MA CONTROL / MEASURE ENABLE
LO = X-RAYS ON U13 PINS 6-7 CLOSED U27-1 FILAMENT B+ SENSE

WHICH ALLOWS MA CONTROL VOLTAGE FLUORO X-RAYS OFF = 3.9 VDC MA PULSES
FLUORO X-RAYS ON = 3.6 - 4.2 VDC TP8 MA CONTROL
TO BE FED TO ERROR AMP U15. 200 mV dc
(X-RAY ON VOLTAGE VARIES DEPENDING FLUORO @ 5MA = -1.7VDC
100 us .3MM 70 KVP @ 20 MAS = -1.13 VDC ARMED = -4.17 VDC
HI = X-RAYS OFF U13 PINS 6-7 OPEN ON THE AMOUNT OF ERROR AMP VOLTAGE
AT TP4). .6MM 70 KVP @ 300 MAS = -6.84 VDC ARMED = -6.84 VDC
WHICH REMOVES MA CONTROL VOLTAGE
THIS VOLTAGE IS DETERMINED BY THE GENERATOR SOFTWARE.
FROM ERROR AMP U15.
.3MM FILM = 4.3 VDC, ARMED = 3.9 VDC
THIS SIGNAL SWITCHES FROM LO TO HI .6MM FILM = 4.5 VDC, ARMED = 3.4 VDC
WHEN TP9 KVPM IS 1.5 VDC OR HIGHER. MA SENSE TP11 MA MEASURE
( THE KVP IS 30 OR ABOVE ) 100 mV dc SCALE FACTOR:
U27-6 FILAMENT B+ CONTROL 100 us FLUORO 8 MA / VOLT ( .125 VOLTS / MA )
FLUORO = 3.9 VDC X-RAYS OFF FILM 40 MA / VOLT ( .025 VOLTS / MA )
3.75 VDC X-RAYS ON TYP.
U7-16 MA ERROR ENABLE .3MM FILM = 4.3 VDC, ARMED = 3.9 VDC
.6MM FILM = 4.5 VDC, ARMED = 3.4 VDC THESE COMPONENTS
HI = X-RAYS ON U13 PINS 10-11 OPEN MA SENSE ARE COVERED BY THE
WHICH TURNS ON ERROR AMP U15. X-RAY REGULATOR PCB
TP9 KVP MEASURE
U27-7 FILAMENT REGULATOR
LO = X-RAYS OFF U13 PINS 10-11 SHORTED 50 mV dc
100 us R82 MA SERVO ENABLE U19 TURNS ON
WHICH TURNS OFF ERROR AMP U15. FLUORO = 3.18 VDC X-RAYS OFF MA SERVO WHEN THE VOLTAGE AT
4.5 VDC X-RAYS ON TYP. TP9 IS 1.5 VDC OR HIGHER.
THIS SIGNAL IS CONTROLLED BY THE
X-RAY ON CIRCUITRY VIA PAL U7. .3MM FILM = 2.37 VDC, ARMED = 3.14
U13
.6MM FILM = 2.03 VDC, ARMED = 4.23 2 V dc
100 us
U10-14 .3MM / .6MM SELECT U5

A2J3
TTL LO IN ALL FLUORO MODES 6
AND FILM MODE BELOW 110 MAS
7 U15 U19 KVPM
(.3MM SPOT). 1
6 TP4 TP9
TP8 2 MA ERR E1
MA CNT 5
U5 IS COVERED BY
TTL HI IN FILM MODE 110 MAS AND
THE BATTERY GND R27 MA MS
ABOVE (.6MM SPOT) U21
CHARGER PCB TP5 MA SNS
P3
TP6 TP11
U10-14 GOES HI WHEN FILM MODE R50
IS ARMED FOR THE FIRST EXPOSURE MA PLS K1
AT OR ABOVE 110 MAS AND REMAINS E1 JUMPER MA SERVO DISABLE
TP7
HI UNTIL THE MAS IS SET BELOW 110
AND THE SYSTEM IS ARMED FOR ANOTHER WHEN A JUMPER IS INSTALLED AT E1
U27 MA ERROR ENABLE FROM U7 KV PAL
EXPOSURE OR FLUORO MODE IS SELECTED. 1
U30 U31
U10 U7 7 1 7
IS OVERRIDDEN, PREVENTING ANY
1 MA ERROR CORRECTION DURING
TP21 3 6 7
3 5 CR15 3 6
ANY X-RAY FLUORO OR FILM.
FILAMENT DRIVE A
16
5 14 R91
FILAMENT DRIVE B 6 13
12 OEC-DIASONICS,INC.
15 P4 X-RAY REGULATOR
00-873616- ( )
FLUORO AUTO MODE 67 KVP @ 2.3 MA

(BOOT UP DEFAULT CONDITION)
X-RAYS OFF.
2
FIL DR B FLUORO MANUAL MODE 67 KVP @ 2.3 MA

X-RAYS ON
2 V dc 2 V dc 2
100 us 100 us
MA ERROR 9600 C-ARM
MAXIMUM
MA ERROR For Reference Only Page 1 of 2
2 V dc CORRECTION
100 us
RANGE MA_LABSS.DS4 6/6/96
FIL DR A
2 V dc 2 V dc
100 us 100 us MA GENERATION
SIGNAL SHEET
R8 REGULATED FILAMENT VOLTAGE

F3 B+ VOLTAGE
Q1 Q2
P1
Q3 Q4 FLUORO = 160 VDC WITH X-RAYS OFF
.3MM FILM = 175 VDC, ARMED 160 VDC F3 HAS FULL BATTERY VOLTAGE
.6MM FILM = 185 VDC, ARMED 140 VDC PRESENT WHEN EVER THE +24
VOLT INTERLOCK IS ON.
WHEN AN EXPOSURE IS BEING MADE THE SEE PRECHARGE CONTROL BLOCK
VOLTAGE FROM THE FILAMENT REGULATOR
IS CHANGED BY THE ERROR AMP U15 ON
R8 THE X-RAY REGULATOR BOARD TO 6
REGULATE THE MA.
Q10 F3
Q11 COLLECTOR .3MM / .6MM SPOT SELECT
+24 VOLTS IN ALL FLUORO MODES

AND FILM MODE BELOW 110 MAS
P2
T2 (.3MM SPOT).
GENERATOR DRIVER
.7 VOLTS IN FILM MODE 110 MAS AND

ABOVE (.6 MM SPOT).
Q11
00-873613- ( )
Q11 TURNS ON WHEN FILM MODE

IS ARMED FOR THE FIRST EXPOSURE 6
AT OR ABOVE 110 MAS AND REMAINS
TP2 K1 ON UNTIL THE MAS IS SET BELOW 110
AND THE SYSTEM IS ARMED FOR
TP4 ANOTHER EXPOSURE OR FLUORO MODE
TP3 IS SELECTED.
3456 9 10 11 P3
FIL DR A TEST CONDITIONS

FLUORO AUTO MODE 67 KVP @ 2.3 MA
5 V dc
100 us (BOOT UP DEFAULT CONDITION)
X-RAYS OFF.
FIL DRIVE
50 V dc
100 us 9600 C-ARM
FIL DR B
5 V dc
100 us
MA_LABSS.DS4 6/6/96
MA GENERATION
SIGNAL SHEET
REFERENCE TO
C-ARM (MAINFRAME)
INTERCONNECT DIAGRAM
SCH. #875500 OR #877972
POWER/MOTOR
RELAY PCB LS1 - TOP
1 LIFT_115VAC_B RED
SCH. #875997
C6 M1
LS2 - BOTTOM LIFT
1 WARNING! SYSTEMS FROM
3 LIFT_115VAC_A BLACK
MOTOR SERIAL #69-1001 AND UP
5 LIFT_MOT0R_AC_RTN BLUE CARRY VOLTAGE POTENTIALS
ON AC RETURN LINES
1
POWER/SIGNAL P6
INTERFACE PCB 6
SCH. #876001 5
OR #877998
P3 USE THIS PAGE FOR
2
8 69-0001 TO 69-2000
P7 +
P6
*(115VAC PH 2)
- 1 1 LIFT_UP_SW
*SIGNAL NAME FOR
115VAC_PH_MTR 1 10 5 P2 SERIAL NUMBERS
TP1 K12 P4 LIFT UP
1 3 S4 69-0001 TO 69-1000
+24V 20 7 8 4
6
4 5 1
6 +
7 DC_RTN_SW 7
3
1 + E5 - 2 P5 LIFT DOWN
8
115VAC_RTN_MTR 4 3 - D K3 + 3 S5
*(NEUTRAL) K4 D - 1 2 LIFT_DN_SW 2 1
REFER TO SYSTEM 10 11
K13
POWER DISTRIBUTION P7 ROTATE CCW
BLOCK DIAGRAM 6 3
FOR DETAILS OF + 5
TP2 1 S7
THESE CIRCUITS
- 3
2
D K9 8 P6 ROTATE CW
+ 3 S6
24V INTERLOCK RELAY - 1 4 ROTATE_CCW_SW 4 1
SEE GENERATOR INTERLOCK
BLOCK DIAGRAM FOR DETAILS K5
*SIGNAL NAME FOR 6 L-ARM

5
SERIAL NUMBERS MOTOR POWER M2
69-0001 TO 69-1000 3 PCB ROTATION
SCH. #876378 MOTOR
2
8 TB2
+
1 CHASSIS
- 1 3 ROTATE_CW_SW 3
7 MTR_BLK
RELAYS K6 10 10 8 2 8 CAP_A
SHOWN 9 LS3_B
DE-ENERGIZED 5 ROTATE_115VAC_B 5 3 5 10 LS3_A
6 6
1 ROTATE_115VAC_A 1 1 4 3 LS4_A
C7
2 2 4 LS4_B
5 CAP_B
1 6 MTR_RED
9 ROTATE_AC_RTN 9 6 3 2 MTR_WHITE
10 10
P3 TB1
P4 P1
9600 C-ARM
POWER/SIGNAL
DISTRIBUTION PCB For Reference Only Page 1 of 2
SCH. #875968
LIFT&ROT.DS4 12/9/96
LIFT & ROTATION MOTOR

BLOCK DIAGRAM
REFERENCE TO
C-ARM (MAINFRAME)
SCH. #878376
POWER/MOTOR
RELAY PCB LS1 - TOP
1 LIFT_115VAC_B RED
SCH. #875997
C6 M1
LS2 - BOTTOM LIFT
1 WARNING! SYSTEMS FROM
3 LIFT_115VAC_A BLACK
MOTOR SERIAL #69-1001 AND UP
5 LIFT_MOT0R_AC_RTN BLUE CARRY VOLTAGE POTENTIALS
ON AC RETURN LINES
1
POWER/SIGNAL P6
INTERFACE PCB 6
5
SCH. #877998
P3 USE THIS PAGE FOR
2 69-2001 AND HIGHER &
8
+ 62-0001 AND HIGHER
P6 P7
- 1 1 LIFT_UP_SW
115VAC_PH_MTR 1 10 5 P2
TP1 K12 P11 LIFT UP
4 1 3 S4
+24V 20 7 8 6
4 5 1
6 +
7 DC_RTN_SW 7
3
1 + E5 - 2 P5 LIFT DOWN
8 S5
115VAC_RTN_MTR 4 3 - D K3 + 3
K4 D - 1 2 LIFT_DN_SW 2 1
REFER TO SYSTEM 10 11
K13
POWER DISTRIBUTION P7 ROTATE CCW
BLOCK DIAGRAM 6 3 S7
FOR DETAILS OF + 5
TP2 1
THESE CIRCUITS
- 3
2
D K9 8 P12 ROTATE CW
+ 3 S6
24V INTERLOCK RELAY - 1 4 ROTATE_CCW_SW 4 1
SEE GENERATOR INTERLOCK
BLOCK DIAGRAM FOR DETAILS K5
6 L-ARM
5 MOTOR POWER M2
3 PCB ROTATION
SCH. #876378 MOTOR
2
8 TB2
+
1 CHASSIS
- 1 3 ROTATE_CW_SW 3
7 MTR_BLK
RELAYS K6 10 10 8 2 8 CAP_A
SHOWN 9 LS3_B
DE-ENERGIZED 5 ROTATE_115VAC_B 5 3 5 10 LS3_A
6 6
1 ROTATE_115VAC_A 1 1 4 3 LS4_A
C7
2 2 4 LS4_B
5 CAP_B
1 6 MTR_RED
9 ROTATE_AC_RTN 9 6 3 2 MTR_WHITE
10 10
P3 TB1
P4 P1
9600 C-ARM
COLUMN I/O PCB
SCH. #878492 For Reference Only Page 2 of 2
LIFT&ROT.DS4 12/9/96
LIFT & ROTATION MOTOR

BLOCK DIAGRAM
LIFT MOTOR UP
P6-1
100 V ac
5 ms
P6_3
100 V ac
5 ms
TP2
LIFT MOTOR DOWN
K3
P6-1
100 V ac
5 ms
K4
P6-3
100 V ac
E5
5 ms
K5 ROTATE CW
K12 P4-5
100 V ac
K13 5 ms
K6
ASSY 00-875999- ( )
P4-1
3
1
100 V ac
P6
5 ms
6
4
10 1
ROTATE CCW
P4
P4-5
100 V ac
5 ms
9600 C-ARM
P4-1
100 V ac LFT&RTSS.DS4 6/6/96
5 ms
LIFT / ROTATATION MOTORS
SIGNAL SHEET
T1 2 KEY SWITCH P3 7
+24V
FROM 2A
ISOLATION 2 K2 CB3 (3A) PS4
100-127 VAC CORD ASSEMBLY SURGE SUPPRESSOR PCB TRANSFORMER 1

(1C3)
+24V TO
SCH. #876784 3 8 2B
CB1 4 L_MON
RESET ONLY 128 CB1 (0.2A) 12VDC Supply
P1 P2 AC1 RESET ONLY
10A (1E7) +24V TO 2C
TB1 C2 RV3 120 9
1 1 T1 CR1 U1 R_MON
C1 (1F5) CB2 (3A)
3 6 110 (1E7) (1F6) 8 P6
1 2 RT1 RT3 (1B3)
5 2 1
RT2 RT4 104 1 3 +12V N.O.
3 4 9 9 - + 7812
C3 RV4
1 RV1 RV2
98
2
K1
5 6 6 P1 RV2 (1C4)
COM
8 P4
E1 E2 CT 6 AC1
E1
DS1 1 2D
GREEN LAMP 7 1 5 240VAC
128 D1
TO TB2
240 VAC 3
120 AC2 2E
4
3 4
110
CB1 NEUT.
RV1 8 2F
RESET ONLY 104 2
P1 2 N.O.
1
TB1 10A 98 D2
1
AC2 E4
3 COM
1 2 5 SHLD POWER CONTROL PCB F1 (2A S.B.) 120VAC
P6 TO PS4
9 E3 00-876547 1 (+24V)
3 4 2G
1 6 E1 E2 E3 E4 E5 E6 (1C2)
NEUTRAL
2 TO PS4
5 6 2H
8
E19 E1 - E6 ARE MOUNTING HOLES (GROUND)
E1
DS1 (Mounting)
GREEN LAMP
200-250VAC CORD ASSEMBLY K4 K3

CB2 (10A) (1D2) (1D4)
RESET ONLY 3 R5
(1E5)
P5 TP1 DELAY CIRCUIT
5 4
R1
C-ARM 3A
19 120V PH2 19 4 6 3
(1E5)
TO POWER/SIGNAL TP2 TP3 1
INTERFACE PCB 4 5
13 120V PH1 13 1 3 6
3B 2 U2
1 1 C5 (1D5) R2 (1D5)
22 NEUTRAL 22 2 CR4
See Sheet 3 3C (1D4) 13
N.O. 8 N.O. 8 C3 12
for C-Arm E1 16 CHASSIS GND 16 (1D6)
Power E9 P2
18 LOOP1
Distribution LOOP1 18 LOOP1 3
1 KEY_PWR 1 KEY_PWR 2
3D
TO POWER/MOTOR
RELAY PCB 12 CNCT_ON 12 CNCT_ON 4
3E
LOOP2 10 LOOP2 10 LOOP2 1 LOOP2
J1 INTERCONNECT P1
CABLE
DS1 is a green light that turns on when the Power Cord

1 3 240 VAC between TP1 & TP2
is plugged into a wall outlet. when Workstation is plugged in to outlet WORKSTATION
Strap T1 to match Hospital AC as follows: and interconnect cable is connected to C-Arm INTERCONNECT DIAGRAM
2 876158 9600 C-Arm
220 -250 VAC Cord Assembly
Transformer TAP 98 104 110 Br 110 & Br/Wt 120 120 128 For Reference Only Page 1 of 3
Input VAC Range 186 - 200 201 - 214 215 - 225 226-234 235-248 249-269 PWERBLK1.DS4 12/3/96
100 - 127 VAC Cord Assembly Use this drawing with system 9600 System Power Distribution
Transformer TAP 98 104 110 120 128 serial numbers 69-0001 to 69-1000 Functional Schematic
Input VAC Range 94 -100 101 - 107 108 - 115 116-124 125-134 Workstation Distribution
P5
1 +12V
1A 2 GND N/C
DC POWER DISTRIBUTION PCB
P8
P3 14-16 5 1 3 8-11 00-876839 1 +12V
ETI (Elapsed Time Indicator)
2 GND
1C Right Mon.
+24VDC P7
+5V 1 +12V
Left Mon. at P6.2 Spare Disk Drive
2 +5V
+24VDC P6.3 (GND) +12V 3 GND
1B DO NOT
at P6.2 4 GND
-12V ADJUST CB7
P6.3 (GND)
U1 P6
-5V R43 1 +12V
MAX694 CPA 2 +5V
GND Floppy Disk Drive
(1C5) 3 GND
CB3 (5A) R53 4 GND
RESET ONLY OUT 2 VCC OUT
V ADJ OUT 1 1 7
CB3 P4
1 +5V
AC1 V ADJ BAT RST 2 +5V
AC1 1 R21
7 GND
8 GND
1D 1 2 PS1 PFI PFO R1 3
RT1 +12V
P16 +/-5 VDC E18 4 +5V Hard Disk Drive
2 CB4
AC2
120
J16 +/- 12VDC WDI GND
CB5
9 GND
VAC 10 GND
1E 1 2 F1 (4A) 5 +12V
3 6 +5V
AC1 FAST BLOW 11 GND
NEUTRAL 12 GND
1F 4 C1 P2
NEUTRAL
R2 1 SYSRST*
2 +5V
3 +12V
120 5 4 -12V
VAC 5 GND
P1 2 1 6 GND
1G AC2 VIA F1 6 7 GND
CB1 8 386 Motherboard
GND
120/240VAC 9 -5V
10 +5V
1H 7 OUTLET STRIP 11 +5V
AC1 1 CB2 12 +5V
NEUTRAL NEUTRAL 2 13 +5V
RT2
14 +12V
8
AC2 AC2 3
4 P3
1 SYSRST*
2 +5V
TB2 3 +12V
4 -12V
5 GND
E8 6 GND Control Panel Interface PCB
7 GND
8 GND & Contrast / Brightness PCB
9 -5V
Ground to 10 +5V
CB6 11 +5V
Power Control PCB 12 +5V
P6 pins 4,5,6 13 +5V
TB2.6 AC2 (BRN) P9
14 +12V
See Sheet 1 TP2 TP3
TB2.5 NEUT (WHT) 1 +5V +12V P1
YELLOW
WHITE/RED
1 +5V
SONY 890 OR 910 2 CB9 2 +5V
BLACK
SONY VCR THERMAL IMAGER 9 GND

WHITE
INTERNAL LENZAR (Optional) 10 GND

HARD COPY CAMERA (Optional) 3
3 +5V
(Optional) 4 +12V
4 5 -12V
11 -5V Auxiliary Interface PCB &
5 12 GND Video Switching PCB &
AC2 CB8 13 GND
TB2.7 Image Processor PCB
R11 6 6 +5V
R6 7 +12V
V ADJ AC1 CR1 CR2 8 -12V
DO NOT TB2.1 7 14
GROUND, -5VDC & -12VDC -5V
ADJUST TP1 TP5 TP4 15 GND
PS4 8 -5V -12V connections from P9, to the connectors 16 GND
+24VDC GND
9 at the right side of the diagram
are not shown to simplify this diagram.
10
NEUTRAL
2 2
TB2.5
FAN B1 FAN B2 FAN B3
9600 C-Arm
WORKSTATION 1 U1 monitors +5VDC. If it falls below 4.65VDC,
INTERCONNECT DIAGRAM U1.7 (SYSRST*) goes low resetting the 386 Motherboard. PWERBLK1.DS4 12/3/96
876158 It goes high 200 mS after 4.7VCD is reached. Use this drawing with system
serial numbers 69-0001 to 69-1000 9600 System Power Distribution
2 -5 and -12 VDC are NOT CIRCUIT BREAKER PROTECTED Functional Schematic
Workstation Distribution
TP2
P1
6 5
KEY_PWR 1 1 KEY_PWR 1D
14
TP2 CNCT_ON 15 12 12 CNCT_ON
120V PH1 1E
(1D6)
SWITCHED
SEE STATOR RELAY/STATORSENSE
K10 AND LIFT/ROTATION
(1B7) NEUTRAL FOR FUNCTIONAL SCHEMATICS
ROTATION, FOR DETAILS OF THESE CIRCUITS
120V PH2 LIFT,
& STATOR
SEE GENERATOR INTERLOCK,
PRE-CHARGE,
TP1 +24V STATOR RELAY/STATOR SENSE,
POWER/MOTOR
AND LIFT/ROTATION
RELAY PCB
FUNCTIONAL SCHEMATICS
SCH. #875997
FOR DETAILS OF +24V AND
+24V INTERLOCK CIRUITRY
12 6 3 10 7 P7
WORKSTATION
DS2 INTERCONNECT DIAGRAM
DRAWING #876158
E1 16 16 E9
10 13 17 24 4 1 20 P6
P12
MOTHERBOARD 22 22
2 NEUTRAL NEUTRAL 1C
SCH. #875539 P2 (1C6)
CB9 (1B4) 1 120V PH2 13
6 1 3 CB8 13 120V PH2 1A
PS1 12 2 LF2 5 (1B4) 4 120V PH1 19 19
+15V 1 3 +12V 120V PH1 1B
VR2 SEE PAGE 1 TO
2 (1B5) (1B5) P5 J1 INTERCONNECT P1 CONTINUE THESE
+5 7
CB6 CB7 CABLE SIGNALS
+15 4 +24V 4 +24V
-15V 2 3 -12V CB5
-15 2 8
VR1 CB4
DC COMMON 3
1
P1 120V PH1
1 P8 P7 (1C5) SWITCHED
TO +12V 1
5 2 -15 CB1 PS2
CONTROL PANEL 6
1 +15 24V
PROCESSOR PCB
6 +5
P8 P9 1 +12V
TO 14 -15 FROM
5 +12V TP2
X-RAY 1 +15 MOTHERBOARD P4 TP1, 3,
REGULATOR 8 +5 12, 13
BATTERY CHARGER PCB 18 17
PCB - P1
SCH. #876643
P10
P11
T1 (1A7) TO CONTROL PANEL
2 +5
CONTROL PANEL PROCESSOR PCB
PROCESSOR PCB - P3 SCH. #875601
P2 P1 (1C7)
2 NEUTRAL 3 2 5
CR1 (1B5)
5 120 PH2 5 1 LF3 3
(1B7) CB3
SEE BATTERY CHARGER C-ARM
BLOCK DIAGRAM FOR + - NC (1C6)
DETAILS OF THE 2 5
(1B5) POWER/SIGNAL INTERCONNECT DIAGRAM
9600 C-Arm
BATTERY CHARGER PCB 3 120V PH1 9 1 LF1 3 CB2 INTERFACE PCB DRAWING #875500
SCH. #876001
PWERBLK1.DS4 12/3/96
Use this drawing with system
serial numbers 69-0001 to 69-1000 9600 System Power Distribution
Functional Schematic
C-Arm Distribution
T1 2 KEY SWITCH P3 7
+24V
FROM 2A
ISOLATION 2 K2 CB3 (3A) PS4
100-127 VAC CORD ASSEMBLY SURGE SUPPRESSOR PCB TRANSFORMER 1

(1C3)
+24V TO
SCH. #876784 3 8 L_MON 2B
CB1 4
RESET ONLY 125 AC1 CB1 (0.2A) 12VDC Supply
P1 P2 RESET ONLY +24V TO
TB1 10A C2 RV3 115 (1E7) 9 2C
R_MON
1 1 T1 CR1 U1
C1 105 (1F5) CB2 (3A)
3 6 (1E7) (1F6) 8 P6
1 2 RT1 RT3 (1B3)
5 2 1
RT2 RT4 CT 1 3 +12V N.O.
3 4 9 9 - + 7812
C3 RV4 COM
1 RV1 RV2 CB3 (4A) 2
K1
5 6 6 RESET ONLY P1 RV2 (1C4)
E4
8 P4
E1 E1 E2 6
DS1 AC1 AC1 2D
AC1 5 1
GREEN LAMP 7 125 4 240VAC
AC2 TO TB2
115 240 VAC 3
AC2 AC2
AC2
4 4 2E
105 6
AC
CB1
RV1 8 GND
RESET ONLY
P1
POWER CONTROL 1
N.O. 2 2F
TB1 10A COM

2
00-878001
1 RTN E4
3 E1 E2 E3 E4 E5 E6
1 2 E3 SHLD F1 (2A S.B.) 120VAC
5 E1 - E6 ARE MOUNTING HOLES (GROUND) P6 TO PS4
9 (+24V)
3 4
1 1 2G
5 6
1 6 120 VAC
(1C2)
GND
8 WARNING! 2 2H
E1 AC RETURN LINES E19 3
DS1 IN THIS SYSTEM (Mounting)
GREEN LAMP CARRY VOLTAGE
CB2 (12.5A)
POTENTIALS
RESET ONLY
200-250VAC CORD ASSEMBLY K4 K3
(1D2) (1D4)
3 R5
(1E5)
P5 5 TP1 4 DELAY CIRCUIT
3 R1
C-ARM 3A 19 115VAC_RTN 19 4 6
(1E5)
TO POWER/SIGNAL 4 TP2 5 TP3 1
INTERFACE PCB 6
13 115VAC_PH 13 1 3
3B 2 U2
1 1 C5 (1D5) R2 (1D5)
22 GROUND 22 2 CR4
See Sheet 3 3C 8 8 (1D4) 13
N.O. N.O. C3 12
for C-Arm E1 16 CHASSIS GND 16 (1D6)
Power E9 P2
18
Distribution LOOP1 18 LOOP1 LOOP1 3
1 KEY_PWR 1 KEY_PWR 2
TO POWER/MOTOR 3D
RELAY PCB 12 CNCT_ON 12 CNCT_ON 4
3E
LOOP2 10 LOOP2 10 LOOP2 1 LOOP2
J1 INTERCONNECT P1
CABLE
DS1 is a green light that turns on when the Power Cord

1 3 120 VAC between TP1 & TP2
WORKSTATION
is plugged into a wall outlet. when Workstation is plugged into outlet
and interconnect cable is connected to C-Arm. INTERCONNECT DIAGRAM
2 Strap T1 to match Hospital AC as follows: 00-877970 9600 C-Arm
220 -250 VAC Cord Assembly
Transformer TAP 105 115 125 For Reference Only Page 1 of 3
Input VAC Range 196 - 214 215 - 234 235 - 254 PWERBLK2.DS4 9/19/96
USE THIS DRAWING
WITH SYSTEM SERIAL NUMBERS
100 - 127 VAC Cord Assembly 69-1001 AND HIGHER & System Power Distribution
Transformer TAP 105 115 125 62-0001 AND HIGHER Functional Schematic
Input VAC Range 98 -107 108 - 117 118 - 127 Workstation Distribution
P5
1 +12V
1A 2 GND N/C
DC POWER DISTRIBUTION PCB
P8
P3 14-16 5 1 3 8-11 00-876839 1 +12V
ETI (Elapsed Time Indicator)
2 GND
1C Right Mon.
+24VDC P7
+5V 1 +12V
Left Mon. at P6.2 Spare Disk Drive
2 +5V
+24VDC P6.3 (GND) +12V 3 GND
1B DO NOT
at P6.2 4 GND
-12V ADJUST CB7
P6.3 (GND)
U1 P6
-5V R43 1 +12V
MAX694 CPA 2 +5V
GND Floppy Disk Drive
(1C5) 3 GND
R53 4 GND
OUT 2 VCC OUT
V ADJ OUT 1 1 CB3 P4
1 +5V
V ADJ BAT RST 2 +5V
1 R21
AC1 7 GND
8 GND
1D 1 2 PS1 PFI PFO R1 3 +12V
P16 +/-5 VDC E18 4 +5V Hard Disk Drive
2 CB4
AC2 J16 +/- 12VDC WDI GND
CB5
9 GND
10 GND
1E 120 RT1 1 2 F1 (4A) 5 +12V
VAC 3 6 +5V
FAST BLOW 11 GND
GND 12 GND
1F 4 C1 P2
R2 1 SYSRST*
2 +5V
3 +12V
5 4 -12V
120
5 GND
VAC 2 1 6 GND
1G AC2 VIA F1 6 P1
CB1 7 GND
8 GND 386 Motherboard
120/240VAC 9 -5V
10 +5V
1H GND 7 OUTLET STRIP 11 +5V
AC1 1 CB2 12 +5V
GND 2 13 +5V
RT2
14 +12V
8
AC2 3
4 P3
1 SYSRST*
2 +5V
TB2 3 +12V
4 -12V
5 GND
E8 6 GND Control Panel Interface PCB
7 GND
8 GND & Contrast / Brightness PCB
9 -5V
Ground to 10 +5V
CB6 11 +5V
Power Control PCB 12 +5V
P6 pins 4,5,6 LINE (BRN) P9 13 +5V
See Sheet 1 TB2.6 14 +12V
TP2 TP3
GND (WHT) 1 +5V +12V P1
TB2.5
YELLOW
WHITE/RED
1 +5V
SONY 890 OR 910 2 CB9 2 +5V
BLACK
SONY VCR THERMAL IMAGER 9 GND

WHITE
INTERNAL LENZAR (Optional) 10 GND

HARD COPY CAMERA (Optional) 3
3 +5V
(Optional) 4 +12V
4 5 -12V
11 -5V Auxiliary Interface PCB &
5 12 GND Video Switching PCB &
CB8 13 GND
TB2.7 Image Processor PCB
R11 6 6 +5V
R6 7 +12V
V ADJ CR1 CR2 8 -12V
DO NOT TB2.2 7
WARNING! GROUND, -5VDC & -12VDC 14 -5V
ADJUST TP5 TP4 15 GND
PS4 AC RETURN LINES 8 TP1
IN THIS SYSTEM GND -5V -12V connections from P9, to the connectors 16 GND
+24VDC
CARRY VOLTAGE 9 at the right side of the diagram
POTENTIALS are not shown to simplify this diagram.
10
GND 2 2
TB2.5
FAN B1 FAN B2 FAN B3
9600 C-Arm
WORKSTATION For Reference Only Page 2 of 3
INTERCONNECT DIAGRAM 1 U1 monitors +5VDC. If it falls below 4.65VDC,
PWERBLK2.DS4 9/19/96
00-877970 U1.7 (SYSRST*) goes low resetting the 386 Motherboard. USE THIS DRAWING
It goes high 200 mS after 4.7VCD is reached. WITH SYSTEM SERIAL NUMBERS System Power Distribution
2 -5 and -12 VDC are NOT CIRCUIT BREAKER PROTECTED 62-0001 AND HIGHER
Workstation Distribution
P1
6 5 115VAC_PH_IN
115VAC_ PH_SW KEY_PWR 1 1 KEY_PWR 1D
+ 14
TP2 CNCT_ON 15 12 12 CNCT_ON
1E
- (1D6)
SEE PAGE 1 TO
K10 SEE STATOR RELAY/STATORSENSE CONTINUE THESE
FOR AND LIFT/ROTATION SIGNALS 3B
(1B7) 115VAC_RTN_MTR ROTATION,
FUNCTIONAL SCHEMATICS
WARNING! 115VAC_PH_MTR LIFT, FOR DETAILS OF THESE CIRCUITS 3C
AC RETURN LINES & STATOR
SEE GENERATOR INTERLOCK,
IN THIS SYSTEM PRE-CHARGE,
CARRY VOLTAGE POWER/MOTOR STATOR RELAY/STATOR SENSE,
RELAY PCB TP1 +24V
AND LIFT/ROTATION
POTENTIALS SCH. #875997 FUNCTIONAL SCHEMATICS
USE -04 (SHEET 2) FOR DETAILS OF +24V AND
+24V INTERLOCK CIRUITRY
12 6 3 10 7 P7
WORKSTATION
DS2 INTERCONNECT DIAGRAM
DRAWING #877970
10 17 13 24 4 1 20 P6
E1 16 16 E9 3B
P2 P12
MOTHERBOARD (1C6)
6 1 3 CB10 CB11 2 GROUND 22 22 GROUND 1C 3C
SCH. #875539 (1B4)
OR #878396 CB9 1 115VAC_PH 13 115VAC_PH 1B
13
PS1 LF1 5 4 115VAC_RTN 19 19 115VAC_RTN 1A
+15V 1 3 +12V 12 2 CB8
VR2 (1B5) SEE PAGE 1 TO
2 (1B5) P5 J1 P1
+5 7 (1B5) INTERCONNECT CONTINUE THESE
CB6 CB7 CABLE SIGNALS
+15 4 4 +24V_PS2
-15V 2 3 -12V CB5
-15 2 8 DC COMMON
VR1 CB4
DC COMMON 3
1
P1 OR P5 +12V
1 P8 OR P5 (1C5) P4 TP2
+12V P7 115V_ PH_PS2 1
TO CB1 TP1, 3,
5 2 -15 PS2 SERIAL NUMBERS
CONTROL PANEL 115V_RTN_PS2 6 17 12, 13
1 +15 24V 69-1001 TO 69-2000
PROCESSOR PCB
6 +5
CONTROL PANEL
P8 PROCESSOR PCB
P9 1
TO 14 -15 SCH. #875601
5 +12V FROM
X-RAY 1 +15 MOTHERBOARD
REGULATOR 8 +5
BATTERY CHARGER PCB PCB 18
SCH. #877995 +12V
P10 TP3
P11 CB12
T1 (1A7) TO P4 J3 P3 TP4 SERIAL NUMBERS
2 +5
CONTROL PANEL 69-2001 AND HIGHER
17 15 15
PROCESSOR PCB &
CONTROL PANEL 62-0001 AND HIGHER
P2 P1 COLUMN I/O PCB PROCESSOR I/O PCB
(1C6)
SCH. #878492 SCH. #878489
CR1
LF2 (1B5) C-ARM
4 115VAC_PH_CH 4 1 3
SEE BATTERY CHARGER (1B7) CB2
BLOCK DIAGRAM FOR 2 CHASSIS GND 2 4 DRAWING #877972 OR #878376
9600 C-Arm
DETAILS OF THE + -
BATTERY CHARGER PCB For Reference Only Page 3 of 3
(1B6) POWER/SIGNAL
3 115VAC_RTN_CH 3 2 5 USE THIS DRAWING
CB3 INTERFACE PCB PWERBLK2.DS4 9/19/96
WITH SYSTEM SERIAL NUMBERS
SCH. #877998
69-1001 AND HIGHER & System Power Distribution
62-0001 AND HIGHER
C-Arm Distribution
1 THE CONTROL PANEL DISPLAYS 19 ARROWS AT THIS TIME
CONTROL PANEL DISPLAY + -
BATTERIES BATTERIES
CB1
30 AMP
ANALOG INTERFACE PCB MOTHER BOARD X-RAY (1C8)
SCH. #876738 SCH.#875539 REGULATOR PCB
OR #878396 SCH. #877458
P2 J6 (1B6)
225V
.2V (Numbers in parentheses P4 P3 P2 K1 BATTERY
on connector P4 P5
U44 6 CHARGER PCB
1 5V represent pin numbers 9
RESISTOR seen on Sch. 878396.) 3 SCH. # 876643
PACK F1
Q4 (2B2) 3 AMP 250VDC OR #877995
PRECHRG 18 18 35 35 4 B
U38 19 4 16 6 11 (1) - SLO-BLOW
U45 CR2
PIO CR15 (1A8) (1B7)
A +
(2D7)
.7V
Q1 GENERATOR DRIVER PCB
R1 1K (1B7) SCH. #877461
Q5 (2B2) CONTACT 19 19 (1B7) 25W
18 17 3 7 10 INTERLOCK BX1
(1B6) C2E1
+24V 1 B1
K2 P1 225V
(2C6) (2C5) E1
CR17 6 E2 6
BUS
2 5V 5 E2
DRIVER
CR18 B2
CR1 2 (1C5)
(2A1) + C1 BX2
(1A8) F3
36 36 5 1 -
(23)
SEE GENERATOR 5.3
INTERLOCK R11
Q2 (1D4)
BLOCK DIAGRAM
THIS OCCURS AFTER THE TECHNIQUE PROCESSOR FOR DETAILS (1B7)
2
DETECTS APPROXIMATELY 185VDC ON THE C2E1 BX1 +200V
PRE-CHARGE CAPACITORS C2 & C3
B1 P2 R10 Sense
E1 (1D4)
E2 6
E2
B2
C1 BX2
TP1 TP2 TP21 TP22
225V
(1C7) P3 1
+
TP24 TP25 TP23
C2 C3
+5V +12V +15V
Primary A
High
Voltage
Tank
Primary B (1A8)
5.3V GENERATOR CONTROLLER ASSEMBLY L1 C1
(1B8)
SEE TECHNIQUE PROCESSOR/
ANALOG INTERFACE SAMPLE A2J3
BLOCK DIAGRAM MUX 8 200VSNS 41 41 22 22 1
FOR DETAILS OF U3 (34)
THIS CIRCUITYRY (1D6) RELAYS SHOWN IN THE DE-ENERGIZED POSITION
9600 C-ARM
REFERENCE TO
C-ARM (MAINFRAME) PRECHG.DS4 12/4/96
SCH. # 875500, #877972, or 878376
PRE-CHARGE
BLOCK DIAGRAM
TP1
GND
C44
P1
5
U2 +200V GND
SENSE TP21
12
8
U3
CR17
R10
Q5 R11
CR15
Q4 C F3
CR18
Q4
P2
P2
U38-19 U38-18 F3
GENERATOR DRIVER
19 18
U7
U38
14 TP1
C7
U8 CR33
C9
C8
U45
43 U38-19
U9 RISING EDGE = RISING EDGE =
B+ CHARGE STARTED U38-19 B+ CHARGE STARTED 2 V dc
1s
2 V dc
50 ms
F3
RISING EDGE = C2, C3 CHARGE VOLTAGE VIA

+24V INTERLOCK ON Q4 C 100 V dc
R1 & K1 IN GENERATOR TRAY 1s

10 V dc
FALLING EDGE = 50 ms
B+ CHARGE STARTED
K1 (PRECHARGE) RELAY ON
TP22
GND
F3
P1
100 V dc
1s
TP2 C2, C3 CHARGE VOLTAGE IS

MEASURED BY U7 ADC VIA U38-18
GND +200V
+200V SENSE FROM GENERATOR SENSE
DRIVER PCB.
2 V dc
2 V dc
AS +200V SENSE REACHES APPROX. 5s
1s
4.6 VOLTS K2 (B+ CONTACTOR)
IS TURNED ON BY U38-18 VIA Q5.
WITH K2 ON, THE VOLTAGE ON

C2, C3 IS EQUAL TO THE BATTERY
CHARGER VOLTAGE OF 225 VOLTS,
+200V
SENSE 9600 C-ARM
WHICH RAISES THE VOLTAGE OF For Reference Only Page 1 of 1
+200V SENSE TO 5.3 VOLTS. 2 V dc
THIS TELLS THE SYSTEM THAT 5s
PRECHARGE HAS BEEN SUCESSFULLY PRECHGSS.DS4 6/5/96
COMPLETED.
PRE-CHARGE CONTROL
SIGNAL SHEET
SEE SYSTEM POWER
ANALOG INTERFACE PCB 2 THE CONTROL PANEL DISPLAYS 19 ARROWS AT THIS TIME BLOCK DIAGRAM 1 WARNING! SYSTEMS FROM
SCH. #876738 CONTROL PANEL DISPLAY FOR DETAILS OF
POWER DISTRIBUTION SERIAL #69-1001 AND UP
CARRY VOLTAGE POTENTIALS
TTL LOGIC HIGH-STATOR STARTING ON AC RETURN LINES
TTL LOGIC HIGH-STATOR RUNNING
115 VAC_PH_MTR 115VAC_RTN_MTR DS2 DS1
2
3.6V DC-STATOR STARTING START
3.6V DC-STATOR RUNNING P7 ON ON
P2 J6 P2 10 3 MODE
P1
U44 RUN
POWER/MOTOR OFF ON
RESISTOR RELAY PCB
MODE
PACK SCH. #875997 SLEEP
Q3 (2B2) STAT_RUN 106 106 18 5 STATOR_RUN (1&2B5) OFF OFF
1 MODE
U38 20 15 5 8 9 CB2
U45
PIO CR16 (1&2B6) 2A P5
(2D7) K1 STATOR 1
BUS 5
5
DRIVERS 6
Q7 (2A2) STATSTRT 105 105
STATOR RUN P2
23 13 U43 7 3 14 1 40 VAC
RELAY DS1
On for stator operation
- (1&2B6) 5 STATOR CAP 1 C5
(2C6) (2C5) DURING
CR20
+ 8 +24V From PHASE
RUN CAP
Interlock Circuit 4 STATOR CAP 2
CONDITION (1A1)
CR18 TP4
(2A1) K2 (1&2A6) (1B7)
115 VAC 5 40 VAC
6
3.6V DC-STATOR STARTING 40 VAC 7 10 STATOR 2
2 TTL LOGIC LOW-STATOR RUNNING STATOR
START 8 STATOR_RTN
+ 1 3
RELAY DS2
TTL LOGIC HIGH-STATOR STARTING (1&2A6)
On for 2sec - 1 4 3 P5
TTL LOGIC LOW-STATOR RUNNING
STATOR_START then turns off
17 6 T1
(1B5) 3 10 5 A4J5
TTL LOGIC LOW
STATOR DRAWING CURRENT XFMR_115VAC
+5V 1 2 1 High Voltage
1 Cable Assembly
+5V
R16 8 6 2 P2 7 8 P1 900602 or 900927
(2B8)
U27 (2A7) 40 VAC
CR7
PIO 3 CR6 T3
4 5
(2B7) 10 U24 MOTHER BOARD STATOR
SCH.# 875539 TRANSFORMER
(2A7) C17 CR5 10 5 1 7 3 J15
R15 OR #878376
XFMR_AC_RTN 10 5 1 7 3 P15
(1B1)
R13 TEMP THERMAL

SENSOR SWITCH C P M
2 R12 CR4 CR3 103 103 15 STATOR SENSE
R14 -
1
U19 STATOR SENSE RETURN
+ 3 104 104 16
XRAY TUBE
C22 (2A8)
(2A8)
REFERENCE TO
IMAGE SYSTEM
+12V P3 A1J3 INTERCONNECT DIAGRAM
TP1 TP2 TP21 TP22 6 +12V
SCH.#875410, #877971, OR #878377 RELAYS SHOWN IN DE-ENERGIZED POSITION
SAMPLE
MUX 23 HOUSTEMP 55 55 3 HOUSING_TEMP 9600 C-ARM
U3
(1D6)
TP24 TP25 TP23
SEE TECHNIQUE PROCESSOR/ STATOR.DS4 6/5/96
+5V +12V +15V ANALOG INTERFACE BLOCK
DIAGRAM FOR DETAILS OF REFERENCE TO
THIS CIRCUITYRY C-ARM (MAINFRAME) STATOR RELAY / STATOR SENSE
INTERCONNECT DIAGRAM BLOCK DIAGRAM
SCH. # 875500, #877972, OR #878376
STATOR
START
12
DS1
DS2
U38-23 TP1 CR3 C
GND
Q3 C
P7
6
1
2 V dc U19-1
500 ms
CR3
TP2
GROUND
GND
CR4
TP4
STATOR
RUN
321 TP21
U19 R14
K1 INTERLOCKED +24 V
R13
U38-20
C22
R14
2 V dc CR5
DS2 DS1 500 ms
CR6 CR16
START C17
ON ON R15
MODE U24-5
K2 CR7
RUN 54 Q3
MODE OFF ON
STATOR U24
START P2
SLEEP U38-20
OFF OFF
MODE
Q7 C
T1
R16
CB2
10 V dc
500 ms 31
1
10 20
U27-10 U38
STATOR
U27
RUN 23
8 3 7 U43
Q3 C
9 14 13
U38-23 5 U44
10 V dc U45
500 ms
15
Q7
CR20
ASSY 00-875999- ( )
U27-10
Q7 C
2 V dc
500 ms

P5
STATOR
5
1
SENSE
P1
TP22
10
6
TP2 GND
GND
STATOR 1
P5-5
U19-1 U24-5
200 V dc
500 ms
5V ac 2 V dc
5 ms 20 ms
STATOR 2 9600 C-ARM
P5-10 For Reference Only Page 1 of 1
CR3-C
200 V dc STATORSS.DS4 5/17/96
500 ms 10 mV ac
50 ms STATOR RELAY / STATOR SENSE
SIGNAL SHEET
Battery Packs
Red Blue Black
Connector Connector Connector
(1B8)
5-20 mA DC Trickle Charger Battery Charger PCB

T1
C26, CR9, CR10 876643
(1A7)
(1B6) CB1
(1A6) (1C8)
VR3 +12SEP L1 CR3
VR1 T2 J1
1
C10 C11
(1B4) TP3
Power / Signal Interface PCB -12SEP (1D8) Current
P1 VR2 F1 K2 (1B6)
876001 10 Amp P2 Low Pass
Lemo Sense (1B7)
Current Ideal Diode Filter
+
Connector U4, CR8, Q9
(1B4)
U4, C17
Limiter 5 5 R19
J1 (1B3) R18 6 5
P12 CB3 Current C2
(1D1) (1C7) (1C4)
5 AMP Low Voltage Cutoff Sensor
(1C6) (1C7)
Q10 shuts off Q2 when battery
19 PH 2 1 LF 3 RT2 voltage falls below 160 VDC +12SEP K1 (1B6) R1
(1B5) R48, R16, CR11, Q10
R37 6 n.o.
22 NEUT. 2 3 + Q2
+
CR1 (1C5)
(1B5)
7 2
(1C6) (1B7) U5 + 3 1.1 VDC
R39 9 C3
13 PH 1 4 3 n.c.
LF 1 1 (1B7)
(1B5) RT1
CB2 R6 R11
16 GND 5 AMP
(1C7)
9 3 L2
R10 See Precharge Control Block Diagram
(2A7)
10 Amp 3
Charger R28 14
Current (1A4) X-Ray Regulator PCB
Output R32 877458
Limiter P1 Generator
2 Adjust U3 (1D5)
Volts X-RAYS ON = HI Driver
(1A5)
15 J3 CR6 F3
Display (Hi charge) PCB
(1C6)
2
CR2 Adjust 877461
E1 -12SEP R25
(2C1)
X-RAYS OFF = LO R11(1D4)
6 (1D5)
(1D4) (Normal charge) 5.1 VDC +200
Q1
(1B5) R26 See Precharge R10 volt
14 TP1 See KV Block Diagram
Block Diagram sense
Reference Drawing R2 Volt X-Ray Regulator PCB
Mainframe Interconnect Diagram 4 Feedback
U2 (1D4) Charger Current
875500 (1C8) 4
(1B7) R1 Current
CR7
(1C6) Q7 Line Sense
J2 Sensor
1 Charger Disable
2 16
6 HI = Charger Disabled
Overvoltage P4 18 24 23 22
R2 C4 130 to 160 VDC Protection TP2
(1B4) Mother PCB 875539
(1B6) Q6, Q8, Volt
+ U1, U3, P6 37 43 42 41
1 Sense 42
(1D5) CR6 P2 37 43 41
7.5 VDC
DS1 DS2 Analog Interface PCB
R7
BATTERY CHARGER ADJUSTMENT PROCEDURE: VOLTS (1D7) MILLIAMPS (1D6) 876738 (2B7) 18 10 9 8
(1B6)
U27 PIO U3 Sample Mux
160
170
180
190
200
210
220
230
240
250
100
105
220
320
450
625
25
40
50
75
1. CONNECT A DVM FROM J1-1 TO CHASSIS GROUND. R8 C9 (1D6)
2. ADJUST R10 FOR 220 VOLTS ON THE DVM.
3. ADJUST R32 UNTIL THE 220 VOLT SEGMENT ON DS1 GOES OFF AND 9600 C-Arm
THE 210 VOLT SEGMENT LIGHTS.
4. ADJUST R32 UNTIL THE 210 VOLT SEGMENT GOES OUT AND THE
220 VOLT SEGMENT JUST LIGHTS. CHGBLK.DS4 12/3/96
5. ADJUST R10 FOR 225 VOLTS ON THE DVM.
9600 Battery Charger Block Diagram
Serial # 69-0001 to 69-1000
BATTERY CHARGER ERROR MESSAGES
REMEMBER, CHARGER OUTPUT VOLTAGE
P5 CHARGER OUTPUT
IS MEASURED THRU +200 SENSE
NORMAL = 225 VDC
RECHARGE NEEDED -ALLOW 24 HOURS HI CHARGE = 230 VDC
(R11/R10 JUNCTION ON GENERATOR DRIVER PCB
TO U3-8 ON ANALOG INTERFACE PCB)
PRESS ANY KEY TO CONTINUE
THIS MESSAGE IS DISPLAYED DURING BOOT UP IF THE SYSTEM
HAS NOT BEEN TURNED ON FOR 6 MONTHS.
IF 6 MONTHS HAVE PAST SINCE THE SYSTEM HAS BEEN

PLUGGED IN AND TURNED ON, LET THE SYSTEM RUN
WITHOUT MAKING X-RAYS FOR 24 HOURS TO ALLOW THE
BATTERIES TO RECHARGE AND THE IMAGE TUBE TO DEGAS.
THIS ERROR MAY ALSO BE DISPLAYED AFTER INSTALLING C-4 FILTER CAP VOTAGE
A COPY OF THE BACKUP GENERATOR SOFTWARE, MIN. LOAD = 160 VDC
IN THIS CASE PRESS ANY KEY ON THE CONTROL PANEL AND MAX. LOAD = 130 VDC
CONTINUE USE AS NORMAL.
TP1 VOLTAGE FEEDBACK
NORMAL = 5.15 VDC (MIN. CURRENT)
P5 HI CHARGE = 4.55 VDC (MAX. CURRENT)
WARM-UP NEEDED - ALLOW 4 HOURS R10 CHARGER OUTPUT

PRESS ANY KEY TO CONTINUE VOLTAGE ADJSUTMENT
THIS MESSAGE IS DISPLAYED DURING BOOT UP IF THE SYSTEM

HAS NOT BEEN TURNED ON FOR 2 MONTHS.
IF 2 MONTHS HAVE PAST SINCE THE SYSTEM HAS BEEN

PLUGGED IN AND TURNED ON, LET THE SYSTEM RUN R8 LINE SENSE
WITHOUT MAKING X-RAYS FOR 4 HOURS TO ALLOW THE 7.5 VDC = NORMAL
BATTERIES TO RECHARGE AND THE IMAGE TUBE TO DEGAS. LINE VOLTAGE
TP2 VOLT SENSE
NORMAL = 3.3 VDC
THIS ERROR MAY ALSO BE DISPLAYED AFTER INSTALLING (CHARGER OUTPUT @ 225 VDC)
A COPY OF THE BACKUP GENERATOR SOFTWARE,
IN THIS CASE PRESS ANY KEY ON THE CONTROL PANEL AND HI CHARGE = 4.2 VDC
CONTINUE USE AS NORMAL. (CHARGER OUTPUT @ 230 VDC)
P4 R10
R6
TP1
BATTERY DISCONNECTED
THIS MESSAGE IS DISPLAYED DURING BOOT UP (-1 ARROWS) R8 TP2
IF THE SOFTWARE THINKS THE BATTERIES ARE DISCONNECTED. U2-14
THIS IS CHECKED BY DISABLING THE BATTERY CHARGER AND
WAITING FOR 2 SECONDS, THE +200 VOLT SENSE LINE IS THEN
READ. IF 180 VOLTS OR LESS IS READ, THE SOFTWARE ISSUES U2
A SHUTDOWN COMMAND AND DISPLAYS THE
" BATTERIES DISCONNECTED" MESSAGE. TP3 CURRENT SENSE
MIN. CURRENT = .08 VDC
IF THE BATTERIES ARE DISCONNECTED OR CB1 IS OPEN U3 (CHARGER OUTPUT = 25 MA)
CR7
R25
THE ERROR "PRECHARGE FAIL" MAY BE DISPLAYED INSTEAD OF
BATTERIES DISCONNECTED. MAX. CURRENT = 5.2 VDC
TP3
2 V dc PWM OUTPUT DRIVE PULSES TO Q1 (CHARGER OUTPUT = 2.5 AMPS)
20 us
CHARGER FAILED
THIS MESSAGE IS DISPLAYED IF THE SOFTWARE SENSES THAT
THE BATTERY VOLTAGE IS LESS THAN 225 VOLTS AND THAT
THE CHARGER OUTPUT CURRENT IS LESS THAN 1.0 AMPS.
R6
THE SOFTWARE CHECK FOR CHARGER FAILURE RUNS IN THE U2-4 R32 CHARGER OUTPUT
BACKGROUND ALL THE TIME EXCEPT DURING X-RAYS.
70% CHARGE
THIS MESSAGE IS DISPLAYED IF THE SOFTWARE THINKS THAT
DS2
DS1
THE CHARGE CAPACITY OF THE BATTERIES HAS BEEN
DEPLETED TO 70% OR LESS.
THE 70% CHARGE MESSAGE IS DISPLAYED INTERMITTANTLY ON
THE CONTROL PANEL AND DOES NOT AFFECT 500 mV dc
SYSTEM OPERATION. 20 us CURRENT SENSOR INPUT TO PWM
R25
HIGH CHARGE MODE
50% CHARGE
THIS MESSAGE IS DISPLAYED IF THE SOFTWARE THINKS THAT 9600 C-Arm
THE CHARGE CAPACITY OF THE BATTERIES HAS BEEN CR7 CATHODE "CHARGER DISABLE"
DEPLETED TO 50% OR LESS. CHARGER ON = 0 VDC (THE CHARGER IS ON ALL THE TIME EXCEPT DURING
CHARGER OFF = 3 VDC DURING FILM EXPOSURES AND FOR A SHORT TIME R32 VOLTAGE DISPLAY ADJUSTMENT
THIS PAGE GIVES THE LAYOUT
THE 50% CHARGE MESSAGE IS DISPLAYED INTERMITTANTLY ON TIME AT THE END OF THE STSTEM BOOT PROCESS.)
THE CONTROL PANEL, SYSTEM OPERATION IN FLUORO MODE IS FOR THE 877997 PCB. REFER TO THE CHGBLK.DS4 12/3/96
ALLOWED BUT FILM EXPOSURES ARE SUSPENDED UNTIL THE POWER DISTRIBUTION SECTION
CALCULATED CHARGE OF THE BATTERIES RISES ABOVE 50%.
IN THE SERVICE MANUAL 9600 Battery Charger
FOR THE OLDER PCB LAYOUT. Signal Sheet
Battery Packs
Red Blue Black
(1B8)
T1
C26, CR9, CR10 Sch. #877995
(1A7)
(1B6) CB1
(1A6)
L1 P5 (1C8)
+12SEP CR3
VR3 VR1 T2 1
C10 C11
Power / Signal Interface PCB (1B4) TP3
877998 VR2 -12SEP (1D8) Current
F1 K2 (1B6)
10 Amp P1 P2 Low Pass Sense (1B7)
Lemo Current Ideal Diode
+
(1B4)
Filter
Connector Limiters 3 3
U4, CR8, Q9
R19 U4, C17
(1B3)
J1 (1C7) Current R18 6 5 C2
CB3
(1D1)
P12 Low Voltage Cutoff Sensor (1C4)
10 AMP LF2 RT2 (1C7)
19 115_VAC_RET 1 +12SEP
voltage falls below 160 VDC K1 (1B6) R1
(1B5) (1C6)
RT1 R48, R16, CR11, Q10
R37 6 n.o.
13 115_VAC_PH 4 + Q2
+
CR1 (1C5)
(1B5) 2
CB2 (1B7) 7 U5 + 3 1.1 VDC
10 AMP R39 3 n.c. 9 C3
22 GROUND
2 1 (1B7)
R6
16 CHASSIS 4 4 L2
(2A7) R10 See Precharge Control Block Diagram
3 Charger 14
2 2 P1
(1A4) X-Ray Regulator PCB
Output R32 877458
Adjust U3 (1D5) Generator
(1A5)
15 J3 CR6 F3
Display (Hi charge) PCB
(1C6)
2
CR2 Adjust 877461
E1 -12SEP (2C1)
X-RAYS OFF = LO R11(1D4)
6 (1D4) R25 (Normal charge) 5.1 VDC
Q1 (1D5)
+200
(1B5) R26 See PrechargeR10 volt
Block Diagram sense
Mainframe Interconnect Diagram 4 Feedback 4 Charger Current
U2 (1D4)
#877972 or #878376 (1B7) R1 Current (1C8) 1 Line Sense
CR7
(1C6) Q7
J4 Sensor 6 Charger Disable
2 16 HI = Charger Disabled
P4 12 35 31 34
Overvoltage
Mother PCB 875539 or 878396
(1B4) P6 37 43 42 41
(1B6) Q6, Q8, Volt
+ P2 37 43 42 41
1 U1, U3, Sense
(1D5) CR6 Analog Interface PCB
7.5 VDC
DS1 DS2 876738 (2B7) 18 10 9 8
R7
VOLTS (1D7) MILLIAMPS (1D6) U27 PIO U3 Sample Mux
(1B6)
BATTERY CHARGER ADJUSTMENT PROCEDURE: (1D6)
100
105
220
320
450
625
160
170
180
190
200
210
220
230
240
250
25
40
50
75
R8 C9
1. CONNECT A DVM FROM P5-1 TO CHASSIS GROUND.
2. ADJUST R10 FOR 220 VOLTS ON THE DVM. 9600 C-Arm
3. ADJUST R32 UNTIL THE 220 VOLT SEGMENT ON DS1 GOES For Reference Only Page 3 of 3
OFF AND THE 210 VOLT SEGMENT LIGHTS.
4. ADJUST R32 UNTIL THE 210 VOLT SEGMENT GOES OUT AND THE CHGBLK.DS4 12/3/96
220 VOLT SEGMENT JUST LIGHTS.
5. ADJUST R10 FOR 225 VOLTS ON THE DVM. 9600 Battery Charger Block Diagram
Serial # 69-1001 and Higher
Battery Packs
Red Blue Black
(1B8)

T1
C26, CR9, CR10 877458
(1A7)
(1B6) CB1
(1A6) (1C8)
+12SEP L1 P5
VR3 VR1 T2 CR3
1
C10 C11
Power / Signal Interface PCB (1B4) TP3
877998 VR2 -12SEP (1D8)
Current F1 K2 (1B6)
10 Amp P1 P2 Low Pass
Ideal Diode Sense (1B7)
Lemo Filter
+
Current (1B4)
Connector Limiters U4, CR8, Q9 U4, C17
3 3 (1B3)
R19
J1 (1C7) Current R18 6 5 C2
(1D1) CB3 (1C4)
P12 Low Voltage Cutoff Sensor
10 AMP LF2 RT2 (1C7)
19 115_VAC_RET1 +12SEP
voltage falls below 160 VDC K1 (1B6) R1
(1B5) (1C6) R48, R16, CR11, Q10
RT1 6 n.o.
13 115_VAC_PH 4 + R37
Q2
+
CR1 (1C5)
(1B5) 2
CB2 7 1.1 VDC
10 AMP
(1B7)
U5 + 3 R39 9
22 GROUND 3 n.c. C3
2 (1B7)
1
16 CHASSIS R6
4 4 L2
(2A7) R10 See Precharge Control Block Diagram
3 Charger 14
2 2 P1 (1A4) X-Ray Regulator PCB
Output 877458
R32 Generator
Adjust U3 (1D5)
(1A5)
Display 15 J3 CR6 F3 (1C6)
2 (Hi charge) PCB
CR2 Adjust
(2C1) 877461
E1 -12SEP X-RAYS OFF = LO R11(1D4)
6 (1D4) R25 (Normal charge) 5.1 VDC
Q1 +200
(1D5)
(1B5) R26 See PrechargeR10 volt
Block Diagram sense
4 Feedback
Mainframe Interconnect Diagram U2 (1D4)
4 Charger Current
#877972 or #878376 (1B7) R1 Current (1C8) 1 Line Sense
(1C6) Q7
Sensor CR7 6 Charger Disable
J4
2 16 HI = Charger Disabled
P4 12 35 31 34
Overvoltage
Mother PCB 875539 or 878396
(1B6) Q6, Q8, Volt
(1B4) P6 37 43 42 41
+ 1 U1, U3, P2 37 43 42 41
Sense
(1D5) CR6 Analog Interface PCB
7.5 VDC
DS1 DS2 876738 (2B7) 18 10 9 8
R7
VOLTS (1D7) MILLIAMPS (1D6) U27 PIO U3 Sample Mux
(1B6)
BATTERY CHARGER ADJUSTMENT PROCEDURE: (1D6)
100
105
220
320
450
625
160
170
180
190
200
210
220
230
240
250
25
40
50
75
R8 C9
1. CONNECT A DVM FROM J1-1 TO CHASSIS GROUND.
2. ADJUST R10 FOR 220 VOLTS ON THE DVM. 9600 C-Arm
3. ADJUST R32 UNTIL THE 220 VOLT SEGMENT ON DS1 GOES For Reference Only Page 3 of 3
OFF AND THE 210 VOLT SEGMENT LIGHTS.
4. ADJUST R32 UNTIL THE 210 VOLT SEGMENT GOES OUT AND THE CHGBLK.DS4 6/4/96
220 VOLT SEGMENT JUST LIGHTS.
5. ADJUST R10 FOR 225 VOLTS ON THE DVM. 9600 Battery Charger Block Diagram
Serial # 69-1001 and Higher
CONTROL PANEL ASSEMBLY
X-RAY CONTROL PANEL POWER/SIGNAL MOTHERBOARD ANALOG INTERFACE PCB MOTHERBOARD

SWITCH PROCESSOR PCB INTERFACE PCB SCH. #875539 SCH. #876738 SCH. # 875539
P5 SCH. # 875601 P4 SCH. #876001
OR #877998 R33 & C36 (2C7)
XRAY REGULATOR PCB
2 14 X-RAY SWITCH 13 16 16 300MS. 1 U25 2 3 U24 2
DELAY SCH. #877458
J6 P2 CIRCUIT (2B7) (2B7)
(2C8) CR12
4 2 SECURITY 1 18 18 16 16 1 U51 7
L
5 +5V TP20 P4 P3
(2C7) P2 J6 L
84 84 4 U50 6
P10 P9 P1 9 26 26 XRAY EN 7 7 3
8 XRAYEN 1 3
U41 U6
U35
L 10 (2B5) GAL
P7 1
L (1B8)
86 86 1 12 8 8 13 11
2 2 BOOST 4 4 U52 6 3 11 XRAYON 27 27 XRAY ON 2 (1B7)
BOOST SW2 U6
2 U21 U41 12
SCOUT 3 3 FLUORO ONLY 8 85 85 1 U50 7 13 (2B5)
L (2B5)
FLUORO SW3 P2
L
1 1 SAVE(L/R) 6 81 81 1 U52 7 L
SAVE SW1
(2C8) 26 5
PROCESS 6 6 X-RAY SWITCH 2 24 U7
FLUORO SW4 15
U27 KV PAL
D 0-7 PIO +5V +12V
7 7 SECURITY 10 12 XRYDISBL 88 88 XRAYINH 9 TP22 TP23 4
U38 (2B7) (1B7)
4 4 I SOURCE 16 100 100 3 U25 4 10 PIO
(2C7)
P2 J2 (2D7) L=XRAY ALLOWED 3
FOOTSWITCH TP 5 -12V U10
9 U25 8 11 TP24 FIL PAL
P3 J3 (2C6) 2
2 2 L (2D4) (1A7)
PROCESS BOOST 3
6 TP27
BOOST 5 12
SW1 7 7 SECURITY 9 U25 U22
(2C7) PIO 40 101 101 STORE 13
13
SCOUT 3 3 FLUORO ONLY 7 (2D7) P1
FLUORO SW2
10 15 U1 16 X-RAY_LAMP
L P1
DATA BUS TO/FROM
+5V CR1 (1C6)
SAVE TECHNIQUE PROCESSOR 17 27 9
SW3 1 1 SAVE (L/R) 5 R40
1 3 REFER TO TECHNIQUE PROCESSOR/
FL2
4 4 I SOURCE 15 ANALOG INTERFACE (1B5)
POWER/MOTOR
(2C8)
BLOCK DIAGRAM FOR DETAILS 8 P2 RELAY PCB
SCH. #875997
HANDSWITCH POWER PANEL
+5V +12V +15V
TP 1, 2,21, 22 TP24 TP25 TP23
1 CONTROL PANEL POWER/SIGNAL

U50, 51, &52 PROCESSOR PCB INTERFACE PCB
OPTOCOUPLERS SCH. # 875601 SCH. #876001
P4 P10 P9
INPUT
C-ARM +5V 16 15
OR #877998
17
OUTPUT
REFERENCE TO CAMERA
P5 1 3
9600 C-ARM
A LOGIC HIGH INPUT
INTERCONNECT DIAGRAM 9600 C-ARM
SCH. #875500
GIVES A LOGIC LOW OUTPUT
OR #877972 For Reference Only Page 1 of 3
XRAY_ON.DS4 6/20/96
LAMP IN X-RAY
SWITCH ON XRAY-ON / DISABLE
CONTROL PANEL 3 3 3 3
X-RAY COLUMN I/O PCB POWER/SIGNAL MOTHERBOARD ANALOG INTERFACE PCB MOTHERBOARD
SWITCH SCH. #878492 INTERFACE PCB SCH. #878396 SCH. #876738 SCH. # 878396
P10 P4 SCH. #877998
CR2 R33 & C36 (2C7)
XRAY REGULATOR PCB
2 14 X-RAY SWITCH 13 16 14 300MS. 1 U25 2 3 U24 2
DELAY SCH. #877458
J6 P2 CIRCUIT (2B7) (2B7)
CR1 (2C8) CR12
4 2 SECURITY 1 18 17 16 16 1 U51 7
L
5 TP20 P4 P3
(2C7) P2 J6 L
+5V 84 84 4 U50 6
P10 P9 P5 9 26 26 XRAY EN 3 7 3
8 XRAYEN 1 3
U41 U6
U35
L 10 (2B5) GAL
P7 1
L (1B8)
86 86 1 12 28 8 13 11
2 2 BOOST 4 4 U52 6 3 11 XRAYON 27 27 XRAY ON 2 (1B7)
BOOST SW2 U6
2 U21 U41 12
SCOUT 3 3 FLUORO ONLY 8 85 85 1 U50 7 13 (2B5)
L (2B5)
FLUORO SW3 P2
L
1 1 SAVE(L/R) 6 81 81 1 U52 7 L
SAVE SW1
(2C8) 26 5
PROCESS 6 6 X-RAY SWITCH 2 24 U7
FLUORO SW4 15
U27 KV PAL
D 0-7 PIO +5V +12V
7 7 SECURITY 10 12 XRYDISBL 88 88 XRAYINH 9 TP22 TP23 4
U38 (2B7) (1B7)
4 4 I SOURCE 15 100 100 3 U25 4 10 PIO
(2C7)
P2 J2 (2D7) L=XRAY ALLOWED 3
FOOTSWITCH TP 5 -12V U10
9 U25 8 11 TP24 FIL PAL
P3 J3 (2C6) 2
2 2 L (2D4) (1A7)
PROCESS BOOST 3
6 TP27
BOOST 5 12
SW1 7 7 SECURITY 9 U25 U22
(2C7) PIO 40 101 101 STORE 13
13
SCOUT 3 3 FLUORO ONLY 7 (2D7) P1
FLUORO SW2 16 X-RAY_LAMP
L 10 15 U1
P5
DATA BUS TO/FROM
+5V CR1 (1C6)
SAVE TECHNIQUE PROCESSOR 16 27 9
SW3 1 1 SAVE (L/R) 5 R40
1 3 REFER TO TECHNIQUE PROCESSOR/
FL2 (1B5)
4 4 I SOURCE 14 ANALOG INTERFACE POWER/MOTOR
(2C8)
BLOCK DIAGRAM FOR DETAILS 8 P2 RELAY PCB
SCH. #875997
HANDSWITCH POWER PANEL
+5V +12V +15V
TP 1, 2,21, 22 TP24 TP25 TP23
COLUMN I/O PCB POWER/SIGNAL

1
U50, 51, &52 C-ARM SCH. # 878492 INTERFACE PCB
SCH. #877998
OPTOCOUPLERS P4 P10 P9
+5V 16 15 17
REFERENCE TO
INPUT 9600 C-ARM
OUTPUT
INTERCONNECT DIAGRAM P10 1 3 CAMERA
SCH. #878376
A LOGIC HIGH INPUT

USE THIS PAGE FOR SERIAL NUMBERS 9600 C-ARM
GIVES A LOGIC LOW OUTPUT
62-0001 AND HIGHER For Reference Only Page 2 of 3
XRAY_ON.DS4 6/20/96
LAMP IN X-RAY
SWITCH ON
CONTROL PANEL XRAY-ON / DISABLE
3 3 3 3
2 2 2 2
1 1 1 1
POWER PANEL
ON C-ARM
INTERCONNECT CABLE
AUXILIARY INTERFACE
SCH. #876502
L=XRAY ALLOWED L=XRAY ALLOWED
VIDEO SWITCHING
SCH. #872237 (1D8) TP14 P10
13 12 (1D8)
XRAYDIS* P9-1 13
U1 11 (1D7) 8 XRAYINH
12 U5
10 STORE*
L=VIDEO PRESENT +5
(1B8) U33
TP35 SER-PAR IMAGE PROCESSOR 1 VIDEO
(1B7) R9 (1D8)
14 REG. 4 J8-1 SCH. #875952 1
P6-11 1 6 2
5 U42 U1
+5
VMDAT (1B7)
+5 H R17 TP13
R155 CR4 LED ARRAY ON TOP
U3 18 X-RAY _LAMP*
1 OF WORKSTATION
9 PIO #2 2 2
J8-2 7 7 19 (1D6) +12V +5V J9 P9 J11 P11
U42 8 XRAY_ON 3
10 (2D2) 14 P6-11 R13
(1D8) E1 1 3 1 13 13 2 2
(1A8) VMDAT D E3 2
5 2 25 25 3 3
18 6
U38 5 2 U28 13 5 5 SYNCDET U1 3 4
(2A7)
(1D8) U1
(2B8) P8
9 P6 P6 H=SYNC PRESENT D
AT COMM PCB
SCH. #872125
SEPINCSY P6-1 9 U1 8
DRINTLK
U17 INPUT FROM (1B5)
(1D6) U13 P3
(1D3) (4C4) A:D ROOM P14 U14
TP10 MUX R4
1 TP16 TP3 INTERFACE LATCH
(4C3)
5 (1D6) 20 2 8 1
J6 U6 J11-5 P4-5 VIDEO IN (1A5)
U15 +5 20 20 4
SYNC 5 A/D XRAYINH
STRIP
(1D4)
VIDEO
TP7
WORKSTATION
(1D5) AGND
REFERENCE TO
XRAYON 6 9600 WORKSTATION
TP25,23,
P9-2 STORE* 22 STORE* 22 INTERCONNECT DIAGRAM
+5V -5V +12V -12V
39,40 SCH. # 876158
TP27 TP24 TP28, 31 TP19
OR #877970
VIDEO P1
U26
DUART
7 DRINTLK 7 2
(1C5)
+5V -5V +12V -12V TP1-4

TP2 & 16 TP15 TP1&6 TP9
TP 3-5,7-8
9600 C-ARM
E1 NORMALLY JUMPERED 1-2 For Reference Only Page 3 of 3
2
WOULD ONLY BE JUMPERED 2-3 IF XRAY_ON.DS4 6/20/96
DOOR INTERLOCK SIGNAL AT P6-1
NEEDED TO BE INVERTED
XRAY-ON / XRAY DISABLE
2A
TP20 XRAYSW
Normally high, goes low when Process
2A
U41-8 XRAYEN Fluoro footswitch or control panel
X-ray switch is pressed.
TP23
Normally low, goes high when TP1 +15
GND
Boost, Scout, Process, Fluoro GND
or control panel X-RAY Switch TP21
9 10 11 12 14 15
U38-10 (X-RAY
2A SW)
is pressed. U35
DS1
Normally low, goes high when Process
2A TP20 Fluoro footswitch or control panel
U41-11 XRAYON 8 9 10 11 12 13
U41 XRAY SW X-ray switch is pressed.

3 2 2 1
Normally low, goes high when U24 U25

U27-24 CPU Verified X-ray goes low
after Boost, Scout, Process, Fluoro 2J
2A
or control panel X-ray Switch is pressed. U38-11 (BOOST)
U22 U27 U38 2F
3 12 13 12 11 10 Normally low, goes high when
2A
TP28 VIDSTBL 40 24 Boost is pressed.
TP28
VID STBL
Normally low, goes high2F when X-rays 6 5
are turned on until video level stabilizes
TP27 U23
then goes low. TP24 STORE
+5 2A
U38-12 (SCOUT FLUORO)
Normally low, goes high when

TP27 STORE 2A Scout is pressed.
Normally High,
goes Low when X-rays are on,
goes High when X-rays are off.
2A
Last Image Hold = High U27-12 (X-RAY DISABLE)
GND
TP22 Normally low, goes high to disable X-rays.
2A Selecting PULSE MODE causes this line
+12
U27-24 (CPU Verified X-ray On) TP25
to toggle high and low at an
4 pulse per second rate.
GND
Normally high, goes low when CPU receives TP2
X-ray on command from U38-10 (XRAYSW) 9600 C-ARM

XRAYONSS.DS4 12/4/96
X-RAY ON / DISABLE
SIGNAL SHEET
9600 Mobile Digital C-Arm - Image System Block Diagrams, Test Points, and Waveforms
POWER &
FIELD SIZE P4
IMAGE SELECT IMAGE
INTENSIFIER FUNCTION
& PCB
POWER SUPPLY
CAMERA
MOTORS P3 P1
& CONTROL
CCD CAMERA
IRIS
COLLIMATOR
P5
P2 P3 P2
VIDEO
CONTROL
J1 P1 HARDCOPY
CAMERA
PIXEL FILTER PCB TECHNIQUE AND
ANALOG VCRS
OR PROCESSOR
INTERFACE
PIXEL/COLUMN PCB
PCB
FILTER PCB
TP1 & TP6 VIDEO IS
J2 VIDEO LEVEL ALWAYS INTERLACE
SERIAL FORMAT
P3
COMMUNICATIONS
CAMERA GAIN P2 TP10 TP18 TP3 TP1 P4 TP20 TP2
L
TO LEFT VIDEO BNC
HIGH VOLTAGE ON REAR PANEL
VIDEO CABLE ASSY. VIDEO INTERCONNECT IMAGE VIDEO
P1 J11 P4 PROCESSOR SWITCHING
CABLE P.10-1 J6
MAINFRAME AUX. VIDEO BOARD BOARD
INTERFACE SWITCHING P4
MOTHERBOARD R TO RIGHT VIDEO BNC
BOARD BOARD P9 TP6 TP17 TP4 ON OLDER REAR
PANEL
DIGITAL RIGHT VIDEO DIGITAL LEFT VIDEO

LEFT
J2 TP2 FASTSCAN
J4 MONITOR
IMAGE SYSTEM INTERCONNECT MAINFRAME INTERCONNECT WORKSTATION INTERCONNECT
FAST SCAN
CONVERTER
TP2 TP2 RIGHT
TO FAST SCAN BNC
J8 J5
ON REAR PANEL FASTSCAN
MONITOR
VIDEO TO THE LEFT & RIGHT
MONITORS IS ALWAYS
HIGH SCAN NON-INTERLACED
VIDEO
REFER TO
STATOR RELAY / STATOR SENSE BLOCK DIAGRAM
FOR DETAILS OF X-RAY TUBE WIRING
9600 C-ARM
USE THIS PAGE FOR
SERIAL NUMBERS 4/9/96
96VIDOVR.DS4
69-0001 TO 69-2000
9600 IMAGE SYSTEM OVERVIEW

BLOCK DIAGRAM
9600 Mobile Digital C-Arm - Image System Block Diagrams, Test Points, and Signal Waveforms
IMAGE POWER &

INTENSIFIER FIELD SIZE
& SELECT
POWER SUPPLY
CAMERA
MOTORS
CCD CAMERA & CONTROL
P2 P3
VIDEO
J1 IRIS HARDCOPY
COLLIMATOR CAMERA
E1
AND
IMAGE ANALOG TECHNIQUE
FUNCTION VCRS
PIXEL FILTER PCB INTERFACE PROCESSOR
PCB PCB PCB
TP1 & TP6 VIDEO IS
J2 ALWAYS INTERLACE
P6 VIDEO LEVEL
FORMAT
CAMERA SERIAL
ASSEMBLY COMMUNICATIONS
TP10 TP18 TP3 TP1 P4 TP20 TP2
CAMERA GAIN L
TO LEFT VIDEO BNC
VIDEO ON REAR PANEL
J1 INTERCONNECT IMAGE
HIGH VOLTAGE P3 P1 J11 P4 PROCESSOR SWITCHING
CABLE P.10-1 J6
P1 MAINFRAME AUX. VIDEO
CABLE ASSY. BOARD P4 BOARD
MOTHERBOARD INTERFACE SWITCHING R
BOARD BOARD P9 TP6 TP17 TP4
P2 J2
VIDEO VIDEO
DIGITAL RIGHT VIDEO DIGITAL LEFT VIDEO
LEFT
IMAGE SYSTEM INTERCONNECT J2 TP2 FASTSCAN
J4 MONITOR
MAINFRAME INTERCONNECT WORKSTATION INTERCONNECT
FAST SCAN
CONVERTER
TP2 TP2 RIGHT
TO FAST SCAN BNC J5
J8 FASTSCAN
ON REAR PANEL
MONITOR
VIDEO TO THE LEFT & RIGHT
MONITORS IS ALWAYS
HIGH SCAN NON-INTERLACED
VIDEO
REFER TO
STATOR RELAY / STATOR SENSE BLOCK DIAGRAM
FOR DETAILS OF X-RAY TUBE WIRING
9600 C-ARM
USE THIS PAGE FOR
SERIAL NUMBERS 96VIDOVR.DS4 4/9/96
62-0001 AND HIGHER 9600 IMAGE SYSTEM OVERVIEW
BLOCK DIAGRAM
TECHNIQUE PROCESSOR PCB ANALOG INTERFACE PCB
SCH. #876735 OR 877742 SCH. #876738
MOTHER BOARD MOTHER BOARD IMAGE FUNCTIONS PCB
SCH.# 875539 0 - 10V SCH.# 875539 SCH. #874750
P2 J6 P3 P1 CCD CAMERA
P2 J5 J6 P2 P3 P2
U3
A/D_0-7 A/D_0-7 22 VLI 54 54 VIDEO_LEVEL 1 VIDEO_LEVEL 23 10 VIDEO LEVEL
U31 U7 7
MICROPROCESSOR U8
(5D7)
(1D6)
U30
(1C5) SAMPLE MUX 0 - 10V
DATA BUS DUAL & A/D CONVERTER
PORT TP24
RAM +5V
80C188 TP13
U18
J3 P1 (1B6) 25 6
- CAM_GAIN 56 56 2 6 CAMERA_GAIN 20 9 CAMERA_GAIN
P1 J2 +
U29
(1A4)
TP23 TP25
D/A CONVERTER +15V +12V
TP19
P4
ABS SOFTWARE RESIDING IN RAM U31 25 6
- KVPCONT 47 47 28
WILL ATTEMPT TO KEEP THE CAMERA VIDEO (1B6) +
U33 (1A4) TP18
CONSTANT BY CONTROLLING 23 2
KV,MA, & CAMERA GAIN IN THE AUTO MODE - MACONT 53 53 34 P5 3
+
OR CAMERA GAIN ONLY IN THE MANUAL MODE U33 (1A4)
D/A CONVERTER
TP28 (2D3) P2
P1 8
U22 3 5 6 VIDSTBL 89 89 VIDSTAB* 10
(2D7) SEE CAMERA VIDEO &
U23 TP1 TP2 TP21 TP22 PIXEL/COLUMN FILTER PCB
BLOCK DIAGRAM
FOR DETAILS OF
PIO THIS CIRCUITRY
PIXEL/COLUMN
FILTER PCB
SCH. # 878045
OBJECT
VIDSTAB* NOTE: THE PIXEL/COLUMN FILTER PCB

WAS NOT INSTALLED ON ALL SYSTEMS
386 AT AT COMMUNICATIONS PCB

MOTHERBOARD SCH. #872125
AUXILIARY
INTERFACE PCB
SCH. #876502 J0 (876158)
1
P1 (877970)
(1D7)
U27 TP10 J14 P14
(1B5) P3 P14 P10
U14
DATA BUS 39 15 (1A5) 5 19 19 VIDSTAB* 9 4 4 INTERCONNECT 7 X-RAY REGULATION CIRCUITRY
CABLE
SEE KV AND MA BLOCK DIAGRAMS
TP7
LATCH FOR DETAILS
LEMO
DUART CONNECTOR REFERENCE TO
IMAGE SYSTEM INTERCONNECT DIAGRAM
TP 1, 2, 3, 4 SCH. # 875410 OR #877971
ELECTRONICS BOX PANEL
(LOWER REAR RIGHT)
9600 C-ARM
REFERENCE TO For Reference Only Page 1 of 2
C-ARM (MAINFRAME)
INTERCONNECT DIAGRAM USE THIS PAGE FOR ABSLOOP.DS4 4/12/96
SCH. # 875500 OR #877972 SERIAL NUMBERS
REFERENCE TO
WORKSTATION INTERCONNECT DIAGRAM 69-0001 TO 69-2000
1
SCH. # 876158 OR #877970 ABS LOOP
TECHNIQUE PROCESSOR PCB ANALOG INTERFACE PCB
SCH. #877742 SCH. #876738
MOTHER BOARD MOTHER BOARD
SCH.# 878396 0 - 10V SCH.# 878396
P2 J6 P1 CCD CAMERA
P2 J5 J6 P2 P3 J2 P2
U3
A/D_0-7 A/D_0-7 22 VLI 54 54 VIDEO_LEVEL 27 19 19 10 VIDEO LEVEL
U31 U7
MICROPROCESSOR U8
(5D7)
(1D6)
U30
(1C5) SAMPLE MUX 0 - 10V
DATA BUS DUAL & A/D CONVERTER
PORT TP24
RAM +5V
80C188 TP13
U18
J3 P1 (1B6) 25 6
- CAM_GAIN 56 56 CAMERA_GAIN 26 18 18 9 CAMERA_GAIN
P1 J2 +
U29
(1A4)
TP23 TP25
D/A CONVERTER +15V +12V
TP19
P4
ABS SOFTWARE RESIDING IN RAM U31 25 6
- KVPCONT 47 47 37
WILL ATTEMPT TO KEEP THE CAMERA VIDEO (1B6) +
U33 (1A4) TP18
CONSTANT BY CONTROLLING 23 2
KV,MA, & CAMERA GAIN IN THE AUTO MODE - MACONT 53 53 14
+
OR CAMERA GAIN ONLY IN THE MANUAL MODE U33 (1A4)
D/A CONVERTER
TP28 (2D3) P2
U22 3 5 6 VIDSTBL 89 89 VIDSTAB* 10

(2D7)
U23 TP1 TP2 TP21 TP22
PIO
OBJECT
VIDSTAB*
386 AT AT COMMUNICATIONS PCB

MOTHERBOARD SCH. #872125
AUXILIARY
INTERFACE PCB
SCH. #876502
(1D7) P1
U27 TP10 J14 P14
(1B5) P3 P14 P10
U14
DATA BUS 39 15 (1A5) 5 19 19 VIDSTAB* 9 4 4 INTERCONNECT 7 X-RAY REGULATION CIRCUITRY
CABLE
SEE KV AND MA BLOCK DIAGRAMS
TP7
LATCH FOR DETAILS
LEMO
DUART CONNECTOR REFERENCE TO
IMAGE SYSTEM INTERCONNECT DIAGRAM
TP 1, 2, 3, 4 SCH. # 878377
ELECTRONICS BOX PANEL
(LOWER REAR RIGHT)
9600 C-ARM
USE THIS PAGE FOR
REFERENCE TO
SERIAL NUMBERS ABSLOOP.DS4 4/12/96
C-ARM (MAINFRAME)
REFERENCE TO INTERCONNECT DIAGRAM 69-2001 AND HIGHER &
WORKSTATION INTERCONNECT DIAGRAM SCH. # 878376 62-0001 AND HIGHER
SCH. #877970 ABS LOOP
GND
TP1 ANALOG INTERFACE PCB A
THE VIDEO LEVEL SIGNAL VARIES
FROM 1 VOLT WITH X-RAYS OFF
TO 6 VOLTS WITH X-RAYS ON.
TYPICAL VIDEO LEVEL VOLTAGE IS
TP21
GND
5.75 - 6.0 VOLTS DC DURING X-RAYS.
U3
AUXILIARY INTERFACE PCB
DS1
TP7
GND
22
A
B THE CAMERA GAIN SIGNAL
VARIES FROM 0 TO 6 VOLTS DC
AS REQUIRED BY THE ABS
SOFTWARE TO GET A VIDEO LEVEL
SIGNAL OF APPROX. 6 VOLTS FROM
THE CAMERA VIDEO PCB.
3
C
U22
THE MA CONTROL SIGNAL WILL

U7
ADJUST UP OR DOWN AS THE ABS
P14
SOFTWARE ON THE TECHNIQUE
PROCESSOR MAKES ADJUSTMENTS
VID STBL
E TO ACHIEVE THE PROPER VIDEO

U8
TP28
LEVEL SIGNAL
U23
D THE KV CONTROL SIGNAL WILL

ADJUST UP OR DOWN AS THE ABS
VIDSTB*
TP10
SOFTWARE ON THE TECHNIQUE E
PROCESSOR MAKES ADJUSTMENTS
P10
TO ACHIEVE THE PROPER VIDEO
MA CNT
LEVEL SIGNAL
TP18
C
U33
U29
KVP CNT
HIGH TO LOW TRANSITION

TP19
E
CAM GAIN
TP13
B D
VIDEO STABLE GOES FROM HIGH TO
LOW AFTER THE ABS LOOP HAS
BEEN SATISFIED AND THE VIDEO
SIGNAL IS STABLE.
U18
U31
TP22
GND
9600 C-ARM
GND
TP2
GENERATOR WORKSTATION For Reference Only Page 1 of 1
ABSLOPSS.DS4 5/17/96
9600 ABS LOOP

SIGNAL SHEET
POWER/MOTOR
RELAY PCB
SCH. #875997
(1D7)
TP1 P5 P2 IMAGE FUNCTIONS PCB
SCH. #874750 P3 P1 CCD CAMERA
SEE GENERATOR INTERLOCK +24V _IN 7 +24V 1 3 22 2 +24V_CAMERA
BLOCK DIAGRAM FOR DETAILS
OF +24V DISTRIBUTION 2 4 19 1 DC_COM_CAM
P7

SCH. #876738
MOTHER BOARD
SCH.# 875539
P2 J6 P3
40 12 U19
U38 11 (S3) 64 64 (S3) 10 18 INTEGRATE 12 11 11 10 13 5 INTEGRATE 1
13 U26 (1D8)
(2D7) RS232 3 4 15 8 UNITY GAMMA
RECEIVER/ 2
SEE TECHNIQUE PROCESSOR/ DRIVER 13 12 14 7 ANTI_VIGNETTE
ANALOG INTERFACE 3
5 6 16 4 TEST PATTERN
BLOCK DIAGRAM
PIO 4
FOR DETAILS OF
THIS CIRCUITRY U5
+15V (1C3)
+5V
20 24 +15V 1 U9 3 +5V E9 (1B8)
(1A5) 5
R21
R22 ASM TEC POWER

TECHNIQUE PROCESSOR PCB 8 3 COOLER +
SCH. #876735 OR 877742
MICRO R4
CONTROLLER 7 1 COOLER RTN
P2 J5
U17 A13P1
RXD 70 70 21 2 IFBTX 19 24 18 U16 8 U6 13
(1D8) (1C6) /
U39 TXD 22 1 IFBRX 9 10 17 (1C3) 16
72 72
19 INTEGRATE USED IN PULSED MODE TO HALT
1
SCANNING OF CCD SENSOR. LOW=SCANNING IS HALTED
SEE APPROPRIATE C-ARM OUTPUT
COMMUNICATIONS BLOCK DIAGRAM LATCH TP3 NORMAL IMAGING - GAMMA=.07 - SIGNAL IS HIGH
RS232 D
FOR DETAILS (1B7) 2 SUBTRACTION OR ROADMAPPING - GAMMA=1.0(LINEAR)
RECEIVER/ 19 G
SIGNAL IS LOW
DRIVER
S
Q3 (1A5) ANTI-VIGNETTING USED TO CORRECT SHADING IN
SEE IMAGE FUNCTIONS PCB (1B8) 3
TP1 TP2 PERIPHERY OF IMAGE FOR OVERALL EVEN SHADING
& COLLIMATOR MOTORS ACTIVE LOW SIGNAL. USED IN LARGE FIELD ONLY.
OF MICRO CONTROLLER CIRCUITRY
4 TEST PATTERN NOT USED
5 E9 JUMPERS ARE FOR CURRENT LIMITING

THE COOLER +5V. THEY ARE NOT USED AT 9600 C-ARM
THIS TIME
C-ARM (MAINFRAME) IMAGE SYSTEM CAMCNTRS.DS4 6/6/96
INTERCONNECT DIAGRAM INTERCONNECT DIAGRAM USE THIS PAGE FOR
SCH. # 875500 OR #877972 SCH. # 875410 OR #877971 SERIAL NUMBERS
69-0001 TO 69-2000 CCD CAMERA CONTROLS
C-ARM (MAINFRAME) IMAGE SYSTEM
INTERCONNECT DIAGRAM INTERCONNECT DIAGRAM
SCH. # 878376 SCH. # 878377
POWER/MOTOR
RELAY PCB
SCH. #875997
(1D7)
TP1 P5 P3 MOTHER BOARD CCD CAMERA
P3 J2 P2 J1
SCH.# 878396
SEE GENERATOR INTERLOCK +24V _IN 7 +24V 1 4 6 13 13 2 +24V_CAMERA
OF +24V DISTRIBUTION 2 3 5 12 12 1 DC_COM_CAM
P7
IMAGE FUNCTIONS PCB

SCH. #878398
SCH. #876738
MOTHER BOARD
SCH.# 878396 P2 J1
P2 J6 J1 P2
(S3)
40 12 U19
U38 11 (S3) 64 64 (S3) 64 64 INTEGRATE 12 11 11 10 17 17 8 15 15 5 INTEGRATE 1
13 U26 (1D8)
(2D7) RS232 3 4 13 13 25 17 17 8 UNITY GAMMA*
RECEIVER/ 2
SEE TECHNIQUE PROCESSOR/ DRIVER 13 12 11 11 24 16 16 7 ANTI_VIGNETTE
ANALOG INTERFACE 15 7 14 14 3
5 6 15 4 TEST PATTERN
BLOCK DIAGRAM
PIO 4
FOR DETAILS OF
THIS CIRCUITRY U5
(1C3)
+5V E9 (1B8)
R21
5
R22 ASM TEC POWER

TECHNIQUE PROCESSOR PCB 117 117 28 20 20 3 COOLER +
SCH. #877742
MICRO R4
CONTROLLER 119 119 29 21 21 1 COOLER RTN
P2 J5
A13P1
RXD 70 70 71 71 IFBTX19 U17 24 18 U16 8 U6 13
(1D8) (1C6) /
U39 TXD 72 72 73 73 IFBRX 9 10 17 (1C3) 16
19 INTEGRATE USED IN PULSED MODE TO HALT

1
SCANNING OF CCD SENSOR. LOW=SCANNING IS HALTED
SEE APPROPRIATE C-ARM OUTPUT
COMMUNICATIONS BLOCK DIAGRAM LATCH TP3 NORMAL IMAGING - GAMMA=.07 - SIGNAL IS HIGH
RS232 D
FOR DETAILS RECEIVER/ (1B7) 2 SUBTRACTION OR ROADMAPPING - GAMMA=1.0(LINEAR)
19 G
TP7 SIGNAL IS LOW
+5V
J4 P1 +5V DRIVER
S
Q3 (1A5) ANTI-VIGNETTING USED TO CORRECT SHADING IN
55 55 (1B8)
SEE IMAGE FUNCTIONS PCB TP1 TP2 3 PERIPHERY OF IMAGE FOR OVERALL EVEN SHADING
TP8 & COLLIMATOR MOTORS ACTIVE LOW SIGNAL. USED IN LARGE FIELD ONLY.
+15V +15V BLOCK DIAGRAM FOR DETAILS
34 34 OF MICRO CONTROLLER CIRCUITRY
4 TEST PATTERN NOT USED
E9 JUMPERS ARE FOR CURRENT LIMITING

5
THE COOLER +5V. THEY ARE NOT USED AT 9600 C-ARM
THIS TIME For Reference Only Page 2 of 2
USE THIS PAGE FOR CAMCNTRS.DS4 6/6/96
SERIAL NUMBERS
62-0001 AND HIGHER CCD CAMERA CONTROLS
ANALOG INTERFACE PCB MOTHER BOARD

SCH. #876738 SCH.# 875539 IMAGE FUNCTIONS PCB +15 1 2 +10V CCD CAMERA
U1 P3 P3
SCH. #874750
(1B8) +CAM_ROT
10 1 +
0 - 6.8V ROTATION
9 -CAM_ROT 2 - MOTOR
P2 J6 P3 P2
5 CAM_ROT_HI 5
25 59 59 7 8 CAM_ROT_WIPER 21 7

SAMPLE
ANALOG INTERFACE
MUX
BLOCK DIAGRAM
U3 +CAM_IRIS
FOR DETAILS OF 11 3 +
THIS CIRCUITRY (1D6) IRIS
12 -CAM_IRIS 4 - MOTOR
6 CAM_IRIS_HI 6
26 60 60 30 5 CAM_IRIS_WIPER (NOT USED) 24 8
3 CAM_POTS_LO 9
THE CAMERA IRIS IS CLOSED

+15V +5V TO MINIMUM ONLY DURING A SHOT IN
THE PULSED BOOST
20 24 +15V 1 U9 3 (1A5)
(1A5)
FLUOROGRAPHY MODE
TP1 TP2
TECHNIQUE PROCESSOR PCB

SCH. #876735 OR 877742
1
U3
MICRO (1D2)
CONTROLLER 2 3
P2 J5 U11 21 SEE COLLIMATOR MOTOR DRIVE
EN1 1 1 BLOCK DIAGRAM FOR DETAILS
(1D3) 6
7 OF MICRO CONTROLLER CIRCUITRY
21 IFBTX 19 U17 24 18 U16
RXD 70 70 2 8
U39 (1D8) (1C6) /
TXD 72 72 22 1 IFBRX 9 10 17 23 10 11
20 EN2 9
22 15 14
SEE APPROPRIATE C-ARM
COMMUNICATIONS BLOCK DIAGRAM RS232 MOTOR
FOR DETAILS LATCH MOTOR
RECEIVER/
PLD DRIVER
DRIVER
9600 C-ARM
USE THIS PAGE FOR 6/6/96
SERIAL NUMBERS CAMMTRS.DS4
C-ARM (MAINFRAME) IMAGE SYSTEM 69-0001 TO 69-2000
INTERCONNECT DIAGRAM INTERCONNECT DIAGRAM CCD CAMERA MOTOR DRIVE
SCH. # 875500 OR #877972 SCH. # 875410 OR #877971 IRIS / ROTATION MOTORS
TECHNIQUE PROCESSOR PCB IMAGE FUNCTIONS PCB
SCH. #877742 SCH. #878398
SCH. #876738
SEE COLLIMATOR MOTOR DRIVE
0 - 6.8V BLOCK DIAGRAM FOR DETAILS
U3
MICRO (1D2)
25 CONTROLLER 2 3
U11 21 EN1 1
(1D3) 6
7
SEE TECHNIQUE PROCESSOR/ U17
SAMPLE IFBTX 19 24 18 U16 8
ANALOG INTERFACE (1D8) (1C6) /
MUX
BLOCK DIAGRAM IFBRX 9 10 17 23 10 11
U3
FOR DETAILS OF
20 EN2 9
THIS CIRCUITRY (1D6)
RXD 22 15 14
U39 TXD
RS232 MOTOR
LATCH MOTOR
26 RECEIVER/
PLD DRIVER
DRIVER
COMMUNICATIONS BLOCK DIAGRAM (1A5)
FOR DETAILS TP1 TP2
+15 1 U1 2 +10V
(1B8)
60 P2 P2 P2 71 73 35 29 27 25 23 21 19
59 72 70
60 59 J6 72 70 J5 J1 71 73 35 29 27 25 23 21 19
CAM_POTS_LO
CAM_IRIS_HI
CAM_ROT_HI
-CAM_IRIS
+CAM_IRIS
MOTHER BOARD -CAM_ROT
REFERENCE TO SCH.# 878396 +CAM_ROT
C-ARM (MAINFRAME)
SCH. # 878376 P3 16 15 17 14 12 11 13 10 9
J2 8 7 9 6 4 3 5 2 1
REFERENCE TO
IMAGE SYSTEM P2 8 7 9 6 4 3 5 2 1 P3
SCH. # 878377
1 +
ROTATION
2 - MOTOR
5
CAM_ROT_WIPER 7
3 +
IRIS THE CAMERA IRIS IS CLOSED
TO MINIMUM ONLY DURING A SHOT IN
4 - MOTOR
THE PULSED BOOST 9600 C-ARM
6 FLUOROGRAPHY MODE For Reference Only Page 2 of 2
CAM_IRIS_WIPER (NOT USED) 8
USE THIS PAGE FOR CAMMTRS.DS4 6/6/96
9 SERIAL NUMBERS
CCD CAMERA ASSEMBLY
62-0001 AND HIGHER
CCD CAMERA MOTOR DRIVE
IRIS / ROTATION MOTORS
1 DS2, WHEN ILLUMINATED, INDICATES THAT THE E5 JUMPER INSTALLED ONLY DURING COLLIMATOR
3
COLLIMATOR IRIS DID NOT GO TO THE EXPECTED IRIS SIZE CALIBRATION. WITH E5 INSTALLED THE IRIS
SIZE FOR THE MAG MODE SELECTED POTENIOMETER VALUES ARE WRITTEN TO THE
EEPROM U7 FOR EACH MAG MODE.
2 DS1 BLINKS ON AND OFF AS A VISUAL INDICATION
THAT THE MICROCONTROLLER IS RUNNING
IMAGE FUNCTIONS PCB

SCH. #874750
+5
R19 TERMINAL
1 FL4 3 BLOCK COLLIMATOR
P1
DS2
1
(1C3) (1C8) 3 IRIS_POT_HI 3
IRIS CLOSED = .7V 1 3 2 IRISSIG 10 IRIS
U2
+5 IRIS OPENED = 4.3V COL_IRIS_RTN 6 POT
1
R3 U6 18 (1C8)
(1C3) 10 +COL_IRIS 5 +
OUTPUT IRIS
DS1 9
(1C2)
(1C3) LATCH -COL_IRIS MOTOR
U5 U18 9 4 -
E5 (1C8)
2 1 38 (1C2)
2 14 7 6
3 U7 17 EN1 1
TECHNIQUE PROCESSOR PCB 8MHZ. (1D4)
MOTHER BOARD 15 2 3 6 +SHUT_IN/OUT 8
SCH. #876735 OR 877742 3 67 AD 0-7 +
SCH.# 875539 Y1 EEPROM
U11 LEAF IN/OUT
P3 P2 (1D7) U16 +5V -SHUT_IN/OUT 1
P2 P5 (1D3) 10 7 - MOTOR
TP4 (1C6)
SEE CONTROL PANEL PROCESSOR/ EN2 9
TECHNIQUE PROCESSOR 6 16 16 15 14
BLOCK DIAGRAM FOR DETAILS U8
(1D6) E8 ADDRESS 4 +SHUT_ROT 9 +
OF THE MASTER RESET CIRCUIT
75 75 MRESET* 18 21 1 7 23 DECODING
MOTOR LEAF ROTATION
U15 DRIVER -SHUT_ROT MOTOR
U12 (1C4) 5 2 -
WATCHDOG TIMER (1C5)
(150MS) AND U4
POWER MONITOR (5%) (1D2)
BOOT 7 6
U10 PROM 19 EN1 1
(1D6)
2 3
U17 A 0-7
RXD 70 70 21 2 IFBTX 19 24 18
(1D8)
U39 TXD 72 72 22 1 IFBRX 9 10 17 15 14
22
STATIC
+15V RAM 18 EN2 9
23 10 11
20 24 A 8-15 U13
COMMUNICATIONS BLOCK DIAGRAM (1B4)
RS232
FOR DETAILS CS_EPROM
MOTOR
RECEIVER/
CS_SRAM DRIVER 6
DRIVER CS_EEPROM CHIP 4
CS_INPUT SELECT
CS_OUTPUT
PAL 11 11
CS_MOTORS 13
1
+
39 PWM0 MOTOR 4
LATCH K3 4 RELAY SHOWN IN THE
16 DEENERGIZED POSITION
PLD -
MICRO +5V (1A5)
CONTROLLER
TP1 TP2
+15V 1 U9 3
(1A5)
9600 C-ARM
REFERENCE TO REFERENCE TO USE THIS PAGE FOR
COLLMTRS.DS4 6/6/96
C-ARM (MAINFRAME) IMAGE SYSTEM SERIAL NUMBERS
INTERCONNECT DIAGRAM INTERCONNECT DIAGRAM 69-0001 TO 69-2000
SCH. # 875500 OR #877972 SCH. # 875410 OR #877971 COLLIMATOR MOTOR DRIVE
IRIS / LEAF MOTORS
1 DS2, WHEN ILLUMINATED, INDICATES THAT THE E5 JUMPER INSTALLED ONLY DURING COLLIMATOR
3
COLLIMATOR IRIS DID NOT GO TO THE EXPECTED IRIS SIZE CALIBRATION. WITH E5 INSTALLED THE IRIS
SIZE FOR THE MAG MODE SELECTED POTENIOMETER VALUES ARE WRITTEN TO THE
EEPROM U7 FOR EACH MAG MODE.
2 DS1 BLINKS ON AND OFF AS A VISUAL INDICATION
THAT THE MICROCONTROLLER IS RUNNING
IMAGE FUNCTIONS PCB

SCH. #878398 TERMINAL
BLOCK
MOTHER BOARD
+5 SCH.# 878396
R19
1 FL4 3 P6 COLLIMATOR
P2 J1
DS2
1 IRIS_POT_HI
(1C3) (1C8) 106 106 5 3
IRIS CLOSED = .7V 1 3 85 85 IRISSIG 11 10 IRIS
U2
+5 IRIS OPENED = 4.3V 87 87 COL_IRIS_RTN POT
8 6
R3 U6 18 (1C8)
80 80 +COL_IRIS 7 5 +
(1C3)
OUTPUT IRIS
DS1 9
(1C2)
(1C3) LATCH 78 78 -COL_IRIS 6 4 MOTOR
U5 E5 (1C8) U18 -
2 1 38 (1C2)
2 14 7 6
3 U7 17 EN1 1
TECHNIQUE PROCESSOR PCB 8MHZ. (1D4)
MOTHER BOARD 3 67 AD 0-7 15 2 3 96 96 +SHUT_IN/OUT 9 8 +
SCH. #877742 Y1 EEPROM
SCH.# 878396 LEAF IN/OUT
U16 U11
P2 P5 J1 P2 (1D7) +5V 10 94 94 -SHUT_IN/OUT 3 1 - MOTOR
TP4 (1D3)
(1C6)
SEE CONTROL PANEL PROCESSOR/ EN2 9
TECHNIQUE PROCESSOR 6 16 16 15 14
BLOCK DIAGRAM FOR DETAILS U8
(1D6) E8 ADDRESS 100 100 +SHUT_ROT 10 9 +
OF THE MASTER RESET CIRCUIT
75 75 MRESET* 90 90 1 7 23 DECODING
MOTOR LEAF ROTATION
U15 DRIVER 98 98 -SHUT_ROT 4 2 MOTOR
U12 (1C4) -
WATCHDOG TIMER (1C5)
(150MS) AND U4
POWER MONITOR (5%) (1D2)
BOOT 7 6
U10 PROM 19 EN1 1
(1D6)
2 3
U17 A 0-7
RXD 70 70 71 71 IFBTX 19 24 18
U39 (1D8)
TXD 72 72 73 73 IFBRX 9 10 17 22 15 14
STATIC
RAM 18 EN2 9
RS232 23 10 11
SEE APPROPRIATE C-ARM A 8-15 U13
RECEIVER/ (1B4)
COMMUNICATIONS BLOCK DIAGRAM DRIVER
FOR DETAILS CS_EPROM MOTOR
CS_SRAM DRIVER 6
CS_EEPROM CHIP 4
J4 P1 CS_INPUT SELECT
+15V +15V TP8 CS_OUTPUT 11 11
CS_MOTORS
PAL 13
1
+
+5V +5V TP7 39 PWM0 MOTOR 4
LATCH K3 16 REFERENCE TO
PLD - REFERENCE TO
TP1 TP2 MICRO C-ARM (MAINFRAME) IMAGE SYSTEM
CONTROLLER INTERCONNECT DIAGRAM INTERCONNECT DIAGRAM
(1A5) 4 RELAY SHOWN IN THE
SCH. # 878376 SCH. # 878377
DEENERGIZED POSITION
9600 C-ARM
USE THIS PAGE FOR
SERIAL NUMBERS COLLMTRS.DS4 6/6/96
62-0001 AND HIGHER COLLIMATOR MOTOR DRIVE
IRIS / LEAF MOTORS
CAMERA ROTATION MOTOR CW
COLLIMATOR IRIS MOTOR - OPEN

U3-3
DS1
10VDC
U18-6 10S
U2
U3
10 VDC U3-6
500MS
U4
DS2
U8
U18-3 TP4 U17
GND
K3 TP1
CAMERA ROTATION MOTOR CCW
COLLIMATOR IRIS MOTOR - CLOSE U3-3
10VDC
10S
OEC MEDICAL SYSTEMS, INC.

U18-6
IMAGE FUNCTION PCB

U3-6
ASSY 00-874752- ( )
10 VDC
500MS
U18-3 CAMERA IRIS MOTOR

U18
1 23
GND P2
TP2 2 24
LEAF MOTOR - OUT U3-11
COLLIMATOR IRIS POTENIOMETER WIPER LEAF ROTATION MOTOR-DYNAMIC BRAKING CONTROL LEAF ROTATION MOTOR - CW
U2-1 OR U16-9 10VDC
10S
U4-6 OPENED 3.45VDC
CLOSED .83 VDC U4-14 U3-14
10VDC
10S 10VDC
U18-14 10S
U4-3 10VDC
U4-11
500ms
CAMERA ROTATION POTENIOMETER WIPER
P3-21, P2-8, OR ANALOG INTERFACE PCB U3-25
Signal seen during rotation
FULLY CW 0 VDC
LEAF MOTOR - IN
LEAF ROTATION MOTOR - CCW FULLY CCW 6.56 VDC
USE THIS PAGE FOR

IFBRX SERIAL NUMBERS
U4-6 U17-9 69-0001 TO 69-2000
U4-14
SERIAL 10VDC 9600 C-ARM

10VDC COMMUNICATIONS 2ms 10VDC For Reference Only
10S FROM Page 1 of 4
10S
TECHNIQUE PROCESSOR COLCAMSS.DS4
IFBTX 7/9/96
U4-3 U17-19
U4-11
COLLIMATOR & CAMERA SIGNAL SHEETS
COLLIMATOR & CAMERA MOTORS
CAMERA ROTATION MOTOR CW CAMERA ROTATION MOTOR CCW
U3-3 U3-3
10VDC
10VDC
10S
10S
U3-6
U3-6
ASSY 00-878400- ( )
IMAGE FUNCTION PCB
U18
LEAF ROTATION MOTOR - CW LEAF ROTATION MOTOR - CCW

GND
TP2
U4-14 U4-14
10VDC 10VDC
10S 10S
U4-11 U4-11
K3
U8
U4 LEAF ROTATION MOTOR-DYNAMIC BRAKING CONTROL CAMERA IRIS MOTOR
U3 U2
TP4
U3-11
U18-14 10VDC
10S
GND
TP1 10VDC U3-14
500ms
Signal seen during rotation

I.F. FAULT mP GOOD
IFBTX IFBRX
TP6 TP5 COLLIMATOR IRIS

DS2 DS1
POTENIOMETER WIPER
IFBRX U2-1
TP5
OPENED 3.45 VDC
CLOSED .83VDC
COLLIMATOR IRIS MOTOR - OPEN COLLIMATOR IRIS MOTOR - CLOSE LEAF MOTOR - OUT LEAF MOTOR - IN
10VDC
2ms CAMERA ROTATION
POTENIOMETER WIPER
ANALOG INTERFACE PCB U3-25
U4-6 IFBTX
U18-6 U4-6 TP6 FULLY CW 0VDC
U18-6
FULLY CCW 6.56VDC
SERIAL
COMMUNICATIONS
U18-3 FROM 9600 C-ARM
U18-3 U4-3 TECHNIQUE PROCESSOR For Reference Only Page 2 of 4
U4-3
COLCAMSS.DS4 7/9/96
USE THIS PAGE FOR
SERIAL NUMBERS
10 VDC 10 VDC 10VDC 10VDC
500MS 500MS 10S 10S 62-0001 AND HIGHER COLLIMATOR & CAMERA MOTORS
INTEGRATE
UNITY GAMMA IFB P3-13, U5-10 OR CAMERA J1-5 +5V
IFB P3-15, U5-4 OR CAMERA J1-8 PULSE MODE OR PULSE BOOST MODE
HI (+5V WHEN NOT IN SUBTRACTION OR ROAD MAP) ALL OTHER MODES, +5V 0V
LO (0V WHEN IN SUBTRACTION OF ROAD MAP)
TEST PATTERN (NOT USED) IFB P3-16, U5-6 OR CAMERA J1-4 ANTI VIGNETTE
HI WHEN NOT ENABLED IFB P3-14, U5-12 OR CAMERA J1-7 CAMERA VIDEO SIGNAL - NO X-RAYS
LO CAUSES TEST PATTERN 5 1/2" X 5 1/2" NORMAL MODE - LOW
REFER TO FSB #94-025 MAG 1 - HI
MAG 2 - HI
24 2 P3
23 1
DS1
CAMERA GAIN
IFB P3-20 OR CAMERA J1-9
MIN. 0V
MAX. +9V
U5 VIDEO LEVEL INDICATOR CAMERA VIDEO SIGNAL

DS2 IFB P3-23 OR CAMERA J1-10 CENTER PIN OF CAMERA J2
MIN. 0V
TP1 MAX. 9.5V
GND AUTO MODE +4.5V - FLAT FIELD
AUTOMODE +4.5V - MESH TOOL
J1
1
J2
IMAGE FUNCTION PCB
ASSY 00-874752- ( )
1 23
TP2 P2
GND 2 24
IF FAULT 9600 C-ARM

+24V IFB P2-11, U5-8 For Reference Only Page 3 of 4
IFB P2-3, OR CAMERA J1-2 DS2 OFF - 0V WHEN NOT FAULT USE THIS PAGE FOR
DS2 ON - +5V WHEN FAULT IS INDICATED SERIAL NUMBERS COLCAMSS.DS4 7/9/96
69-0001 TO 69-2000

CAMERA CONTROLS
CAMERA VIDEO SIGNAL - NO X-RAYS
ASSY 00-878400- ( )
IMAGE FUNCTION PCB
GND
TP2
+24V
CAMERA J1-2
CAMERA VIDEO SIGNAL

CENTER PIN OF CAMERA J2
U5
J1
GND
1
J2
TP1
I.F. FAULT mP GOOD
DS2 DS1
CAMERA GAIN
CAMERA J1-9
MIN. 0V
MAX. +9V VIDEO LEVEL INDICATOR
ANTI VIGNETTE CAMERA J1-10
UNITY GAMMA IF FAULT IFB U5-12 OR CAMERA J1-7 MIN. 0V
IFB U5-4 OR CAMERA J1-8 IFB U5-8 NORMAL MODE - LOW MAX. 9.5V
HI (+5V WHEN NOT IN SUBTRACTION OR ROAD MAP) DS2 OFF - 0V WHEN NOT FAULT MAG 1 - HI AUTO MODE +4.5V - FLAT FIELD
LO (0V WHEN IN SUBTRACTION OF ROAD MAP) DS2 ON - +5V WHEN FAULT IS INDICATED MAG 2 - HI AUTOMODE +4.5V - MESH TOOL
9600 C-ARM
TEST PATTERN (NOT USED) IFB U5-6 OR CAMERA J1-4 INTEGRATE For Reference Only
+5V Page 4 of 4
HI WHEN NOT ENABLED IFB U5-10 OR CAMERA J1-5 USE THIS PAGE FOR
LO CAUSES TEST PATTERN 5 1/2" X 5 1/2" PULSE MODE OR PULSE BOOST MODE SERIAL NUMBERS COLCAMSS.DS4 7/9/96
REFER TO FSB #94-025 ALL OTHER MODES, +5V 0V
62-0001 AND HIGHER
CAMERA CONTROLS
POWER/MOTOR
RELAY PCB TP2
SCH. #875997
IMAGE FUNCTIONS PCB
SCH. #874750 IMAGE INTENSIFIER
(1D7) (900753)
TP1
P7 P5 P2
+24V _IN 7 5 4 II_24V 6 9 +24/II
TP4
SEE GENERATOR INTERLOCK 24V_INTERLOCK 1 + 8 12 DC COM II
BLOCK DIAGRAM FOR DETAILS TP8
OF +24V DISTRIBUTION AND (1D7) II_ON 12
24V INTERLOCK DETAILS -
K7
P1 1
G1 G2 G3 G4 GND E PC A
ANALOG INTERFACE PCB MOTHER BOARD

SCH. #876738 SCH.# 875539

ANALOG INTERFACE P4 J7
BLOCK DIAGRAM
FOR DETAILS OF P2 J6 P2 2 0V 4
THIS CIRCUITRY
II_ON 70 70 31 7 Ue 1
U38
24 8 U43 12
(2D7) (2C6) Q6
6 M1 3
TP1, 2, 21, 22 (2B2)
+15V P3 MEDFIELD
+5V 6
7 II HIGH VOLTAGE
PIO 20 24 +15V 1 U9 3 5
3 POWER SUPPLY
(1A8) 2 5 M2 7
4 (900752)
SMALLFLD
1 E1
+
Q1
SMALL (1B3)
TECHNIQUE PROCESSOR PCB FIELD 8
- K1
SCH. #876735 OR 877742
MICRO
CONTROLLER
P2 J5
CR4
21 IFBTX 19 U17 24 18 U16 8 U6 14
RXD 70 70 2 CR5
(1D8) (1C6) / 3
U39 TXD 72 72 22 1 IFBRX 9 10 17 (1C3) 15 2
4
1
+
OUTPUT Q2 CR3
SEE APPROPRIATE C-ARM (1B3)
COMMUNICATIONS BLOCK DIAGRAM LATCH 8
RS232 -
FOR DETAILS RECEIVER/ MED
FIELD K2
DRIVER
(1A5)
TP1 TP2
SEE COLLIMATOR MOTOR DRIVE
9600 C-ARM
C-ARM (MAINFRAME) IMAGE SYSTEM USE THIS PAGE FOR IICNTRLS.DS4 9/19/96
INTERCONNECT DIAGRAM INTERCONNECT DIAGRAM SERIAL NUMBERS
SCH. # 875500 OR #877972 69-0001 TO 69-2000
SCH. # 875410 OR #877971
IMAGE INTENSIFIER CONTROLS
FUNCTIONAL SCHEMATIC
POWER/MOTOR
RELAY PCB TP2
SCH. #875997
IMAGE INTENSIFIER
(1D7) (900753)
TP1
P7 P5 P3 P3
+24V _IN 7 5 4 II_+24V 6 II_+24V 2 20
TP4
SEE GENERATOR INTERLOCK 24V_INTERLOCK 1 + 8 DC COM II 1 22
BLOCK DIAGRAM FOR DETAILS TP8
OF +24V DISTRIBUTION AND (1D7) II_ON 12
24V INTERLOCK DETAILS -
K7
P1 1
P2 G1 G2 G3 G4 GND E PC A
31

SCH. #876738

ANALOG INTERFACE J7 II HIGH VOLTAGE
BLOCK DIAGRAM POWER SUPPLY
FOR DETAILS OF P2 J6 IMAGE FUNCTIONS PCB Ue 1
THIS CIRCUITRY SCH. #878398
P2 J1 (900752)
II_ON 70 70 0V 4
U38 3 3
24 8 U43 12
(2D7) (2C6) Q6 5 5 21 M1 3
TP1, 2, 21, 22 (2B2)
6 MEDFIELD
7
PIO 5
3 9 9 23
2 M2 7
4 SMALLFLD
1 E1
+
Q1
SMALL (1B3)
TECHNIQUE PROCESSOR PCB FIELD 8
- K1
SCH. #877742
MICRO
CONTROLLER
P2 J5
J1 P2
CR4 MOTHER BOARD
71 71 U17 24 18 U16 8 U6 14 SCH.# 878396
RXD 70 70 IFBTX19 CR5
(1D8) (1C6) / 3
U39 73 73 (1C3) 15 2
TXD 72 72 IFBRX 9 10 17 4
1
+
MOTHER BOARD OUTPUT Q2 CR3
SEE APPROPRIATE C-ARM SCH.# 878396 (1B3)
COMMUNICATIONS BLOCK DIAGRAM LATCH 8
RS232 -
FOR DETAILS RECEIVER/ MED
FIELD K2
TP7
+5V
J4 P1 +5V DRIVER
55 55 (1A5)
TP1 TP2 REFERENCE TO REFERENCE TO
TP8 C-ARM (MAINFRAME) IMAGE SYSTEM
+15V +15V SEE COLLIMATOR MOTOR DRIVE INTERCONNECT DIAGRAM INTERCONNECT DIAGRAM
34 34 SCH. # 878376 SCH. # 878377
9600 C-ARM
USE THIS PAGE FOR IICNTRLS.DS4 9/19/96
SERIAL NUMBERS
62-0001 AND HIGHER IMAGE INTENSIFIER CONTROLS
FUNCTIONAL SCHEMATIC
POWER/MOTOR
RELAY PCB
TP4 - "+24V INTLK"
10VDC
7 1
10S
CR8
TP4 TP1 TP8
P4
TP2 POWER/MOTOR E1
K7
CR4
CR3
RELAY PCB
K1
K2
TP8 - "II_ON"
U6
R6
R5
Q1 Q2
POWER/MOTOR U17
RELAY PCB
P5-6 - "+24VII"
10VDC TP1
10S
POWER/MOTOR
RELAY PCB
TP8 - "II_ON"

IMAGE FUNCTION PCB
ASSY 00-874752- ( )
IMAGE
FUNCTION PCB
U6-15
10VDC
ASSY 00-875999- ( )
10S TP2 1 23
P2
2 24
IMAGE
FUNCTION PCB
P4-6
(MEDFIELD)
P5
5
1
IMAGE
FUNCTION PCB
10
U6-14
6
10VDC
10S
IMAGE
9600 C-ARM
FUNCTION PCB
USE THIS PAGE FOR
P4-5 SERIAL NUMBERS
(SMALLFLD)
69-0001 TO 69-2000 II_CNTSS.DS4 10/8/96
IMAGE INTENSIFIER CONTROLS

SIGNAL SHEET

IMAGE FUNCTION PCB
POWER/MOTOR ASSY 00-878400- ( )
RELAY PCB
TP4 - "+24V INTLK"
10VDC
10S
CR8
TP4 TP1 TP8
TP2 POWER/MOTOR
K7
RELAY PCB
TP8 - "II_ON"
P2
POWER/MOTOR
RELAY PCB
P5-6 - "+24VII"
10VDC
10S
POWER/MOTOR
RELAY PCB
U6
TP8 - "II_ON"
14
15
Q1
E1
K1
GND
TP2
K2
U16
IMAGE CR3
Q2
FUNCTION PCB CR4
GND
U6-15
TP1
CR5
10VDC
ASSY 00-875999- ( )
10S
10
9
U17
19
24
IMAGE
FUNCTION PCB
P2-5
P1
(MEDFIELD)
P5
5
1
IMAGE
FUNCTION PCB
10
U6-14
6
10VDC
10S
IMAGE
9600 C-ARM
FUNCTION PCB USE THIS PAGE FOR For Reference Only Page 2 of 2
P2-9
(SMALLFLD) SERIAL NUMBERS II_CNTSS.DS4 10/8/96
62-0001 AND HIGHTER IMAGE INTENSIFIER CONTROLS
SIGNAL SHEET
PIXEL/COLUMN FILTER PCB

SCH.# 878045
MOTHERBOARD
SCH. #875539
+5P
CCD CAMERA NOTE: THE +5P IS SOURCED PIXEL FILTER CIRCUITRY
FROM THE CCD CAMERA AND R11 R10
IS USED ONLY FOR PIXEL FILTER
CIRCUITRY C10 C11
J2 P3 P2 J1
P2 J1 R12
3 1 29 1 14
VIDEO 1 2
1 2 COAX SHIELD 28 2 15
COAX SHIELD 2 1
U4 5 INTERCONNECT
(1D4) 5 6 PIXEL FILTER PCB - SCH.#877789 CABLE TO
1 IS MADE UP OF COMPONENTS
7 WORKSTATION
WITHIN DOTTED LINES
Q1
60nS (1D3) TP1 (1C2)
DELAY CIRCUIT R1
+5P TP2
P3 J3
+5V
8 6 R2
7 5
COLUMN FILTER CIRCUITRY
R3 R4
U3
REFERENCE TO
8 CAMERA_GAIN VREF 16 IMAGE SYSTEM
DA 0-3 INTERCONNECT DIAGRAM
5 4 PIXCLK 25
SCH. # 875410 OR #877971
(1B2)
3 3 HDRV 44 7 DACLK 12
20
+5V
U2 D/A
2
(1F5) CONVERTER
1
OFF 0-3 D 0-7

SW1 U1
(1F7)
P3 20
IPOS 0-3
SW2 A 0-9
P2 P5
6 CAMERA_GAIN 3 16 POSITION
ROTARY SWITCHES
SEE ABS LOOP EPROM
BLOCK DIAGRAM ADDRESS
OF CAMERA GAIN +15V 1 U20 3 +5V 1 CONTROLLER PROGRAMMED WITH
CIRCUIT (1A7) 2 EPLD COLUMN CORRECTION
DATA FOR THE PARTICULAR
CCD CHIP ON THE CAMERA
TP1 & 2
IMAGE FUNCTION PCB

9600 C-ARM
NOTE: SOME SYSTEMS MAY HAVE THE
SCH.# 874750 1
PIXEL FILTER PCB IN PLACE OF THE For Reference Only Page 1 of 2
REFERENCE TO PIXEL/COLUMN FILTER PCB
C-ARM (MAINFRAME) PIX_COL.DS4
INTERCONNECT DIAGRAM 4/19/96
USE THIS PAGE FOR
SCH. # 875500 OR #877972
SERIAL NUMBERS CAMERA VIDEO &
69-0001 TO 69-2000
+5
CCD CAMERA
R1 R2
C1 C2
J1 P1 P2 J2
J1
R3 J2
P2 3 1 14
J1
VIDEO 1 2
1 2 COAX SHIELD 15
COAX SHIELD 2 1
U4 5 HIGH VOLTAGE POWER INTERCONNECT

(1D4) 5 6 CABLE ASSEMBLY PANEL CABLE TO
7 WORKSTATION
Q1
60nS (1D3)
DELAY CIRCUIT PIXEL FILTER PCB
SCH. # 877789
+5
A13P3
+5V
1 E1
CAMERA ASSEMBLY
C-ARM (MAINFRAME) IMAGE SYSTEM
INTERCONNECT DIAGRAM INTERCONNECT DIAGRAM
SCH. # 878377 SCH. # 878376
9600 C-ARM
USE THIS PAGE FOR For Reference Only Page 2 of 2
SERIAL NUMBERS
69-2001 AND HIGHER & PIX_COL.DS4 4/19/96
62-0001 AND HIGHER
CAMERA VIDEO &
LMON VIDEO
RMON VIDEO
GENERATOR SERIAL LINK

IR XMIT PCB
00-873936
Auxiliary Interface PCB Thermal Imager VCR 1 Hardcopy Camera
REMOTE 00-876502
CONTROL IR - Signal Distribution
- Status LEDs
Photocell
VCR
IR RCVR PCB CONTROL
00-874220 Technique
Processor
PCB
- Convert IR
to TTL VCR 1 VIDEO HARD COPY VIDEO Camera
- Ambient Light VCR 2 Video
Left Sensor Right Auxiliary
Monitor Monitor Interface PCB
Video Switching PCB
TP10
00-872237 00-876502
- 8:1 Video Switches (6)

Normal Interlaced Video - Log Amp (Subtraction Mode)
Rear Panel (BNC) - Anti-Aliasing Filter
Contrast/ Brightness PCB - GenLock Control
00-876351 Video Switching
Matirx High Scan
- Brite/Cont. Control Non-interlaced Video
Brightness - Ambient Light Adj. Brightness Rear Panel (BNC)
and and
Contrast Contrast Video Matrix Serial Data
Control Control
TP4 TP7 TP5

Control Panel Interface PCB AT Communications PCB GSP/Control & PIOs High Rate Scan Converter PCB
00-876611
EO 00-872125
- Interface "AT" to Two Serial Links:

00-876397
-Normal Interlace to High Scan

- Switch Decode for: - IR Interface
Front Panel - LED Driver (1) Control Panel Serial Link Image Processor PCB R L Non Interlace Conversion
Trackball Panel - Serial Link to AT (2) Generator Serial Link 00-875952 D:A D:A A:D -D:A Video (8 bit Left and Right)
Key Board Panel - Tone Generator - Option PROM (CMOS Setup) - GSP (Graphics System Processor)
- Solid State Track Ball Control - VCR Control performs image processing.
- Printer Control - A:D Video (8 bit - 256 levels) Right & Left
- Status LED Control - D:A Video (8 bit - left and right) Digital Video Memory Digital Video
- Disk Drive Selection Jumpers - Circular Blanking
(E1, E2, E3) - Region of Interest
- Text Generator
- Gray Scale LUT (Look Up Tables)
Front Panel
Querty Key Bd
Track Panel
Control
Control
Control
386 Motherboard PCB

00-900658
NOTE: 386 Motherboard has 9600 C-ARM

built-in disk controller.
4TH_BLK1.DS4 12/4/96
Printer 3.5" Floppy Drive
40 MB Hard Drive A:\ 1.2 meg; Image Backup 9600 WORKSTATION
NOTE: Control Panel Processor Serial Link to AT Motherboard via
AT Communications PCB must be working for this cart to boot up.
C:\ 10 MB; DOS & Application S/W & Level 2 Diagnostic Access
BLOCK DIAGRAM
D:\ 30 MB; 100 Image Storage
DISK DRIVE SELECTION JUMPERS E1-E3 386 (WITH 4 OR 30 FPS) 386 Mother PCB Boot Sequence Screen
386 (NO 4 OR 30FPS)
Jumpers located on AT Communications PCB MINIMUM CONFIGURATION (Viewed on external monitor using an external video card
MINIMUM CONFIGURATION
(Verify the Motherboard) with jumper E4 Removed from AT Comm. PCB)
(Verify the Motherboard)
SYSTEM TYPE
MOTHERBOARD & DISK E1 E2 E3 1. To boot the Motherboard, the AT Communications PCB can first be removed. 1. To boot the Motherboard, the IP-SCSI board(s) can first be removed.
The floppy drive should still be accessed (with the service boot disk). The floppy drive should still be accessed (with the service boot disk). AMIBIOS (C)1991 American Megatrends Inc.,
386 (AMI BIOS) WITH + + G 386NSX - P/Ns 06018-07 - 9/17/92
IDE DISK
386 (AMI BIOS) WITH G + G 2. Next, the Image Processor can be removed. The floppy drive should still be accessed 2. The AT Communications PCB can be removed. The floppy drive should still be accessed (with the service boot disk).
SCSI DISK (with the service boot disk) but no monitor images will be displayed when the Image 001664 KB OK
Processor is removed. 3. Next, remove the DOS SCSI Disk Controller PCB.
The floppy should be accessed. (with the service boot disk) WAIT......
NOTE: An external video card and monitor can be used to observe the
motherboard boot process and to examine A: & C: drives. 4. Then, the Image Processor can be removed. The floppy drive should still be accessed (with the service boot disk)
BIOS ROM\BOOT CODES Remember to remove jumper E4 on the AT Comm. PCB to monitor but no monitor images will be displayed when the Image Processor is removed. Adaptec AHA-1520 BIOS
mother board boot process. Version 1.4
E0 - Normal Boot Code NOTE: An external video card and monitor can be used to observe the Motherboard boot process and to examine Copyright 1990 Adaptec, Inc.
98 - Hard Disk Error 3. If the system still fails to boot, verify power. See Workstation Power Block Diagram. the A: drive. Remember to remove jumper E4 on the AT Comm. PCB to monitor mother board boot process. All Rights Reserved
90 - Boot Disk Not Available Finally , the Motherboard may need to be replaced..
82 - GSP Load Failure 5. If the system still fails to boot, verify power. See Workstation . Power Block Diagram. Finally, try replacing the Motherboard.
AMIBIOS System Configuration
BE - Boot-up with Diagnostic Diskette. (C) 1985-1991, American Megatrends Inc.
FO - Workstation Program Exited to DOS
(Internal Workstation Communications Error Main Processor : 80386SX Base Memory Size : 640 KB
"System Error #253") Numeric Processor : None Ext. Memory Size : 1024 KB
1.44 Meg Floppy Drive Floppy Drive A: : 1.44 MB, 3.5" Hard Disk C Type : 35
Floppy Drive B: : None Hard Disk D Type :None
For a complete listing of BIOS ROM codes, see Backup Display Type : Color 80X25 Serial Port(s) : 3F8, 2F8
Service Manual Workstation Software Section. Battery AMIBIOS Date : 12/12/91 Paralell Port(s) : 378
Aux. Interface PCB Video Switching PCB
HiMEM: DOS XMS Driver, Version 2.78 - 09/19/91
XMS Specification Version 2.0
Copyright 1988-1991 Microsoft Corp.
Status LEDs J10 Ext. Batt.
Connection Installed A20 Handler Number 1.
64K High Memory Area is available.
U25 MICROSOFT Expanded Memory
Option
Prom
MICROSOFT Expanded Memory Manager 386 Version 4.33.06X
(C) Copyright Microsoft Corporation 1986, 1990
E4
P5
EMM386 successfully installed.
Status LED
Available expanded memory ......256 KB
U25 Option Prom Driver
- Programs UARTs U20, 22, 26, & 27 LIM/EMS version.......4.0
and then loads CGA Driver for IP PCB. Total expanded memory pages.......40
- Verifies/rewrites AT CMOS RAM. Available expanded memory pages....16
E2 Total handles.......64
E4 Jumper + G Active handles.....1
- Remove this jumper to disable internal G
E3 Page frame segment....CC00 H
CGA (Image Processor) video driver when P4 +
using an external CGA/EGA video card E1 J17 Floppy Disk Total upper memory available...15 KB
(for diagnostic purposes only) +G J16 Hard Disk Larges upper memory block available....15 KB
2 Megabytes Ram Upper memory starting address....C800 H
Mother Board Power
Serial link to
AT Comm. PCB EMM386 Active.
See Control Panel Processor DC Dist PCB MS-DOS Version 5.00
Block Diagram PS1 +5VDC
P3 NBKSHELL Loaded
FASTOPEN installed
U27
TSRSER Loaded Sucessfully
DUART
Control Panel Processor PCB 9600 WORKSTATION
L R
ENHANCED AVERAGING
FLUORO ONE-SHOT ONE-SHOT
O C
SERIES 9600 AT 4TH_AT2.DS4 12/5/96
Communications
PCB
AT Comm. PCB IDE Hard Drive (non-cine systems) 9600 WORKSTATION MOTHERBOARD
Image Processor PCB C:\ 10 MB; DOS & Application S/W
NOTE: Control Panel Interface Serial Link to
High Rate Scan Converter PCB D:\ Up to 200 image storage BLOCK DIAGRAM
Motherboard via AT Communications PCB
must work for normal cart boot-up process. 386 Mother Board See 9600 Workstation Configuration Block Diagrams
SET CONFIGURATION
Line Frequency (Hz): 60
System Model: SP
SYSTEM CONFIGURATION
Archive: 0
Language: ENGLISH
1. Press "SETUP OPTIONS" on the annotation keyboard P8
2. Install the service disk in the floppy drive at the rear of the Workstation
3. Select "Access Level 2" from the menu
4. Select "System Configuration" from the menu
Image Processor PCB
5. Select "Set System Configurations" from the menu
Serial Number: 69-1107 Sch. #875952 J2
6. Set the configuration by making selections from the following menu:
Hospital Name: OEC TRAINING (See Image Path Block Page 2)
Mars Table: DOMESTIC
Date Format: MM/DD/YYYY 386 Motherboard

Use the cursor arrow keys to select P/N 900658
Press [ENTER] to accept (See 9600 Workstation &
Press [ESC] to exit
9600 Workstation AT Motherboard
Block Diagrams)
SOFTWARE FORMATTED DISK AT COMM. PCB DRIVE

VERSION HARD DISK CONTROLLER OPTION PROM PARTIONING
NOTES 1.44 Meg
PART # PART # (U25) Floppy Drive
C: DRIVE 10M Drives used: Fujitsu M2684TAU P/N 900669
J17 J16
10 00-877024-02 NONE -02 Seagate ST3660A P1 Data
D: DRIVE 30M Data IDE DRIVE
Western Digital AC1365
C: DRIVE 10M
11 00-877024-03 NONE -03
D: DRIVE 60M See page 2 for hard drive jumper settings. P1 Power
J6
TRACKPAD PANEL
DC Power J2 J11
WINDOW
Distribution PCB
AT COMMUNICATIONS BOARD
876839
DISK DRIVE SELECTION JUMPERS E1-E3
FOR IDE DISKS
(See Workstation Power J4
NEGATE Power
SYSTEM TYPE Block Diagram #1)
MOTHERBOARD & DISK E1 E2 E3
386 (AMI BIOS) WITH + + G

IDE DISK
AUTO HISTO ON/OFF
See also 9600 Workstation Motherboard
Block Diagram
LEVEL
9600 C-ARM
FRONT PANEL For Reference Only Page 1 of 4
NON_CINE.DS4 11/13/96
AVERAGING L R
FLUORO ONE-SHOT ENHANCED
9600 WORKSTATION
SP, GSP, ESP - (NON CINE) CONFIGURATIONS
SP SOFTWARE & HARDWARE CONFIGURATION
SET CONFIGURATION
System Model: SP
Archive: 4
Language: ENGLISH
1. Press "SETUP OPTIONS" on the annotation keyboard P8
Image Processor PCB
Serial Number: 69-1107 Sch. #875952
5. Select "Set System Configurations" from the menu J2
Hospital Name: OEC TRAINING
6. Set the configuration by making selections from the following menu: (See Image Path Block Page 2)
Date Format: MM/DD/YYYY 386 Motherboard

Use the cursor arrow keys to select P/N 900658
Press [ENTER] to accept
(See 9600 Workstation &
Press [ESC] to exit
Block Diagrams)

NOTES 1.44 Meg
J17 J16
C: DRIVE 10M
11 00-877024-03 NONE -03
J6
TRACKPAD PANEL
DC Power J2 J11
WINDOW
Distribution PCB
AT COMMUNICATIONS BOARD 876839
DISK DRIVE SELECTION JUMPERS E1-E3 (See Workstation Power
NEGATE FOR IDE DISKS J4
Block Diagram #1) Power
SYSTEM TYPE

IDE DISK
AUTO HISTO ON/OFF
Block Diagram
LEVEL
9600 C-ARM
AVERAGING L R
FLUORO ONE-SHOT ENHANCED
9600 WORKSTATION
GSP SOFTWARE & HARDWARE CONFIGURATION
SET CONFIGURATION
System Model: ESP
(Digital Spot Option: Yes/No)
Cine Disk: None
1. Press "SETUP OPTIONS" on the annotation keyboard
ENGLISH
P8
Language:
VCR1: Sony
VCR2: Sony Image Processor PCB
Digital Print: No Sch. #875952
5. Select "Set System Configurations" from the menu J2
Serial Number: 69-1107
6. Set the configuration by making selections from the following menu: (See Image Path Block Page 2)
Measurements: NO 386 Motherboard
Date Format: MM/DD/YYYY P/N 900658
Use the cursor arrow keys to select
Press [ESC] to exit
Block Diagrams)

NOTES 1.44 Meg
J17 J16
C: DRIVE 10M
11 00-877024-03 NONE -03
J6
TRACKPAD PANEL
DC Power J2 J11
WINDOW
AT COMMUNICATIONS BOARD Distribution PCB
DISK DRIVE SELECTION JUMPERS E1-E3 876839
FOR IDE DISKS (See Workstation Power
ZOOM NEGATE SYSTEM TYPE J4
Block Diagram #1) Power

IDE DISK
VCR RECORD SHARPEN AUTO HISTO ON/OFF See also 9600 Workstation Motherboard
Block Diagram
VCR PLAY LEVEL
9600 C-ARM
TRACKPAD
AVERAGING
FLUORO ONE-SHOT DIG. SPOT RECALL SAVE L R
9600 WORKSTATION
ESP SOFTWARE & HARDWARE CONFIGURATION
CN 5
CNH 1
13 14
5 3 1
1 2 J8
6 4 2
WESTERN DIGITAL AC 1365

FUJITSU M2684TA
JUMPER AS ILLUSTRATED
SEAGATE ST3660A
9600 C-ARM
7 5 3 1
FRONT
9600 WORKSTATION
8 6 4 2
JUMPER SETTINGS FOR IDE DRIVES
8 Bit Digital Left Video
SET CONFIGURATION
System Model: ESP
Digital Spot Option: Yes
Cine Disk: ALTA4
Language: ENGLISH
VCR1: Sony
VCR2: Sony
Digital Print: No P8
Image Processor PCB
Measurements: NO
875952 J2
Date Format: MM/DD/YYYY (See Image Path Block Page 2)
Use the cursor arrows to select
386 AT Motherboard
Press [ESC] to exit
900658
Block Diagrams) P9
SOFTWARE FORMATTED DOS SCSI DISK IP-SCSI DISK AT COMM. PCB IP SCSI
DRIVE
VERSION HARD DISK CONTROLLER CONTROLLER OPTION PROM Disk
PARTIONING J5 Controller J9
PART # PART # PART # (U25) 00-900661-01
00-900659-02 C: DRIVE 10M Master
10 00-877025-01 00-900661-01 -02 P5
ADAPTEC D: DRIVE 30M 1.44 Meg
00-900659-02 C: DRIVE 10M Floppy Drive Drive 1
11 00-877025-02 00-900661-01 -03 900669 Data
D: DRIVE 60M SCSI DRIVE
ADAPTEC
P1 Data J17
DOS
P1 Power SCSI
NOTES J6 Disk J2
TRACKPAD PANEL Controller
Drives used: Fujitsu M2684SAU, M2623FA, or M2624FA
J6 00-900659-02
Seagate ST3550N or ST5660N
ACQUIRE IMAGES Hitachi DK325C-57 Drive 1
WINDOW Power
See pages 5 & 6 for hard drive jumper settings.
DC Power J11
PLAY/PROCESS ZOOM NEGATE Distribution PCB J2
FOR SCSI DISKS Block Diagram #1) J4
VCR RECORD SHARPEN AUTO HISTO ON/OFF SYSTEM TYPE
386 (AMI BIOS) WITH G + G

SCSI DISK
VCR PLAY LEVEL See also 9600 Workstation Motherboard

Block Diagram
9600 C-ARM
TRACKPAD
4&8_CINE.DS4 11/13/96
AVERAGING
9600 WORKSTATION CONFIGURATIONS
ESP/4, ESP/BVAS, VASC/4 - (4 & 8 FPS) OPTIONS
ESP/4 HARDWARE & SOFTWARE CONFIGURATION
SET CONFIGURATION
System Model: BVAS
Cine Disk: ALTA8
Language: ENGLISH
VCR1: Sony
VCR2: Sony
Image Processor PCB
Measurements: NO
875952 J2
386 AT Motherboard
Press [ESC] to exit
900658
Block Diagrams) P9
DRIVE
VERSION HARD DISK CONTROLLER Disk
CONTROLLER OPTION PROM PARTIONING J5 Controller J9
PART # PART # PART # (U25) 00-900661-01
C: DRIVE 10M Master
00-900659-02
10 00-877025-01 00-900661-01 -02 P5
11 00-877025-02 00-900661-01 -03 900669 Data SCSI DRIVE
ADAPTEC D: DRIVE 60M
P1 Data J17
DOS
SCSI
P1 Power
NOTES J6 Disk J2
Controller
TRACKPAD PANEL Drives used: Fujitsu M2684SAU, M2623FA, or M2624FA 00-900659-02
Seagate ST3550N or ST5660N J6
ACQUIRE IMAGES Hitachi DK325C-57 Drive 1
WINDOW Power
DC Power J11
VCR RECORD SHARPEN AUTO HISTO ON/OFF SYSTEM TYPE

SCSI DISK
VCR PLAY LEVEL See also 9600 Workstation Motherboard

Block Diagram
9600 C-ARM
TRACKPAD
4&8_CINE.DS4 11/13/96
AVERAGING
FLUORO ONE-SHOT DIG. SPOT ROADMAP SUBTRACT RECALL SAVE L R 9600 WORKSTATION CONFIGURATIONS
ESP/BVAS HARDWARE & SOFTWARE CONFIG.
SET CONFIGURATION
System Model: VAS
Cine Disk: ALTA4
Language: ENGLISH
VCR1: Sony
VCR2: Sony
Image Processor PCB
Measurements: NO
875952 J2
386 AT Motherboard
Press [ESC] to exit
900658
Block Diagrams) P9
DRIVE
PARTIONING J5 J9
PART # PART # Controller
PART # (U25)
00-900661-01
10 00-877025-01 00-900661-01 -02 P5
11 00-877025-02 00-900661-01 -03 900669 Data
ADAPTEC D: DRIVE 60M SCSI DRIVE
P1 Data J17
DOS
SCSI
P1 Power
NOTES J6 Disk J2
Controller
TRACKPAD PANEL Drives used: Fujitsu M2684SAU, M2623FA, or M2624FA 00-900659-02
Seagate ST3550N or ST5660N J6
Hitachi DK325C-57 Drive 1
ACQUIRE IMAGES LANDMARK ZOOM
Power
WINDOW
DC Power J11
PLAY/PROCESS REGISTRATION SHARPEN Distribution PCB J2
876839
AT COMMUNICATIONS BOARD (See Workstation Power
DISK DRIVE SELECTION JUMPERS E1-E3 Block Diagram #1) J4
PEAK OPACIFY AUTO HISTO
FOR SCSI DISKS
VCR RECORD ON/OFF
SYSTEM TYPE

SCSI DISK
VCR PLAY MASK NEGATE LEVEL
Block Diagram
9600 C-ARM
TRACKPAD
4&8_CINE.DS4 11/13/96
AVERAGING
FLUORO ONE-SHOT DIG. SPOT ROADMAP SUBTRACT RECALL SAVE L R 9600 WORKSTATION CONFIGURATIONS
VASC/4 HARDWARE & SOFTWARE CONFIGURATION
SCSI Troubleshooting Notes
Terminator Values: Boot-up Problems

U57, U58, U59: 1. If the system Application software boots up,
220/330 Ohms the DOS SCSI Disk Controller PCB is probably OK.
U57 Otherwise, remove the IP SCSI Disk Controller PCBs and reboot.
If this caused the system to not boot, replace this board.
Terminator RP1, RP2: 2. Try booting with the diagnostic disk in the A:\ drive.
Resistors
RN4
U58 100pf/100 Ohms If this is successful, you need to replace the
Must be P5 DOS SCSI Disk Controller PCB or the Hard Disk Drive.
Pin 1
Removed U15: 22 Ohms
U59 CINE LOOP Problems
RN3
1. Examine the green, yellow and red LEDs on the

IP-SCSI Disk Controller PCB. After boot-up,
use the table below to determine the probable cause of failure.
2. If only the cine loop is not working, try deleting the Header.Dat
file on the C:\ drive BUT YOU WILL LOOSE ALL PREVIOUS
RN2
RP1 CINE RUNS AND ALL 200 PATIENT IMAGES.

Pin 1 Reboot the system and verify operation.
J6 P9 See also Formatting the Cine Partition.
U15 3. Try replacing the IP-SCSI Disk Controller PCBs.
RP2 Formatting the Cine Partition.
J5 1. With the cart powered on, insert the diag. disk & press
SETUP OPTIONS, Select Access Level 2.
J9 2. Select "Prepare CINE Disk"
3. Reboot the system and verify operation.
J8
P3
SCSI 900659-02
IP SCSI Disk Controller Status LEDs
G Y R
JUMPER SETTING
O=OPEN S=SHORT off on off = Normal Condition

G
J5-1 O J6-1 S J8-1 O J9-1 O Y LEDs on on off = IP-SCSI Failure
J5-2 O J6-2 S J8-2 O J9-2 O

R on off on = IP-SCSI Failure
J5-3 O J6-3 S J8-3 O J9-3 O on on on = IP-SCSI Failure
J5-4 O J6-4 O J8-4 O J9-4 S on off on = IP-SCSI Failure
off on on = SCSI HDD Failure

J5-5 S J6-5 O J8-5 O J9-5 O
J5-6 S J6-6 O J8-6 O J9-6 S

J9
J5-7 O J6-7 O J8-7 O J9-7 S
J5-8 O J6-8 O J8-8 O J9-8 S

9600 C-ARM
ADAPTEC IP SCSI CONTROLLER - MASTER (4/8/15/30 FPS)

4&8_CINE.DS4 11/13/96
4 & 8 FPS CINE OPTIONS 9600 WORKSTATION CONFIGURATIONS
DOS SCSI & IP-SCSI DISK CONTROLLER CONFIG.
CNH 2
1 2 CNH7 5 6
CN 6
2 10 1 2
JUMPERED CN 5
AS SHOWN FIFTY PIN RIBBON
CONNECTOR
CNH5 TERMINATING
RESISTOR
INSTALLED
23 24
CNH1 CNH4 PIN 1
CNH 1
15 16
TERMINATOR 1 2 PIN 1
INSTALLED FOUR PIN POWER
CONNECTOR
FUJITSU M2684SAU
FUJITSU M2623FA AND M2624FA JUMPER AS ILLUSTRATED
9600 C-ARM
4&8_CINE.DS4 11/13/96

FUJITSU SCSI DISK JUMPER SETTINGS
7
6
JP3 246
15 1 2 1 PCB
J1 J3 J5
JP2 13 5
16 2
J3
7 J12
8
6 5
4 3
BOTTOM VIEW 2 1
Pin 1
J4
J8 PCB
7 1
Pin 1
J3
J6 8 2
33 31 23 20 19
18 17
16 15 531 31
14 13
34 32 24 12 11 J9 J6
10 9 PCB PCB
J8 8 7 642 4 2
6 5
4 3
2 1
NO JUMPERS J8
PCB
SEAGATE ST5660N SEAGATE ST3550N
7 1
J7
8 2
9600 C-ARM
TOP VIEW For Reference Only Page 6 of 6
4&8_CINE.DS4 11/13/96
HITACHI DK325C-57
HITACHI & SEAGATE SCSI DISK JUMPER SETTINGS
SET CONFIGURATION
System Model: ESP
Cine Disk: ALTA15
Language: ENGLISH
VCR1: Sony
VCR2: Sony
Image Processor PCB
Measurements: NO
875952 J2
Press [ESC] to exit
386 AT Motherboard
900658
Block Diagrams) P9
DRIVE
PARTIONING J5 Controller J9
PART # PART # PART # (U25) 00-900661-01
10 00-878230-01 00-900661-01 -02 P5
Q Logic D: DRIVE 30M 1.44 Meg
11 00-878230-02 00-900661-01 -03 900669 Data
D: DRIVE 60M SCSI DRIVE
Q Logic
P1 Data J17
DOS
P1 Power SCSI
NOTES J6 Disk J2
TRACKPAD PANEL Controller
Drives used: Fujitsu M2932SAU
J6 00-900659-02
Seagate ST11950N, ST12550N, or ST32550N
ACQUIRE IMAGES Micropolis 4221 Drive 1
WINDOW Power
See page 4 for hard drive jumper settings.
DC Power J11
876839
AT COMMUNICATIONS BOARD
(See Workstation Power
DISK DRIVE SELECTION JUMPERS E1-E3
FOR SCSI DISKS
Block Diagram #1) J4
VCR RECORD SHARPEN AUTO HISTO ON/OFF
SYSTEM TYPE

SCSI DISK
VCR PLAY LEVEL
Block Diagram
9600 C-ARM
TRACKPAD
15_CINE.DS4 11/13/96
AVERAGING
ESP/15, VASC/15 - (15 FPS) OPTIONS
ESP/15 HARDWARE & SOFTWARE CONFIGURATION
SET CONFIGURATION
System Model: VAS
Cine Disk: ALTA15
Language: ENGLISH
VCR1: Sony
VCR2: Sony
Image Processor PCB
Measurements: NO
875952 J2
Press [ESC] to exit
386 AT Motherboard
900658
SOFTWARE FORMATTED DOS SCSI DISK IP-SCSI DISK AT COMM. PCB Block Diagrams) P9
DRIVE
VERSION HARD DISK CONTROLLER CONTROLLER OPTION PROM IP SCSI
PARTIONING Disk
PART # PART # PART # (U25) J5 J9
Controller
00-900659-04 C: DRIVE 10M 00-900661-01
10 00-878230-01 00-900661-01 -02 Master
Q Logic D: DRIVE 30M 1.44 Meg P5
00-900659-04 C: DRIVE 10M Floppy Drive
11 00-878230-02 00-900661-01 -03 Drive 1
Q Logic D: DRIVE 60M 900669 Data SCSI DRIVE
P1 Data J17
DOS
SCSI
NOTES P1 Power
J6 Disk J2
Drives used: Fujitsu M2932SAU Controller
TRACKPAD PANEL 00-900659-02
Seagate ST11950N, ST12550N, or ST32550N J6
Micropolis 4221
Drive 1
Power
WINDOW
DC Power J11
PLAY/PROCESS REGISTRATION SHARPEN Distribution PCB J2
VCR RECORD PEAK OPACIFY AUTO HISTO ON/OFF SYSTEM TYPE

SCSI DISK
VCR PLAY MASK NEGATE LEVEL See also 9600 Workstation Motherboard
Block Diagram
9600 C-ARM
TRACKPAD
15_CINE.DS4 11/13/96
AVERAGING
FLUORO ONE-SHOT DIG. SPOT ROADMAP SUBTRACT RECALL SAVE L R
VASC/15 HARDWARE & SOFTWARE CONFIG.
J2
JP5 Boot-up Problems
Terminator Values: 1. If the system Application software boots up,
J1
the DOS SCSI Disk Controller PCB is probably OK.
3 4 U57, U58, U59: Otherwise, remove the IP SCSI Disk Controller PCBs and reboot.
220/330 Ohms If this caused the system to not boot, replace this board.
U57 2. Try booting with the diagnostic disk in the A:\ drive.
JP7 RP1, RP2: If this is successful, you need to replace the
JP2 DOS SCSI Disk Controller PCB or the Hard Disk Drive.
1
U58 100pf/100 Ohms
JP6 2 P5
Pin 1 CINE LOOP Problems
3 4
U15: 22 Ohms 1. Examine the green, yellow and red LEDs on the
U59 IP-SCSI Disk Controller PCB. After boot-up,
9 10 BIOS ROM use the table below to determine the probable cause of failure.
JP3 1 3 2. If only the cine loop is not working, try deleting the Header.Dat
JP4 file on the C:\ drive BUT YOU WILL LOOSE ALL PREVIOUS
7 1
CINE RUNS AND ALL 200 PATIENT IMAGES.
8 2
Reboot the system and verify operation.
RP1 See also Formatting the Cine Partition.
P2 P1 Pin 1
3. Try replacing the IP-SCSI Disk Controller PCBs.
P9 U15
Formatting the Cine Partition.
RP2 1. With the cart powered on, insert the diag. disk & press
2. Select "Prepare CINE Disk"
J1
1
J9
50 P3
J2
1 2 G Y R
3
330
I/O J10
QLOGIC off on off = Normal Condition
1 3 SCSI
J3 PROCESSOR J8 on on off = IP-SCSI Failure
230 J6 2 G
OUT
ASYNC
1 2
SYNC
IN BIOS ROM 1
Y LEDs on off on = IP-SCSI Failure
SCSI ID 7 SCSI ID 6
OUT
DISABLE
1 2 IN
ENABLE
TERM DIS
R on on on = IP-SCSI Failure
PARITY NO PARITY A B
SEE TABLE 1 SEE TABLE 1
3 4 on off on = IP-SCSI Failure
9 10 off on on = SCSI HDD Failure
J4
J5
IRO BIOSROM
7 1
8
15 12 11 10
2 J9
9600 C-ARM
15_CINE.DS4 11/13/96
Q LOGIC (2 MODELS) IP SCSI CONTROLLER - MASTER (4/8/15/30 FPS)
15 & 30 FPS CINE OPTIONS ESP/15, VASC/15 - (15 FPS) OPTIONS
JUMPER AS ILLUSTRATED DOS SCSI & IP-SCSI DISK CONTROLLER CONFIG.
FUJITSU M2932SAU
OEC JUMPERS
CN6: D (INTERNAL DIAGNOSTIC) OFF
P (PARITY SETTING) ON
A (AUTOMATIC MOTOR START) ON
ID1 ID0 CN4: ID0 OFF
ID1 OFF
RN1
ID2 OFF
CN7: SY (SPINDLE SYNC SIGNAL) OFF

ID2 NOT USED
R (DISK DRIVE RESET) OFF
RN2 W1 OPTION
WP (WRITE PROTECT) OFF
W3 JUMPER
TM (TERMINATION) ON
BLOCK
SEAGATE ST32550N
OEC JUMPERS
OEC JUMPERS
NO JUMPERS ON OPTI0N JUMPER BLOCK PIN 5 PIN 1
NO JUMPERS ON ID0, ID1OR ID2 PIN 6 PIN 2
MICROPOLIS 4221 JUMPER W1 & W3 J1
W1 JUMPER PINS 1 & 2 (TERMINATE POWER FROM DRIVE)
W3
JUMPER PINS 5 & 6 (ENABLE SCSI TERMINATION)
RN1 AND RN2 INSTALLED
NO JUMPERS ON J2 & J4
SEAGATE ST11950N AND ST12550N

PIN 1
OEC JUMPERS
J01
J4 - NO JUMPERS INSTALLED
PIN 2
J4 PIN 1
B POSITION
PIN 3 A POSITION
J01 9600 C-ARM
TERM. POWER FROM DRIVE: For Reference Only Page 4 of 4
SCSI 15_CINE.DS4 11/13/96
CONNECTOR POWER
PIN 1 CONNECTOR 9600 WORKSTATION CONFIGURATIONS
SCSI DISK JUMPER SETTINGS
SET CONFIGURATION
System Model: VAS
Cine Disk: ALTA30
Language: ENGLISH
VCR1: Sony
VCR2: Sony
4. Select "System Configuration" from the menu P8
Digital Print: No IP SCSI P9
6. Set the configuration by making selections from the following menu: Disk
Image Processor PCB J4 Controller J9
Measurements: NO
875952 J2 900661
(See Image Path Block Page 2) Slave
Date Format: MM/DD/YYYY DRIVE 2 (Right)
P5
386 AT Motherboard Drive 2 Drive 2
Press [ESC] to exit P3 Data Power
900658
(See 9600 Workstation & P3
Block Diagrams)
SOFTWARE FORMATTED DOS SCSI DISK IP-SCSI DISK AT COMM. PCB P9
DRIVE IP SCSI
VERSION HARD DISK CONTROLLER CONTROLLER OPTION PROM PARTIONING Disk
PART # PART # PART # (U25) J5 Controller J9
900661
2 REQUIRED 2 REQUIRED Master
1 MASTER&1SLAVE 1.44 Meg P5
00-900659-04 C: DRIVE 10M Floppy Drive Drive 1 Drive 1
10 00-878230-01 00-900661-01 -02
Q Logic D: DRIVE 30M 900669 Data Power
J17 DRIVE 1 (Left)
00-900659-04 C: DRIVE 10M P1 Data
11 00-878230-02 00-900661-01 -03
Q Logic D: DRIVE 60M
SCSI
NOTES P1 Power Disk
J6 Controller J2
Drives used: Fujitsu M2932SAU 900659
TRACKPAD PANEL Seagate ST11950N, ST12550N, or ST32550N
J6
Micropolis 4221
WINDOW
DC Power J11
REGISTRATION SHARPEN Distribution PCB J2
PLAY/PROCESS
SYSTEM TYPE
VCR RECORD PEAK OPACIFY AUTO HISTO ON/OFF MOTHERBOARD & DISK E1 E2 E3

SCSI DISK
VCR PLAY MASK NEGATE LEVEL See also 9600 Workstation Motherboard
Block Diagram
9600 C-ARM
TRACKPAD
30_CINE.DS4 11/13/96
AVERAGING
FLUORO ONE-SHOT DIG. SPOT ROADMAP SUBTRACT RECALL SAVE L R
VASCULAR WITH 30FPS CINE LOOP OPTION
HARDWARE & SOFTWARE CONFIGURATION
J1
J2 1
J9
50
JP5
J2
J1 1 2
3 4 3
330
I/O J10
QLOGIC
1 3 SCSI
J3 PROCESSOR J8
JP7 230 J6 2
JP2 1
OUT 1 2 IN BIOS ROM 1
ASYNC SYNC OUT 1 2 IN TERM DIS
JP6 2 SCSI ID 7 SCSI ID 6 DISABLE ENABLE
PARITY NO PARITY A B
3 4
3 4 9 10
J4
9 10 BIOS ROM J5
BIOSROM
JP3 1 3 7
IRO
1
JP4 8 2
7 1 15 12 11 10
8 2
P2 P1
DOS SCSI CONTROLLERS
Q LOGIC (2 MODELS)
9600 C-ARM
15 & 30 FPS CINE OPTIONS
30_CINE.DS4 11/13/96
DOS SCSI CONTROLLER CONFIGURATIONS
Terminator Values: Boot-up Problems

1. If the system Application software boots up,
U57, U58, U59: the DOS SCSI Disk Controller PCB is probably OK.
220/330 Ohms Otherwise, remove the IP SCSI Disk Controller PCBs and reboot.
U57 U57 If this caused the system to not boot, replace this board.
RP1, RP2: 2. Try booting with the diagnostic disk in the A:\ drive.
If this is successful, you need to replace the
U58 100pf/100 Ohms U58 Pin 1
P5 P5 DOS SCSI Disk Controller PCB or the Hard Disk Drive.
Pin 1
U15: 22 Ohms CINE LOOP Problems
U59 1. Examine the green, yellow and red LEDs on the
IP-SCSI Disk Controller PCB. After boot-up,
U59 use the table below to determine the probable cause of failure.
2. If only the cine loop is not working, try deleting the Header.Dat
file on the C:\ drive BUT YOU WILL LOOSE ALL PREVIOUS
RP1 CINE RUNS AND ALL 200 PATIENT IMAGES.
RP1 Reboot the system and verify operation.
Pin 1
P9 P9 Not Installed See also Formatting the Cine Partition.
U15 U15
3. Try replacing the IP-SCSI Disk Controller PCBs.
RP2 Formatting the Cine Partition.

RP2 1. With the cart powered on, insert the diag. disk & press
2. Select "Prepare CINE Disk"
P3 P3
G Y R
off on off = Normal Condition

G G on on off = IP-SCSI Failure
Y LEDs LEDs
R Y on off on = IP-SCSI Failure
R on on on = IP-SCSI Failure
on off on = IP-SCSI Failure
off on on = SCSI HDD Failure
J9 J9
9600 C-ARM
IP SCSI CONTROLLER - MASTER (4/8/15/30 FPS) IP SCSI CONTROLLER - SLAVE (30FPS) 30_CINE.DS4 11/13/96
IP-SCSI CONTROLLER CONFIGURATIONS
FUJITSU M2932SAU
OEC JUMPERS
CN6: D (INTERNAL DIAGNOSTIC) OFF
P (PARITY SETTING) ON
A (AUTOMATIC MOTOR START) ON
ID1 ID0 CN4: ID0 OFF
ID1 OFF
RN1
ID2 OFF
CN7: SY (SPINDLE SYNC SIGNAL) OFF

ID2 NOT USED
R (DISK DRIVE RESET) OFF
RN2 W1 OPTION
WP (WRITE PROTECT) OFF
W3 JUMPER
TM (TERMINATION) ON
BLOCK
SEAGATE ST32550N
OEC JUMPERS
OEC JUMPERS
NO JUMPERS ON OPTI0N JUMPER BLOCK PIN 5 PIN 1
NO JUMPERS ON ID0, ID1OR ID2 PIN 6 PIN 2
MICROPOLIS 4221 JUMPER W1 & W3 J1
W1 JUMPER PINS 1 & 2 (TERMINATE POWER FROM DRIVE)
W3
JUMPER PINS 5 & 6 (ENABLE SCSI TERMINATION)
RN1 AND RN2 INSTALLED
NO JUMPERS ON J2 & J4
SEAGATE ST11950N AND ST12550N

PIN 1
OEC JUMPERS
J01
J4 - NO JUMPERS INSTALLED
PIN 2
J4 PIN 1
B POSITION
PIN 3 A POSITION
J01 9600 C-ARM
TERM. POWER FROM DRIVE: For Reference Only Page 4 of 4
SCSI 30_CINE.DS4 11/13/96
CONNECTOR POWER
PIN 1 CONNECTOR 9600 WORKSTATION CONFIGURATIONS
SCSI DISK JUMPER SETTINGS
10 U20, U21 U13 P7
VCC DIAGNOSTIC 2
DIAG_DISPLAY_WR LED 7 6
P4 10
1 11 LATCH
13 12 2 3
1 Electronic Rack Assembly
DS1 DIAGNOSTIC LED (1D2)
U11
(2D5) Externally Auxiliary AT Communications PCB
(2C4) Mounted
Interface 00-872125
VCC VCC
(1D4)
U24 PCB
1 7
MAX694 00-876502
FORCE SENSITIVE RESISTOR CONTROL 2
(Power 5
37 Monitor &
Watchdog 6 U11
HSO.0 28
13 VREF (1D5) Timer) 1
TP11
6 U11
Cart Control Panel 4 P0.3 14 2
OSC 5 Y1
Processor PCB 7 P0.2 12 MHZ
00-876611 P1.1 20
(1D3)
5 P0.1 TP12
ACQUIRE IMAGES
U27
WINDOW 6 P0.0 RESET15 DUART
PLAY/PROCESS ZOOM NEGATE 12 AGND (1B5)

(1D7) (1C8)
U16, U17 (1C6) RESET J2 P9 P12 P14 P3
VCR RECORD SHARPEN AUTO HISTO ON/OFF TRACK PANEL TP2
P1
LED
LED_16-31_WR 1 2 8 8 8 CPICTS 23 23 11 12 U33
LATCH CTS 44 3 4 U16 12 - OP1
VCR PLAY LEVEL 11 E5 DATA
13 BUFFER
(2D3) TP7 (1B3)
RXD 17 1 2 10 10 10 CPIRXD 24 24
TRACKPAD 20 19 U16 11 - TXDB
E3 3 2
(1D7)
(1C6) U7
AD0 - AD15 MAX233 To & From
U12, U19 TP6 Motherboard
P6 FRONT PANEL 1 2 6 6 CPITXD 25 25 4 6 See Motherboard
LED TXD 18 1 18 6
U5 U15 10 - RXDB Block Diagram
LATCH LED_00-15_WR E2
Track Panel 11
80C196KC TP3 (1B4) U30,U31
(2C3) (1B6) 1 2 4 4 CPIRTS 5 5 ADDR
RTS 39 2 5 4
U15 4 - IP1 BUFFER
E4 10 8
(1B6)
(1C8)
U15, U23 P2.2 15 35-CEN
KEY BOARD
INPUT LATCH
(COLUMN READ) COL_READ
URTBSEL*
11 VCC
(2D5)
FLUORO ONE-SHOT DIG. SPOT ROADMAP SUBTRACT AVERAGING RECALL SAVE L<--->R
1
R11 TP14 P1
23
5 TP4
U18, U22 2
+5VIN
Front Panel KEY BOARD +12VIN
4 U24
OUTPUT LATCH 1 22V10
(ROW DRIVE) 3 ADDR
ROW_DRV TP1, TP10 5
11 DECODE
3 TP8, TP13
P5 (2B5)
U14,U2 U3
ADDRESS 74LS08 (2D7)
DECODE D
(1D7)
74ABT573
1 2
(1B2)
LATCHED ADDR. 0 - 15
SEGMENT 10 BLINKS ON & OFF
1 TO INDICATE THAT THE MICRO
P3 CONTROLLER (U5) IS RUNNING
U9
IR LCL Opto_I +12VIN 1 See IR Remote
TP5 1 IR_LCL 2 Control Block
+12VRET 3 Diagram for
7 4 4 more Details
+12VRET
U4 PAL U10 U1
ADDRESS
DECODE
EPROM
(BOOT)
STATIC
RAM
(1D7) 9600 C-ARM
(1B1) (1C2) (1C1)
IR RMT For Reference Only Page 1 of 2
TP9
U8
5 (not used) CPI_BLK1.DS4 6/17/96
RS422
INPUT
(1D7)
Key Board RESET 9600 CONTROL PANEL PROCESSOR
BLOCK DIAGRAM
9600 Mobile Digital C-Arm - Workstation Block Diagrams, Test Points, and Signal Waveforms
GND
DURING BOOT UP
TP4
GND
TP1
Screen
Waveforms
Image
U33
C
B
A TP2
CTS
5 Vdc
5S
U15-1 TP5
P1
COL_READ IR LCL
100 mVdc 500 mVdc
200 ns 50 ms
TP3
RTS
5 Vdc
5S
U31
U30
E
TP6
TXD
ASSY 00-876613 2 Vdc
CONTROL PANEL PROCESSOR 5 ms
9600 MONITOR CART
U24
F
TP2
U1 TP1 C
TP7
CTS P1 1 2 3 4 5 6 P2 P3 RXD
GND
2 Vdc
E2 E3 5 ms
R11
1 1
U2 1 1
E4 E5 U3
TP3 TP4
D
U4 U7 U8 U9
TP5
RTS +12V B
TP6 TP7 IR
Y1 E F
LCL
U5 TXD RXD TP9 TP8 C
U16
U10
U11 U12 U13
U14 IR GND
11
RMT 12
DS1 11 A 3 F
13
TP10 TP11 TP12 U15 2
OP1 12
SEGMENT 10
U16 U17 TXDB 11
GND OSC RST* RXDB 10
G 8 E
U18
L 18 U19 6
10 4
I
U20 U21 U22 K 6 P7-1
SPKR
U15
U23 U24 IP1 4 D
10 Vdc
100 us
U27
P5
J H P7 G
TP13 H
COMMUNICATIONS PCB
TP14
P4 P6
OEC-DIASONICS INC
P7-2
GND +5V SPKR
10 Vdc
00-872126-01
100 us
P3
Screen
Waveforms
Image
GND
TP2
GND
TP3
K
L
J I
U20-18 TP11
SEG. 10 OSC U24-6 TP12
2 Vdc 1 Vac WDI RESET
200 ms 50 ns 2 Vdc 2 Vdc
1 ms 500 ms
9600 C-ARM
Measurements For Reference Only Page 2 of 2
CPI_BLK1.DS4 6/17/96
9600 CONTROL PANEL PROCESSOR

BLOCK DIAGRAM
2
A/D Clamp 50 Hz
See Image Path Block See Video Matrix
Diagram (U7; SW201) Block Diagram
A/D Clamp Circuit Video Switching PCB Image

00-872237 Processor
PCB
+ 5V 00-875952
B
U6 2A See Image Path
P6 P6 Block Diagram
R156
Camera Video (High=50Hz; Low=60Hz) 50Hz 31 31
Out of U13 R25 C26 2 5
Sync Separator
See Image Path Clamp Output 1
Block Diagram DS1/DS2 Display Driver Sync Generator 3
U42 A
1
SepIncsy (1D5)
+ 5V + 5V U39 2
(2B3)
Buffer
-3.3V 2N HDRV* 23 23
+2.5V 4 2
R87 U40 2O VDRV* 25
R96=1k -0.8V 5 7 25
Vertical Sync Separator Sync Generator
(3.3V) 2P CSYNC* 19 19
5 5 12 10 To GSP (U140)
1 & Memory
+ 5V R93=1k 12 DS1 2 - MODE 2Q CBLANK* 17 17
13 15
(1.7V)
U45 On with 16 Addressors
Cart 2M
2B 4 9-CLK
(2B6) 3 (2B3) To U42.13
R107 R94=1k 15 - VRST See "LOG" on
U32 4
Q8 U41 Image Path Block Diagram
R105 2-B 14 Buffer Page 1 of 5
5-Q 8 - OSC
4 2R EVENFLD 27 27
(1C7) 1 2
12-Q (2B3)
1-A TP38
(2B6) 5 2S CLAMP 21 21
Correction Voltage 6
+ 5V
2G (2.5V) CLAMP
-2.5V B
+1.7V 9-CLK (2A3)
R95 PIXEL CLK 29 29
-0.8V
Horizontal Edge Comparator/Camera Sync Detection 2
3 Syncdet
1 10 1 3 3
U28 3 U37 7 DS2
2-B 13-Q U45 On with
HI = 60Hz Stand-Alone
Syncdet - To P6.3 3 Camera
(2B6) 9 Lo = Camera Sync Present
Sync Detect (2B6)
4-Q 2T 1 Y1 Y2 1
1-A
(2A7) 60Hz 50Hz HI = 50Hz Stand-Alone
Lo = Camera Sync Present
U44 25.8 Mhz 25.6 Mhz
Edge 3 3
Enable
Enable
+ 5V U29
U38
Comparator
VCO Adjustment 2I
2D PAL16V8
2C 10-B 5-Q 2F
9 18
Camera
9-A 12-Q 14 - "A" U43 1
TP33 17
(2B8) Voltage Controlled (High=50Hz; Low=60Hz)
3 - "B"
13
Oscillator VCO 2H 5
2K
+ 5V
12
U38 1 2
2-B 13-Q 2E 1 3 U36 8 10 19
C89 L12 E4
Cart (2A4) 3 4
CSYNC* 4-Q 7 - Genlock 16 U36
A 1-A (2B7) 18 (2A5)
(2A8) 2 3 (2B4) (2A4)
2J 2L
1 Adjust C89 so DS1 & DS2 are equally illuminated 3 SYNC WITH CAMERA
High = Enabled (Camera Sync Present) 9600 C-ARM
U29 Pin 8 is frequency input pin.
and both monitors have stable images when camera sync present. When camera sync is present, Sync Detect = TTL High. This signal is monitored by the
Low = Disabled (Camera Sync Not Present) For Reference Only Page 1 of 2
TP33 will equal approximately 25.8 MHz. Image Processor and forces GENLOCK bit TTL High. This forces U29 to use pin 8 as
U29 Pin 9 is frequency input pin.
TP38 will equal approximately 2.5 VDC. the input frequency for the sync generation circuitry. GEN_LOK1.DS4 6/19/96
STAND-ALONE MODE 3
When camera sync is not present, Sync Detect = TTL Low. This signal is monitored by GenLock
2 This video control bit is changed through software for 50 or 60 Hz systems. 9600 WORKSTATION "GEN-LOCK"
the Image Processor and forces GENLOCK bit TTL Low. This forces U29 to use pin 9 as See Video Matrix
To do this: 1) Power on Cart, 2) Insert Diag. Disk, 3) Press F10, 4) Access Level 2, the input frequency for the sync generation circuitry, using the 50Hz or 60Hz crystal. Block Diagram BLOCK DIAGRAM / WORKSHEET
5) Select Config & Hard Disk, 6) Set System Config. Then follow screen instructions.
TP23 TP27 TP28 TP26 VIDEO SWITCHING PCB R129
AUXILLARY INTERFACE PCB
AGND +5V +12V +5VA 872237 TP10 876502
TP25 TP24 TP19 TP30 4A P10
7
DGND -5V -12V +5VR U13 Mux IN0
5 8
U4
- J6 J1 1 J13 P1 CAMERA
VIDEO
(1D6) IN1
IN2 (1D7) + 5 2 14 FROM
2 20
U6 VOUT
1
IN3
J7 J2 3 15 C-ARM
TO GEN-LOCK IN4
1 SYNC IN5 23 LEFT
& SYNC BLOCK
SEPARATOR L L L IN6 4 MON
DIAGRAM A2 A1 A0 IN7 J12 24 VIDEO
1 2 3
(1D5) (NOT
USED)
8 TP3
J5 INSIDE WORKSTATION
TP16 See Gen-Lock
4B LMON 3 ELECTRONICS BOX OUTSIDE WORKSTATION
A/D VIDEO - 7 Diagram N. C. ELECTRONICS BOX
8 2 (SEE 9600 WORKSTATION
U4 AT MOTHERBOARD
(1D4) +5 2
TP2 BLOCK DIAGRAM)
3 U8 Mux
1
9
IN0
IN1
J3 J4
U7 (1C6)
Clamp IN2 20 3 8 LVID 5 LEFT VIDEO
SW201 IN3 VOUT U1
3 Output IN4
1 6 (REAR PANEL)
IN5
(1D4) IN6 L H L TP5
IN7
A0 A1 A2
3 2 1 HCO 9
CBLANK* J6
(2B3) 10
13 (H) HARD COPY VIDEO
11 (FRONT OF ELECTRONICS BOX)
U42 12 See 5 TP8
IN0 U12 Mux
2 1 VMDATA IN1 AUXOUT 3
LOG Block (1A6) 4
+5V R50 R80 R51 -5V A0 IN2 20
1 L Diagram IN3 VOUT 4 N. C.
TP22 U19 Mux TP21 IN4
IN5
1
2 R80 typically does not need to be adjusted.
NOTE:
5
(LOG) 4D IN6 L L L TP4 This pot adjusts the DC offset for U26 so Shorting the J9 (Bypass) connector on
4 IN7
7 (2D7) + IN0
VOUT
8 A0 A1 A2 the 3
DC level of TP16 matches that of TP22. the Video Switching PCB will direct live
- 7 U26 IN1 3 2 1 RVIDEO 7 4
U46
8 - 8 5 (2D5) N. C. camera video to the "Video" BNC
5 (2D6) 3 A/D CLAMP - See Gen-Lock Block Diagram connector on the rear panel of the
+ 8 SW201 closes pins 2 & 3 when a TTL low is placed on pin 1.
7 IN0 U9 Mux
Pin 1 goes low during vertical and horizontal retraces.
Workstation. This can be used for
Log Amp
IN1
(1C6) This ensures the A/D video signal is grounded (or clamped) troubleshooting purposes as required.
IN2
IN3 VOUT
20 3
U2 J5 to eliminate video noise during retrace. See page 4 of this drawing for
IN4
1 RMON 1 location of the J9 connector.
IN5
N. C. Connected to rear panel BNC connector on system serial
IN6 L L H 4 4
IN7 numbers 69-0001 to 69-1000
A0 A1 A2
3 2 1
1
1 A0 A/D VIDEO 5
Anti-Alias Filter H U10 Mux TP6
TP29 U18 Mux TP18
IN0
J4 J2
(Always Used) IN1 (1B6)
4E 4
(ANTI-ALIAS) 4C IN2
IN3
20 TOVCR1 3 TOVCR1
8 VOUT
3 8 4 10 IN0 IN4
4
U25 U24 IN1
VOUT IN5 1 (INTERNAL VCR)
5 (2D4) IN6 L L L
(2C5) (2C4) IN7
A0 A1 A2
3 2 1 AUXILLARY INTERFACE PCB
876502
5 TP7
IN0 U11 Mux P19
IN1
(1B6)
TP20 IN2
IN3
20 TOVCR2 1 9 P21 N.C.
1 Default patterns after boot-up shown. VOUT
LDAC See 9600 Workstation "VMDAT"
IN4 1 2 10 TOVCR2
TP17 IN5 Q3
4F RDAC
Video Matrix Data Block Diagram IN6
IN7
L L L 1 1
20 bits from VMDAT. A0 A1 A2 P20 N.C.
TP12 2 2
4F 18 (6 MUXs; 3 address bits each)
1 (LOG amp enable)
3 2 1 (1C7) FROM VCR2 9600 C-ARM
1 (Anti-Alias filter enable) IN4 VCR2 Q2 For Reference Only Page 1 of 5
TP13 3 J1 FROM VCR1
IN3
VCR1 (1C8) 4 (INTERNAL VCR) IP_BLK1.DS4 12/5/96
P1
J17 LEFT IMAGE PATH
J11 5 6 9 10 1 2 P6 FAST SCAN VIDEO BLOCK DIAGRAM
2A 2B 2C 2D 2E (REAR PANEL)
1A A/D LEFT 1C RIGHT 1E FAST
1B 1D
VIDEO VIDEO VIDEO FROM VIDEO SWITCH PCB SCAN
OUT OUT (See Sheet 1) VIDEO
TO
REAR
PANEL
LEFT MONITOR RIGHT MONITOR
J1 J1
P4
VIDEO IN 5 LEFT & RIGHT
6 FAST SCAN
VIDEO
RIGHT VIDEO OUT 1
2 OUTSIDE WORKSTATION J8 J7
ELECTRONICS BOX
LEFT VIDEO OUT 9 INSIDE WORKSTATION ELECTRONICS BOX
RS170 SYNC SIGNALS 10
TO / FROM VIDEO
SWITCHING PCB DIGITAL IMAGE DATA
SEE GEN-LOCK & TO / FROM IP-SCSI PCB(S)
SYNC BLOCK ON CINE SYSTEMS
DIAGRAM
LEFT & RIGHT DIGITAL VIDEO
AND SEE 9600 WORKSTATION CONFIGURATION 2 X 8 BIT VIDEO DATA & TIMING
VIDEO MATRIX BLOCK DIAGRAMS FROM IMAGE PROCESSOR PCB
DATA BLOCK 5G 5H
DIAGRAM
J5 J6 J8 J9 J3 J4
TP1 TP6 TP3 TP7
P9 P8 AGND J2
P6 TP4 TP2 TP6 TP7 TP1
U16 U2 TP3
RDAC LDAC U17
SCAN CONVERTER PCB
5J 5J 5J
U3 U4 P4 ADC
PIO PIO ASY. 876399 / SCH. 876397
OR
F/F (FULL FRAME) SCAN CONVERTER PCB
ASY.878891 / SCH. 878889
P3
TP4
GND TP8
+5V
+5 VOLTS & GROUND

FROM MOTHERBOARD
9600 C-ARM
U140
GSP For Reference Only Page 2 of 5
IP_BLK1.DS4 12/5/96
P1 P2
IMAGE PATH
GSP SOFTWARE DOWNLOADED
FROM AT MOTHERBOARD
BLOCK DIAGRAM
Data Bus To/From Technique Processor
See Technique Processor/ Analog Interface
Block Diagram
AUXILIARY INTERFACE VIDEO SWITCHING IMAGE PROCESSOR
00-876502 +5 00-872237 00-875952
TP27 Lemo U3
U22
Store conn. R155 L with X-rays
PIO_3 P2 P106 P2 P10 P9 P8 P6 PIO
P1 P6
U23 10
101 101 13 4 STORE (X-ray On) 10 2 2 XRAYON 7 7 X_RAY_ON
40 U42 19 1
13 12 8
9
(2D4)
(1A8)
(2D2)
L with X-rays
(2D7)
AT COMMUNICATIONS
MOTHERBOARD 00-872125
00-875539 TP7 P14 P3 U14 8 Bit
LATCH Data Bus to
22 22 AT Mother PCBr
6
XRAYON
(1A5)
ANALOG INTERFACE
00-876736
GENERATOR WORKSTATION
1 Image Processor Enable (This signal has nothing to do with X-ray logic.
A TTL Low indicates the system is taking X-rays and the IP is enabled.
9600 C-ARM
IP_BLK1.DS4 12/5/96
IMAGE PATH
BLOCK DIAGRAM
To view Left and Right DAC and Monitor AUTO FLUORO MODE - NOTHING IN FIELD
outputs, use this computer generated image. Amplitude may vary slightly.
(Press TEST PATTERN; Swap L>R; TEST PATTERN) This is one horizontal line from the image
shown on the left. Note the gray scale levels.
Your waveform may vary slightly depending
on which horizontal line being viewed.
1E
1F
To IP
A:D
From From
IP RDAC IP LDAC 200 mV dc
10 us
TP29 P6
J11
200 mV dc TP3
This computer generated image should appear TP2 U8-Mux
TP17 TP20
10 us LMON RDAC LDAC
on both left and right monitors. LVID 1 2 3
To Aux. Interface PCB
& Interconnect Cable J9
J5
(Not Used) TP18 BYPASS
J7 A/DV TP21 (NOT INSTALLED)
U9-Mux
1 2 3
TP4
RVID
TP39 TP13
AGND VCR1
TP5 TP6
HCO U10-Mux
TOVCR1 1 2 3
From C-Arm TP10

Camera DGND
AUTO FLUORO MODE - NOTHING IN FIELD J6
Amplitude may vary slightly. TP16
A/DVIDEO
TP40 VIDEO
U11-Mux
1 2 3
TP26
SWITCHING
+5VA
TP8
AUXVOUT
U12-Mux TP27
PCB
1 2 3 TP23 +5V TP30
AGND TP25 +5VR
DGND TP28
+12V
TP19 TP24
1A U13-Mux
-12V -5V
1 2 3
200 mV dc
10 us AUTO FLUORO MODE - NOTHING IN FIELD
Amplitude may vary slightly.
AUTO FLUORO MODE - NOTHING IN FIELD
AUTO FLUORO MODE - NOTHING IN FIELD Amplitude may vary slightly.
Amplitude may vary slightly.
1D
1B 1C 9600 C-ARM
IP_BLK1.DS4 12/5/96
500 mV dc
10 us
IMAGE PATH
500 mV dc
200 mV dc
10 us BLOCK DIAGRAM
10 us
To view Left and Right DAC and Monitor
outputs, use this computer generated image. This is one horizontal line from the image shown on the left.
(Press TEST PATTERN; Swap L>R; TEST PATTERN) This is one horizontal line from the image Note the horizontal timing and the gray scale levels.
shown on the left. Note the gray scale levels. Your waveform may vary slightly depending
Your waveform may vary slightly depending AUTO FLUORO MODE - NOTHING IN FIELD on which horizontal line being viewed.
on which horizontal line being viewed. Amplitude may vary slightly.
2G 2H 2J
200 mV dc 200 mV dc 200 mV dc

This computer generated image should appear 10 us 10 us 5 us
on both left and right monitors.
TP1 TP6 TP3 TP7

P6 P9 P8 AGND
J5 J6 J8 J9 J3 J4
U16 U2 J2
TP4 TP2 TP1
RDAC LDAC U17
P4 ADC
SCAN CONVERTER PCB
ASY. 876399 / SCH. 876397 J5 J6 J8 J9 J3 J4 TP5
OR AGND
TP10
F/F (FULL FRAME) SCAN CONVERTER PCB TP9
ASY.878891 / SCH. 878889 The illustration in the dotted box shows
the locations of test points on the
F/F Scan Converter PCB. Asy. #878891
9600 C-ARM
IP_BLK1.DS4 12/5/96
P1 P2 IMAGE PATH
BLOCK DIAGRAM
Image Processor PCB 24 Bits into Three 8 Bit Video Switching PCB
00-875952 Serial to Parallel Shift Registers
A 00-872237
+5V U33 - 74LS595
TP35 Bit 24
(1B7)
VMDAT 15-QA
14-IN 1-QB + 5V
X-RAY DISABLE - See X-Ray Disable Block Diagram
TP36 2-QC GENLOCK - See Gen Lock Block Diagram
10-MR 3-QD
VMLCLK 50 Hz - See Gen Lock Block Diagram
12-RCK 4-QE LOG - See Image Path Block Diagram & Gen Lock Block R144
B 11-SRCK
5-QF
6-QG
A2 ANTI ALIAS - See Image Path Block Diagram
U3 A1
7-QH
PIO To U13
+ 5V 13 9-OUT See Image Path U27
Block Diagram PAL16V8
U34 - 74LS595 2
P6 P6 R154
A0
+5V (1A7) 15-QA 1 E A2
15 9 VMEN* 9 14-IN 1-QB 4 18 To U8 - See Image Path
5 A1
2-QC 17 A0
13 VM-DTCLK 13 10-MR 6 Block Diagram
13 3-QD 16 A2
12-RCK 4-QE 7 15 To U9 - See Image Path
11 VMDATA 8 A1
From GSP 14 11 5-QF 14 A0 Block Diagram
See Image 11-SRCK 6-QG 9 13
15 VM-LTCLK A2
Path Block 11 15 7-QH
Diagram
13 9-OUT To U10
11 (1A7)
See Image Path
Block Diagram
U35 - 74LS595
(1A7) A1 R146
(2D2) +5V 15-QA A0
C 14-IN 1-QB A2
2-QC A1 To U11 - See Image Path
10-MR 3-QD A0 Block Diagram
TP37 12-RCK 4-QE A2
VMDCLK 5-QF A1 To U12 - See Image Path
11-SRCK 6-QG A0 Block Diagram
7-QH
Bit 1
13 9-OUT
D
P6
VIDEO SWITCHING PCB J9 TP35 VMDAT
C
TP37 VMDCLK
U33
E 1 U27 2
U34 A
TTL Low = Normal State WAVEFORMS & DATA
TP36 VMLCLK TP37 VMDCLK TP35 VMDAT TAKEN AFTER SYSTEM
HAS SUCCESSFULLY
U35 13 BOOTED UP.
B
TP36 VMLCLK
D
TTL Low = Shift Register
Enable
5 V dc
20 us
+5VA
TP23
TP26
TP30 9600 C-ARM
AGND +5VR
DGND Bit 24 (U27.2) For Reference Only Page 1 of 1
TP25 +5V 1
This bit is always set low. This allows PAL U27 to initialize muxes U8 & U9 using the data
TP19 TP27 TP28
TP24 +12V from U34. If this bit is high (i.e., due to a transmission error) U27 will set mux U8 to the VM_DAT1.DS4 6/19/96
-12V -5V BYPASS mode (see note 1 above).
9600 WORKSTATION "VMDAT"
VIDEO MATRIX DATA
IR Receiver PCB
00-874220
RP1
PhotoCell
E3 E1 E2
TP1 typical voltage range:
Dark room = -1.2 VDC
Lighted room = +1.2 VDC
P6 3 1 2
TP1
+12V U2 P4
R13 R10 R9 3
+ R36 R14 2
P1 1 LEFT MONITOR
See
1 +12V 2 LM324 CONTRAST
Workstation TP2 R8 C6 -
2 +5V R11
Power
4 -12V
Block
3 R3 R18 R16
Diagram
P3
4 1 16 CR2
1
R5
2 R6 5 + U2 CR4
R25 LEFT MONITOR 5
LEFT 7
3 8 6 BRIGHTNESS
CONTRAST C5
n.o. 4 -
R2
5 R7
6 R4 R27 R23
P2
2
LEFT
BRIGHTNESS 3 9
R1 n.o. 13 P5
5 R24 R23 10 U2
+ 8 R37 R33 2
11 RIGHT MONITOR
K1
9 CONTRAST
R22 C8 -
R12
P3
2 R26 R35
RIGHT R34
-12V
CONTRAST 3
R4
CR5
5
R17 R19 U2
12 CR3
P2 + 14 R29 RIGHT MONITOR 5
2 BRIGHTNESS
13
RIGHT C7 -
BRIGHTNESS R15
3
R3 R31 R30 9600 C-ARM
5 For Reference Only Page 1 of 2
TP2 R21
CON_BRT1.DS4 6/17/96
High Scan Brightness / Contrast Control

MONITOR CONTRAST & BRIGHTNESS
+5
00-876351
BLOCK DIAGRAM
Monitor PCB
Brightness
Adjustment
Monitor PCB
Contrast
Adjustment J1
R3
Video
Input
R4
J1
J3 Video
Input
J6
J3 Brightness
Adjustment
J6
Contrast
R1 Adjustment
V
CENT R2
VLIN
H V
VFRQ *
CENT SIZE
There should be no bleeding
HFRQ
* of the white part of the image.
Look here to check for excessive
SUB contrast pot adjustment..
Monitor Adjustment CONT * A33P12
Q1
Access Holes R1
R2 All steps in the gray
scale should be visable.
DO NOT ADJUST * To Ambient Room light sensor
(Part of IR Receiver PCB)
A33P6 C1
H U1
SIZE
A33P7
Monitor Side View CR1

A35P9 K1
For Monitor Adjustment refer to
REMOTE CONTRAST/BRIGHTNESS/
IMAGE SYSTEM CALIBRATION
A35P3
To Left Monitor Contrast Pot
MONITOR BRIGHTNESS & CONTRAST SETUP
C2 Setup the monitor brightness and contrast in normal room lighting conditions.
OEC-DIASONICS,INC
Monitor Adjustment
ASSY 00-876353- ( )
To Left Monitor Brightness Pot A35P2
Access Holes A33P1
1. Turn off AUTO HISTO & WINDOW / LEVEL
DO NOT ADJUST 2. Call up TEST PATTERN on both monitors by pressing
* To Right Monitor Contrast Pot
A33P3 the TEST PATTERN button and the L-R button.
C5
3. Adjust brightness and contrast pots R1 - R4 to minimum.
R4
TP2
R3
C3
*
G2 Sub Brightness C4 R5 R6 R7 4. Adjust the brightness pots R1 & R3 until the raster lines on both monitors
To Right Monitor Brightness Pot A33P2
C6 are just visable.
Monitor PCB R10 R8
Focus
CR2
R9 R11 5. Adjust the contrast pots R2 & R4 until all steps in the gray scale test pattern
R36 R12 R13
R14 R15 on both monitors can be seen without causing the white areas of the image to bleed.
R16 R17 C7
U2 R19 R20
A35P4 R18
9600 C-ARM
To J3 on Left Monitor Circuit PCB
C10
C9
R21 C8
R22
R25 R23 R24 For Reference Only Page 2 of 2
To J3 on Right Monitor Circuit PCB R28 CR3 R26
R27 CR4
A33P5 R31 CON_BRT1.DS4
R37
R29 R30
CR5 R32 TP1 typical voltage range: 6/17/96
R35 Dark room = -1.2 VDC
Monitor Bottom View R33 R34
TP1 Lighted room = +1.2 VDC MONITOR CONTRAST & BRIGHTNESS
Adjustment access holes are BLOCK DIAGRAM
located in the monitor mounting plate
Top of
AT Communications PCB
P3 P14 P15 Electronics
00-872125
Auxiliary Box VIDEO CABLE P/N
+5V
See 9600Workstaion
Interface 00-876803-03
R4 (2D5) PCB For Sony 9500
Block Diagram 1
To & From 00-876502 P10
AT Motherboard Internal
(2D5) VCR
2 3 4 5 6 7 8 9 10 Control
U18 A 2 VCRSTP1* 3 See Image Path
18 1 46 46
Buffer U8 Block Diagram
PORTD-W
Data 16 B 1 2 RECORD1* 27 27 4
U17
15 C 3 4 PAUSE1* 29 29 6
1 U17
14 D 11 10 PLAY1* 32 32 7
U17 VCR 1
11 13 E 5 6 FFORWD1* 31 31 8
U17
CLK 12 F REWIND1* 34 34 9 CONTROL CABLE P/N
9 U17 8
(2D6) 00-876802-01
(2D5) For Sony 9500
See 9600 Service Manual
Peripherals Section
U6 2 G PLAYIN1 35 35 10
Buffer
U26 PORTE-R 4 1
DUART-PIO 4 H STOP U38
Test Point PAUSE RECORD PLAY Control Cable On/Off
6 (2D5)
5 Pulses LOW when VCR Record N/C from
6 I RECIN1* 44 44 2 HIGH Lite turned OFF on Trackpad. HIGH PAUSE
A
Addr 1
15
VCREN* Pulses LOW when VCR Record N/C from
K 8 J PAUSEIN1 37 37 11 B HIGH Lite turned ON on Trackpad.
HIGH PAUSE
(2D6)
With VCR Record Lite ON, this
+5V pulses LOW when a) X-ray
C Pulses LOW when VCR Play Pulses LOW without
2 HIGH switch pressed or released, or
Lite turned ON or OFF. control cable connected.
(1C5) 19 b) VCR record lite turned OFF.
50 50 20
2
D Pulses LOW when VCR Pulses LOW without
HIGH HIGH control cable connected.
Record Lite turned OFF.
U24 R17
PAL22V10 E N/C from
HIGH HIGH HIGH PAUSE
19 CONTROL CABLE P/N CONTROL CABLE P/N N/C from

PORTDW* 00-876452-01 00-876534-01 F HIGH HIGH HIGH PAUSE
L
G Pulses HIGH when VCR TRI-STATE without

LOW Record Lite turned OFF. LOW control cable connected.
21
PORTER*
M HIGH HIGH N/C from
H HIGH PAUSE
(2D7)
LOW = VCR Record Lite ON N/C from
HIGH HIGH PAUSE
I HIGH = VCR Record Lite OFF
HIGH = VCR Record Lite ON &

J X-ray switch pressed. HIGH without control
LOW PULSES HIGH = VCR Record HIGH = VCR Play Lite ON cable connected.
Lite turned OFF.
AT COMMUNICATIONS PCB N/C from
K
1 Test point data taken with VCR connected and LOW LOW LOW PAUSE
P3 P4 P5 TP1 configured in software (F10 with disk, Access PULSES LOW = VCR Record
GND Lite turned ON & X-ray switch PULSES LOW when VCR PULSES LOW without
Level 2, Configuration/Hard Disk, Set System L HIGH Play Lite turned ON or OFF.
pressed, or when VCR Record control cable connected.
Configuration. Lite turned OFF.
TP2 U6 U38
GND M PULSES LOW PULSES LOW every 6mS PULSES LOW every 6mS N/C from
every 6mS
2 Pin-for-pin connection (APPROX.).
(APPROXIMATELY). (APPROXIMATELY). PAUSE
VCR Control
U18
U24
9600 C-ARM
TP3
GND
TP4 PERPHRL1.DS4 6/19/96
GND
9600 WORKSTATION PERIPHERALS
AT Extender Board
Video Switching PCB TP5

00-872237 HCO Located on the RESET PROGRAM EXPOSE
J3
9
10
J6 front of electronics box
HARDCOPY CAMERA
USR 5
(1C3)
See Image Path 1
Block Diagram
Page 1 J28
Coax cable with

BNC connectors
on each end 20 conductor
ribbon cable
This is one horizontal line from the image

J6 J7 shown on the right. This amplitude will be As viewed from the Solder Side
twice as large if measuring an unterminated output.
2 4 6 8 10 12 14 16 18 20
TP5
J3
J28
HCO
1 3 5 7 9 11 13 15 17 19
Remote Video
Panel In
TP39 2 4 6 8 10 12 18 Seg. X 4
AGND 74LS05
J01 Display
1 3 5 7 9 11
1
This image can be used to adjust the hard
copy camera’s image. To adjust the hard
copy camera adjust the BRIGHTNESS &
CONTRAST controls located on the hard 200 mV dc
SEE 9600 SYSTEM SERVICE MANUAL
copy camera control panel. When adjusting 10 us PERIPHERALS SECTION
the BRIGHTNESS & CONTRAST make
sure that "AUTO HISTO" is TURNED OFF. This portion of the signal will appear
HI as long as a button is pressed.
After the camera has been adjusted properly Trouble Shooting Hints
to the Test Pattern, use the WINDOW & LEVEL
CONTROLS or AUTO HISTO to adjust Other pins
LED test: To test the LED display, turn on the Workstation Key
diagnostic images on the hard copy camera. listed on
and observe that all segments of the display light up momentarily J28 & J01
Do not use the brightness & contrast knobs
as the multi format camera powers up. If the LEDs do not light
found on the back of the monitors.
properly, verify that J28 is plugged in correctly.
Button Tests: All tests listed are done with the camera turned on.
If the buttons do not respond when pressed, check the following signals:
Reset: Press reset and verify that J01-11 and J28-3 goes HI (+5V). J28-4
Program: Press program & check for pulse at J28-4, J01-9 and J28-11.
Up: Press up & check for pulse at J28-4, J01-7 and J28-12.
Down: Press down & check for pulse at J28-4, J01-5 and J28-15.
To view this computer generated image Advance: Press advance and check for pulse at J28-4, J01-3 and J28-14.
for the left monitor: 2 V dc Hard Copy Camera
VIDEO 1
(Press TEST PATTERN)
Expose: Press expose and check for pulse at J28-4, J01-1 and J28-13. 50 us
SWITCHING If there are no pulses at J28-4, the problem is in the camera itself. 9600 C-ARM
PCB If there are pulses at J28-4, but no pulses on the other pins listed above For Reference Only Page 2 of 3
the problem is in the panel assembly.
PERPHRL1.DS4 6/19/96

AT Communications PCB Auxiliary
00-872125 P4 P3 Interface
19 A R15 PD0 2 2 PCB
U34
00-876502
Rear SEE 9600 SYSTEM SERVICE MANUAL
Buffer 18 B R14 PD1 3 3
PORTA-W Printer Cable
Panel PERIPHERALS SECTION
17 C R13 PD2 4 4
Data 16 D R12 PD3 5
00-876450 5
P18
Printer
15 E R11 PD4 6 6
14 F R10 PD5 7 7
PORTAW* Pin-for-pin connection
CLK 13 G R9 PD6 8 8
11 (2C5) 12 H R8 PD7 9 Pin-for-pin connection 9 25 Pin
U19 19 1 2 R1 STROBE* 1 1 D-SUB Parallel
U11
Buffer (2B2) I Printer
PORTC-W
18 3 AUTOLF* 14 14
U11 4
See 9600 Workstation (2B2) J
Block Diagram 17 9 INIT* 16 16
To & From U7 8 Parallel
K
AT Motherboard
PORTCW*
(2B2) Printer Cable
CLK 16 9 8 SLCT_IN* 17 17
U11
11 (2B2) L
(2B2)
15 15
U28 2 2 1
Buffer U10 13 13
PORTC-R (2B2) 1
3 4 3
U10 12 12 Test Point Idle or Printing Start of Print (Momentary)
(2B2)
4 A LOW PULSES
10 10
PORTCR* B HIGH PULSES
1&19 5 6 5 11 11
U10 C LOW PULSES
U29 (2B2) (2B2)
PAL22V10 15 R D HIGH PULSES
U23
Buffer 5 M E LOW PULSES
ERROR*
Addr 16 S PORTB-R F LOW
6 N PULSES
SLCT
G LOW PULSES
22 T 7 O PE
H LOW PULSES
8 P ACK*
23 U PORTBR* 1&19 I HIGH HIGH
(2B3) 9 Q 8 9 BUSY
(2A2) U10 J HIGH HIGH
(2A2)
18 18 K HIGH HIGH
- -
L LOW LOW
25 25
M Tri-State Tri-State
N Tri-State Tri-State
O LOW LOW
AT COMMUNICATIONS PCB P Tri-State Tri-State

Q 2 HIGH HIGH
P3 P4 P5 TP1 1 Test point data taken by printing patient summary.
GND Press F5, then print. Some lines toggle as shown R HIGH HIGH
in the "Start of Print" column. Then, they return to
TP2 the same state as when the printer is setting idle. S HIGH HIGH
GND
T HIGH HIGH
U HIGH PULSES
U19
2 High = Printer On-Line Printer
U23 Low = Printer Off-Line
9600 C-ARM
TP3 U28 U29 For Reference Only
GND Page 3 of 3
U34 TP4 PERPHRL1.DS4 6/19/96

GND

AT Extender Board BLOCK DIAGRAM / WORKSHEET
Side View
Keypads/Switches
IR XMIT PCB
Top View
9VDC Battery
DISK
VIEW
AVERAGING
SELECT
ACQUIRE
IMAGES 4 Assy. Screws
IMAGE DIR PLAY/PROCESS
IR Transmitter PCB E1 Jumper = 13-14

ENTER 00-873936
IR Receiver PCB
U1
Keypad Decode
CR14 00-874220
Q4-Q6
RECALL REGISTRATION
IR LED Driver L2, C8
1
Local Oscillator
+ 5V U1
ZOOM SHARPEN
(1E4) IR Pre-Amp L2
7 CR15
SNS 7 TP1
WINDOW/LEVEL
ON/OFF 0-6 CR16 CR3 1 COIL1
Q1-Q3
IR LED Driver Infra-Red
WINDOW LEVEL 7 Pulse Train COIL2
(1E6) 1 10 + 5V
DRV IN1
0-6 20 (1E6) CR17 Q1
Vcc COMPONENTS Q1-Q3, CR16. &CR17 NOT 9 R5
AUTO-HISTO NEGATE INSTALLED IN EARLIER REVISIONS
(1E3) E7
Q7-Q10, CR4
LOW
BATTERY (1C5) Low Battery + 5V 8 R1 E6
12 11 Detection Circuit
(1D5) (1E4)
R3 CR1
E5 E4
Y1 - 455 kHz P2 P1
From 9V Low Battery + 12V
REMOTE CONTROL ASSEMBLY Battery Indicator
See 9600 Control Panel Block Diagram Cart Control Panel

Processor PCB
00-876611
VCC
1 P3
U9
U5 +12VIN 1
R11 IR LCL Opto_I
80C196KC
5 TP5 1 IR_LCL 2
(1B6)
+12VRET 3
7 4 +12VRET 4
P2.2 15 U3 2 (1D7)
74LS08
3 1
(1D7) IR RMT
TP9
U8
5 (not used) RS422
(1D7)
INPUT 1 - CR3 is physically located behind the dark lens. This
eliminates the visible light spectrum allowing only
9600 C-ARM
TP5 IR (Infra-Red) light to pass and be detected by CR3.
IR LCL For Reference Only Page 1 of 1
500 mVdc If this lens is mispositioned, ambient light can strike
50 ms
CR3 creating unwanted random pulses.
REM_BLK1.DS4 5/21/96
- The clear lens is used to detect ambient light and
Waveform taken when pressing the
ENTER button on the Remote Control.
change the brightness of both monitors to match room
light intensity. See Contrast/Brightness & Monitors 9600 IR REMOTE CONTROL
Block Diagram for this detector and circuitry. BLOCK DIAGRAM

Oec 9600 Blocks Diagram

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Oec 9600 Blocks Diagram

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SERIES9600

3- TP24 TP25 TP23

TP23 TP24 TP22 TP5

GENERATOR KV CIRCUIT FAULTS

Other kV settings will be useful for

U11 R35 GND

FAULT PAL OUTPUT TRUTH TABLE

9600 GENERATOR FAULTS

SEE SERVICE MANUAL U30

P1 CONNECTS TO THE LEFT CONTROL PANEL TP2

USE THIS DIAGRAM

TXD = TRANSMIT DATA

MICROCONTROLLER 9600 C-ARM

USE THIS DIAGRAM C-ARM COMMUNICATIONS

TXD = TRANSMIT DATA

1 LEMO CONNECTOR PINS SHOWN AUX INTERFACE PCB

USE THIS DIAGRAM

SEE SERVICE MANUAL U30

P1 CONNECTS TO THE LEFT CONTROL PANEL

USE THIS DIAGRAM CONTROL PANEL PROCESSOR/

USE THIS DIAGRAM C-ARM COMMUNICATIONS

TXD = TRANSMIT DATA

COM U52 TP 3, 7, (1B5)

1 LEMO CONNECTOR PINS SHOWN

USE THIS DIAGRAM

2 SWITCHES 1 & 2 OF SW1 MUST BE ON TO

TXD = TRANSMIT DATA

COM U52 TP 3, 7, (1B5)

1 LEMO CONNECTOR PINS SHOWN

2VDC 9600 C-ARM

TEST POINTS IN COMMUNICATION SIGNALS

TECHNIQUE PROCESSOR PCB RXD_A

CONTROL PANEL PROCESSOR/

TECHNIQUE PROCESSOR PCB

CONTROL PANEL PROCESSOR/

U44-CPU (1A6) U14-BOOTPROM

TECHNIQUE PROCESSOR PCB (5D7) D ADDRESSING

P1 P2 P1 (Serial Numbers 69-0001 to 69-2000)

TARGET (not used) U38 Q3 - "Stator Run" - K1 on Power/Motor Relay PCB

6 THERE ARE 16 A/D CHANNELS, BUT ONLY 10 ARE BEING USED.

P2-107 P2-35 P3-16 P2-1 P4-12 P4-10

J6-107 J6-35 P4-10 P1-1 P10-11 P10-9

CONTROL PANEL DISPLAY GENERATOR INTERLOCK

P2-107 P2-35 P3-16 P2-1 P4-12 P4-10

J6-107 J6-35 P4-30 P1-1 P10-11 P10-9

CONTROL PANEL DISPLAY GENERATOR INTERLOCK

1F TTL Low without Camera

Stays GEN_LOK1.DS4 6/19/96

9600 WORKSTATION "GEN-LOCK"

CPU INTERLOCK FROM ANALOG SUPPORT PCB

ANALOG INTERFACE PCB

HV DRV A 29 10 13 U8, U28, Q4 HV DRV B TP23 TP24

In the manual fluoro mode, use a

U3 P2 P3 TP7 SCALING AMP 8mA/Volt Fluoro

5 FIL DR B Q3 For Reference Only Page 1 of 1

TP21 MA CONTROL / MEASURE ENABLE

LO = X-RAYS ON U13 PINS 6-7 CLOSED U27-1 FILAMENT B+ SENSE

U10-14 .3MM / .6MM SELECT U5

FLUORO AUTO MODE 67 KVP @ 2.3 MA

FIL DR B FLUORO MANUAL MODE 67 KVP @ 2.3 MA

R8 REGULATED FILAMENT VOLTAGE

+24 VOLTS IN ALL FLUORO MODES

.7 VOLTS IN FILM MODE 110 MAS AND

Q11 TURNS ON WHEN FILM MODE