Shahrukh Athar EE / CS - 320 Computer Organization and Assembly Language Course Outline

EE / CS - 320
Computer Organization and Assembly Language
2011 / 2012
Instructor’s Name: Shahrukh Athar Year:

Office, Email & Ext: Room 9-319, 3rd floor SSE, shahrukh.athar@lums.edu.pk, 8356 Semester: Fall

Office Hours: Monday & Tuesday (10:00 am to 12:00 pm) Category: Core
(Juniors)
TA information: Saira Hussain, Hassan Ilyas, Omer Majid Mir & Muhammad Imran

Course Code EE / CS - 320 (4 Credit Hours)

(Credits)

Course https://lms.lums.edu.pk/ (University Learning Management System (LMS))

Website

Course Modern computer technology requires professionals of every computing specialty to

Description understand both hardware (HW) and software (SW). The interaction between HW and SW
also offers a framework for understanding the fundamentals of computing. This course will
have HW focus in the class and students will study topics such as Instruction Set
Architecture, Basic Assembly Instructions, Addressing Modes, Computer Performance
evaluation, Floating Point Data, Data Path Design for Single Cycle and Multiple Cycle
Computers, Pipelined Data Path Basics, Hazards in Pipelining, Memory hierarchy design,
storage and I/O. The Lab will have focus on MIPS Assembly Level Programming and some
HW experiments. The course will have one comprehensive design project in which
students will design and implement an 8-bit MIPS architecture based processor using HW
components.

Core/Elective Core for EE Majors

Core for CS Majors
Elective for others

Pre-requisites 1. Digital Logic Circuits (EE-220), and

2. Introduction to Programming (CS-200)

Talk to the instructor if you are unsure about the background needed to take this course.

Goals & To learn:

Learning  The link: High-Level Language (For example C Language)  Assembly Language
Objectives (such as MIPS Assembly)  Machine Language.
 The language of the computer using the MIPS Assembly Language as an example.
 The arithmetic of the computer.
 The design of a basic 5-stage single cycle Processor.
 The design of a basic 5-stage pipelined Processor.
 Data and Control hazards in pipelining.
 Memory hierarchy Design.
 Storage and I / O.
 Working as team players in a group of engineering students in designing and
implementing a comprehensive hardware project.

Fall Semester 2011-12 EE Department, SSE LUMS Page 1 of 4

Shahrukh Athar EE / CS - 320 Computer Organization and Assembly Language Course Outline

EE / CS - 320
Computer Organization and Assembly Language
Year: 2011 / 2012

Semester: Fall

TextBooks, Required Text:

Programming “Computer Organization and Design: The Hardware / Software Interface”
Environment, by David A. Patterson and John L. Hennessy (4th Edition)
etc.
Reference Texts:
1. “Computer Organization and Architecture” by William Stallings (8th Edition)
2. “Computer Organization” by Carl Hamacher, Zvonko Vranesic and Safwat Zaky (5th
Edition)
3. “MIPS Assembly Language Programming” by Robert L. Britton

Programming Environments:
1. PCSPIM MIPS Assembly Language Simulator
2. Visual MIPS Simulator

Lectures,  Two weekly lectures of 75 minutes duration each (schedule given by RO)
Labs,  One weekly laboratory of 120 minutes duration (schedule given by RO)
Tutorials,  There may be some tutorials (if required)
Attendance &  Attendance is strongly recommended as lectures will build upon the material
Policies covered in previous lecture(s). There may also be surprise quizzes.
 Policies:
 One class quiz will be dropped. There cannot be any makeup quiz.
 Assignments will be due at the beginning of the class on the due date. Late
Assignments will not be accepted.
 The project will be divided into modules and each module will have a specific deadline.
Late module submission may either result in a penalty or may not be accepted at all.
 All instances of cheating will be dealt with strictly in accordance with university rules.

Grading Quizzes: 15%

Assignments: 3%
Labs: 12% (Lab Quizzes: 2%, Lab Attendance and Task Completion: 10%)
Project: 15%
Midterm: 25%
Final: 30%

Re-grading Any contests of Assignments, Quizzes, Labs, Mid-term Exam and Final Exam must be
Deadlines resolved within 2 days of the return of the graded item (No exceptions).

Fall Semester 2011-12 EE Department, SSE LUMS Page 2 of 4

Shahrukh Athar EE / CS - 320 Computer Organization and Assembly Language Course Outline

EE / CS - 320
Computer Organization and Assembly Language
Class Lecture Details (27 Sessions) Year:
2011 / 2012

Semester: Fall

Module Topics Sessions Readings

1 Introduction 1 CH-1 TB
 History and System Level View
 Some important design considerations

Language of the Computer

2  Operation and Operands of HW 6 CH-2 TB
 Signed and Unsigned Numbers
 Representing Instructions in the Computer
 Logic Operations
 Instruction for Making Decisions
 Supporting Procedures in HW (Stack)
 Addressing Modes
 Intro to Compilers
 A Sort procedure and its assembly
 Pointers versus Arrays

3 Arithmetic for Computers 3 CH-3 TB

 Addition and Subtraction
 Multiplication and Division
 Floating Point

4 CPU Performance Factors 1 Sec 1.4 TB

The Processor (Single Cycle)

5  Building a Datapath 2 CH-4 TB
 Simple Implementation Scheme (Control)

Mid Term Exam

The Processor (Pipelined)

6  Pipelined Datapath and Control 5 CH-4 TB
 Introduction to Stalling and Forwarding CH-8 RB2
 Data Hazards and Control Hazards
 Exceptions

Memory Hierarchy
7 5 CH-5 TB
 A Top Level View
CH-4, 5 RB1
 Cache Memory
 Main Memory
 Virtual Memory

8 Storage, Input / Output and OS Support 4 CH-6 TB

 Storage Devices CH 6 to 8 RB1
 I / O Topics
 Introduction to OS Support

Fall Semester 2011-12 EE Department, SSE LUMS Page 3 of 4

Shahrukh Athar EE / CS - 320 Computer Organization and Assembly Language Course Outline

EE / CS - 320
Computer Organization and Assembly Language
Laboratory Details Year:
2011 / 2012

There will be 10 Laboratory exercises. Semester: Fall

 Labs 1 & 7 will introduce some HW components necessary for the project later on in the semester.
 Labs 2 to 6 & 8 will cover various aspects of MIPS Assembly Language using the PCSPIM Simulator.
 Labs 9 & 10 will illustrate single cycle and pipelined processors using the Visual MIPS Tool
(Developed by Dr Jahangir Ikram).

Lab Topics Week

1 HW Lab: Using ROM, RAM and ALU IC chips 2

2 Introduction to PCSPIM MIPS Assembly Language Simulator and basic 3

assembly instructions

3 Control instructions, Pseudo instructions and arrays 4

4 System Calls and Procedure Calls 5

5 Using the Stack. Multiplication in the MIPS Assembly Language 6

6 Recursion (Factorial) and Sorting in MIPS Assembly Language 7

7 HW Lab: Using a Register File 9*

8 Using the MIPS Floating Point Architecture in PCSPIM 10*

9 Introduction to MIPS Instruction Set Architecture using the Visual MIPS Tool 11*
(Single Cycle and Pipelined Processor)

10 Introduction to Data Hazards and Branch Hazards using the Visual MIPS Tool 12*

* Subject to Mid-Term Schedule and Eid-ul-Azha holidays.

Fall Semester 2011-12 EE Department, SSE LUMS Page 4 of 4