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Colour Television Chassis

VES1.1E
LA

See table of contents on page 3

Published by MB/SC 1363 Quality Printed in the Netherlands Subject to modification EN 3122 785 19393
2013-Mar-29

2013 © TP Vision Netherlands B.V.


All rights reserved. Specifications are subject to change without notice. Trademarks are the
property of Koninklijke Philips Electronics N.V. or their respective owners.
TP Vision Netherlands B.V. reserves the right to change products at any time without being obliged to adjust
earlier supplies accordingly.
PHILIPS and the PHILIPS’ Shield Emblem are used under license from Koninklijke Philips Electronics N.V.
EN 2 1. VES1.1E LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0
• First release.

Manual xxxx xxx xxxx.1


• Added the Service Mode menu.

Manual xxxx xxx xxxx.2


• Added several new sets to this chassis, see table 2-1 Described
model numbers.
• Added the section Hotel Mode setup menu.

Manual xxxx xxx xxxx.3


• Added several schematics of the SSB.
• Added the schematics of the PSU.

2. Technical Specifications and Connections


Index of this chapter:
Technical specifications
Directions for Use

Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).

Technical Specifications

For on-line product support please use the links in Table 2-1. Here is
product information available, as well as getting started, user manuals,
frequently asked questions and software & drivers.

Table 2-1 Described model numbers

CTN Styling Published in:


19PFL2908H/12 2900 3122 785 19392
22PFL2807H/12 2800 3122 785 19390
22PFL2908H/12 2900 3122 785 19392
24HFL2808D/12 2800 3122 785 19392
24PFL2908H/12 2900 3122 785 19392
26HFL2808D/12 2800 3122 785 19392
26PFL2908H/12 2900 3122 785 19392
32PFL2807H/12 2800 3122 785 19390

Directions for Use

You can download this information from the following websites:


http://www.philips.com/support
http://www.p4c.philips.com

2013-Mar-29 back to
div. table
Contents
1 Introduction ............................................................................................................................................. 6
1.1 General Block Diagram................................................................................................................... 7
1.2 SSB Placement of Blocks .................................................................................................................. 8
2 Tuner (TU3) .............................................................................................................................................. 9
2.1 General description of the Sony RE216 tuner.................................................................................. 9
3 Audio amplifier stage with AZAD2102 (U163, U164) ............................................................................. 11
3.1 General description ........................................................................................................................ 11
3.2 Features.......................................................................................................................................... 12
3.3 Absolute Ratings ........................................................................................................................... 13
3.3.1 Electrical Characteristics ....................................................................................................... 13
3.3.2 Operating specifications ....................................................................................................... 14
3.4 Pinning ............................................................................................................................................ 15
4 Audio amplifier stage with TPA3113 (U168) .......................................................................................... 15
4.1 General Description ....................................................................................................................... 15
4.2 Absolute Ratings............................................................................................................................. 16
4.2.1 Electrical Characteristics ........................................................................................................ 16
4.2.2 Operating Specifications ...................................................................................................... 17
4.3 Pinning ........................................................................................................................................... 17
5 Power stage ............................................................................................................................................ 18
5.1 Power management....................................................................................................................... 21
6 Microcontroller – MSTAR (U5) ............................................................................................................... 23
6.1 Description ..................................................................................................................................... 23
6.2 MSTAR block diagram .................................................................................................................... 27
6.3 Reset circuit .................................................................................................................................... 28
7 CI interface ............................................................................................................................................. 28
8 USB interface .......................................................................................................................................... 29
9 DDR2 SDRAM K4T1G164QF (U155) ....................................................................................................... 30
9.1 Description ..................................................................................................................................... 30
9.2 Features.......................................................................................................................................... 30
Pinning........................................................................................................................................................ 31
10 Scaler and LVDS sockets ..................................................................................................................... 32
10.1 LVDS sockets block diagram .......................................................................................................... 32
10.2 Panel supply switch circuit ............................................................................................................. 32
11 SPI flash memory - MX25L1005 (U158) ............................................................................................. 33
11.1 General Description ....................................................................................................................... 33
11.2 Features.......................................................................................................................................... 33
11.3 Absolute maximum ratings ............................................................................................................ 34
11.4 Pinning............................................................................................................................................ 34
12 NAND Flash memory – NAND512XXA2C (U162) ................................................................................ 35
12.1 General Description ....................................................................................................................... 35
12.2 Features.......................................................................................................................................... 35
12.3 Pinning ............................................................................................................................................ 36
13 LNBH23L (U6) ..................................................................................................................................... 37
13.1 Description ..................................................................................................................................... 37
13.2 Features.......................................................................................................................................... 37
13.3 Block diagram ................................................................................................................................. 38
14 Advanced DVB-S/S2 demodulator M88DS3002 (U3) ....................................................................... 38
14.1 Description ..................................................................................................................................... 38
14.2 Features.......................................................................................................................................... 38
14.3 Pin Assignment .............................................................................................................................. 40
15 LM1117 (U175, U180, U181) .............................................................................................................. 41
15.1 General description ........................................................................................................................ 41
15.2 Features.......................................................................................................................................... 41
15.3 Applications .................................................................................................................................... 41
15.4 Absolute maximum ratings ............................................................................................................ 41
15.5 Pinning ............................................................................................................................................ 42
16 MP2012 (U176) .................................................................................................................................. 42
17 General description ............................................................................................................................ 42
17.1 Features.......................................................................................................................................... 42
17.2 Pinning ............................................................................................................................................ 43
18 RTA8283A (U23, U173) ....................................................................................................................... 43
18.1 General description ........................................................................................................................ 43
18.2 Features.......................................................................................................................................... 43
18.3 Pinning ............................................................................................................................................ 45
19 MP1583 (U174) .................................................................................................................................. 46
19.1 General description ........................................................................................................................ 46
19.2 Features.......................................................................................................................................... 46
19.3 Pinning ............................................................................................................................................ 46
20 FDC642 ............................................................................................................................................... 47
20.1 General description ........................................................................................................................ 47
20.2 Features.......................................................................................................................................... 47
20.3 Pinning ............................................................................................................................................ 47
21 FDC604P ............................................................................................................................................. 48
21.1 General description ........................................................................................................................ 48
21.2 Features.......................................................................................................................................... 48
21.3 Pinning ............................................................................................................................................ 48
22 Connectors ......................................................................................................................................... 49
22.1 SCART (SC1) .................................................................................................................................... 49
22.2 HDMI (CN707, CN708) ................................................................................................................... 49
22.3 VGA (CN711) ................................................................................................................................. 50
23 Service menu mode............................................................................................................................ 51
23.1 Main service menu ......................................................................................................................... 51
23.2 Video Settings................................................................................................................................. 52
23.3 Audio Settings ................................................................................................................................ 52
23.4 Options 1 ........................................................................................................................................ 53
23.5 Options 2 ........................................................................................................................................ 53
23.6 Tuning Settings ............................................................................................................................... 54
23.7 Source Settings ............................................................................................................................... 54
23.8 Diagnostic ....................................................................................................................................... 54
23.9 USB operations ............................................................................................................................... 54
23.10 Profile Operations ...................................................................................................................... 57
23.10.1 Upload profile Data from USB ............................................................................................ 57
23.10.2 PQ Files Operations ............................................................................................................ 57
23.10.3 Upload PQ files from USB ................................................................................................... 57
23.10.4 Ci+ credentials key update ................................................................................................. 57
23.10.5 HDCP keys update .............................................................................................................. 57
23.10.6 Edid update ....................................................................................................................... 58
23.10.7 DDR settings update ........................................................................................................... 58
23.10.8 MAC address update .......................................................................................................... 58
23.11 Hotel Mode setup menu ............................................................................................................ 58
23.11.1 Hotel TV welcome image update (only available in Hotel TVs) ......................................... 58
24 Software update ................................................................................................................................. 59
25 Troubleshooting ................................................................................................................................. 59
25.1 No backlight problem ..................................................................................................................... 59
25.2 CI module problem......................................................................................................................... 61
25.3 LED blinking problem ..................................................................................................................... 63
25.4 IR problem ...................................................................................................................................... 63
25.5 Keypad touchpad problems ........................................................................................................... 64
25.6 USB problems ................................................................................................................................. 65
25.7 No sound problem.......................................................................................................................... 65
25.8 No sound problem at headphone .................................................................................................. 66
25.9 Standby On/Off problem................................................................................................................ 66
25.10 DVD problems ............................................................................................................................ 67
25.11 No signal problem ...................................................................................................................... 67
26 Styling sheet ....................................................................................................................................... 69
27 Schematics.......................................................................................................................................... 70
27.1 SSB .................................................................................................................................................. 70
27.2 PSU ................................................................................................................................................. 79

1 Introduction

The SSB is driven by a MStar SOC. This IC is capable of handling Video and audio
processing, Scaling-Display processing, 3D comb filter, OSD and text processing, LVDS
transmitting, channel and MPEG2/4 decoding, integrated DVB-T/C demodulator and
media center functionality.

The TV supports PAL, SECAM, NTSC colour standards and multiple transmission
standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo. Also DVB T,
DVB-C are supported internal demodulators of Mstar IC and DVB-S/S2 is supported with
external demodulator.

Sound system output is supplying max. 2 × 2.5 W (less 10% THD at maximum output)
with 4 Ω speakers or 2 × 6 W for stereo 8 Ω speakers.

Supported peripherals are:

1 RF input VHF I, VHF III, UHF @ 75 Ω (Common)


1 Side AV (CVBS, R/L_Audio)
1 SCART socket (Common)
1 YPbPr (Optional)
1 PC input (Common)
2 HDMI 1.3 input (1 HDMI input is common, 1 input is optional)
1 S/PDIF output (Optional)
1 Headphone (Optional)
1 Common interface (Common)
1 USB (Common)
1 DVD (Optional)
1 On-board Keypad (Optional)
1 External Keypad (Optional)
1 External TouchPad (Optional)
1.1 General Block Diagram

D3K
GPIO

Mstar

••

VGA

2XIi'H
.O.UDIO AU'
HDIJI1 -HPOErecr-.
!
i
Block Diagram
V1.1
Drawn By Ulas Dere i
03.01.2011
1.2 SSB Placement of Blocks

YPbPr SAV HP
USB Keypad
Sat
Demod
Nand
Flash
(U162) Speaker
Satellite Tuner Con.
CI Connector
Tuner(T3
)

SCART
Connec
Main IC
External tor
Keyboard (U5)
Touchboard HDMI VGA
Connectors Led
Con

DVD
Connector DDR2
LVDS SPI Inv.
RAM Adapter DC Con
Flash
Connectors (U155) Input SPDIF
Out
Power Connector
2 Tuner (TU3)
A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands (From 48 MHz to 862 MHz for COFDM, from 45.25 MHz to 863.25 MHz for CCIR
channels). The tuning is available through the digitally controlled I2C bus (PLL).

In the active antenna option, the following circuits are used. ANT_CTRL pin is controlled by
microcontroller. If ANT_CTRL is low, ANT_PWR will be low. If ANT_CTRL is high,
ANT_PWR will be high.

OVER_CUR_DETECT pin is a monitor for short circuit in antenna. OVER_CUR_DETECT


is low, ANT_CTRL will be low, so ANT_PWR will be low. Finally, short circuit protection is
done by circuits and microcontroller.

2.1 General description of the Sony RE216 tuner


The SUT-RE216 is designed for terrestrial TV (digital & analog) and digital cable
reception. It includes a full band tuner and a channel filtering for digital signals. It provides
a low IF output after channel filtering to drive a channel demodulator. Tuning, band
switching and initialization are made via an I2C bus
interface. The module is built on a low-loss printed
circuit board carrying all the components in a metal
housing frame with top and rear covers. The single
aerial connector is mounted on one frame side and all
other connections are made via pins at the bottom.

Features:

 Full frequency range from 47 to 870 Mhz


• Digital Platform (DVB-T/T2, DVB-C, ISDB-T & ATSC)
 Analog platforms (PAL B/G/I/D/K, NTSC M & SECAM L/L’)
 Low IF tuner concept
./ Programmable channel Filter bandwidth
./ Fully I2C bus controlled
./ For Hybrid TV applications

3.3V pull up

1000 1uF
----{)-------w. -

AGC:
I
1KO

:---------------------------------------•------o..-----'M'h\--{®f-----....-!-'N\\-OIAocI
---Pinning Table

and Application Block Diagram of Tuner---

3 Audio amplifier stage with AZAD2102 (U163, U164)

3.1 General description


This chassis uses two 2.5 W Class D Mono Audio Amplifers for from 16" to 24"
TVs. AZAD2102B is a 2.9 Watts (max. can offer 3.0 Watts @ Load = 3 Ω,THD = 10%,
AVdd = DVdd = 5.5 Volt) with high efficiency filter-free class-D audio power amplifier
in a 1613 mm x 1613 mm wafer chip scale package (WCSP). AZAD2102B uses
Current- switch technology to achieve high performance class-d amplifier that
features 0.03% THD, 85% efficiency, –70 dB PSRR, to improve RF-rectification immunity.

AZAD2102B provide a Vibration-Spectrum modulation clock for PWM Output. This


vibration frequency is around 10 kHz shift (+/- 5 kHz of Fpwm).

The advantage of the small size package (WCSP) makes AZAD2102B very suitable for
mobile phone and PDA device application. And the Class-D amplifier structure let
AZAD2102B to have highly efficiency power consumption than Class-AB amplifier.
AZAD2102B can shrink the application board, reduce system cost, and external
components.

ESD level protection I/O embedded in AZAD2102B. For general applications, there is
no need to add extra ESD protection devices (like Varistors) in application systems for
AZAD2102B’s I/O.
3.2 Features
• CMOS Technology
• High Efficiency 85%
• High PSRR 70 dB at 217 Hz
• Differential OP-amp Input
• AZAD2102B provides Vibration-Spectrum Modulation clock for reduce EMI
• Provide Mute function (set Mute_B to GND will go into Mute status)
• For the input stage AZAD2102B built-in a 10Kohm resistors (Gain
setting = 29.5 dB)
• Maximum Battery Life and Minimum Heat
• Efficiency With an 8 Ω Speaker:
• 3.5 mA Quiescent Current
• Output Power at 10% THD
• 2.85 Watts at AVdd = DVdd = 5.0 Volt, Rload = 4 Ω
• 1.45 Watts at AVdd = DVdd = 3.6 Volt, Rload = 4Ω
• 0.30 Watts at AVdd = DVdd = 3.0 Volt, Rload = 4Ω
• 1.75 Watts at AVdd = DVdd = 5.5 Volt, Rload = 8Ω
• 0.87 Watts at AVdd = DVdd = 3.6 Volt, Rload = 8Ω
• 0.41 Watts at AVdd = DVdd = 3.0 Volt, Rload = 8Ω
• Eliminate Power on and Power-off “Pop” noise
• A fewer external components
• Optimized PWM output stage eliminates LC output filter
• Internally generate 290 kHz switching frequency to eliminate capacitor and resistor
• Improve PSRR (–70 dB) and wide supply voltage (3.0 V to 5.5 V)
• Fully differential design reduces RF rectification
• This chip has been built-in a very strong ESD protection.
• System level ESD 4 KV (IEC 61000-4-2 ESD Contact Level)
• Wafer chip scale package (WCSP)
• TSSOP package with exposed pad
3.3 Absolute Ratings

3.3.1 Electrical Characteristics


VDD = AVdd = DVdd, VSS = AVss = DVss = Ground

.
TA = 25˚C, Filter Bandwidth = 20 Hz -20 kHz
PARAMETER Symbol TEST COND TIONS MNI TYP MAX UNIT
Operating Votlage Vop AVdd-DVdd to AVss-DVss 3.0 5 5.5 v
VDD = 5.5 V,VI= 0 V,AV = 6 V/V 4.5 6.5

Output offset voltage vos VDD = 3.6 V,VI= 0 V,AV = 6 V/V 2.1 4.0 mV

VDD = 3.0 V,VI= 0 V,AV = 6 V/V 1.2 3.0


VDD = 3.0 V to 5.5 V, AV = 2 V/V
Power supply rejection input ac grounded with
PSRR -68 dB
ratio Ci=2.2uF,Vripple=200mVpp,
RL=80 f=217Hz
Common mode rejection VDD = 3.0 V to 5.5 V,Vic = VDD/2 to
Cf':lRR -65 dB
ratio 0.5 V,Vi c = VDD/2 to 0.5 VDD -0.8 V,
High level nput
IIIHII VDD= 5.5V,Vi=5.8V 25 uA
current
Low level Input
IIlLI VDD= 5.5V,Vi=-0.3V 1 uA
current
VDD = 5.5 V,no load 3.6 5.0

Operation current lop VDD = 3.6 V,no load 3.0 4.2 mA

VDD = 3.0 V,no load 2.5 3.5

VDD = 5.5 V,no load 290


Output
Fpwm VDD = 3.6 V,no load 300 KHz
switching
frequency VDD = 3.0 V,no load 315
Vibration-Spectrum
Fvs VDD = 5.0 V,no load +/-5 +/-10 KHz
Modulation clock Ranqe
Under Voltage
Protection
UVP Vin+ and Vin- connect to GND,no load 2.0 2.5 v
Mute_B pin Impedance RMuB Mute_B to Ground 270 KQ
VDD=5.0V,Ri=5K0+10K
Gain Gain
O (Av=20V/V)
18
I 20
I 22 V/V
3.3.2 Operating specifications
TA = 25°C,Gain = 20 V/V,
PARAMETER TEST COND TIONS MIN TYP MAX UNIT

VDD = 5.0V 2.85


THO+ N = 10%, f = 1kHz,RL
= 4Q
VDD = 3.6 V 1.45 w
VDD = 3.0 V 0.77

VDD = 5.0 V 2.25


1%, f = 1 kHz,
THO + N =
RL = 4 Q
VDD = 3.6 V 1.15 w
VDD = 3.0 V 0.60
Pw Output power
VDD = 5.0 V 1.75
THO+ N = 10%, f = 1kHz,RL
= 8Q
VDD = 3.6 V 0.87 w
VDD = 3.0 V 0.47

VDD = 5.0 V 1.39


THO + N =
RL = 8 Q
1%, f = 1 kHz,
VDD = 3.6 V 0.70 w
VDD = 3.0 V 0.36

VDD = 5.0 V,PO = 1W,RL = 8 Q, f = 1kHz 0.15


Total harmonic
THD+N VDD = 3.6 V,PO = 0.5 W,RL = 8 Q, f = 1 kHz 0.12 %
distortion plus noise
VDD = 3.0 V,PO = 200 mW, RL = 8 Q, f = 1kHz 0,09
VDD = 3.6 V, F = 217 H.z,
Supply ripple
PSRR Av=20V/V,Inputs connect to VRipple = 200 dB
rejection ratio -67
grounded with Ci = l.OJ,JF mVpp
SNR Signal-to-noise ratio VDD = 5 V,PO = 1W,RL = 8 Q 95 dB
VDD = 3.6 V,f = 20 Hz to 20 No weighting 45
Vnoise Output noise level kHz, nputs ac-grounded with J,JVRMS
Ci = l.OJJF A weighting 40
Common mode -72
CMRR VDD = 3.6 V,Vin = 100mVpp f = 217Hz dB
rejecti on ratio
ZI Input impedance 8 10 12 kQ

ZF Feedback resistor 120 150 180 kQ


3.4 Pinning

4 Audio amplifier stage with TPA3113 (U168)

4.1 General Description


This chassis uses a 6 W Class D Mono Audio Amplifier for from 26” to 32” TVs.
The TPA3113D2 is a 6 W (per channel) efficient, Class-D audio power amplifier for driving
bridged-tied stereo speakers. Advanced EMI Suppression Technology enables the use of
inexpensive ferrite bead filters at the outputs while meeting EMC requirements.
SpeakerGuard™ speaker protection circuitry includes an adjustable power limiter and a
DC detection circuit. The adjustable power limiter allows the user to set a "virtual" voltage
rail lower than the chip supply to limit the amount of current through the speaker. The DC
detect circuit measures the frequency and amplitude of the PWM signal and shuts off the
output stage if the input capacitors are damaged or shorts exist on the inputs.

The TPA3113D2 can drive stereo speakers as low as 4 Ω. The high efficiency of the
TPA3113D2, 87%, eliminates the need for an external heat sink when
playing music.

The outputs are also fully protected against shorts to GND, VCC, and output-to-output.
The short-circuit protection and thermal protection includes an auto-recovery feature.
3.2. Features
• 6 W/ch into an 8-Ω Loads at 10% THD+N From a 10-V Supply
• 12-W into a 4-Ω Mono Load at 10% THD+N From a 10-V Supply
• 87% Efficient Class-D Operation Eliminates Need for Heat Sinks
• Wide Supply Voltage Range Allows Operation from 8 V to 26 V
• Filter-Free Operation
• SpeakerGuard™ Speaker Protection Includes Adjustable Power Limiter plus DC
Protection
• Flow Through Pin Out Facilitates Easy Board Layout
• Robust Pin-to-Pin Short Circuit Protection and Thermal Protection with Auto
Recovery Option
• Excellent THD+N / Pop-Free Performance
• Four Selectable, Fixed Gain Settings
• Differential inputs

4.2 Absolute Ratings

4.2.1 Electrical Characteristics


4.2.2 Operating Specifications
AC CHARACTERISTICS
TA = 25•c, Vee = 12 V, RL = 8 0 (unless otherwise noted)
PARAMETER TEST COND
ITIONS MIN TYP MAX UNIT
200 mVpp ripple from 20 Hz-1kHz,
KsvR Supply ripple rejection -70 dB
Gain = 20 dB,Inputs ac-coupled to AGNO
THO+N Total harmonic distortion +noise RL = 8 0, f = 1kHz, Po = 3 W (half-power) 0.06 %
65 IJV
Vn Output integrated noise 20 Hz to 22 kHz,A-weighted filter, Gan
i = 20 dB
-80 dBV
Crosstalk P0 = 1 W,Gain = 20 dB, f = 1 kHz -100 dB
Maximum output at THO+N < 1%, f = 1 kHz,
SNR Signa-l to-noise ratoi 102 dB
Gain = 20 dB, A-weighted
fosc Oscillator frequency 250 310 350 kHz
Thermal trip point 150 ·c
Thermal hysteresis 15 ·c

4.3 Pinning
PIN
Pin 110/P DESCRIPTION
NAME
Number
Shutdown logic input for audio amp (LOW = outputs Hi-Z,HIGH = outputs
so 1 I
enabled).TTL logic levels with compliance to AVCC.
Open drain output used to display short circuit or de detect fault status.Votlage
compilant to AVCC.Short circuit faults can be set to auto-recovery by connecting
FAULT 2 0
FAULT pin to SO pin. Otherwise, both short circuit faults and de detect faults must
be reset by cycling PVCC.
LINP 3 I Postiive audio input for left channeL Biased at 3V.
LINN 4 I Negative audio input for left channeL Biased at 3V.
GAlNO 5 I Gan
i select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 6 I Gan
i see
l ct most significant bit TTL logic levels with compliance to AVCC.
AVCC 7 p Analog supply
AGNO 8 Analog signalground. Connect to the thermal pad.
High-side FET gate drive supply.Nominalvoltage is 7V. Also should be used
GVOO 9 0
as supply for PLIMIT function
Power limti leveladjust Connect a resistor divider from GVOO to GND to set
PLIMIT 10 I
powerlimit. Connect directly to GVOO for no power limit.
R
INN 11 I Negative audio input for right channe.
l Biased at 3V.
R
INP 12 I Positive audio input for right channeL Biased at 3V.
NC 13 Not connected
PBTL 14 I ParallelBTL mode switch

p Power supply for right channel H-bridge. Right channeland left channelpower
PVCCR 15
supply inputs are connect internally.
p Power supply for right channel H-bridge. Right channelandleft
PVCCR 16
channelpower supply inputs are connect internally.
BSPR 17 I Bootstrap 110 for right channel, positive high-side FET.
OUTPR 18 0 Class-0 H-bridge positive output for right channel.
PGNO 19 Power ground for the H-bridges.
OUTNR 20 0 Class-0 H-bridge negative output for right channel.
BSNR 21 I Bootstrap 1/0 for right channel, negative high-side FET.
BSNL 22 I Bootstrap 1/0 for left channe,l negative high-side FET.
OUTNL 23 0 Class-0 H-bridge negative output for left channel.
PGNO 24 Power ground for the H-bridges.
OUTPL 25 0 Class-0 H-bridge positive output for left channeL
BSPL 26 I Bootstrap 1/0 for left channe,l positive high-side FET.

p Power supply for left channelH-bridge. Right channel and left channel power
PVCCL 27
supply inputs are connect internally.

p Power supply for left channelH-bridge. Right channel and left channel power
PVCCL 28
supply inputs are connect internally.
5 Power stage

The DC voltages required at various parts of the chassis and panel are provided by a
main power supply unit. This chassis can operate with the different supplies: IPS60,
IPS16, IPS17, PW26, PW27 as main power supply and also with 12V adaptor.

CN706 is used for IPS60, IPS16 and IPS17 and CN1 is used for PW26 and PW27.

JK9 is used for the adapter option and also CN705 inverter socket or DB32 chassis with
CN706 is used to supply backlight.

The power supplies generate 18V, 12V, 5V, 3,3V and 12V, 5V, stand- by mode DC
voltages. Power stage which is on-chassis generates 5V, 3V3 stand by voltage and 12V,
8V, 5V, 3V3, 2.5V, 1,8V and 1,2V supplies for other different parts of the chassis. Chassis
block diagram is indicated below.
The blocks on power block diagram is using dependent to main supply. For PW26 and
PW27 just common blocks are enough for proper operation.

For IPS16, IPS17, IPS60 below blocks must work properly.

For adapter case also below blocks are necessary.


Short CCT Protection Circuit

Short circuit protection is necessary for protecting chassis and main IC against damages
when any Vcc supply shorts to ground. Protect pin should be logic high while normal
operation. When there is a short circuit protect pin shold be logic low. After any short
detection, SW forces LEDs on LED card to blink.
5.1 Power management

--- Power Management with Adaptor---

--- Power Management with PW25/ PW26---


--- Power Management with IPS16/IPS17/IPS60/PW05---

--- Power Management with PW03/PW04/PW07---


6 Microcontroller – MSTAR (U5)

6.1 Description

MSD9WB9PT-2 (Main IC) (U5)

The MSD9WB9PT-2 is MStar’s most up-to-date system-on-chip solution for flat panel
integrated digital television products. Building on the success of MStar’s preceding SOC
series, the MSD9WB9PT-2 provides most cost-effective solution for DTV application with
creative and attractive features exclusively presented by MStar.
The MSD9WB9PT-2 integrates DTV/multi-media all-purpose AV decoder, DVB-T
demodulator, VIF demodulator, and Sound/Video processor into a single device. This
allows the overall BOM to be reduced significantly making the MSD9WB9PT-2 a very
competitive multi-media DTV solution. For ATV users, the MSD9WB9PT-2 provides multi-
standard analog TV support with adaptive 3D video decoding and VBI data extraction.
The build-in audio decoder is capable of decoding FM, AM, NICAM, A2, BTSC and EIA-J
sound standards. The MSD9WB9PT-2 supplies all the necessary A/V inputs and outputs
to complete a receiver design including a multi-port HDMI receiver and component video
ADC. All input selection multiplexed for video and audio are integrated, including full
SCART support with CVBS output. The equipped MStar MACE-5 color engine is the
latest masterpiece from
MStar famous color engine series providing excellent video and picture quality in Full-HD
and large-scale displaying system.
To meet the increasingly popular energy legislative requirements without the use of
additional hardware, the MSD9WB9PT-2 has an ultra low power standby mode during
which an embedded MCU can act upon standby events and wake up the system as
required.

The MSD9WB9PT-2 is composed of several modules:

• High Performance Micro-processor


o Ultra high speed/performance 32-bit RISC CPU
o One full duplex UARTs
o Supports USB and ISP programming
o DMA Engine
• Transport Stream De-multiplexer
o Supports parallel and serial TS interface, with or without sync signal
o Supports TS input and output for external CI module
o Maximum TS data rate is 104 Mb/sec for serial or 16 MB/sec for parallel
o 32 general purpose PID filters and section filters for each transport stream
de-multiplexer
o Supports additional audio/video/PCR filters
o Supports TS DMA channel for time-shift
o Supports 3DES/DES and AES encryption/decryption
• MPEG-2 Video Decoder
o ISO/IEC 13818-2 MPEG-2 video MP@HL
o Automatic frame rate conversion
o Supports resolution up to HDTV (1080i, 720p) and SDTV
• MPEG-4 Video Decoder
o ISO/IEC 14496-2 MPEG-4 ASP video decoding
o Supports resolutions up to HDTV (1080p@30fps)
o Supports DivX1 Home Theater & HD profilesOptional
o Supports VC-1Optional, FLV video format decoding
• Hardware JPEG
o Supports sequential mode, single scan
o Supports both color and grayscale pictures
o Following the file header scan the hardware decoder fully handles the
decode process
o Supports programmable Region of Interest (ROI)
o Supports formats: 422/411/420/444/422T
o Supports scaling down ratios: 1/2, 1/4, 1/8
o Supports picture rotation
• NTSC/PAL/SECAM Video Decoder
o Supports NTSC-M, NTSC-J, NTSC-4.43, PAL (B,D, G, H, M, N, I, Nc),
and SECAM standards
o Automatic standard detection
o Motion adaptive 3D comb filter
o Five configurable CVBS & Y/C S-video inputs
o Supports Teletext, Closed Caption (analog CC 608/ analog CC 708/digital
CC 608/digital CC708), V-chip and SCTE
• Multi-Standard TV Sound Processor
o SIF audio decoding
o Supports BTSC/A2/EIA-J demodulation
o Supports NICAM/FM/AM demodulation
o Supports MTS Mode Mono/Stereo/SAP in BTSC/ EIA-J mode
o Supports Mono/Stereo/Dual in A2/NICAM mode
o Built-in audio sampling rate conversion (SRC)
o Audio processing for loudspeaker channel, including volume, balance,
mute, tone, EQ,virtual stereo/surround and treble/bass controls
o Advanced sound processing options available,for example: SRS1, BBE2,
QSound3, Audyssey4
o Supports digital audio format decoding:
 MPEG-1, MPEG-2 (Layer I/II), MP3, Dolby Digital (AC-3), AAC-LC
 Supports Optional Dolby Digital Plus, Dolby mPulse, and MS10
multistream decoder, including Dolby Digital Encoder for
transcoding streams to Dolby Digital 5.1 (DDCO)
 Supports MPEG Audio, Dolby Digital, Dolby Digital Plus format AD
(Audio Description)
o Supports PVR and time-shifting
• Audio Interface
o One SIF audio input interface with minimal external saw filters
o Four L/R audio line-inputs
o Two L/R outputs for main speakers and additional line-outputs
o Supports stereo headphone driver
o I2S digital audio input & output
o S/PDIF digital audio output
o HDMI audio channel processing
o Programmable delay for audio/video synchronization
o Analog RGB Compliant Input Port
o Three analog ports support up to 1080P
o Supports PC RGB input up to SXGA@75Hz
o Supports HDTV RGB/YPbPr/YCbCr
o Supports Composite Sync and SOG Sync-on-Green
o Automatic color calibration
o AV-link support
o Analogue RGB Auto-Configuration & Detection
o Auto input signal format and mode detection
o Auto-tuning function including phasing, positioning, offset, gain, and jitter
detection
o Sync Detection for H/V Sync
• DVI/HDCP/HDMI Compliant Input Port
o Two HDMI/DVI Input ports
o HDMI 1.3 Compliant
o HDCP 1.1 Compliant
o 225 MHz @ 1080P 60 Hz input with 12-bit Deep-color support
o CEC support
o Single link DVI 1.0 compliant
o Robust receiver with excellent long-cable support
• MStar Advanced Color Engine (MStarACE-5)
• 10/12-bit internal data processing
• Fully programmable multi-function scaling engine
o Nonlinear video scaling supports various modes including Panorama
o Supports dynamic scaling for VC-1
• High-Quality DTV video processor
o 3D motion video deinterlacer with motion object stabilizer
o Edge-oriented deinterlacer with edge and artifact smoother
o Automatic 3:2/2:2/M:N pull-down detection and recovery
o 3D multi-purpose noise reduction for DTV or lousy air/cable input
o MPEG artifact removal including de-blocking and mosquito noise
reduction
o Arbitrary frame rate conversion
• MStar Professional Picture Enhancement:
o Dynamic brilliant and fresh color
o Dynamic Blue Stretch
o Intensified contrast and details
o Dynamic Vivid Skin
o Dynamic sharpened Luma/Chroma edges
o Global and local dynamic depth of field perception
o Accurate and independent color control
o Supports sRGB and xvYCC color processing
o Supports HDMI 1.3 deep color format
• Programmable 12-bit RGB gamma CLUT
• Output Interface
o Single/dual link 8/10-bit LVDS output
o Supports panel resolution up to Full-HD (1920x1080) @ 60Hz
o Supports TH/TI format
o Supports dithering options to 6/8-bit output
o Spread spectrum output for EMI suppression
• CVBS Video Encoder
o Supports all NTSC/PAL TV Standard
o Stand-alone scaling engine
o Programmable Hue, Contract, Brightness
o Supports TTX/CC/WSS output

o CVBS Video Output


o Allows CVBS output of all source inputs
• 2D Graphics Engine
o Hardware Graphics Engine for responsive
o Interactive applications
o Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid
draw
o BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt
o Raster Operation (ROP)
o Support Porter-Duff
• VIF Demodulator
o Compliant with NTSC M/N, PAL B, G/H, I, D/K, SECAM L/L' standards
o Audio/Video dual-path processor
o Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution
o Maximum IF gain of 37 dB
o Programmable TOP to accommodate different tuner gain and SAW filter
insertion loss to optimize noise and linearity performance
o Multi-standard processing with single SAW
o Supports silicon tuner low IF output architecture
• DVB-T Demodulator
o Digital carrier frequency offset correction: ±500KHz
o Optimised for SFN channels with pre/post-cursive echoes inside/outside
the guard
o Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset
o Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test
requirement
o ±400kHz internal carrier offset recovery range
o 6.8 usecs echo cancellation at 7 Msym/s
o Supports IF, low-IF, zero-IF inputs
o Ultra-fast automatic blind UHF/VHF channel scan (constellations and
symbol rate)
• Connectivity
o Two USB 2.0 host ports
o USB architecture designed for efficient support of external storage
devices in conjunction with off air broadcasting
• Miscellaneous
o DRAM interface supporting one 16-bit DDR2 @1066MHz
o Supports PVR
o Supports Common Interface for conditional access support
o Bootable SPI interface with serial flash support
o Parallel interface for external NAND flash support
o Power control module with ultra low power MCU available in standby
mode
o 380-ball LFBGA package
o Operating Voltages: 1.26V (core), 1.8V (DDR2), 2.5V and 3.3V (I/O and
analog)
6.2 MSTAR block diagram
6.3 Reset circuit
Reset circuit using for initiliazing main Mstar IC. Reset condition is high and nomal
working condition is low for RESET pin.

7 CI interface

CI Interface Power Switch:


It is used for CI module supply, when Module is inserted (it means CI detect is low) This
circuit is opened or closed by CI_POWER_CTRL port of main uController
8 USB interface
Main Concept IC has integrated 2 USB 2.0 interface. One of them is used for ethernet
function, the other one is used for USB connectivity for last user. Last user can play video,
picture and audio files. Also digital channels can be record to external storage device by
this interface. All SW files can be updated with interface.

USB circuit has 3 main parts


• Integrated USB 2.0 Host interface of D3K (U5)
• Protection IC (U145)
• Over current protection IC (U8)
9 DDR2 SDRAM K4T1G164QF (U155)

9.1 Description
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8
banks device. This synchronous device achieves high speed double-data-rate transfer
rates of up to 1066Mb/sec/pin (DDR2-1066) for general applications. The chip is designed
to comply with the following key DDR2 SDRAM features such as posted CAS with additive
latency, write latency = read latency - 1, Off-Chip Driver (OCD) impedance adjustment and
On Die Termination. All of the control and address inputs are synchronized with a pair of
externally supplied differential clocks. Inputs are latched at the crosspoint of differential
clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional
strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to
convey row, column, and bank address information in a RAS/CAS multiplexing style. For
example, 1Gb (x8) device receive 14/10/3 addressing. The 1Gb DDR2 device operates
with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 1 Gb DDR2 device is
available in 60 ball FBGA(x8) and 84ball FBGA(x16).

9.2 Features

• JEDEC standard VDD = 1.8V ± 0.1V Power Supply


• VDDQ = 1.8V ± 0.1V
• 533MHz fCK for 1066Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 4, 5, 6, 7
• Programmable Additive Latency: 3, 4, 5. 6
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional
feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support - PASR(Partial Array Self Refresh) - 50ohm ODT - High
• Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE <
95°C
• All of products are Lead-free, Halogen-free, and RoHS compliant
Pinning

1 2 3 7 8 9

Voo NC Vss VssQ UOQS VoDQ


OQ14 VssQ UOM UOQS VssQ DQ15
VoDQ OQ9 VooQ VoDQ DQ8 VoDQ
OQ12 VssQ DQ11 DQ10 VssQ OQ13
Voo NC Vss VssQ LDQS VoDQ
DQ6 VssQ LDM LOQS VssQ OQ7
VoDQ OQ1 VooQ VoDQ DQO VoDQ
DQ4 VssQ OQ3 OQ2 VssQ OQ5
VooL VREF Vss VssoL CK Voo
CKE WE RAS CK OOT
BA2 BAO BA1 CAS cs
A10/AP A1 A2 AO Voo
Vss A3 AS A6 A4
A7 A9 A11 A8 Vss
Voo A12 NC NC NC

1 2 3 4 s 6 7 8 9
Ball Locations (x16)
AB ••••••++++++•·•••••
EFD •••+++•· ••
c
• Populated ball
+
++••••
Ball not populated

GH•••++
• •+++•· •• ••
Top view
J
KL •••••
+••+++•·• •
• + +
(See the balls throughpackage)

MN + • •
•••+++•·+++•·
•+ · •••
+ •
R •••+++••+
p •
10 Scaler and LVDS sockets

10.1 LVDS sockets block diagram

10.2 Panel supply switch circuit


This switch is used to open and close panel supply of TCON. It is controlled by port of
main ucontroller. Also with this circit panel sequency could be adjusted correctly. 3 panel
supplys are connected to this circuit. All of them are optional according to panels.
11 SPI flash memory - MX25L1005 (U158)

11.1 General Description


MX25L1005 is a CMOS 1,048,576 bit serial Flash memory, which is configured as
131,072 x 8 internally.The MX25L1005 feature a serial peripheral interface and software
protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock
input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the
device is enabled by CS# input. The MX25L1005 provide sequential read operation on
whole chip. After program/erase command is issued, auto program/ erase algorithms
which program/ erase and verify the specified page or sector/block locations will be
executed. Program command is executed on page (256 bytes) basis, and erase
command is executes on chip or sector(4K-bytes) or block(64K-bytes). To provide user
with ease of interface, a status register is included to indicate the status of the chip. The
status read command can be issued to detect completion status of a program or erase
operation via WIP bit. When the device is not in operation and CS# is high, it is put in
standby mode and draws less than 10uA DC current. The MX25L1005 utilize MXIC's
proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.

11.2 Features
• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
• 1,048,576 x 1 bit structure
• 32 Equal Sectors with 4K byte each, Any Sector can be erased individually
• 2 Equal Blocks with 64K byte each, Any Block can be erased individually
• Single Power Supply Operation
• 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V

11.3 Absolute maximum ratings

RATING VALUE
Ambient Operating 0°C to 70°C
Temperature
Storage Temperature -55°C to 125°C
Applied Input Voltage -0.5v to 4.6v
Applied Output Voltage -0.5v to 4.6v
VCC to Ground Potential -0.5v to 4.6v

11.4 Pinning
8-PIN SOP (150mil)

SYMBOL DESCRIPTION
CS# Chip select
SI Serial Data Input
SO Serial Data Output
SCLK Clock Input
HOLD# Hold, to pause the device without
deselecting the device
VCC +3.3v Power Supply
GND Ground
12 NAND Flash memory – NAND512XXA2C (U162)

12.1 General Description


The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that
uses the single level cell (SLC) NAND technology. It is referred to as the small page
family.

The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of 512


Mbits and operate with either a 1.8 V or 3 V voltage supply. The size of a page is either
528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the
device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8
or x16 input/output bus. This interface reduces the pin count and makes it possible to
migrate to other densities without changing the footprint.

To extend the lifetime of NAND flash devices it is strongly recommended to implement an


error correction code (ECC). The use of ECC correction allows to achieve up to 100,000
program/erase cycles for each block. A write protect pin is available to give a hardware
protection against program and erase operations.

12.2 Features
• High density NAND flash memories
o 512-Mbit memory array
o Cost effective solutions for mass storage applications

• NAND interface
o x8 or x16 bus width
o Multiplexed address/ data

• Supply voltage: 1.8 V, 3 V


• Page size
o x8 device: (512 + 16 spare) bytes
o x16 device: (256 + 8 spare) words

• Block size
o x8 device: (16K + 512 spare) bytes
o x16 device: (8K + 256 spare) words

• Page read/program
o Random access: 12 μs (3 V)/15 μs (1.8 V) (max)
o Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)
o Page program time: 200 μs (typ)
• Copy back program mode
• Fast block erase: 2 ms (typ)
• Status register
• Electronic signature
• Chip Enable ‘don’t care’
• Security features
o OTP area

• Serial number (unique ID) option


• Hardware data protection
o Program/erase locked during power transitions

• Data integrity
o 100,000 program/erase cycles (with ECC)
o 10 years data retention

• RoHS compliant packages


• Development tools
o Error correction code models
o Bad blocks management and wear leveling algorithms

12.3 Pinning
13 LNBH23L (U6)

13.1 Description
Intended for analog and digital satellite receivers,the LNBH23L is a monolithic voltage
regulator
and interface IC, assembled in QFN32 5 x 5 specifically designed to provide the 13 / 18 V
power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna
dish or to
the multi-switch box. In this application field, it offers a complete solution with extremely
low
component count, low power dissipation together with simple design and I²C standard
interfacing.

13.2 Features

• Complete interface between LNB and I²C bus

• Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ.
93% @ 0.5 A)

• Selectable output current limit by external resistor

• Compliant with main satellite receivers output voltage specification

• Auxiliary modulation input (EXTM pin) facilitates DiSEqC™ 1.X encoding

• Accurate built-in 22 kHz tone generator suits widely accepted standards

• Low-drop post regulator and high efficiency step-up PWM with integrated power
NMOS allow low power losses

• Overload and over-temperature internal protections with I²C diagnostic bits

• LNB short circuit dynamic protection

• +/- 4 kV ESD tolerant on output power pins


13.3 Block diagram

14 Advanced DVB-S/S2 demodulator M88DS3002 (U3)

14.1 Description

The M88DS3002 is an advanced single-chip demodulator for digital satellite television


broadcasting. It is fully compliant with the DVB-S/S2 standard and can support QPSK,
8PSK, 16APSK and 32APSK demodulation schemes. The chip provides a fast, easy-to-
apply and cost-effective front-end solution for digital satellite receiver. The M88DS3002
accepts baseband differential or single ended I and Q signals from a tuner, then
digitizes, demodulates and decodes the signals, and finally outputs an MPEG transport
stream. The M88DS3002 supports symbol rate from 1 Msps up to 45 Msps, and code
rate from 1/4 to 9/10. Its features cover blind scan, fade detection, timing and carrier
recovery, performance monitoring, co-channel interference cancellation, command
interface, and DiSEqC™ 2.X interface, etc. The device is controlled via a 2-wire serial
bus. The M88DS3002 works properly with 1.25 V and 3.3 V voltage supplies. Typically,
the power consumption is around 390 mW. The chip is available in a 64-pin QFN
package and is RoHS compliant.

14.2 Features

• Multi-standard demodulation
• Compliant with DVB-S/S2 specification
• QPSK, 8PSK, 16APSK and 32APSK demodulation schemes
• Maximum channel bit rate is 130 Mbps
• Maximum symbol rates are: 45 Msps for QPSK and 8PSK; 36 Msps for 16APSK
and 28 Msps for 32APSK
• DSP features
• Symbol rate sweeping
• I/Q impairment cancellation
• Automatic spectrum inversion
• Adaptive equalizer for RF reflection removal
• Roll-off factor automatic identification
• Blind scan for programming search
• High performance on-chip micro-controller
• Multi-error monitor
• Accurate SNR estimation
• Multi-lock indicators
• Clipping rate reporter
• DC removal
• Automatic frequency correction (AFC)
• Fast timing loop acquisition
• Robust frame synchronization scheme
• Phase noise indicator
• Fast system recovery from fading or other abnormal conditions
• Co-channel interference cancellation
• Constellation monitor

• Interface
• DVB-S/S2 common, parallel and serial MPEG output interface compliant
• 2-wire serial bus to configure the device
• 2-wire bus repeater for tuner configuration
• DiSEqC™ 2.X compliant interface
• General purpose output (GPO)
• Dedicated reference clocks (13.5MHz / 27MHz) generation

• System
o On-chip 8-bit ADC
o On-chip PLL for master clock from a 27 MHz external clock or quartz
crystal
o Sleep mode supported
---Block Diagram of M88DS3002---

14.3 Pin Assignment


15 LM1117 (U175, U180, U181)

15.1 General description


The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA
of load current. It has the same pin-out as National Semiconductor’s industry standard
LM317. The LM1117 is available in an adjustable version, which can set the output
voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also
available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is
available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10μF
tantalum capacitor is required at the output to improve the transient response and
stability.

15.2 Features
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
• LM1117 0°C to 125°C
• LM1117I -40°C to 125°C

15.3 Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators 15
• 32” TFT TV Service Manual 10/01/2005
• Battery Charger
• Battery Powered Instrumentation

15.4 Absolute maximum ratings


15.5 Pinning

16 MP2012 (U176)

17 General description
The MP2012 is a fully integrated, internally compensated 1.2MHz fixed frequency PWM
step-down converter. It is ideal for powering portable equipment that runs from a single
cell Lithium-Ion (Li+) Battery, with an input range from 2.7V to 6V. The MP2012 can
provide up to 1.5A of load current with output voltage as low as 0.8V. It can also operate
at 100% duty cycle for low dropout applications. With peak current mode control and
internal compensation, the MP2012 is stable with ceramic capacitors and small inductors.
Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown.

17.1 Features
• 2.7-6V Input Operation Range
• Output Adjustable from 0.8V to VIN
• 1 μA Max Shutdown Current.
• Up to 95% Efficiency
• 100% Duty Cycle for Low Dropout
• Applications
• 1.2MHz Fixed Switching Frequency
• Stable with Low ESR Output Ceramic
• Capacitors
• Thermal Shutdown
• Cycle-by-Cycle Over Current Protection
• Short Circuit Protection
• Available in 6-pin 3x3mm QFN
17.2 Pinning

Pin Name Description


#
1 FB Feedback input. An external resistor divider from
the output to GND, tapped to the FB pin sets the
output voltage.
2 GND, Ground pin. Connect exposed pad to ground
Exposed plane for proper thermal performance.
Pad
3 SW Switch node to the inductor.
4 PVIN Input supply pin for power FET.
5 VIN Input Supply pin for controller. Put small
decoupling ceramic near this pin.
6 EN Enable input, “High” enables MP2012. EN is
pulled to GND with 1Meg internal resistor.

18 RTA8283A (U23, U173)

18.1 General description


The RT8283A is a high-efficiency, monolithic synchronous step-down DC/DC converter
that can deliver up to 3A output current from a 4.5V to 23V input supply. The RT8283A's
current mode architecture and external compensation allow the transient response to be
optimized over a wide range of loads and output capacitors. Cycle-by-cycle current limit
provides protection against shorted outputs and soft-start eliminates input current surge
during start-up. The RT8283A also provides output under voltage protection and thermal
shutdown protection. The low current (<3μA) shutdown mode provides output disconnect,
enabling easy power management in batterypowered systems. The RT8283A is available
in a SOP-8 package.

18.2 Features
• ±1.5% High Accuracy Feedback Voltage
• Integrated N-MOSFET Switches
• Current Mode Control
• Fixed Frequency Operation : 340kHz
• Output Adjustable from 0.8V to 20V
• Up to 95% Efficiency
• Thermal Shutdown Protection
18.3 Pinning

Pin No. Pin Description


Name
1 BOOT Bootstrap for high-side gate driver. Connect a 0.1μF or
greater ceramic capacitor from BOOT to SW pins.
2 VIN Input Supply 4.5V to 23V. Must bypass with a suitably
large ceramic capacitor.
3 SW Phase Node--Connect to external L-C filter..
4, 9 (Exposed GND Ground.
Pad)
5 FB Feedback Input pin is connected to the converter output.
It is used to set the output of the converter to regulate to
the desired value via an internal res divider. For an
adjustable output, an external res divider is connected to
this pin.
6 COMP Compensation Node. COMP is used to compensate the
regulation Control loop. Connect a series RC network
from COMP to GND. In some cases, an additional
capacitor from COMP to GND is required.
7 EN Enable Input Pin. Logic high enables the converter; a
logic low forces the RT8253A into shutdown mode.
Attach this pin to VIN with a 100kΩ pull up resistor for
automatic startup.
8 SS Soft-Start Control Input. SS controls the soft-start period.
Connect a capacitor from SS to GND to set the soft-start
period. A 0.1μF capacitor sets the soft-start period to
13.5ms.
19 MP1583 (U174)

19.1 General description


The MP1583 is a step-down regulator with a built-in internal Power MOSFET. It
achieves
3A of continuous output current over a wide input supply range with excellent load and
line regulation. Current mode operation provides fast transient response and eases
loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and
thermal shutdown. An adjustable soft-start reduces the stress on the input source at start-
up. The MP1583 requires a minimum number of external components, providing a
compact solution.

19.2 Features
• 3A Output Current
• Programmable Soft-Start
• 100mΩ Internal Power MOSFET Switch
• Stable with Low ESR Output Ceramic Capacitors
• Up to 95% Efficiency
• 20μA Shutdown Mode
• Fixed 385KHz Frequency
• Thermal Shutdown
• Cycle-by-Cycle Over Current Protection
• Wide 4.75V to 23V Operating Input Range
• Output Adjustable from 1.22V to 21V
• Under-Voltage Lockout

19.3 Pinning

Pin Pin Description


No. Name
1 BOOT High-Side Gate Drive Bootstrap Input. BS supplies the drive for the
high-side N-Channel MOSFET switch.
2 IN Power Input. Drive IN with a 4.75V to 23V power source.
3 SW Power Switching Out is the switching node that supplies power to the
output
4 GND Ground.
5 FB Feedback Input. FB senses the output voltage and regulates it. Drive
FB with a resistive voltage divider from the output voltage. FB
threshold is 1.222V.
6 COMP Compensation Node is used to compensate the regulation control
loop.
7 EN Enable/UVLO. A voltage greater than 2.71V enables operation. For
complete low current shutdown the EN pin voltage needs to be at less
than 900mV. When the voltage on EN exceeds 1.2V, the internal
regulator will be enabled and the soft-start capacitor will begin to
charge. The MP1583 will start switching after the EN pin voltage
reaches 2.71V.
8 SS Soft-Start Control Input. SS controls the soft-start period.

20 FDC642

20.1 General description


This P-Channel 2.5V specified MOSFET is produced using Fairchild’s advanced
PowerTrench® process that has been especially tailored to minimize on-state resistance
and yet maintain low gate charge for superior switching performance.

These devices have been designed to offer exceptional power dissipation in a very small
footprint for applications where the larger packages are impractical.

20.2 Features
• Max rDS(on) = 65 mΩ at VGS = -4.5 V, ID = -4.0 A
• Max rDS(on) = 100 mΩ at VGS = -2.5 V, ID = -3.2 A
• Fast switching speed
• Low gate charge (11nC typical)
• High performance trench technology for extremely low rDS(on)
• SuperSOTTM-6 package: small footprint (72% smaller than standard
SO-8); low profile (1 mm thick)
• Termination is Lead-free and RoHS Compliant

20.3 Pinning
21 FDC604P

21.1 General description


This P-Channel 1.8V specified MOSFET uses Fairchild’s low voltage PowerTrench
process. It has been optimized for battery power management applications.

21.2 Features
• –5.5 A, –20 V. RDS(ON) = 33 mΩ @ VGS = –4.5 V
• RDS(ON) = 43 mΩ @ VGS = –2.5 V
• RDS(ON) = 60 mΩ @ VGS = –1.8 V
• Fast switching speed.
• High performance trench technology for extremely low RDS(ON)(S)

21.3 Pinning
22 Connectors

22.1 SCART (SC1)

22.2 HDMI (CN707, CN708)


22.3 VGA (CN711)

15.

14. VERTICAL SYNC


15. DOC CLOCK _. -.
23 Service menu mode

To enter the service menu, press MENU-4-7-2-5 keys consecutively, on the remote control. The top-level
service menu will appear. All submenus can be selected via Up/Down keys and displayed by pressing OK
key. When a submenu is displayed, top-level service menu disappears. Pressing RETURN key, returns to
the one level higher menu. Pressing the MENU key will exit service menu.

Some items are changeable at service menu, the values of which are stored in the NVM when the menu is
closed. Some items are read-only, which can only be changed by Profile Manager and displayed in service
menu for convenience.

23.1 Main service menu


Service menu or a sub-menu is displayed on the screen when the TV is in one of the TV/AV/PC modes. It
shows what the items are set in Profile Manager. It is a read-only screen, not writable.

It shows the following items:

 TV Life Time: The number of minutes the set is in the “On” mode.

 Standby SW Version: The version number of the Stand-by software.

 Mboot Version: The version number of the Mboot software.

 PANEL: The LCD panel identification including the software version information.

 PQ: Picture quality tool version information.

 PROFILE: TV specific option profile

 PIX FILES: Not applicable

 HW Profile Version: The version number of the hardware profile.

 SW Profile Version: The version number of the software profile.

 Lan Profile Version: The version number of the Lan profile.

 Customer: Philips

Items exist in the main screen of service menu. Also, software version number and DCF id are written in
the header of service menu.
The main items in Service Menu:

23.2 Video Settings


RF AGC adjustments for neighbour and image channels exist or don't. Also, ADC Calibration gain
and offset values for RGB separately due to selected sources

23.3 Audio Settings


Surround type and surround mode text items are displayed.
23.4 Options 1
Profile options such as AUTO TV off time, Power up mode, EPG type, etc. are displayed in options 1.

23.5 Options 2
Profile options such as APS sorting, Dynamic Menu, Auto zoom mode etc. are displayed in Options 2.
23.6 Tuning Settings
Tuner type is displayed.

23.7 Source Settings


Enable and disabled sources are displayed.

When TV is disabled, Items which are connected to Tuner are picked off from menu. (Install and Retune
Menu, Channel List Menu...).

23.8 Diagnostic
The result of various diagnostic tests are displayed here.

23.9 USB operations


USB operations are performed by pressing that button.

See Service Menu Design Idea for Menu structure, look and feel, position, etc…
Video Settings • RF AGC SECAM

• RF AGC NEIGHBOUR NO IMAGE NO

• RF AGC NEIGHBOUR NO IMAGE YES

• RF AGC NEIGHBOUR YES IMAGE NO

• RF AGC NEIGHBOUR YES IMAGE YES

• RF AGC

• ADC Calibration Source

• ADC Calibration R Gain

• ADC Calibration G Gain

• ADC Calibration B Gain

• ADC Calibration R Offset

• ADC Calibration G Offset

• ADC Calibration B Offset

Audio Settings • Surround Type

• Surround Mode Text

Options 1 • Auto TV OFF

• Power Up mode

• Backlight Trick Mode

• Cable Support

• EPG Type

• Hotel Mode

• LCN

• PC Standby

• Stby Search

• Test Tool

• Local Key

• Volume Level

Options 2 • Aps Sorting

• Dynamic Menu

• EPG Menus

• Transparent Text
• HDMI Number

• Remote control type

• DCF ID

Tuning Settings • Tuner Type

Source Settings • TV

• EXT1

• EXT2

• EXT2-S

• FAV

• S-VIDEO

• HDMI 1

• HDMI 2

• HDMI 3

• HDMI 4

• YPBPR

• VGA/PC

• Blu-ray

Diagnostic • Remote control test

• UHF test

• VHF test

• Factory reset

• Tuner I2C

• IF I2C

• HDMI I2C

• Ethernet

• EDID Status

• HDCP Status

• DDR Settings

• CI+ Credentials

• MAC Address
USB Operations Press this button to perform USB operations.
USB stick should be connected before this operation.

23.10 Profile Operations


VES1.1E LA profile data are kept in the flash file system as separate files. So they can be downloaded to
USB memory stick or uploaded to TV from a memory stick individually.

23.10.1 Upload profile Data from USB


1. Create a folder named profile in the USB stick.
2. Copy mb62_swprofile.bin and mb62_hwprofile.bin into the USB profile folder.
3. Plug the USB stick into the TV.
4. Open service menu and select “USB Operations”.

The files will be automatically copied to the TV flash file system.

After a reboot, App/Mw will start to use new profiles. It is possible to upload hardware or software profiles
separately.

23.10.2 PQ Files Operations


It is also possible to download/upload PQ files from/into the SSB when USB Operations button in service
menu is pressed.

Whenever a USB stick is connected to TV set and USB Operations button in service menu is pressed, /pq
folder is checked.

If it exists and if they include some files, necessary copy/delete operations are performed.

23.10.3 Upload PQ files from USB

1. Create a folder named “pq” in the USB stick.


2. Copy VESTEL_D1_Plus_PNL.bin, Titania2_Main.bin and Titania2_Main_Text.bin into USB “pq”
folder.
3. Connect USB stick to TV.
4. Open service menu, select “USB Operations”.

The files named VESTEL_D1_Plus_PNL.bin, Titania2_Main.bin, Titania2_Main_Ex.bin and


Titania2_Main_Text.bin will be copied from USB to TV.

23.10.4 Ci+ credentials key update


1. Create a “spi” folder in root of the memory stick
2. Copy mb62_credentials.bin to “spi” folder
3. Connect the USB stick to the TV.
4. Perform USB Operations in the service menu.

23.10.5 HDCP keys update


1. Create a “spi” folder in root of the memory stick.
2. Copy “mb62_hdcp.bin” to “spi” folder.
3. Connect the USB stick to the TV.
4. Perform USB operations in the service menu.
23.10.6 Edid update
1. Create a “spi” folder in root of the memory stick.
2. Copy “edid.edid” to the “spi” folder.
3. Connect the USB stick to the TV.
4. Perform USB operations in the service menu.

23.10.7 DDR settings update


1. Create a “spi” folder in root of the memory stick.
2. Rename the ddr binary file to be used which resides in the config_mb62 folder as mb62_ddr.bin.
3. Copy the file “mb62_ddr.bin” to the “spi” folder.
4. Connect the USB stick to the TV.
5. Perform USB operations in the service menu.

23.10.8 MAC address update


1. Create “spi” folder in root of the memory stick.
2. Copy the file “mb62_mac.bin” to the “spi” folder.
3. Connect the USB stick to the TV.
4. Perform USB operations in the service menu.

23.11 Hotel Mode setup menu


The hotel mode setup menu has a normal and a high security mode.

To enter the hotel mode setup menu of a set in the normal security mode, press “MENU 7935” on the
remote control belonging to this set.

To enter the hotel mode setup menu of a set in the high security mode, the yellow service remote control
is needed. To navigate through the menu, the remote control that belongs to the set is needed.
To enter the hotel mode setup menu on a set with high security mode, first put the yellow remote in RC5
mode and then press the “Home/Menu” button.

• Note: To order a yellow remote, use order code: 22AV8573/00 or 12NC 8670 000 67389.

23.11.1 Hotel TV welcome image update (only available in Hotel TVs)


In the VES1.1E LA the welcome image can be updated:
Copy To USB
There are two steps and both are independent of each other.
Copy the updated welcome image to USB as “hotel_wel.png”. Copy NVRAM data (service list,
preferences, etc.) to the USB device. In this chassis all nvram data is stored in 8 × 32KB Flash
files named as Flash0.bin, Flash1.bin ... Flash7.bin. When a Copy to USB is called, those files
are copied from TV to USB. Then they can be used for various purposes testing on another TV
or testing/debugging on observatory etc. Note that USB should be plugged before this
operation.

Copy From USB


There are two steps and both are independent of each other.
If there is file named “hotel_wel.png” in directory “welcome_image”. It is copied to the tv to use
as welcome image.
Copy from USB device data to NVRAM. Just the reverse operation is done by a copy to USB
call. Previously copied nvram files (Flashx.bin) are copied into TV. If there is no flash file or
some of them are available on USB, the available ones are copied. If no USB is connected,
nothing happens.
• Note: For the clone function a USB stick (Copy to USB – Copy from USB) must be formatted to FAT32. If the
USB stick is not formatted to FAT32 the other TVs will not accept cloned data and cause performance issues.
24 Software update
In the VES1.1E LA there is only one software package. From following steps software update
procedure can be seen:

1. MB62_en.bin, mboot.bin and usb_auto_update_T4.txt documents should copy directly inside of a


flash memory(not in a folder).
2. Put flash memory to the tv when tv is powered off.
3. Power on the and wait when the tv is opened.
4. If first time installation screen is displayed, it means the software update procedure is successful.

25 Troubleshooting

25.1 No backlight problem


Problem: If TV is working, led is normal and there is no picture and backlight on the panel.

Possible couses: Backlight pin, dimming pin, backlight supply, stby on/off pin

Backlight pin should be high in open position. If it is low, please check Q181 and panel
cables.

Dimming pin should be high or square wave in open position. If it is low, please check
S16 for Mstar side and panel or power cables, connectors.
Backlight power supply should be in panel specs. Please check CN705 for the SSB,
related connectors for power supply cards.
STBY_ON/OFF should be low for standby on condition, please check R1677.

25.2 CI module problem


Problem: CI is not working when CI module inserted.

Possible couses: Supply, suply control pin, detect pins, mechanical positions of pins
CI supply shoul be 5V when CI module inserted. If it is not 5V please check
CI_POWER_CTRL, this pin should be low.
Please check mechanical positions of the CI module.

Detect ports should be low. If it is not low please check the Cl connector pins, Cl module
pins and 3V3_VCC on the SSB.
R1632

PCM D3
PCM D4
4
PCM DS
PCM D6
Cl Detect PCM D7
7 PCM CB N
8
PCM AlO
PCM OB_N
10 PCM All
11 PCM A9
12 PCM AS
13 PCM A13
14 PCM A14 3V3_VCC

21
22
23 12p
24 sov

".
25

27
28
29
Cl Detect 30
'A 31
25.3 LED blinking problem
Problem: LED blinking, no other operation

This problem indicates a short on Vcc voltages. Protect pin should be logic high while
normal operation. When there is a short circuit protect pin will be logic low. If you detect
logic low on protect pin, unplug the TV set and control voltage points with a multimeter to
find the shorted voltage to ground.

25.4 IR problem
Problem: LED or IR not working
Check LED card supply on the SSB.
LED SOCKET

L--<J SV STBY
F259
+----·2-- - -·[>IR IN
C949 600R

·H
Ql70

Ql7l
@ .-< BC949B

25.5 Keypad touchpad problems


Problem Keypad or Touchpad is not working.

Check keypad supply and keyboard pin on the SSB.


25.6 USB problems
Problem: USB is not working or no USB Detection.

Check USB Supply, It should be nearly 5V.

25.7 No sound problem


Problem: No audio at main TV speaker outputs.
Check supply voltages of VDD_AUDIO, 5V_VCC and 3V3_VCC with a voltage-meter.
There may be a problem in headphone connector or headphone detect circuit (when
headphone is connected, speakers are automatically muted). Measure voltage at
HP_DETECT pin, it should be 3.3v.

25.8 No sound problem at headphone


Problem: No audio at headphone output.

Check HP detect pin, when headphone is. Check 5V_VCC and 3V3_VCC with a voltage-
meter.

25.9 Standby On/Off problem


Problem:
Device cannot boot, TV hangs in standby mode.
There may be a problem about power supply. Check 12V_VCC, 5V_VCC and 3V3_VCC with a voltage-meter. Also there
may be a problem about SW. Try to update TV with latest SW. Additionally it is goood to check SW printouts via
hyper-terminal (or Teraterm). These printouts may give a clue about the problem.

25.10 DVD problems


Problem: DVD is not working.

Check that DVD source is selected in Service menu. Check supply voltage of DVD
namely 12V_VCC.

25.11 No signal problem


Problem: No signal in TV mode.

Check tuner supply voltage; 3V3_TUN. Check tuner options are correctly set in Service menu. Check AGC voltage at
IF_AGC pin of tuner.
26 Styling sheet

11 10

7 3
4 2
1

IR 1

17LD98

SCREW P C ZN Y
1
6
2

ASM 2

DISPLAY ASM 32" LED 1

METAL FRAME 32" LED 1

BACK COVER METAL 32130 1

BACK COVER 32130 LED DVD 1


5
10 SCREW P C ZN YFMB 3 x 9.5 8
1
11 COVER FOOT 1
27 Schematics
27.1 SSB
1 2 3 4 5 6 7 8

ACTIVE_ANT_SUPPLY
NUTUNE/SEMCO/LG

5V_VCC
C965
C904 2
C61 100n
1 TP48 100n 22u 16V
ANT-DC 1 ANT-DC 1 10V
1
6V3
ACTIVE_ANT_SUPPLY

TH1
R1595

2R1
2 2
A VCC 3V3_TUNER +3V3 3V3_TUNER TUN_SCL 10k 12V_VCC
IF_AGC_MST
R1597 R1963 A
TU1 10k 1
100R
2
IF_AGC_TUNER

TU3
SCL 3 SCL 3 47R TUN_SCL_MST F304 R1581
TUN_SCL 2
C912 2
C910
R30 ACTIVE_ANT_SUPPLY 1k 100n 100n
4 4 1k FDN336P 1 1

SDA TUN_SDA SDA 47R TUN_SDA_MST Q175 R1590 10V 10V


R29 R1594 Q172 10k ANT_CTRL
GND 5 GND 5 OVER_CUR_DETECT 10k BC848B

10k
TUN_SDA

R4
SUT-RE216
6 6
FK1601

CLK_OUT RESET RESET_TUNER

R1586

R1593
20k

10k
7 7 S40
IF_N DIGITAL_IF_N IF_N DIGITAL_IF_N
8 8 S41
IF_P DIGITAL_IF_P IF_P DIGITAL_IF_P

IF_AGC 9 IF_AGC 9
IF_AGC_TUNER IF_AGC_TUNER
1
TP47
SONY TUNER

B B

F1

3V3_S2_VDDD
1V2_VCC 1V25_S2_VDDI

1V25_S2_VDDI

1V25_S2_VDDI
60R
100n 10V

100n 10V

100n 10V

100n 10V

100n 10V

100n 10V

100n 10V

100n 10V

100n 10V

C60
C 22u
16V
C
C36

C37

C44

C45

C46

C47

C48

C49

C50

NC NC NC NC NC

C35

50V
33p
F2

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50
GNDD 49
3V3_VCC 3V3_S2_VDDD
60R C71
C38

GPO
C59
100n 10V

100n 10V

100n 10V

NC5

NC4

NC3

NC2

NC1

NC9

NC8
10V 100n

VDDD_4

LOCK

OLF
LNB_EN
VCC_9
VCC_10

CKXTAL_13
22u

4
3
D206

C5V6

C39

C40

C43

6V3 R26 12p

27MHz
27 MHZ KULLANILACAK 1 GNDA_1 M_CKOUT 48 47R TSMICLK

X3
50V
R27
2 XTAL_IN M_SYNC 47 47R

1
2
TSMISYNC
3 46

C34
XTAL_OUT VCC_8 1V25_S2_VDDI
3V3_S2_VDDA R28

50V
33p
4 45
C22

50V 50V VDDA_1 M_VAL 47R


3V3_S2_TUN

3V3_S2_TUN

TSMIVALID

C8

C9
C21
27p

27p

10p

10p
5 44 NC
D F4 16V GNDA_2 M_ERR D
3V3_VCC 3V3_S2_TUN X1 C29 10n
60R C58 S2_IP 6 IP M_DATA7 43
5 R4
100n 10V

100n 10V

100n 10V

100n 10V

100n 10V

100n 10V

1 4 4 TS_MDI7
22u 27MHz C30 10n
2 3 7
M88DS3002 42
C57

C56

C52

C53

C54

C55

6V3 S2_IN IN M_DATA6 6 R3 3 TS_MDI6


16V 3V3_S2_VDDD
3V3_S2_VDDA 8 VDDA_2 VDDD_3 41
7 R2 TS_MDI5
14

13

12

11

10

2
9

U3
16V 9 GNDA_3 M_DATA5 40 R1
VDDA4

VDDA3

TS_MDI4
XTALN

XTALP

8 1
TEST1

TEST2

TEST3

C32 10n 47R


F3 S2_QN 10 QN M_DATA4 39 R1584
3V3_VCC 3V3_S2_VDDA R39 C31 10n
60R 3k3 RES VDDA2 3V3_S2_TUN S2_QP 11 QP VCC_7 38 1V25_S2_VDDI
100n 10V

100n 10V

15 7
10n 16V 47R
NC 12 37
C41

C42

16V 16 CAP CK_OUT 6 NC6 M_DATA3 5 R4 4 TS_MDI3


C27

10p

10p
13 36
C10

C11
17 CKDIV_OPT IP 5 S2_IP 3V3_S2_VDDD VDDD_1 M_DATA2 6 R3 3 TS_MDI2
S11
2 1

NC 14 35
U4

3V3_S2_TUN 18 RFBYPASS IN 4 S2_IN 1V25_S2_VDDI VCC_1 M_DATA1 7 R2 2 TS_MDI1


S5
2 1

E NC 15 34 R1
E
19 RESET VDDA1 3 3V3_S2_TUN 1V25_S2_VDDI VCC_2 M_DATA0 8 1 TS_MDI0
C63 L1 M88TS2022 16 33
R1583

ADDR_SEL1

ADDR_SEL0
CN17 LNA_IN QN NC7 VCC_6 1V25_S2_VDDI

CKXTAL_27
S2_QN

DISEQC_IN
20 2

3V3_S2_VDDD
S138 4n7
2 1

VDDD_2
2p2 3.3pF

DISEQC
VCC_3

VCC_4

VCC_5
1

RESET
C62

AAGC
50V TEST QP
50V

S2_QP

SDAT
50V
2p2

21 1

SCLT

VSEL
SDA

SCL
C20

R15
S25

4k7
0.5pF
VDD_REG
VDD_DIG

1n
VDDA6
VDAA5

R44
2

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32
AGC
SDA

SCL

S2_AGC 2k
LNB_OUT 3V3_S2_VDDD
C33

1n 1n 1n 1n 16V RESET_S2
22

23

24

25

26

27

28

10n
C16

C18

C17

C19

3V3_S2_TUN 3V3_S2_TUN

DISEQC_OUT
1V25_S2_VDDI

1V25_S2_VDDI

1V25_S2_VDDI
3V3_S2_VDDD

2
50V 50V 50V 50V R31 R32
00 SEÇILDI WRITE:D0H READ:D1H
2

1k 1k S2_AGC

R16
4k7
2

2
S20

KONTROL EDILECEK
C25

C26

16V 16V
R14

R13
4k7

4k7

1
10n

10n
C28

16V
1

10n

R22 R38
1

F F
2

10k SCL_S2_TUN 33R SCL_SYS 3V3_S2_VDDD


R35 R37
NC
S12

33R SCL_S2_TUN SDA_S2_TUN 33R SDA_SYS


R36
1

SDA_S2_TUN
C72

C73
33R
17mb62-1
18p

18p
50V 50V 50V 50V PROJECT NAME : A3
C23

C24
27p

27p

SCH NAME : TUNER&S2_TUNER&DEMOD SHEET: OF: 8


DRAWN BY : Ulas Dereli 14-03-2011_17:04
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
PC INPUT
SCART

CDA4C16GTH
4

1
D2

CDA4C16GTH
5V_VCC

CDA4C16GTH
SCART VIDEO OUTPUT AMPLIFIER

D1
C663

D3
1

2
2

100n

R1479

R1311

R1310

R1265
1

R124 F179 10V

75R

10k

10k

10k
2
C835
12V_VCC 220R

50V
220p
21 1k
A A

8
1

1
C120
15

16V
100n
20 SC_CVBS_IN

R102

R103
390R
R1949

68k
50V SC_CVBS_OUT 14 100R VGA_VSNC
19 220p C836 C860
1

R1243
Q146
13 100R
2 1

18 BC858B
2 VGA_HSNC
R1233 47p 3

220R
3
C378 12
17 50V
R1249 Q119 2
SCART_CVBS_OUT
47R BC848B 11
16 SC_FB 10u

R1209

R1206
R1587 R620
1

2k7

2k7
10V
50V SC_R SC_CVBS_OUT 75R 100R 10
15 220p

R104
33k
9
2 1

14

R221
100R
C833 R1480
75R 75R 8
13
2 1 2 1

R1481 50V
220p
SCART LT1

75R TX/SDA_SC 7
12
2 1
SC1

R1482 2 1

B 11 C832 SC_G 6 B
75R RX/SCL_SC R1182 5
10
2 1

D178 R1483 1
4k7
2

4
2 1

9
C15V R1187 2 1
R1419
1
22k
2

100n SC_PIN8 3 33R VGA_B


8 50V
10V R1408
220p SC_B C664 2 33R
7 VGA_G
2 1
C853 R1409
50V
C831 1 33R VGA_R
6 75R
2 1
3n3 F205
CN711

1
1
3

4
5
2 NUP4004M5
R1489 1 2

SC_AUD_L_IN
5

R1516

R1515

R1517
600R

75R

75R

75R
SCART_AUD_L_IN

D5
4
F200 R1244

2
1 2 1
100R
2
SC_AUD_L_OUT
3 C854 600R
SCART_AUD_R_IN
50V C857
2
C 3n3 C
1 1
F206
2

SC_AUD_R_IN
4n7
50V
SAV RCA INPUT
F201 600R R1245 47n
1 2
SC_AUD_R_OUT 16V 30062840
100R
1 2

600R JK4
INDIA OPTION
R1420 C808 16V R1415 SAV_CVBS_IN
C858 K2 T1 C795 62R SC_CVBS_IN 6
1
S9
2

33R RIN0M CVBS0 33R YEL 5


47n
C807 16V C800 R1413
30064869 47n K3 U2 62R DVD_CVBS_IN
4n7 VGA_R 16V RIN0P CVBS1 33R SAV_L
1UF 4 S42
1 2

SC_CVBS_IN 50V R1422 16V 47n WHT 3


4 C810 J2 U3
YEL 33R GIN0M CVBS2
47n
16V C806 16V R1412 SAV_R
J3 V2 C799 62R SAV_CVBS_IN 2
1
S39
2

SCART_AUD_L_IN VGA_G GIN0P CVBS3 33R RED


JK7 3 47n 1
WHT 47n R1421 16V 16V R1411
C809 H1 T3 C794 SC_R
33R BIN0M CVBS4 33R
47n 47n 62R
SCART_AUD_R_IN 16V
SAV Slim INPUT
2 C802 H3

1
RED 1 VGA_B BIN0P
47n SC SVHS opt

R1485

R1486

300R
R1423 C861 TP49

R11
75R

75R
1

470R H2 SOGIN0 CVBSOUT0 T2 SCART_CVBS_OUT 1


VGA_G 50V 1n
D TP245 D

2
1

2
L6 HSYNC0 2
VGA_HSNC SAV_CVBS_IN
DVD INTERFACE (for 26" to 32") L5 VCOM U1 6

D171
C959 16V

C5V6

1
C830
VSYNC0

50V
220p
VGA_VSNC
50V

2
47n
R1652 1
TP38 3 C856
75R CN704 16V C882 L3
RIN1M 4 TP250 F203
R1650

!
1

47n 3n3

R1530
1 2 16V C798

33R
1 2

DVD_CVBS_IN 180R JK3 SAV_L_IN


K1 5
SC_R 47n
RIN1P SAV_L 600R
3 4 C973 16V C885 M3
1
TP247 F202
30062423FS1 5 7
TP44 TP5 10u GIN1M
1 2

R1624 1
1

47n SAV_R_IN
DVD_SENSE
1
100R
2
5 6 16V 1 2
12V_VCC U5 600R C855
47n C797 L2
1
TP43 4A/24VDC SC_G 16V GIN1P SAV_R
1

NC
1

TP42 1 7 8 1
S80
2
16V C884 N3
MSD9WB9PT-2 3n3
R1616
2
C628

TP1 BIN1M
10V

4k7
100n

50V
TP242

DVD_WAKEUP 47n
TP4 9 10 DVD_IR C796
1

YPbPr Slim INPUT


1

50V M2
SC_B 16V 47n BIN1P
2

220p
2

C650

R1623 R1505
50V
27p

C862 L1
E DVD_SPDIF 100R SC_CVBS_IN 470R SOGIN1 R1974 TP13 E
1

1n 50V RCA_PR
C972 7 33R
M5 HSYNC1
N4 JK1 5
SC_FB VSYNC1
4
R1975 1
TP3
RCA_Y
16V C881 R2 3 33R
RIN2M
47n
16V C805 R3 6
DVD_IR
BC848B

RCA_PR RIN2P R1976 1


TP2
47n
Q157

RCA_PB

D4 27p 50V
16V C883 P2 2 33R

27p 50V
R694 GIN2M
47n

2
C829

C823

C828
5

8
IR_IN 2
4k7
1
3V3_VCC

50V 27p
16V C803 P1 1
1

1
RCA_Y GIN2P

1
1

47n

CDA4C16GTH

R1619

R1620

R1621
TP50

75R

75R

75R
16V C886 N1
2

BIN2M
47n
2

C804

2
16V N2
R498

BIN2P
47k

RCA_PB 47n
F F

1
470R P3 SOGIN2
RCA_Y
1

DVD_IR_ON/OFF C859
R1494 1n
50V
PROJECT NAME : 17mb62-1 A3
SCH NAME : PERIPHERALs SHEET: OF: 8
DRAWN BY : Ulas Dereli 14-03-2011_17:05
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
U5
MSD9WB9PT-2 DDR18V
3V3_VCC
F187
FLH_3.3V NAND FLASH 3V3_VCC
R1632
10k CN141 CI INTERFACE
C10 A_MADR0 60R

M9
1 A_MADR[0] 35 1

G9

G7

G3

G1
A1

A9
C9

C7

C3

C1
R1

E1

E9
J1

J9
A_MADR[1] D21 A_MADR1 C868
NAND_WPz 1 NC1 NC29 48 PCM_CD1_N 36 2 PCM_D3
C657 C656
A9 A_MADR2 TS_MDO3 PCM_D4

D205

C5V6
2 2

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ5

VDDQ4

VDDQ3

VDDQ2

VDDQ1
A_MADR[2] 22u 37 3

VDDQ10
VDD5

VDD4

VDD3

VDD2

VDD1
100n 100n

VDDL
A_MADR[3] E20 A_MADR3 6V3
1

10V
1

10V 2 NC2 NC28 47 TS_MDO4 38 4 PCM_D5


A_MADR[4] B9 A_MADR4 TS_MDO5 39 5 PCM_D6
A_MADR[5] E19 A_MADR5 AA_MDATA0 DQ0 A0 AA_MADR0 3 NC3 NC27 46
FLH_3.3V R47 TS_MDO6 40 6 PCM_D7
C9 A_MADR6 G8 M8 TS_MDO7 PCM_CE_N
A A_MADR[6]
F20 A_MADR7 AA_MDATA1 AA_MADR1 4 45
3V3_VCC 4k7 41 7
PCM_A10 A
A_MADR[7] G2 DQ1 A1 M3 NC4 NC26 R48 42 8
A_MADR[8] B8 A_MADR8 FLH_3.3V R50 4k7 43 9 PCM_OE_N
A_MADR[9] F19 A_MADR9 AA_MDATA2 DQ2 A2 AA_MADR2 5 NC5 I/O7 44 PCM_A7 PCM_IORD_N PCM_A11
D20 A_MADR10 H7 M7 5 R4 4 4k7
PCM_IOWR_N
44 10
PCM_A9
A_MADR[10] 4k7 45 11
C8 A_MADR11 AA_MDATA3 AA_MADR3 6 43 PCM_A6 TSMISYNC PCM_A8

R1496
A_MADR[11] DQ3 A3 NC6 I/O6 6 R3 R49 46 12

4k7
F21 A_MADR12 H3 N2 3 TS_MDI0 PCM_A13
A_MADR[12] 47 13 R1172
AA_MDATA4 DQ4 A4 AA_MADR4 F_RBZ 7 RB I/O5 42 PCM_A5 TS_MDI1 PCM_A14
C13 A_MDATA0 H1 N8 7 R2 2 TS_MDI2
48 14
PCM_WE_N
4k7 3V3_VCC
A_MDATA[0] R33 49 15 R1425
A_MDATA[1] A19 A_MDATA1 AA_MDATA5 DQ5 A5 AA_MADR5 PF_OEZ 33R 8 R I/O4 41 R1 PCM_A4 TS_MDI3 50 16 33R PCM_IRQA_N
A12 A_MDATA2 H9 N3 8 1
A_MDATA[2] 33R VCC_PCMCIA 51 17 VCC_PCMCIA
A_MDATA[3] B19 A_MDATA3 AA_MDATA6 DQ6 A6 AA_MADR6 NAND_CEz 9 E NC25 40 R1398 52 18
A20 A_MDATA4 F1 N7 TS_MDI4 TSMIVALID
A_MDATA[4] 53 19
A_MDATA[5] B12 A_MDATA5 AA_DDR2_DQS0 LQDS A7 AA_MADR7 10 NC7 NC24 39 C967 TS_MDI5 54 20 TSMICLK
C19 A_MDATA6 F7 P2 TS_MDI6 PCM_A12 C966 NC
A_MDATA[6] 55 21
A_MDATA[7] A13 A_MDATA7 AA_DDR2_DQSB0 LQDS_P A8 AA_MADR8 11 NC8 NC23 38 4p7 50V TS_MDI7 56 22 PCM_A7
B14 A_MDATA8 E8 P8 TSMOCLK PCM_A6
A_MDATA[8]
C18 A_MDATA9 AA_DDR2_DQM0 AA_MADR9 R1388
12
U162 37 PCM_RST
57 23
PCM_A5 12p
A_MDATA[9] F3 LDM A9 P3 33R FLH_3.3V VDD1 VDD2 FLH_3.3V R1171 58 24 50V
A_MDATA[10] C14 A_MDATA10 PF_AD15 8 R1 1 NAND_WPz NAND512-A 3V3_VCC 4k7 59 25 PCM_A4
A18 A_MDATA11 AA_MDATA7 AA_MADR10 PF_ALE 7 R2 2 NAND_ALE 13 36 PCM_A3
B A_MDATA[11]
B18 A_MDATA12 F9 DQ7 A10 M2 PF_CE1Z 6 R3 3 NAND_CLE
VSS1 VSS2
PCM_WAIT_N
R1427
PCM_REG_N
60 26
PCM_A2 B
A_MDATA[12] 33R 61 27
A_MDATA[13] B13 A_MDATA13 AA_MDATA8 DQ8 A11 AA_MADR11 PF_CE0Z 5 R4 4 NAND_CEz 14 NC9 NC22 35 TSMOVALID 62 28 PCM_A1
B17 A_MDATA14 C8 P7 TSMOSTART PCM_A0
A_MDATA[14] 63 29
A_MDATA15 AA_MDATA9 AA_MADR12 TS_MDO0 PCM_D0

HY5PS121621C
128 MEGABYTE
A_MDATA[15] C15 DQ9 A12 15 NC10 NC21 34 64 30
C2 R2 TS_MDO1 PCM_D1
65 31
A_DQS[0] A16 A_DDR2_DQS0 AA_MDATA10 DQ10 BA0 AA_BADR_BA0 NAND_CLE 16 CL NC20 33 TS_MDO2 66 32 PCM_D2

U155
C16 A_DDR2_DQSB0 D7 L2 PCM_CD2_N
A_DQSB[0] 67 33 4k7 VCC_PCMCIA
A_DQS[1] A15 A_DDR2_DQS1 AA_MDATA11 DQ11 BA1 AA_BADR_BA1 NAND_ALE 17 AL I/O3 32 PCM_A3
B15 A_DDR2_DQSB1 D3 L3 5 R4 4 R1642 68 34 R1177
A_DQSB[1] R34 3V3_VCC 10k
AA_MDATA12 AA_RASZ PF_WEZ PCM_A2

BSH103
DQ12 RAS_P 33R 18 W I/O2 31
D1 K7 6 R3 3

Q209
A_DQM[0] B16 A_DDR2_DQM0 R1495
A_DQM[1] C17 A_DDR2_DQM1 AA_MDATA13 DQ13 CAS_P AA_CASZ 3k9 19 WP I/O1 30 PCM_A1
D9 L7 FLH_3.3V 7 R2 2
5V_VCC VCC_PCMCIA
A_MCLK C12 A_MCLK AA_MDATA14 DQ14 WE_P AA_WEZ NAND_WPz 20 NC11 I/O0 29 R1 PCM_A0 C970
B1 K3 8 1 C654 C653
A_MCLKZ B11 A_MCLKZ 33R
2 2

22u
100n 100n
A_MCLKE C20 A_MCLKE AA_MDATA15 DQ15 CS_P 21 NC12 NC19 28 R1389 1

10V
1

10V 6V3
B9 L8

2
B20 A_WEZ AA_DDR2_DQS1 AA_MCLKE 22 27

10V

C1220
A_WEZ B7 UDQS CKE K2 NC13 NC18

100n
B10 A_RASZ
C A_RASZ
A10 A_CASZ AA_DDR2_DQSB1 AA_MCLK 23 26 C
A_CASZ A8 UDQS_P CK J8 NC14 NC17 R1951 R1950
A_BADR[0] C21 A_BADR_BA0 12V_VCC 4k7 10k
A_BADR[1] B21 A_BADR_BA1 AA_DDR2_DQM1 UDM CK_P AA_MCLKZ 24 NC15 NC16 25
B3 K8
A_BADR[2]
A_ODT
D19 A_BADR_BA2
C11 A_ODT
A2 NC1 ODT AA_ODT
K9 R1953
3
TS IN& OUT
P_D0 K21 PCMDATA[0]/CI_DATA[0] TS1DATA[0] P18 TS1_D0 CI_POWER_CTRL 4k7
2
Q208
MVREF F18 MVREF NC2 VSS1 P_D1 L19 PCMDATA[1]/CI_DATA[1] TS1DATA[1] R18 TS1_D1 BC848B TS1_D0 R4 TS_MDI0
E2 A3 P_D2 M19 T18 TS1_D2 TS1_D1 5 4 TS_MDI1
PCMDATA[2]/CI_DATA[2] TS1DATA[2] R3
1

AA_BADR_BA2 P_D3 T12 W19 TS1_D3 TS1_D2 6 3 TS_MDI2


L1 NC3 VSS2 E3 PCMDATA[3]/CI_DATA[3] TS1DATA[3] R2
7 2
P_D4 U13 PCMDATA[4]/CI_DATA[4] TS1DATA[4] Y21 TS1_D4 TS1_D3 R1 TS_MDI3
P_D5 V14 Y19 TS1_D5 8 1
R1367 R3 NC4 VSS3 J3 PCMDATA[5]/CI_DATA[5] TS1DATA[5] 33R
A_MDATA14 1 R1 8 AA_MDATA14 P_IOWR_N R4 PCM_IOWR_N P_D6 V12 PCMDATA[6]/CI_DATA[6] TS1DATA[6] R21 TS1_D6 R1383
A_MDATA9 2 R2 7 AA_MDATA9 NC5 VSS4 P_IORD_N5 R3
4 PCM_IORD_N P_D7 V18 PCMDATA[7]/CI_DATA[7] TS1DATA[7] T21 TS1_D7 TS1_D4 R4 TS_MDI4
A_MDATA12 3 6 AA_MDATA12 R7 N1 P_A13 6 3 PCM_A13 Y20 TS1_CLK TS1_D5 5 R3 4 TS_MDI5
R3 R2 TS1CLK
A_MDATA11 4 R4 5 AA_MDATA11 NC6 VSS5 P_WE_N 7 2 PCM_WE_N P_A0 R19 W20 TS1_VALID TS1_D6 6 R2 3 TS_MDI6
R8 P9 8 R1 1 P_A1 P19
PCMADR[0]/CI_A[0] TS1VALID
R16 TS1_SYNC TS1_D7 7 R1 2 TS_MDI7
22R 33R PCMADR[1]/CI_A[1] TS1SYNC C969
VSSQ10

P_A2 N21 8 1
VSSQ9

VSSQ8

VSSQ7

VSSQ6

VSSQ5

VSSQ4

VSSQ3

VSSQ2

VSSQ1
R1385
VSSDL

R1369 PCMADR[2]/CI_A[2] 12p 33R


VREF

A_MDATA5 1 R1 8 AA_MDATA5 P_WAIT_N PCM_WAIT_N P_A3 N19 50V NC R1382


A_MDATA2 2 R2 7 AA_MDATA2 P_CE_N 5 R4 4 PCM_CE_N P_A4 V20
PCMADR[3]/CI_A[3]
D A_MDATA0 3 R3 6 AA_MDATA0 P_OE_N 6 R3 3 PCM_OE_N P_A5 U20
PCMADR[4]/CI_A[4]
TS1_CLK
R1512
TSMICLK D
7 R2 PCMADR[5]/CI_A[5] 33R
H8

H2

D8

D2

A7
B8

B2
F8

F2

E7
J2

J7

A_MDATA7 4 R4 5 AA_MDATA7 P_IRQA_N 2 PCM_IRQA_N P_A6 T20


DDR18V 1k 8 R1 1 P_A7 T19
PCMADR[6]/CI_A[6]
K20 TS0_D0 TS1_VALID
R1514
TSMIVALID
22R R1364 33R PCMADR[7]/CI_A[7] TS0DATA[0] 33R
R1610 R1399 P_A8 P17 PCMADR[8]/CI_A[8] TS0DATA[1] L20 TS0_D1 R1513
A_MDATA6 1 R1 8 AA_MDATA6 P_A9 N18 PCMADR[9]/CI_A[9] TS0DATA[2] M20 TS0_D2 TS1_SYNC 33R TSMISYNC
A_MDATA1 2 R2 7 AA_MDATA1 C687 P_A10 U17 PCMADR[10]/CI_A[10] TS0DATA[3] T13 TS0_D3
A_MDATA3 3 R3 6 AA_MDATA3 P_A11 V16 U14 TS0_D4
R1355

220n PCMADR[11]/CI_A[11] TS0DATA[4]


1k

A_MDATA4 4 R4 5 AA_MDATA4 10V DDR18V P_A12 R20 PCMADR[12]/CI_A[12] TS0DATA[5] U12 TS0_D5 TS0_D2 R4 TS_MDO2
P_A13 R17 T11 TS0_D6 TS0_D1 4 5 TS_MDO1
22R C718 C715 C714 C716 C711 C713 C1214 R1393 PCMADR[13]/CI_A[13] TS0DATA[6] 3 R3 6
R1366 220n 220n 220n 220n 220n 220n 220n 33R P_A14 T16 PCMADR[14]/CI_A[14] TS0DATA[7] U18 TS0_D7 TS0_D0 R2 TS_MDO0
A_MDATA13 AA_MDATA13 2 7
1 R1 8 10V 10V 10V 10V 10V 10V 10V P_D1 5 R4 4
PCM_D1 P_RESET V19 CI_RST TS0CLK U19 TS0_CLK TS0_D3
1 R1 8
TS_MDO3
A_MDATA10 2 R2 7 AA_MDATA10 P_D0 R3 PCM_D0 TS0VALID P20 TS0_VALID C968 33R
A_MDATA8 3 R3 6 AA_MDATA8 P_D2 6 3 PCM_D2 P_IRQA_N W21 K19 TS0_SYNC
R2 PCM_IRQ/CI_INT TS0SYNC 12p R1384
A_MDATA15 4 R4 5 AA_MDATA15 P_A0 7 2 PCM_A0 P_OE_N TS0_D4 TS_MDO4
F181 R1 U16 PCMOEN 50V 30022165 KULLANILDI
8 1 P_IORD_N V17 2 TS0_D5 5 R4 4 TS_MDO5
22R DDR18V PCMIOR/CI_RD
1V8_VCC
P_D5 PCM_D5 P_CE_N TS0_D6 6 R3 3 TS_MDO6
A_MADR11
R1609
1 R1 8 AA_MADR11 A_ODT
R1603
AA_ODT
60R
2
C712 2
C709 2
C710 C782
P_D6 5 R4 4 PCM_D6 P_WE_N
T17
V21
PCMCEN/CI_CS U5 10V
TS0_D7 7 R2 2 TS_MDO7
22R 22u R3 PCMWEN 100n 8 R1
A_MADR8 2 R2 7 AA_MADR8 1
100n
10V
1
100n
10V
1
100n
10V 6V3 P_D7 6
7 R2
3
2
PCM_D7 PCM_CD2_N T14 CI_CD MSD9WB9PT-2 R6 C906 33R
1
A_MADR6 3 R3 6 AA_MADR6 P_A6 PCM_A6 P_WAIT_N M21
E A_MADR4 4 R4 5 AA_MADR4 A_WEZ 1
R1613
8 AA_WEZ 8 R1 1 P_IOWR_N P16
PCMWAIT/CI_WACK
W1
100R DIGITAL_IF_P R1390
E
R1 33R 3V3_VCC PCMIOW/CI_WR IP R1402
A_MCLKE 2 7 AA_MCLKE P_REG_N N20 Y1 TS0_VALID TSMOVALID

R1977
R1397

180R
22R R2 PCMREG/CI_CLK IM 33R
A_BADR_BA1 3 6 AA_BADR_BA1 P_A1 PCM_A1

R1660
R3 AVDD_DDR 1k R4 R1401

4k7
A_BADR_BA0 4 5 AA_BADR_BA0 P_D3 5 4 PCM_D3 TS0_SYNC TSMOSTART
R4 R1365 R3 100R DIGITAL_IF_N 33R
MVREF P_D4 6 3 PCM_D4 OVER_CUR_DETECT G21
22R R2 GPIO125 R5 C905 R1424

1
P_A4 7 2 PCM_A4 G20 TS0_CLK TSMOCLK
R1 HDMI0_5V 18k R1607 GPIO128 100n 33R

3V3_VCC
8 1 G19
R1332 C683 33R HDMI1_5V 18k GPIO127 330R 10V
A_DDR2_DQM1 AA_DDR2_DQM1 AA2
R1356

R1380 22R 220n R1395 R1606 VIFP 3V3_TUNER


1k

A_BADR_BA2 1 R1 8 AA_BADR_BA2 R1313 10V P_A2 R4 PCM_A2 VIFM Y2


2

F8
1

A_MADR1 2 R2 7 AA_MADR1 A_DDR2_DQM0 AA_DDR2_DQM0 P_REG_N 5 R3 4 PCM_REG_N

R1605

R1604

C913
22R

16V
33k

33k

100n
A_MADR10 3 R3 6 AA_MADR10 P_A3 6 3 PCM_A3 Y3 1k
R2 SIFP

R12
4k7
A_MADR5 4 R4 5 AA_MADR5 P_RESET 7 R1 2 PCM_RST AA3

R1662
SIFM

1k2
8 1
22R R1982 33R IF_AGC_MST R344
A_MCLKZ AA_MCLKZ PF_ALE S81
R1370 22R R1392 U10 PF_ALE/GPIO135 IF_AGC W5 4k7 9k1 1k2 BACKLIGHT_ON/OFF
A_MADR3 1 R1 8 AA_MADR3 A_MCLK 22R AA_MCLK P_A14 PCM_A14 PF_AD15 T9 W4 NC
A_MADR9 2 R2 7 AA_MADR9 P_A10 5 R4 4 PCM_A10 PF_CE0Z
PF_AD[15]/GPIO130 RF_AGC 4k7 R1971
V11 R10 0R
3

R1983 6 R3 3 PF_CE0Z/GPIO131 R1661


A_MADR7 3 R3 6 AA_MADR7 P_A9 PCM_A9 PF_CE1Z U11 AA4 Q181
7 R2 PF_CE1Z/GPIO132 GPIO66
2

4k7
1 2

A_MADR12 4 R4 5 AA_MADR12 P_A5 2 PCM_A5 PF_OEZ U9 Y4 BC848B


8 R1 1 PF_WEZ T10
PF_OEZ/GPIO133 GPIO67
W6
PANEL_VCC_ON/OFF
F 22R R1984 33R PF_WEZ/GPIO134 GPIO68 TUN_SCL_MST F
1

R1368 A_DDR2_DQSB1 22R AA_DDR2_DQSB1 R1394 F_RBZ 33R V9 F_RBZ/GPIO136 GPIO69 Y5 TUN_SDA_MST
A_MADR2 1 R1 8 AA_MADR2 A_DDR2_DQS1 22R AA_DDR2_DQS1 P_A7 PCM_A7
A_MADR0 2 R2 7 AA_MADR0 P_A8 5 R4 4 PCM_A8
R1942

1
R1985 6 R3 3
A_CASZ 3 R3 6 AA_CASZ P_A11 PCM_A11

R1618

R1663
7 R2

4k7

4k7

4k7

4k7
R8

R9
A_RASZ 4 R4 5 AA_RASZ
A_DDR2_DQSB0
R1987
AA_DDR2_DQSB0
P_A12
8 R1
2
1
PCM_A12 PROJECT NAME : 17mb62-1 A3
22R 22R 33R

2
A_DDR2_DQS0 AA_DDR2_DQS0
22R R1396 3V3_VCC SCH NAME : RAM&NAND&CI SHEET: OF: 8
R1986
DRAWN BY : Ulas Dereli 14-03-2011_17:06
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
HDMI2 CN708
21
R1877 20
AUDIO OUTPUTs HDMI_0_RX2P 2
10R
1

R1869
1
2
R1900 HDMI_0_RX2N 2
10R
1
3

OPTIONAL
MAIN_L 100R DSP_MAIN_L C1197 HDMI_0_RX1P 10R 4

HDMI1_5V
2
1

SCART_AUDIO_IN_L C1198 10u 10V N5 AUL0 RXA0N E2 HDMI_1_RX0N R1868 R1887 5


L4 F3
A SCART_AUDIO_IN_R 10u 10V AUR0 RXA0P HDMI_1_RX0P HDMI_0_RX1N 10R
2 1
6 A

R1899

C1183
220k
R5 F2

50V
SAV_AUDIO_IN_L 10u 10V AUL1 RXA1N HDMI_1_RX1N HDMI_0_RX0P 10R 7

4n7
1
2

SAV_AUDIO_IN_R 10u 10V C1196 T6 AUR1 RXA1P G3 HDMI_1_RX1P R1867 R1886 8


C1195 P6 AUL2 RXA2N G2 HDMI_1_RX2N HDMI_0_RX0N 9
R1909 10R
2 1

R1897 P5 AUR2 RXA2P G1 HDMI_1_RX2P HDMI_0_CLKP 10R 10


1k
2 1
2
1

T4 E3

2
MAIN_R 100R DSP_MAIN_R AUL3 RXACKN HDMI_1_CLKN R1879 R1880 11

R1896
T5 E1

4k7
AUR3 RXACKP HDMI_1_CLKP HDMI1_HPD HDMI_0_CLKN 10R
2 1
12

C1184
H5

50V
DDCDA_CK HDMI_1_SCL CEC 13

4n7
R1898
220k
3

DSP_MAIN_L N6 AUOUTL0 DDCDA_DA H6 HDMI_1_SDA 14


R1912 R1888

1
DSP_MAIN_R R6 AUOUTR0 HOTPLUGA J6 2
Q204 15
1k HDMI_0_SCL 10R
2 1 2 1

DSP_SCART_L W9 AUOUTL1 BC848B 10R 16


HDMI_0_SDA

HDMI0_5V
2
1

DSP_SCART_R AA9 AUOUTR1 RXB0N B2 HDMI_0_RX0N


1
R1885 17
DSP_HP_L Y7 EAR_OUTL RXB0P B1 HDMI_0_RX0P 18
HDMI0_5V
C1168 L119 DSP_HP_R AA7 EAR_OUTR RXB1N C2 HDMI_0_RX1N 10R 19
HDMI0_HPD 2 1

RXB1P C1 HDMI_0_RX1P R1878


HP_L DSP_HP_L
2 1

4u7 U5 D2

2
RXB2N HDMI_0_RX2N R1910

R1864

R1865
100u D1

47k

47k
16V MSD9WB9PT-2 RXB2P HDMI_0_RX2P 2
1k
1

R1858
220R
U5 A2

2
AUVRP RXBCKN HDMI_0_CLKN

R1895
U6 3 C3

4k7
16V 10V 1u AUVAG RXBCKP HDMI_0_CLKP HDMI0_HPD

1
U4 J5
B C1170 100n C117410u C1199 C1201 C1200 AUVRM DDCDB_CK
K4
HDMI_0_SCL
HDMI_0_SDA
3
B
10u 6V3 4u7 DDCDB_DA

1
R1911

HDMI1 CN707
10V 10V HOTPLUGB K5 2
Q203
1k
2 1

BC848B 21
RESET_TUNER MODE SELECTION D4 I2S_OUT_MCK
1
20
R1874
C1169 L120 DVD_IR_ON/OFF MODE SELECTION D6 I2S_OUT_SD HDMI_1_RX2P 1
10R
1

ANT_CTRL F4 I2S_OUT_WS 2
HP_R DSP_HP_R R1917 R76 R1870
2 1

4u7 STBY_INFO MODE SELECTION F5 I2S_OUT_BCK CEC H4 12V_VCC HDMI_1_RX2N 3


10R 1k 10R
2 1 2 1 2 1

100u 3
16V HDMI_1_RX1P 10R 4
R1859
220R

E4 I2S_IN_BCK U9 VCC R1884 R1871 5


AMP_MUTE LM809 RST GND
C4 I2S_IN_SD C1 HDMI_1_RX1N 6
PROTECT 10R
2 1

D3 2 1

1
RESET_S2 I2S_IN_WS HDMI_1_RX0P 10R 7

COMMON
2

R74
10R

6V3

R75
10R
C1171 R1872 R1882 8

1u
10u HDMI_1_RX0N 10R
2 1
9
NC

1
10V HDMI_1_CLKP 10R 10

2
R1601

R1838

R1839

R1840

R1892

R1836

R1656

R1614
1

P4

4k7

10k

10k

10k

4k7
R17
4k7

10k

4k7

4k7
SPDIFO R1876 R1883 11
R223 HDMI_1_CLKN 10R
2 1
12

3V3_STBY
SC_L_OUT 2 1
CEC 13

2
100R DSP_SCART_L
2

SPDIF_OUT R1873 14
R1924

C1185
22k

50V
100p

C HDMI_1_SCL
2
10R
1
15 C

3V3_STBY

3V3_STBY

3V3_VCC

3V3_VCC

3V3_STBY

3V3_STBY
HDMI_1_SDA 2 10R 1 16
R1875 17
1

R222 HDMI1_5V 18
SC_R_OUT
2
100R
1
DSP_SCART_R HDMI1_HPD 2 10R 1 19

PRE-AMP for SCART AUDIO


2

R1881
R1925

C1186

2
22k

100p
50V

R1863

R1862
47k

47k
1

R1916

1
V+ 220k 12V_VCC
C1182

R1915
220k
10u
10V

C1177 F301
2 1
12V_VCC
D AUDIO INPUTs SC_AUD_R_OUT
C1181

C1206
100n
16V
600R
R1913
C1180
D
R1914 33k
1 2

10u PL1
10V
2
33k
1
SC_AUD_L_OUT
R1902 C1205
47p 10u
SC_AUD_R_IN 10k SCART_AUDIO_IN_R 50V 10V
R1927 47p PL2
1 OUT1 VDD 8
82k
1 2
50V
R1921

C1187

C1203
12k

470p
50V

R1929 U178 R1926


2 IN1- OUT2 7
SC_R_OUT 20k 82k
1 2 1 2

TL062 R1928 C1202


1u PL3
V+ 3 IN1+ IN2- 6 20k SC_L_OUT
1 2
6V3
4 VSS 1u
R1901 IN2+ 5 V+ 6V3
SC_AUD_L_IN 10k SCART_AUDIO_IN_L PL4
R1920

C1188
12k

470p
50V

E E
COAX SPDIF OUT
R1903
SAV_R_IN 10k SAV_AUDIO_IN_R F5
2 1
5V_VCC
600R
R1918

C1189

2
12k

470p
50V

C15

100n
16V
R1889
4k7

50V
220p NC
3

C1175
1

R1907
TP251

1 2
Q202 2 1
100R
2
SPDIF_OUT
BC848B
1 2

R1904 C1179
C1178

100n
2

1
50V
220p

SAV_L_IN 10k SAV_AUDIO_IN_L


1

10V
R1890
4k7

C1176
2
1

2 NC
R1919

C1190

S92
1 2 1 2
3
12k

470p
50V

JK10 100n
1
2
2

10V
R1908
C5V6

D199

F F
1k

NC
1

PROJECT NAME : 17mb62S A3


SCH NAME :AUDIO_IO&HDMI_INPUTs 8
T. SHT:
DRAWN BY :Ulas Dereli 26-10-2011_15:43
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8

AUDIO AMP for 16" to 24" POP NOISE CIRCUIT

VDD_AUDIO
S87 NC
12V_VCC 1 2

A U163 PT2333
5V_VCC 1
S86 2
A

GNDA

OUTN

VDDA

VDD1

GNDB

OUTP
INP

INN

SDB

1
1N4148

D191
MAIN_L Q160

R1941
BC848B 16V

VDD_AUDIO

3V3_STBY

3V3_VCC
A1

A2

A3

B1

B2

B3

C1

C2

C3

1k
10u

2
C612 R623
4k7
220n L_AUDIO_P_OUT C1032

AMP_EN
10V

R1699
R817
100R

47k
C665 2
L_AUDIO_N_OUT 100n
NC NC

2
1
10V

R1712

R1309
R616
15k

10k

10k
R624
1

4k7
Q195
BC858B

1
2

VDD_AUDIO AMP_EN BC848B

2
NC C1058 Q186
3

R1711

R1701
C617

100k
3

10V

3k9
220n
100n R1702
B 16V 2 2
10k
1

B
VDD_AUDIO

1
3

2
1

R1684

R1718
BC848B

100k
AMP_MUTE 1
10k
2 2

Q185
1

1
U164 PT2333
GNDA

OUTN

VDDA

VDD1

GNDB

OUTP
INP

INN

SDB
3

BC848B
MAIN_R
2

Q133
A1

A2

A3

B1

B2

B3

C1

C2

C3
1
C602 R613
4k7
220n R_AUDIO_P_OUT

AMP_EN
10V
C666
R818
100R

R614
4k7

2
R_AUDIO_N_OUT 10V
1

100n
C C
C608
10V
220n

VDD_AUDIO

CN710 30001734 KULLANILDI


1 F283
12V_VCC
R_AUDIO_P 2 60R
F285NC D19230049510 KULLANILDI
R_AUDIO_N 3 VDD_AUDIO_PWR
60R SK24
L_AUDIO_P 4 F294
5V_VCC VDD_AUDIO
L_AUDIO_N 5 60R
10V 10V
D 6 220u
C870
220u D
C615

Ü.A. DEGISTIRILECEK

AUDIO AMP for 26" to 32"


SLIM HEADPHONE OUTPUT
L124

10u
AMP_EN

F282 F296
VDD_AUDIO 1
L_AUDIO_P
60R L_AUDIO_P_OUT 60R TP230 1
TP51 1
C1121

C942
2
16V

50V
10u

HP_L

1n
C1226
1 SD PVCCL2 28
6

25V
1u
30022132 KULLANILDI S85 2 27
FAULT PVCCL1 TP229 1

100k 30050557 KULLANILDI


C1077 C1045 3
1u 220n HP_R
3 26
E R1715 MAIN_L 6V3
LINP BSPL
25V
L125 C1172 C729
4 E

2
30050557 KULLANILDI
VDD_AUDIO 100k 10n 10n

R1854

R1855
C1075 1u 4 25 10u

10k

10k
R1714 LINN OUTPL 16V 16V
NC 6V3 5 JK6
CONNECT TO DSP_M_L GND F299
NC100k 5 GAIN0 PGND1 24 L_AUDIO_N_OUT L_AUDIO_N

1
R1717 60R 7

C943
C1123 6 23

50V
VDD_AUDIO 10k GAIN1 OUTNL R1704

1n
C1227

R1716 100R U168 C1046


2N7002
680R HP_MUTE 1 TP52
1 8 7 22
25V

ANALOG VCC AVCC BSNL


R1 25V
1u

1u Q192
50V
8
TPA3110D2 220n
21 C1044
R_AUDIO_N_OUT F298 HP_DETECT 4k7 1 3V3_VCC
2 R2 7 AGND BSNR R1149
R_AUDIO_N
C1074 25V 60R
VDD_AUDIO 220n
1u
C944

D203

C5V6
3 R3 6 9 20
50V
GVDD OUTNR L126 3V6 lik zener kullanilmali
1n
C1228

25V
R1687 R1696
4 R4 5 10 19 10u
25V

10k 10k PLIMIT PGND2


1u

R1741 30050557 KULLANILDI


1u R_AUDIO_P_OUT R1960
C1073 C1076 11 RINN OUTPR 18 680R
1u L127 2N7002
6V3 Q210
25V 30050557 KULLANILDI
12 17 C1043220n
RINP BSPR
25V 10u
F 6V3
13 16 F
MAIN_R 1u NC PVCCR1 F297
C1078 F281 R_AUDIO_P
14 PBTL PVCCR2 15 VDD_AUDIO 60R
CONNECT TO DSP_M_R GND
C945

60R
50V
1n

17mb62S
C1122

C1229

PROJECT NAME : A3
16V
10u

25V
1u

SCH NAME :AUDIO_AMP&HP_AMP 8


T. SHT:
DRAWN BY :Ulas Dereli 26-10-2011_15:43
1 2 3 4 5 6 7 8 AX M
1 2 3 4 5 6 7 8
10k
R1835
10k
R1833 TX_B_0_N 30
PCM_CD1_N
J21 PWM0 LVB0P AA19 TX_B_0_P
15.6" LVDS OPTION TP34
TX_B_0_P
1

29

TP14
R1615
3V3_VCC
BACKLIGHT_DIM
2
4k7
1 J20
J19
PWM1
PWM2
LVB0M
LVB1P
AA20
AA18
TX_B_0_N
TX_B_1_P 3V3_STBY
SERIAL FLASH D165
CN3 TP33
TX_B_1_N
1

28
W18
A 3V3_STBY LVB1M TX_B_1_N 3V3_STBY TX_A_0_N 1 2 PANEL_VCC TP32 A

1
1

W17

2
LVB2P TX_B_2_P TX_B_1_P 27

TP15
TP40
TP11
C658 1N5819

R1528

R1357

R1358
Y18

4k7

4k7
4k7
2

LVB2M TX_B_2_N 100n TX_A_0_P 3 4 TP31

R1183
U158
1

W16

4k7
TX_B_CLK_P TX_B_2_N
1

LVBCKP 10V 26
KEYBOARD B4 SAR0 LVBCKM Y17 TX_B_CLK_N MX25L512 5 6 TP30

TP12
1
R1967

1
1

DVD_SENSE C5 SAR1 LVB3P AA16 TX_B_3_P SPI_CSN_1 1 CS# VCC 8 TX_B_2_P 25


100R
1 2

19" TO 22" DOUBLE LVDS FFC OPTIONS


V3 SAR2 LVB3M Y16 TX_B_3_N SPI_SDO 2 7 TX_A_1_N
SC_PIN8 100RR1968 SO HOLD# R1248 7 8 TP29
1 2
1

R1 LVB4P AA15 TX_B_4_P 1 2 3 WP# SCLK 6 1 2


24
FLASH_WPN 100R R1970100R SPI_SCK

1
3V3_STBY 4k7 LVB4M W15 TX_B_4_N R1969 4 GND SI 5 TX_A_1_P 9 10
100R SPI_SDI_1
1 2

1
2 1

NC TX_B_CLK_N 23
DVD_WAKEUP B6 GPIO12 LVA0P W14 TX_A_0_P 11 12 DIMMING TP28

TP41
1

C7 SCZ LVA0M Y15 TX_A_0_N R73 TX_B_CLK_P 22


SPI_CSN_1
B5 SCK LVA1P W13 TX_A_1_P TX_A_2_N 13 14 33k TP27
SPI_SCK PANEL_VCC 1

C6 SDI LVA1M Y14 TX_A_1_N R2 TX_B_3_N 21


SPI_SDI_1
A6 SDO LVA2P AA13 TX_A_2_P TX_A_2_P 15 16 33k BACKLIGHT_ON/OFF TP26
SPI_SDO 1

A7 GPIO14 LVA2M Y13 TX_A_2_N TX_B_3_P 20


FLASH_WPN
LVACKP AA12 TX_A_CLK_P TX_A_CLK_N 17 18 12V_VCC TP25 1

LVACKM W12 TX_A_CLK_N TX_A_0_N 19


3V3_VCC LVA3P W11 TX_A_3_P TX_A_CLK_P 19 20 TP24 1

K6 Y12
B RX/SCL_SC
M6
DDCA_CK/UART0_RX LVA3M
W10
TX_A_3_N KEYBOARD_ONBOARD C630 TX_A_0_P 18 B
1

2
TX/SDA_SC DDCA_DA/UART0_TX LVA4P TX_A_4_P 100n TP23
R1524

R1527

Y11
4k7

4k7

TX_A_4_N
1
LVA4M R793 F248 10V 17
U5 1
47R
2 1 2

KEYBOARD
MSD9WB9PT-2 R1959 TOUCH_PAD_OPTION F249 600R TX_A_1_N 16
2

H19 S76
SCL_SYS DDCR_CK 4 1
4k7
2
3V3_STBY 1 2
3V3_STBY TP22 1

SDA_SYS H20 DDCR_DA GPIO137 Y9 600R TX_A_1_P 15


HP_MUTE
SPDIFI/GPIO139 W7 TP21
DVD_SPDIF R1937 1

GPIO141 AA10 100R HP_DETECT MECH_SWITCH 14


47R SCL_SYS
1 2
C952

Y10
50V

GPIO143 R1954 CI_POWER_CTRL


33p

R1543 R1936
IR_IN A4 IRIN R1952 TX_A_2_N 13
100R 47R SDA_SYS
1 2 1 2

1
4k7 2
3V3_VCC TP20

CN709
1

TX_A_2_P 12

6
TP19
R1533

Y6 XIN GPIO10 B7 STBY_ON/OFF_NOT TX_A_CLK_N 11


1M

24MHz

AA6 E6
XOUT GPIO11
EXT KEYPAD TP18
X2

LED1 1

GPIO7 F6 TX_A_CLK_P 10
S38 LED2
TP17 1

1
TX_A_3_N 9
R1617

R1672

R1671
C951

E5
50V

4k7

4k7

4k7
C RESET 100R HWRESET TP16 C
33p

SINGLE LVDS FFC OPTIONS


2 1 1

R1666 TX_A_3_P 8
C1215

16V

TP9
10n

2
1

7
B3
3V3_STBY

3V3_STBY

USB0_DP 3V3_STBY S15

PANEL_VCC = 5V/12V
A3

PANEL_VCC
USB0_DM 6
2 1

OP_PIN11

OP_PIN27

OP_PIN42

OP_PIN43
TX_A_CLK_P

TX_A_CLK_N
W8

OP_PIN8

OP_PIN9
USB_DP USB1_DP

TX_A_3_P

TX_A_3_N

TX_A_2_P

TX_A_2_N

TX_A_1_P

TX_A_1_N

TX_A_0_P

TX_A_0_N
Y8 USB1_DM 5
USB_DM
J9

2
GND0
H9

S14

S13
GND1 OP_PIN9 4

S3
PANEL_VCC 3

PANEL_VCC
ONBOARD KEYBOARD 1

LED SOCKET TP8 2

CN138
TP10
1

10

11