Experiment No.

6
Date: 7/9/19

ADDRESSING MODES AND SEQUENCE GENERATION

AIM:
a) To learn the following addressing modes of TMS320C54X DSP.
i) immediate
ii) direct addressing
iii) indirect addressing: general type, indexing, circular addressing
iv) memory mapped register addressing
b) To learn various arithmetic and logical instructions supported by various addressing modes.
c) To generate and find the sum of the following arithmetic sequences.
i) 1+2+3+4+ …+ n
ii) 1-2+3-4+ …+ n
2 2 2 2
iii) 1 +2 +3 +…+ n
iv) 1+1+2+3+5+8 …+ n (Fibonacci series) or any sequence
The value of n is to be defined as variable assignment in the program To understand the branch
instructions suitable to define loop functions
THEORY:
a) ADDRESSING MODES:
i) Immediate:
The only addressing mode where the operand is available in Program memory (PM). The
operand is stored along with opcode in PM.
The syntax for immediate addressing mode is the symbol # followed by the operand
ADD #10h,A (opcode src,dst)
If the operand size is 7-bits or less than 7-bits the IW is one word. Then the mode is
called Short immediate addressing.
SUB #1200h,B
If the operand size is greater than 7-bits the IW is two word. One word is opcode and
the next word is operand. Then the mode is called Long immediate addressing.
ii) Direct:
Direct addressing mode is based on paging concept.
It can use either DP (Data Page Pointer) or SP (Stack Pointer).
If DP is used, the data memory address 16-bits (dma) is obtained by concatenating 7
LSBs of opcode with 9 MSBs of DP.
Syntax:
LD #10h,DP
ADD 20h,A
If SP is used, the data memory address 16-bits (dma) is obtained by adding the 7 LSB bits
as postive offset to (SP) stack pointer value.
Syntax:
LD #1000h,SP
ADD 20h,A
iii) Indirect:
In Indirect addressing mode, the address of the operand is stored in a register. Auxiliary
registers (ARs) are used to point the address of the operand.
 For Indirect addressing mode * symbol is used after the opcode in `C54X.
Syntax:
LD #1200h,AR2
ADD *AR2,A
→ General Indirect Addressing Mode:
Using the current content of ARn for data memory address (dma) and if the
address displacement is ± 1 dma locations then it is general Indirect
addressing mode.
Post increment: ADD *AR2+, A
Access the data using the content of AR2 as dma. After the access of current
AR2 content, AR2 is incremented by one by the ARAU.
Pre increment: ADD *+AR2, A
Access the data using the incremented content of AR2 as
dma Post decrement: ADD *AR2-, A
Access the data using the content of AR2 as dma. After the access of current
AR2 content, AR2 is decremented by one by the ARAU.
Pre decrement: ADD *-AR2, A
Access the data using the decremented content of AR2 as dma
→ Indexed Addressing Mode
Using the current content of ARn for data memory address (dma). If the address
displacement is > ± 1 dma locations then Indexed addressing mode is used. The
content of index register is used for specifying the displacement value. If a
separate index register is not available then AR0 reg. is used for indexing.
Syntax:
LD #1200h,AR2
LD #10h, Indx/AR0
ADD *AR2+0,A –
After the access of current AR2 content, AR2 is incremented by the value in index
register by ARAU
ADD *AR2-0,A
After the access of current AR2 content, AR2 is decremented by the value in
index register by ARAU
→ Circular Addressing Mode
To access the data memory locations in a circular way many times without any
instruction overhead.
Syntax:
LD # 0Fh, BK
LD #1020h,AR2
LD #10, AR3
loop ADD *AR2+%,A
ADD *AR2+%, A
Repeat the above instruction 13 times
ADD *AR2+%, A
BANZ *AR3-, loop
→
% Activates Hardware for Circular Addressing
Different Methods to Access Memory Mapped Registers:
1) Immediate Addressing:
LD #20h, BK
 2) Direct Addressing:
LD #20h, A
LD #0, DP
STL A, BK
3) Indirect Addressing:
LD #10h, AR2
LD #20h, A
STL A, +ar2
MEMORY MAPPED REGISTER ADDRESSING MODE:
Memory-mapped register addressing is used to modify the memory-mapped registers without
affecting either the current data-page pointer (DP) value or the current stack-pointer (SP)
value. Because DP and SP do not need to be modified in this mode, the overhead for writing to
a register is minimal.
Forcing the nine most significant bits (MSBs) of data-memory address to 0, regardless of the
current value of DP or SP when direct addressing is used.
Using the seven LSBs of the current auxiliary register value when indirect addressing is used.
STLM src, MMR
LDM MMR, dst
MVDM dmad, MMR
MVMD MMR, dmad
MVMM MMRx, MMRy
POPM MMR
PSHM MMR
STM #lk, MMR
b) SEQUENCE GENERATION
i) 1+2+3+4+…+n
Start Read n
Sum = 0 i=1
for i=1: n

Begin
Store i in memory
Sum=Sum+i
Increment i by 1
End
Store Sum in memory followed by sequence
Stop

ii) 1-2+3-4+…+n
Start
Read n
Sum = 0, Sum1 = 0, Sum2 =0, i=1
for i=1: n
Begin
Store i in
memory If i is odd
Sum1=Sum1+i
Else
 Sum2=Sum2+i
Increment i by 1
Sum = Sum1+negative of (Sum2)
End
Store Sum in memory
Stop
2 2 2 2
iii) 1 +2 +3 +…+n
Start
Read n
Sum = 0, i=1 to n,
a=0 for i=1:n
Begin
Store i in the memory
a=i*i
Store a in memory
Sum=Sum+a
End
Store Sum in the memory
End
iv) 1+1+2+3+5+8+…+n
Start
Read n
a=0, b=1
Store a and b in the memory
for i=1: n-2
Begin
c=a
a=a+b
b=c
Store a in the memory
End
Stop
PROCEDURE:

 Write C54X assembly language code for the following addressing modes to perform all
 arithmetic and logical operations:
o immediate addressing mode (both one word and two word)
o direct addressing mode
o indirect addressing mode (general, index, circular)
 Write the C54X assembly instructions to access memory mapped registers using following
 addressing modes
o immediate
o direct
o indirect
o mmregs addressing mode
 Generate the following sequence values, store them in memory and find the sum of the sequence
 and store it in the last location after the sequence
  ◦ 1+2+3+4+ …+ n
◦ 1-2+3-4+ …+ n 
2 2 2
◦ 1 +2 +3 +…+
2
n 
 ◦ 1+1+2+3+5+8 …+ n (Fibonacci series)
PROGRAM CODES AND INFERENCES:
IMMEDIATE ADDRESSING
.mmregs
.text
ld #10h,a
ld #20h,b
add #10h,a
sub #10h,b
stl a,T
mpy #10h,b
mac #20h,a
and #0h,a
.end
Before Execution After Execution
PC 0x00004000 0x00004011
A 0x00000000 0x00000000
B 0x00000000 0x00000300
T 0x0000 0x0030

DIRECT ADDRESSING
.mmregs
.text
stl a,10h
stl b,20h
ld #0, dp
ld 10h,a
ld 20h,b
ld a,b
add 10h,a
ld 20h,b
ld a,b
add 10h,a
sub 10h,b
stl a,T
mpy 010h,b
mac 04h,b
and 0h,b
ld #100h,a
stl a,sp
ld 20h,2,a
ld #2h,dp
stl b,21h
stl a,22h
nop
.end

Before Execution After Execution

PC 0x00004000 0x00004023
A 0x00000010 0x00000080
B 0x00000020 0x00000000
ST0 0x00000000 0x00000010
T 0x0000 0x0030
[10h] 0x0000 0x0010
[20h] 0x0000 0x0020
[1020h] 0x0000 0x0020
[010h] 0x0010 0x0010
[04h] 0x0010 0x0010
 [0121h] 0x0000 0x0000
[0122h] 0x0000 0x0080
[0000h] 0x0000 0x0000
INDIRECT ADDRESSING
.mmregs
.text
ld #10h,a
ld #20h,b
stl a,ar2
stl b,ar3
add *ar2,a
sub *ar2,b
add *ar2+,a
add *ar3-,b
stm #10h,T
mpy *ar3+,a
ld #3h,a
stl a,ar0
add *ar3+0,b
ld #0h,b
ld #5h,a
stl a,bk
stl a,ar5
ld #120h,a
stl b,ar0
stl a,ar4
loop:
add *ar4+0%,a
banz loop,*ar5-
.end
Before Execution After Execution
PC 0x00004000 0x00004018
A 0x00000000 0xFFFFFFFF
B 0x00000000 0x00000000
T 0x0000 0x0010
AR0 0x0000 0x0000
AR1 0x0000 0x007F
AR2 0x0000 0x9817
AR3 0x0000 0x0120
AR4 0x0000 0x0000
AR5 0x0000 0xFFFF
BK 0x0000 0x0005
MMREG ADDRESSING
.mmregs
.text
mvdm 120h,ar1
mvmd ar1,127h
mvmm ar1,ar2
.end
Before Execution After Execution
PC 0x00004000 0x00004006
AR1 0x0000 0x0081
AR2 0x0000 0x0081
[120h
] 0x0081 0x0081
[127h
] 0x0000 0x0081
SEQUENCE 1:
1+2+3+…+n
.mmregs
.text
 n.set 9
ld #01h, b
nop
nop
stm #1200h, ar2
stm n, ar3

loop1:
stl b, *ar2+
add #1, b
banz loop1, *ar3-
ld #00h, b
nop
nop
stm #1200h, ar2
stm n, ar3
loop2:
add *ar2+, b
banz loop2, *ar3-
stl b, *ar2
nop
nop
.end
Before Execution After Execution
PC 0x00004000 0x0000402B
B 0x00000001 0x00000037
AR2 0x0090 0x120A
AR3 0x0939 0xFFFF
[1200h] 0x0000 0x0001
[1201h] 0x0000 0x0002
[1202h] 0x0000 0x0003
[1203h] 0x0000 0x0004
[1204h] 0x0000 0x0005
[1205h] 0x0000 0x0006
[1206h] 0x0000 0x0007
[1207h] 0x0000 0x0008
[1208h] 0x0000 0x0009
[1209h] 0x0000 0x000A
[120Ah] 0x0000 0x0037

SEQUENCE 2:
1-2+3-4…+n
.mmregs
.text
n.set 9
x.set 4
ld #01h, b
nop
nop
stm #1200h, ar2
stm n, ar3
loop1:
stl b, *ar2+
add #1, b
banz loop1, *ar3-
ld #00h, b
nop
nop
stm #1200h, ar2
stm x, ar3
loop2:
add *ar2+, b
sub *ar2+, b
banz loop2, *ar3-
stl b, *ar2
nop
nop
.end
Before Execution After Execution
PC 0x00004000 0x0000402E
B 0x00000001 0xFFFFFFFB
AR2 0x0091 0x120A
AR3 0x0939 0xFFFF
[1200h] 0x0000 0x0001
[1201h] 0x0000 0x0002
[1202h] 0x0000 0x0003
[1203h] 0x0000 0x0004
[1204h] 0x0000 0x0005
[1205h] 0x0000 0x0006
[1206h] 0x0000 0x0007
[1207h] 0x0000 0x0008
[1208h] 0x0000 0x0009
[1209h] 0x0000 0x000A
[120Ah] 0x0000 0xFFFB
SEQUENCE 3:
2 2 2 2
1 +2 +3 +…+n
.mmregs
.text
n.set 9
ld #01h, b
nop
nop
stm #1200h, ar2
stm n, ar3
loop1:
stl b, *ar2+
add #1, b
banz loop1, *ar3-
ld #00h, b
nop
nop
stm #1300h, ar4
stm #1200h, ar2
stm n, ar3
loop2:
squr *ar2+, b
stl b, *ar4+
banz loop2, *ar3-
stm n, ar3
nop
nop
ld #00h, b
stm #1300h, ar4
loop3:
add *ar4+, b
banz loop3, *ar3-
stl b, *ar2
nop
.end
 Before Execution After Execution
PC 0x00004000 0x0000402E
B 0x00000000 0xFFFFFFFB
AR2 0x005E 0x120A
AR3 0x0939 0xFFFF
AR4 0x026B 0x130A
[1200h] 0x0000 0x0001
[1201h] 0x0000 0x0002
[1202h] 0x0000 0x0003
[1203h] 0x0000 0x0004
[1204h] 0x0000 0x0005
[1205h] 0x0000 0x0006
[1206h] 0x0000 0x0007
[1207h] 0x0000 0x0008
[1208h] 0x0000 0x0009
[1209h] 0x0000 0x000A
[120Ah] 0x0000 0x0181
SEQUENCE 4:
0+1+1+2+3+5+8 …+ n (Fibonacci series)
.mmregs
.text
n.set 3
stm #2000h, ar2
st #0h, *ar2
st #1h, *(2001h)
ld #0h, a
ld #1, b
stm #2001h, ar3
stm n, ar4
loop:
add *ar2+, a
add *ar3+, a
stl a, *ar3
add *ar3, b
ld #0h, a
banz loop, *ar4-
nop
nop
stl b, *+ar3
nop
nop
.end

Before Execution After Execution

PC 0x00004000 0x0000402E
B 0x00000000 0xFFFFFFFB
AR2 0x005E 0x120A
AR3 0x0939 0xFFFF
AR4 0x026B 0x130A
[2000h] 0x0000 0x0001
[2001h] 0x0000 0x0002
[2002h] 0x0000 0x0003
[2003h] 0x0000 0x0004
[2004h] 0x0000 0x0005
[2005h] 0x0000 0x0006
[2006h] 0x0000 0x0007