Malla Reddy Institute of Engineering & Technology

(Sponsored by Malla Reddy Educational Society)

ISO 9001-2008 Certified institution, Affiliated to JNTU, Hyderabad
Maisammaguda, Dhulapally (Post via Hakimpet), Sec’Bad - 500100.
Department of Electronics and Communication Engineering

VLSI PROJECT BATCHES (A, B, C)

IV YEAR ( ECE - A ) PROJECT BATCHES (VLSI)
S.NO. BATCH NO. ROLL NO NAME OF THE STUDENT TITLE GUIDE SIGNATURE
1 16W91A0423 J PREMKAMAL DAS
2 1 16W91A0456 T.VARSHITHA Mr.M.Naresh
3 16W91A0460 Y VAISHNAVI
4 16W91A0430 K KIRANMAI
IMPLEMENTATION OF ARITHMETIC CODING FOR DATA TRANSMITTER AND
5 2 16W91A0449 S.TEJASWINI
RECEIVER USING VERILOG Mr. B. Anil Kumar
6 16W91A0450 S.KAMALAKAR REDDY
7 15W91A0415 D BHARATH REDDY
FAST FOURIER TRANSFORM IMPLEMENTATION OF RADIX - 8 OF 64 SAMPLES BY
8 3 16W91A0401 A V S SRIKANTH
USING DECIMATION IN FREQUENCY(DIF) USING VERILOG Mr. B. Anil Kumar
9 16W91A0408 B POOJA
10 16W91A0444 P SRAVANI
NEW KEY EXPANSION FUNCTION IMPLEMENTATION OF THE RIJNDAEL ADVANCED
11 4 16W91A0411 DEEPAK KUMAR THAKUR
ENCRYPTION STANDARD Mr. B. Anil Kumar
12 16W91A0438 M VAMSHIDHAR REDDY
13 16W91A0445 P.GAYATHRI
14 5 16W91A0448 R SAIPRASAD REDDY Mr.M.Naresh
15 16W91A0410 D KOTESHWARREDDY
16 16W91A0464 B SAI ANUSHA
CIPHERTEXT IMPLEMENTATION OF AES DESIGN IMPROVEMENTS TOWARDS
17 6 16W91A0409 B BALAJI
INFORMATION SECURITY CONSIDERING ATTACKS Mr. B. Anil Kumar
18 16W91A0419 G RISHITHA
19 16W91A0402 A ABHISHEK
FAST FOURIER TRANSFORM IMPLEMENTATION OF RADIX - 8 OF 64 SAMPLES BY
20 7 16W91A0432 K.NAVYASREE
USING DECIMATION IN TIME(DIT) USING VERILOG Mr. B. Anil Kumar
21 16W91A0421 H ANUSHA

IV YEAR ( ECE - B ) PROJECT BATCHES (VLSI)

S.NO. BATCH NO. ROLL NO NAME OF THE STUDENT TITLE GUIDE SIGNATURE
1 16W91A0470 #N/A
INFORMATION CONCEALMENT ENGINE IMPLEMENTATION FOR SECURITY DATA
2 8 16W91A0493 #N/A TRANSMISSION USING VERILOG Mr. B. Anil Kumar
3 16W91A0479 #N/A
4 16W91A0476 #N/A
VLSI DESIGN IMPLEMENTATION OF N=11 BYTES OF WINDOWING TECHNIQUE
5 9 16W91A04C1 #N/A
HAMMING CODE ENCODING SYSTEM BASED ON FPGA Mr. B. Anil Kumar
 VLSI DESIGN IMPLEMENTATION OF N=11 BYTES OF WINDOWING TECHNIQUE
9 HAMMING CODE ENCODING SYSTEM BASED ON FPGA Mr. B. Anil Kumar
6 16W91A0484 #N/A
7 16W91A0488 #N/A
VERILOG IMPLEMENTATION OF EXTENDED RIJINDEAL ALGORITHM FOR DATA
8 10 16W91A04A6 #N/A TRANSMISSION Mr. B. Anil Kumar
9 16W91A0494 #N/A
10 16W91A0492 #N/A
IMPLEMENTATION OF 64-BITS RADIX - 8 IFFT FOR COMPUTATION SPEED BY IDIF
11 11 16W91A04A4 #N/A USING VERILOG Mr. B. Anil Kumar
12 16W91A04D1 #N/A
13 16W91A04B2 #N/A
IMPLEMENTATION OF 64-BITS RADIX - 8 IFFT FOR COMPUTATION SPEED BY IDIT
14 12 16W91A04A7 #N/A USING VERILOG Mr. B. Anil Kumar
15 16W91A04B7 #N/A
16 16W91A04E3 #N/A
MODIFIED TRIPLE DATA ENCRYPTION STANDARD(TDES) IMPLEMENTATION FOR
17 13 16W91A0491 #N/A SECURE DATA TRANSMISSION USING VERILOG Mr. B. Anil Kumar
18 16W91A0483 #N/A
19 16W91A04F5 #N/A
VLSI DESIGN IMPLEMENTATION OF N=11 BYTES OF WINDOWING TECHNIQUE
20 14 16W91A04B1 #N/A HANNING CODE ENCODING SYSTEM BASED ON FPGA Mr. B. Anil Kumar
21 16W91A0496 #N/A
22 16W91A04H1 #N/A
VERILOG IMPLEMENTATION OF EXTENDED BLOWFISH ALGORITHM BY AES FOR
23 15 16W91A0490 #N/A DATA TRANSMISSION Mr. B. Anil Kumar
24 16W91A0475 #N/A
25 16W91A0489 #N/A
IMPLEMENTATION OF ENCODING AND DECODING TECHNIQUES FOR SECURITY
26 16 16W91A04C8 #N/A USING VERILOG Mr. B. Anil Kumar
27 16W91A04D3 #N/A
28 16W91A04B9 #N/A
NETWORK BASED SECURITY MODEL USING SYMMETRIC KEY CRYPTOGRAPHY of
29 17 16W91A0471 #N/A 288-BIT RESISTANCE TO THE RELATED-KEY ATTACKS Mr. B. Anil Kumar
30 16W91A0481 #N/A

IV YEAR ( ECE - C ) PROJECT BATCHES (VLSI)

S.NO BATCH NO ROLL NO NAME OF THE STUDENT TITLE GUIDE SIGNATURE
1 16W91A04K5 #N/A
ENHANCING DATA SECURITY BY AES ALGORITHM USING COMBINATION OF OTHER
2 18 16W91A04Q5 #N/A NEW GENERATION SECURITY ALGORITHM Mr. B. Anil Kumar
3 16W91A04J3 #N/A
4 16W91A04L6 #N/A
VERILOG IMPLEMENTATION OF 16 -BIT RADIX - 4 FFT BY USING DECIMATION IN
5 19 16W91A04P7 #N/A
FREQUENCY(DIF) Mr. B. Anil Kumar
6 16W91A04M1 #N/A
7 16W91A04R2 #N/A
IMPLEMENTATION OF EXTENDED ADVANCED ENCRYPTION STANDARD ALGORITHM
8 20 16W91A04Q1 #N/A FOR DATA TRANSMITTER AND RECEIVER Mr. B. Anil Kumar
9 16W91A04Q8 #N/A
10 16W91A04K9 #N/A
VERILOG IMPLEMENTATION OF 16 -BIT RADIX - 4 FFT BY USING DECIMATION IN
11 21 16W91A04L7 #N/A
TIME(DIT) Mr. B. Anil Kumar
12 16W91A04N9 #N/A
13 16W91A04K6 #N/A
14 17W95A0409 #N/A TEXT DATA LOSSLESS COMPRESSION ALGORITHM IMPLEMETATION FOR
22 CIPHERTEXT FORMATION Mr. B. Anil Kumar
15 16RG1A0401 #N/A
16 15W91A04C0 #N/A

PROJECT CO-ORDINATOR - B. ANIL KUMAR

 Malla Reddy Institute of Engineering & Technology
(Sponsored by Malla Reddy Educational Society)
ISO 9001-2008 Certified institution, Affiliated to JNTU, Hyderabad
Maisammaguda, Dhulapally (Post via Hakimpet), Sec’Bad - 500100.
Department of Electronics and Communication Engineering

IV YEAR ( ECE - A ) PROJECT BATCHES (VLSI)

S.NO. BATCH NO. ROLL NO NAME OF THE STUDENT TITLE GUIDE SIGNATURE
1 16W91A0423 J PREMKAMAL DAS
2 1 16W91A0456 T.VARSHITHA Mr.M.Naresh
3 16W91A0460 Y VAISHNAVI
4 16W91A0430 K KIRANMAI
IMPLEMENTATION OF ARITHMETIC CODING FOR DATA TRANSMITTER AND RECEIVER
5 2 16W91A0449 S.TEJASWINI USING VERILOG Mr. B. Anil Kumar
6 16W91A0450 S.KAMALAKAR REDDY
7 15W91A0415 D BHARATH REDDY
FAST FOURIER TRANSFORM IMPLEMENTATION OF RADIX - 8 64 BITS BY USING
8 3 16W91A0401 A V S SRIKANTH DECIMATION IN FREQUENCY(DIF) USING VERILOG Mr. B. Anil Kumar
9 16W91A0408 B POOJA
10 16W91A0444 P SRAVANI
VERILOG DESCRIPTION IMPLEMENTATION OF THE RIJNDAEL ADVANCED ENCRYPTION
11 4 16W91A0411 DEEPAK KUMAR THAKUR STANDARD Mr. B. Anil Kumar
12 16W91A0438 M VAMSHIDHAR REDDY
13 16W91A0445 P.GAYATHRI
14 5 16W91A0448 R SAIPRASAD REDDY Mr.M.Naresh
15 16W91A0410 D KOTESHWARREDDY
16 16W91A0464 B SAI ANUSHA
CIPHERTEXT IMPLEMENTATION OF AES DESIGN IMPROVEMENTS TOWARDS
17 6 16W91A0409 B BALAJI INFORMATION SECURITY CONSIDERING ATTACKS Mr. B. Anil Kumar
18 16W91A0419 G RISHITHA
19 16W91A0402 A ABHISHEK
FAST FOURIER TRANSFORM IMPLEMENTATION OF RADIX - 8 BY USING DECIMATION
20 7 16W91A0432 K.NAVYASREE IN TIME(DIT) USING VERILOG Mr. B. Anil Kumar
21 16W91A0421 H ANUSHA

PROJECT CO-ORDINATOR - B. ANIL KUMAR

 Malla Reddy Institute of Engineering & Technology
(Sponsored by Malla Reddy Educational Society)
ISO 9001-2008 Certified institution, Affiliated to JNTU, Hyderabad
Maisammaguda, Dhulapally (Post via Hakimpet), Sec’Bad - 500100.
Department of Electronics and Communication Engineering

IV YEAR ( ECE - B ) PROJECT BATCHES (VLSI)

S.NO. BATCH NO. ROLL NO NAME OF THE STUDENT TITLE GUIDE SIGNATURE
1 16W91A0470 #N/A
INFORMATION CONCEALMENT ENGINE IMPLEMENTATION FOR SECURITY DATA
2 1 16W91A0493 #N/A TRANSMISSION USING VERILOG Mr. B. Anil Kumar
3 16W91A0479 #N/A
4 16W91A0476 #N/A
VLSI DESIGN IMPLEMENTATION OF N=11 BYTES OF WINDOWING TECHNIQUE
5 2 16W91A04C1 #N/A HAMMING CODE ENCODING SYSTEM BASED ON FPGA Mr. B. Anil Kumar
6 16W91A0484 #N/A
7 16W91A0488 #N/A
VERILOG IMPLEMENTATION OF EXTENDED RIJINDEAL ALGORITHM FOR DATA
8 3 16W91A04A6 #N/A TRANSMISSION Mr. B. Anil Kumar
9 16W91A0494 #N/A
10 16W91A0492 #N/A
IMPLEMENTATION OF 64-BITS RADIX - 8 IFFT FOR COMPUTATION SPEED BY IDIF
11 4 16W91A04A4 #N/A USING VERILOG Mr. B. Anil Kumar
12 16W91A04D1 #N/A
13 16W91A04B2 #N/A
IMPLEMENTATION OF 64-BITS RADIX - 8 IFFT FOR COMPUTATION SPEED BY IDIT
14 5 16W91A04A7 #N/A USING VERILOG Mr. B. Anil Kumar
15 16W91A04B7 #N/A
16 16W91A04E3 #N/A
MODIFIED TRIPLE DATA ENCRYPTION STANDARD(TDES) IMPLEMENTATION FOR
17 6 16W91A0491 #N/A SECURE DATA TRANSMISSION USING VERILOG Mr. B. Anil Kumar
18 16W91A0483 #N/A
19 16W91A04F5 #N/A
VLSI DESIGN IMPLEMENTATION OF N=11 BYTES OF WINDOWING TECHNIQUE
20 7 16W91A04B1 #N/A HANNING CODE ENCODING SYSTEM BASED ON FPGA Mr. B. Anil Kumar
21 16W91A0496 #N/A
22 16W91A04H1 #N/A
VERILOG IMPLEMENTATION OF EXTENDED BLOWFISH ALGORITHM BY AES FOR
23 8 16W91A0490 #N/A DATA TRANSMISSION Mr. B. Anil Kumar
24 16W91A0475 #N/A
25 16W91A0489 #N/A
IMPLEMENTATION OF ENCODING AND DECODING TECHNIQUES FOR SECURITY USING
26 9 16W91A04C8 #N/A VERILOG Mr. B. Anil Kumar
27 16W91A04D3 #N/A
28 16W91A04B9 #N/A
NETWORK BASED SECURITY MODEL USING SYMMETRIC KEY CRYPTOGRAPHY of 288-
29 10 16W91A0471 #N/A BIT RESISTANCE TO THE RELATED-KEY ATTACKS Mr. B. Anil Kumar
30 16W91A0481 #N/A
PROJECT CO-ORDINATOR - B. ANIL KUMAR
 Malla Reddy Institute of Engineering & Technology
(Sponsored by Malla Reddy Educational Society)
ISO 9001-2008 Certified institution, Affiliated to JNTU, Hyderabad
Maisammaguda, Dhulapally (Post via Hakimpet), Sec’Bad - 500100.
Department of Electronics and Communication Engineering

IV YEAR ( ECE - C ) PROJECT BATCHES (VLSI)

S.NO BATCH NO ROLL NO NAME OF THE STUDENT TITLE GUIDE SIGNATURE
1 16W91A04K5 #N/A ENHANCING DATA SECURITY BY AES ALGORITHM USING COMBINATION OF OTHER
2 1 16W91A04Q5 #N/A NEW GENERATION SECURITY ALGORITHM Mr. B. Anil Kumar
3 16W91A04J3 #N/A
4 16W91A04L6 #N/A
VERILOG IMPLEMENTATION OF 16 -BIT RADIX - 4 FFT BY USING DECIMATION IN
5 2 16W91A04P7 #N/A FREQUENCY(DIF) Mr. B. Anil Kumar
6 16W91A04M1 #N/A
7 16W91A04R2 #N/A
IMPLEMENTATION OF EXTENDED ADVANCED ENCRYPTION STANDARD ALGORITHM
8 3 16W91A04Q1 #N/A FOR DATA TRANSMITTER AND RECEIVER Mr. B. Anil Kumar
9 16W91A04Q8 #N/A
10 16W91A04K9 #N/A
VERILOG IMPLEMENTATION OF 16 -BIT RADIX - 4 FFT BY USING DECIMATION IN
11 4 16W91A04L7 #N/A TIME(DIT) Mr. B. Anil Kumar
12 16W91A04N9 #N/A
13 16W91A04K6 #N/A
14 17W95A0409 #N/A TEXT DATA LOSSLESS COMPRESSION ALGORITHM IMPLEMETATION FOR CIPHERTEXT
5 FORMATION Mr. B. Anil Kumar
15 16RG1A0401 #N/A
16 15W91A04C0 #N/A

PROJECT CO-ORDINATOR - B. ANIL KUMAR