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FACULTY OF COMPUTER SCIENCE & INFORMATION SYSTEM
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Basic Adder

•  Basic adder operation is fundamental to the study of

digital system.

Basic Adders •  Types of basic adder :

–  a) Half Adder
Parallel Binary Adders –  b) Full Adder

•  Basic rules for binary addition

Comparators

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Basic Adder:
Half Adder

(Module: Page 96)

A⊕B

XOR

(Module: Page 149)

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Σ
A Σ
Sum
Basic Adder:

Β

Full Adder The design: Input Carry Cin

Cout Output Carry

STEP 1: Produce a
Accepts two input bits and truth table
n  Σ STEP 2: Map the K-Map
an input carry and A Σ
Sum Inputs Outputs


generates a sum output and Β

A B CIN ∑ COUT
Cout
an output carry. Input Carry Cin
Output Carry
0 0 0 0 0
n  Suitable for adding more 0 0 1 1 0
than 1 bits by cascading the 0 1 0 1 0
full adder. 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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= A⊕B
(Module: Page 149)

= AB

STEP 4: Draw the circuit Half Adder

STEP 3: Simplify K-Map
& get the equation

∑= ABC in + ABC in + ABCin + ABC

in

= (AB + AB)C in + (AB + AB)Cin A⊕B

∑= (A ⊕ B) ⊕ C in
∑= (A ⊕ B) ⊕ C in

∑= (A ⊕ B) ⊕ C in
(A ⊕ B)Cin

Cout = AB + (A ⊕ B)Cin
Cout = AB + ACin + BCin AB Cout = AB + (A ⊕ B)Cin
= AB + (A + B)Cin (Half Adder with 2 half adder)

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Σ Σ A = 1, B = 0, and Cin = 0
1 A Σ
Sum 1 A Σ
Sum =1



Example: 0 Β
Solution: 0 Β
1 + 0 + 0 = 1 with no carry
Cout Output Carry Cout Output Carry =0
0 Cin 0 Cin
∑ = 1, Cout = 0
For each of
the three full
Σ Σ A = 1, B = 1, and Cin = 0
adders, 1 A Σ
Sum 1 A Σ
Sum =0



determine the 1 Β
1 Β
1 + 1 + 0 = 0 with carry 1
Cout Cout
outputs for 0 Cin
Output Carry
0 Cin
Output Carry
=1
∑ = 0, Cout = 1
the inputs
shown.
Σ Σ A = 1, B = 0, and Cin = 1
1 A Σ
Sum 1 A Σ
Sum =0



0 Β
0 Β
1 + 0 + 1 = 0 with carry 1
Cout Cout
1 Cin
Output Carry
1 Cin
Output Carry
=1
∑ = 0, Cout = 1

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Ex Ex
tr tr
a a

Exercise 6.1: Determine the sum ( ∑ ) and the output carry Exercise 6.2: A full adder has Cin = 1. What are the sum ( ∑ )
(Cout) of a half adder for each set of input bits: and the output carry (Cout) when A = 1 and B = 1?

Σ
A Σ
Sum


∑= A ⊕ B Cout = AB Β

Cout Output Carry
Input, A Input, B Sum ( ∑ ) Output carry (Cout) Cin

i) 0 1
ii) 0 0
iii) 1 0
iv) 1 1

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Parallel Adder
(Module: Page 175)

Two or more full adders are

connected to form a parallel
adders.

Carry bit from

right column

In this case, the

carry bit from 2nd
column becomes a
sum bit

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A3 A2 A1
+ B3 B2 B1

∑∑∑∑4 3 2 1

Example:¨  Determine the sum generated by the 3-bit

MSI chip: (74LS283)
parallel adder below and show the
intermediate carries when the binary 4-bit parallel adders
numbers 101 and 011 are being added.
Solution: A3 A2 A1 B3 B2 B1
1 0 1 0 1 1
101
+ 011
1000 A4 A3 A2 A1
+ B4 B3 B2 B1

∑∑∑∑∑
5 4 3 2 1

∑= (A ⊕ B) ⊕ C in

Cout = AB + (A ⊕ B)Cin

17 (MSI: Medium-Scale Integration, module: page 39) 18

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Comparator
(Module: Page 177)

XOR gate as a 2-bit comparator:

•  Compares two n-bit binary
values to determine which
one is larger.
§  Inputs : 2 single-bit inputs (X
and Y).
§  Outputs : 3 lines: X > Y, X =Y ,
X < Y.

•  XNOR gate can be used as

a basic comparator
(Equality)

•  Use XOR to check for single

bit Inequality.
continue...

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•  To check for N bit equality (XNOR), combine the result of Example: Design a single comparator that compares X and
comparing an N single bit comparator. Y. Determine whether X=Y, X<Y or X>Y.

Solution:

The truth table: From the truth table,

the output equations:
Xi Yi X >Y X =Y X <Y
0 0 0 1 0
X > Y → XY
0 1 0 0 1
1 0 1 0 0 X = Y → X Y + XY = X • Y
1 1 0 1 0
X < Y → XY
Figure: Logic diagram for equality comparison of two 2-bit numbers. continue...
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The circuit: Example: Apply each of the following sets of binary numbers to the
comparator inputs in the Figure, and determine the
Design a separate output (equity) by following the logic levels through the
circuit for each output circuit.
and finally combine
them. (a) 10 and 10 (b) 11 and 10

X > Y → XY

X = Y → X Y + XY = X • Y
X < Y → XY

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Solution:
(a) 10 and 10 MSI chip: (74LS85) Figure: Logic symbol for a
4-bit comparator with
4-bit Comparator
inequality indication.

(b) 11 and 10

25 (MSI: Medium-Scale Integration, module: page 39) 26

Example: Determine the A = B, A > B, and A < B outputs for the Solution:
input numbers shown on the comparator in the Figure.
A > B output is
HIGH and the
1 other outputs
are LOW
0

Step 1: Compare A3 and B3 à Number A = B; compare next bits

Step 2: Compare A2 and B2 à Number A > B; stop comparing.

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Ex
tr
a

Exercise 6.3: What are the comparator outputs when binary number of
A = 1011 and B = 1010 applied as the inputs ?

Decoders

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Decoders

n  Function
n  detect the presence of a specified combination of bits (code) on Types of Decoder
its inputs
n  to indicate the presence of that code by a specified output level.

1)  Binary decoder

n  Decoder has
n  n input lines to handle n bits and from one to 2n output lines to
a) 3-Bits decoder (1 from 8) = 3-line to 8-line
indicate the presence of one or more n-bit combinations. b) 4-Bit decoder (1 from 16) = 4-line to 16-line
n  Output is 1 if its label matches input

2)  BCD to Decimal decoder

3)  BCD to 7-segments

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Ex
tr
Decoder: a
Binary Decoder
Exercise 6.4: Develop the logic required to detect the binary code
10010 and produce an active-LOW output.

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Ex
tr
a Binary Decoder:
3-Bit Decoder
Exercise 6.5: When the output is active-HIGH for each of decoding
gates in the Figure, what is the binary code appearing on
the inputs? The MSB is A3.
For this example:
Input active HIGH Output active HIGH
A B C
Decoding
A0 functions: A B C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A0
Q
ABC 0 0 0 1 0 0 0 0 0 0 0 0

A1 ABC 0 0 1 0 1 0 0 0 0 0 0 Q1

A2 A1 ABC 0 1 0 0 0 1 0 0 0 0 0 Q2

A3
ABC 0 1 1 0 0 0 1 0 0 0 0 Q3

ABC 1 0 0 0 0 0 0 1 0 0 0 Q4

A2 ABC 1 0 1 0 0 0 0 0 1 0 0 Q5

ABC 1 1 0 0 0 0 0 0 0 1 0 Q6

A3 ABC 1 1 1 0 0 0 0 0 0 0 1 Q7

(a) (b) Truth Table for 3 bits decoder

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Decoder:
4-Bit Decoder
•  AND is used because we want an active HIGH output.
n to 2n 1 of 2n
•  The each input there will be only one HIGH output.

0 Example: X/Y 0
1
0
2
1 If the input = 101, 3
A0 1 4
0 A1 2 5
the output Q5 = 1
Decoder 0 A2 4 6
8 7
A3
1 0 8
9
0 0 10
Note: 11
0
1 Only one output will 12
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Active active with a unique 14
HIGH CS1 &
output binary pattern at input. 15
ABC CS 2 EN
Active HIGH input

37 (MSI: Medium-Scale Integration, module: page 39) 38

10

0
1
0
1 10
0
1 0 1 0 0
0 EN

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a
tr
(Module: Page 185)
Ex

Example:
Address Decoder.
•  Decoder is use a lot to decode an
address of a computer. Example:
0
Port Address: 01002 0
I/O Request : LOW(0) 1
0

I/O Port: Scanner

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Ex
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a Decoder:
BCD to Decimal
Review . . .
Binary Coded Decimal (BCD)

•  BCD is a way to express each of the decimal digits with a

binary code.
•  There are only 10 code groups in the BCD system

0 1 2 3 4 5 6 7 8 9
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

•  Example: 4310 = 0100 0011

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Decoder:
Binary to 7-Segments

f b
g

e c

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Encoders

Encoders

Type of Encoders:

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Encoder:
Decimal to BCD

Vcc

Vcc

S0
S0
S1
S1
S2
AA0 S2
AA0
S3 A S3
Pengekod B A1 Pengekod BA1
S4 C A2
S4
(Encoder) CA
S5 (Encoder) 3
S5
D
2
D S6 A3
(Kod BCD)
S6 S7
(Kod BCD)
S7 S8
S9
S8
S9
Logic symbols for a decimal to BCD encoder.
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(Module: Page 191)

Exercise 6.6:

Solution 6.6:

Figure: Basic logic diagram of a decimal-

to-BCD encoder. A 0-digit input is not
needed because the BCD outputs are all
LOW when there are no HIGH inputs.
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Encoder:
Priority Encoder

Multiplexers (MUX)

Multiplexers (DEMUX)

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Multiplexers (MUX)
(Data Selector)

21(select bit) = 2 (total input bit)

22(select bit) = 4 (total input bit)
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Example: Multiplexer 1-of-2

Example: Multiplexer 1-of-4

A truth table is produced A more compact form

from the specification. can be produced.

S0 Data Output
0 Y = D0 Y = S 0 D0 + S1D1
1 Y = D1

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Exercise 7: Exercise 7:

The data-input and The data-input and

data-select data-select
waveforms in the waveforms in the
Figure are applied Figure are applied
to the multiplexer. to the multiplexer.

Determine the Determine the

output waveform Y, output waveform Y, Solution 7:
in the relation to the in the relation to the
inputs. inputs.

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Multiplexers (DEMUX)
(Data Distributor)
Exercise 8: What is the output of Y if the binary values of S and D are n  A DEMUX is basically reverse the multiplexing function.
given in the Figure. n  It takes digital information from one line and distributes it to a given
number of output lines.
Solution 8: n  For this reason, DEMUX is also known as a data distributor.
1 n  Decoder can also be used as DEMUX.
0
S1 S0 Q3 Q2 Q1 Q0
Q0
Q1 If
1 only 0 0 0 0 0 1
I Q2

1 I=1 0 1 0 0 1 0
0 Qn-1
1 0 0 1 0 0
1
Y = D1 = 1
1 1 1 0 0 0
Pemilih
Selector (S)

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•  The data-input lines goes to all the AND gates.

•  The 2 data-select lines enable only 1 gate at a time.

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Code Converter

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Code Converter

Parity Generators / Checkers

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Parity Generators / Checkers

Basic Parity Logic

•  Errors can occur as digital codes are being
transferred from one point to another within a
digital system.

•  The errors take the form of undesired changes in

the bits that make up the coded information; that
is, a 1 can change to a 0, or a 0 to a 1.

•  When an error occurs undetected, it can cause

serious problem in a digital system.

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