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FACULTY OF COMPUTER SCIENCE & INFORMATION SYSTEM
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Basic Shift Register (SR) Functions

Module:
•  SR is a register in which binary data can Page 33

be stored, and this data can be shifted to

the left or right when a signal is applied. Memory
Devices in
Digital
•  It consist of arrangements of FFs. Systems

•  Digital System : Important in application

involving:
–  a) Data storage Module:
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–  b) Data transfer/movement
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•  Each FF can
store 1 bit data.

a ) The flip-flop as a storage element •  More bits require b ) Basic Data Transfer/Movements in SR.
(Four bits are used for illustration. The bits move in the direction of the arrows.)
more FF.

When a 1 is on D, Q becomes a 1
at the triggering edge of CLK or
remains a 1 if already. SISO SISO PISO

When a 0 is on D, Q becomes a 0
at the triggering edge of CLK or
remains a 0 if already.
SIPO PIPO continue...
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SISO

•  Accepts data serially, one bit (input) at a time on a

•  A register can shift data one bit at a time.
•  The logical configuration of a serial SR:
–  A chain of FF connected in cascade.
single line
•  Each clock pulse will enter one bit data (Data in) into SR
and at the same time one bit will be shifted to Q7
Data transfer / movement:
(Characteristic)
•  Output produced in serial form too.

•  The operation of SR: Synchronous.

–  Using common clock.

•  Shifting N bit SR will lose all data after 2N clock cycles.

•  Solution: Using rotate. Figure : Logic symbol for an 8-bit
serial in/serial out shift register
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Figure : Four bits (1010) being serially shifted

out of the register and replaced by all zeros.

Example 1:

For n-bit SISO, it requires:

•  n clock cycle to shifted in all
data
LSB shifted in first. •  another n clock cycle to shifted
out all data.
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Example 2: SISO

4 Q3

Example 3:
Q3

5-bit SISO (Right SR)

Data input: 11010
Data shifted in: Data shifted out: MSB
Initially all FFs are cleared.
Clock, t FF0 FF1 FF2 FF3 Clock, t FF0 FF1 FF2 FF3 Data lost
MSB are shifted in first. MSB
Initially 0 0 0 0 Initially 1 0 1 1 X
1 1 0 0 0 1 0 1 0 1 1
Q4 MSB
2 1 1 0 0 2 0 0 1 0 1 5
3 0 1 1 0 3 0 0 0 1 0
Q4 MSB
4 1 0 1 1 4 0 0 0 0 1

Bit MSB will insert first. Bit MSB will go out first MSB
The last FF will hold MSB
continue...
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Clock, t FF0 FF1 FF2 FF3 FF4

Initially 0 0 0 0 0
1 1 0 0 0 0
SIPO
2 1 1 0 0 0
3 0 1 1 0 0
4 1 0 1 1 0 •  Data bits are entered serially one bit at a time.
5 0 1 0 1 1 •  Output is parallel
–  All bits are available simultaneously after n clock
cycles for n-bit SIPO.
For SISO, output only at Q3.
For SIPO output Q3Q2Q1Q0

Self-Test:

Generate a table
for the data
shifting out.
(MSB shifted out
first)

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Ex
tr
a
Example 4: Show the states of 4-bit SIPO shift register (SRG 4) for the
data input 0110 and clock waveforms. The register initially all
is 1s. Exercise 9.1: Show the states of 6-bit SIPO shift register (SRG 6) for the
data input 011001 and clock waveforms.
The register initially all is 0s and MSB will enter first.

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Exercise 9.1: Show the states of 6-bit SIPO shift register (SRG 6) for the
data input 011001 and clock waveforms.
The register initially all is 0s and MSB will enter first.
Solution :

MSB
1
MSB
Self-Test: 0
MSB
0
Generate a table MSB 1
for the data
shifting out.
MSB 1
0 MSB

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Example 5: SIPO (8-bit shift register)

Exercise 9.2: a)  Determine how many bit entered to the SISO (Right SR)
register?
b)  Circle on the timing diagram the valid output.
c)  Determine the data entered. (Assume MSB shifted in first)

•  Input can be A or B
•  CLR’ is active LOW; clear all output
to 00000000
•  Data entered at A or B will appear
at Q0 after the first clock pulse.
•  The data will appear at Q7 after the
8-th clock pulse.
•  A valid parallel data only appear at
all output after 8 clock cycles.

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Ex
tr
a
Exercise 9.3: a)  Determine how many bit entered to the SIPO
Exercise 9.2b: Based on the data entered in exercise 9.2, register?
a)  Redraw the timing diagram with LSB shifted in first. b)  Circle on the timing diagram the valid output.
b)  Circle on the timing diagram the valid output. c)  Determine the data entered. (Assume LSB
c)  Determine which output Q or flip flop hold the LSB bit at shifted in first)
CLK5.
Data = 11010

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PISO

•  Inputs entered
simultaneously into
respective stages on
parallel lines
•  Outputs are one bit at
a time

•  Modes: SHIFT / LOAD

NOTES:
Mode Value Function •  Input pins: D3D2D1D0
LOAD 0 Loads the input values •  MSB appear at Data out (Qn-1)
•  After n+1 clock cycle, all n bits
SHIFT 1 Shifts them out at clock pulse data will lost.

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Exercise 9.4: Complete the timing diagram of 6–bit

Ex
tr
PISO shift register (SRG 6) for the a PIPO
data input 011001.
The register initially all is 0s.
•  Input and output
done in parallel.
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•  Enter all inputs -
Bits appear on the
parallel outputs

(Q5)

•  The parallel data input doesn’t

appear at the output.
•  Output appear at the positive edge
of the clock.

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Example 6: PIPO (4-bit shift register)

RESET

SET
§  Can perform PIPO, PISO, SIPO and RESET
SISO
§  SH / LD 0 1
§  SHIFT / LOAD input 0 0
§  When LOW, data from inputs are 0 1
loaded 0 0
§  When HIGH, data will be shifted
to outputs (Q0 - Q3)
§  J and K are serial data inputs
§  First stage serial input into Q0
§  Serial output will be at Q3
continue...
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Shift Register Counter

•  A shift register with serial output connected back

to the serial input to produce special sequences.

•  In normal counter, to
•  2 most common types:
provide individual digit
outputs instead of a binary
Shift Register Counters or BCD output.
à adding a decoder.
SR Counter

•  But much simpler to use a

different counter structure Ring Johnson
with simple decoder Counter Counter
à shift registers
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Shift Register Counter:

Ring Counter
•  A type of SISO shift register but final output fed back to the
first input.
•  The ring counter uses 1 FF for each state in its sequence
•  For a 10-bit ring counter, there is a unique output for each
decimal digit
–  Initially Q0 = 1 è represents a zero
–  The ‘1’ is shifted round the ring, so next Q1 = 1 (represents a
one)
–  This goes on till Q9 = 1. n-bit = MOD n
(state number)
–  Then the output Q9 is input back into the first FF
Example:
•  **The ‘1’ is always retained and goes ‘round the ring’ at •  For a 10-bit ring counter, there are 10 FFs which make a MOD 10 counter.
•  It will recycle after 10 clock cycles.
each clock pulse

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Example 7: If a 10-bit ring counter has the initial state 0000000101,

determine the waveform for each of the Q outputs.

Solution: D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
0 0 0 0 0 0 0 1 0 1

D0 D1 D2 D8 D9
1 0 1 . . . . . . . . 0 0

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Clock Pulse Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q9
Shift Register Counter:
Johnson Counter
0 0 0 0 0 0 0 0 1 0 1
•  In the Johnson counter the last complemented output is
1 1 0 0 0 0 0 0 0 1 0
fed back in as an input to the first FF
2 0 1 0 0 0 0 0 0 0 1 •  Examples shown with D FF, but can be implemented
3 1 0 1 0 0 0 0 0 0 0 with other types of FF as well.
4 0 1 0 1 0 0 0 0 0 0 •  Number of unique states are 2 times the number of bits
(FF)
5 0 0 1 0 1 0 0 0 0 0
–  4 bits è 4*2 = 8 states n-bit = MOD 2n
6 0 0 0 1 0 1 0 0 0 0 (state number)
–  5 bits è 5*2 = 10 states
7 0 0 0 0 1 0 1 0 0 0 •  Johnson counter will produce a modulus of 2n;
8 0 0 0 0 0 1 0 1 0 0 (n = number of stages)
9 0 0 0 0 0 0 1 0 1 0 •  **modulus 10 a.k.a. mod 10
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Example:
Q3
Clock Pulse Q0 Q1 Q2 Q3
n-bit = MOD 2n 0 0 0 0 0
(state number)
1 1 0 0 0
Example: 2 1 1 0 0
•  For a 4-bit ring
counter, there 3 1 1 1 0
are 4 FFs which
make a MOD 8 4 1 1 1 1
counter.
•  It will recycle
5 0 1 1 1
after 8 clock
6 0 0 1 1
cycles. Complete
7 0 0 0 1 one cycle
Repete
8 0 0 0 0 cycle
9 . . . .
continue... 38
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Ex
tr
a
Summary:
Ring Counter FF3 FF2 FF1 FF0

D3 D2 D1 D0
Q0
n-bit = MOD n
(state number)

Data representation: Truth Table: State Diagram:

D3 D2 D1 D0 1000
Clock FF3 FF2 FF1 FF0
MSB LSB
1 0 0 0 1 1 0 0 0
2 0 1 0 0 0001 0100
3 0 0 1 0
4 0 0 0 1 0010

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Summary: Johnson Counter Ex

tr
a
FF3 FF2 FF1 FF0

D3
Other characteristic of
D2 D1 D0
Johnson counter:

n-bit = MOD 2n Q0 •  Always exist 2 unique

(state number) Clock FF3 FF2 FF1 FF0 AND gate required
for output bits compared to
A B C D
other state.
Truth Table: 1 1 0 0 0
1000
AB •  It will only requires 2
Clock FF3 FF2 FF1 FF0 2 1 1 0 0 BC input decoder to
0000 1100
Data representation: 1 1 0 0 0 3 1 1 1 0 CD decode a state.
2 1 1 0 0 4 1 1 1 1 AD
D3 D2 D1 D0 5 0 1 1 1 AB Example:
3 1 1 1 0 0001 State Diagram: 1110
MSB LSB
1 0 0 0 4 1 1 1 1 6 0 0 1 1 BC
5 0 1 1 1 7 0 0 0 1 CD C
8 0 0 0 0 AD D
6 0 0 1 1 0011 1111
7 0 0 0 1
0111
8 0 0 0 0
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Ex
tr
a

Self-Test:

1.  Given a 3-bit Johnson counter, draw the appropriate sequence

table for 7 clock pulses

2. A modulus-10 Ring counter requires a minimum of

A) 10 FF C) 5 FF
B) 4 FF D) 12 FF

3. A modulus-10 Johnson counter requires

A) 10 FF C) 4 FF
B) 5 FF D) 12 FF

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4. The group of 8 bits 1011 0110 is serially shifted (right most bit first) 6. To parallel load a byte of data into a shift register with a
into an 8-bit parallel output shift register with an initial state of 1110 synchronous load, there must be
0100. After 2 clock pulses, the register contains A) 1 clock pulse
A) 1011 1001 C) 0111 1001 B) 8 clock pulse
B) 1001 0010 D) 0010 1101 C) one load pulse
D) one clock pulse for each 0 in the data
5. To serially shift a byte of data into a shift register, there must be
A) 1 clock pulse
B) 8 clock pulse
C) one load pulse
D) one clock pulse for each 1 in the data

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