5 4 3 2 1

ZAB/ZAB A,B/ZYJA BLOCK DIAGRAM VRAM

DDR4-SODIMM1 Channel A (TYP1)

P9 PCIE 0~3 (TYP1 & 3) R16M GPU 1 channel,dual-rank
PEG R16M-M1-70 25W P16, P17
D FP4 TX/RX
D

IMC TDP: 15 W PCIE 4~7 (TYP1) R16M-M1-30 25W VRAM DDR3_256 Mb x16 *4 pcs = 2 GB
DDR4-SODIMM2 Channel B (TYP1 & 3) S3_23mm X 23mm
VRAM DDR3_256 Mb x16 *8 pcs = 4 GB
P10 Carrizo P11,12,13,14,15
(15h) 60h-6Fh CZ@: CARRIZO/BRISTOL (TYP1)
Bristol
X'TAL
27 MHz SP@: special part
I2C-0 (Touchpad) SP15@: 15" only
SATA - HDD SATA 0 SATA0
(15h) 65h-6Fh SP17@: 17" only
P26 I2C I2C-1 (Touch Screen)
eDP/TS/CCD Con. I2CT@: I2C TS
STONEY EV@ : GPU
SATA - ODD SATA 1 (15H) 70h-7Fh USB2-2 (Touch)
SATA1 Meso@: R16M-M1-70 GPU
P26 P18
USB2-4 (CCD) Exo@ : R16M-M1-30 GPU
EV_SP@: GPU special part
USB2 - 6 DP0 EV_4G@: 8 pcs VRAM
USB3 Con. DP0
P27
USB3 - 2 TPM@ :TPM
GS@ :G-sensor
USB Charger HDT@ : Debug
USB2 - 5 HDMI Con.
C
SLGC55544VTR
P27 USB3.0 DP1
DP1 Repeater KBL@ :KB Backlight C
USB3 Con. P19 P19 IOAC@ :IOAC
P27
USB3 - 1 NAC@:non-IOAC
DP2 DP to VGA
APU CRT Con. FPD@ : POA
P20 P20
BGA 968 DP2 SSD@ : SSD
USB2 - 7
ROM 128 kB
X'TAL SRD@: SATA's Redriver
3.3 V P23 20 MHz URD@: USB3's Redriver
USB3 Type-C Con. M.2
ASM 1061
GPP2
SSD RP@: HDMI Repeater
MUX USB Redriver USB3 - 3 P23 P23 NRD@: no HDMI RPTR
GPP
P28 P28 P28 USB2.0 TYP_C@: Type C solution
GPP1
M.2 CRD@: Type-C's usb redriver
USB2-4 (CCD)
CC
USB2-2 WLAN+BT w/ Debug
P28 USB2-5 (WLAN/BT) X'TAL P22
32.768 kHz
P2,3,4,5,6,7,8 GPP0 RJ45 CONN P21
USB2-3
LAN+Card Reader
POA P31 RTL841B
X'TAL 48 MHz P21
B
C.R. CONN P21
B

17" only USB2 CONN

I/O Board X'TAL
USB2-0 & USB2-1 SPI SPI ROM 8MB 25 MHz
USB2 CONN FFC CONN
1.8 V P6 Reset Button
Phone Jack P27 P30, 32

CLK RTC
BATT
P7
Azalia HDA P37, P38
LPC
BQ24737 ISL62771
SMBUS
G-Sensor Batery Charger P33 CPU CORE / VDDNB
P25

TPM RT6575 RT8068

NPCT650 P25 3V/5V P34 1.8V P39
AUDIO CODEC
ALC255-CG P24
RT8237 ISL62771
EC 0.95V P35 VGPU CORE P40
ROM 128 kB
IT8987E/BX PS/2 P32 3.3 V P32
A G5316 RT8068 P41 A

+1.2VSUS P36 GPU_POWER / VDDC_GFX

Speaker DMIC
P24 P24 I2C-0 (TYP1&3)
LED K/B CONN K/B BL CONN HALL SENSOR FAN CONN Touch Pad
P28 P30 P30 P18
(DAC) P30 CONN
P29 CZ@ :CARRIZO/BRISTOL (TYP1) Quanta Computer Inc.
CZL@ :CARRIZO-L (TYP2)
TYP3@: STONEY PROJECT : ZAB
TYP13@ : CZ/BR & ST Size Document Number Rev
1A
TYP12@ : CZ/BR & CZL Block Diagram
TYP23@ : CZL & ST Date: Friday, January 29, 2016 Sheet 1 of 45
5 4 3 2 1
 1 2 3 4 5 6 7 8

(CPU)

AC-coupling capactior(depend on GenX, not TYPE)

2
A
U31B
TYP1&3:(220nF)CH4222K9B04: Only Gen3 and Both of Gen2&3 A
TYP2 :(100nF)CH4103K1B08: Only Gen2
PCIE

TYP2 no Gen3
U10 P_GPP_RXP[0] P_GPP_TXP[0] R1 PCIE_TXP0_C C628 0.1U/16V/X7R_4
[21] PCIE_RXP0 PCIE_TXN0_C PCIE_TXP0 [21]
LAN U9 P_GPP_RXN[0] P_GPP_TXN[0] R2 C629 0.1U/16V/X7R_4 LAN
[21] PCIE_RXN0 PCIE_TXN0 [21]
T6 P_GPP_RXP[1] P_GPP_TXP[1] R4 PCIE_TXP1_C C621 0.1U/16V/X7R_4
[22] PCIE_RXP1 T5 R3 PCIE_TXN1_C PCIE_TXP1 [22]
WLAN P_GPP_RXN[1] P_GPP_TXN[1] C622 0.1U/16V/X7R_4 WLAN
[22] PCIE_RXN1 PCIE_TXN1 [22]
T9 P_GPP_RXP[2] P_GPP_TXP[2] N1 PCIE_TXP2_C C626 0.1U/16V/X7R_4
[23] PCIE_RXP2 T8 N2 PCIE_TXN2_C PCIE_TXP2 [23]
SSD P_GPP_RXN[2] P_GPP_TXN[2] C627 0.1U/16V/X7R_4 SSD
[23] PCIE_RXN2 PCIE_TXN2 [23]
P7 P_GPP_RXP[3] P_GPP_TXP[3] N4
1.05V VDDP only for CZ with DDR-2133 memory P6 P_GPP_RXN[3] P_GPP_TXN[3] N3
If running DDR-1866 or slower memory,
Platform VDDP should be set to 0.95V R440 196/F_4 P_TX_ZVDD_095 U7 P_ZVDDP P_ZVSS/P_RX_ZVDDP U6 P_RX_ZVDD_095 R439 196/F_4
VDDP_0.95V
TYP13: (196R_CS11962FB00)
B CZL:(1.69K_CS21692FB01) B

P10 P_GFX_RXP[0] P_GFX_TXP[0] M2 PEG_TXP0_C C568 EV@0.22u/10V_4

[11] PEG_RXP0 P9 M1 PEG_TXN0_C PEG_TXP0 [11]
P_GFX_RXN[0] P_GFX_TXN[0] C569 EV@0.22u/10V_4
[11] PEG_RXN0 PEG_TXN0 [11]
X4 : TYP3 (GEN3)
X4 : TYP2 (GEN2)

X4 : TYP3 (GEN3)
X4 : TYP2 (GEN2)
N6 P_GFX_RXP[1] P_GFX_TXP[1] L1 PEG_TXP1_C C566 EV@0.22u/10V_4
[11] PEG_RXP1 N5 L2 PEG_TXN1_C PEG_TXP1 [11]
P_GFX_RXN[1] P_GFX_TXN[1] C565 EV@0.22u/10V_4
[11] PEG_RXN1 PEG_TXN1 [11]
N9 P_GFX_RXP[2] P_GFX_TXP[2] L4 PEG_TXP2_C C570 EV@0.22u/10V_4
[11] PEG_RXP2 PEG_TXN2_C PEG_TXP2 [11]
N8 P_GFX_RXN[2] P_GFX_TXN[2] L3 C571 EV@0.22u/10V_4
[11] PEG_RXN2 PEG_TXN2 [11]
X8 : TYP1 (GEN3)

L7 P_GFX_RXP[3] P_GFX_TXP[3] J1 PEG_TXP3_C C564 EV@0.22u/10V_4

[11] PEG_RXP3 PEG_TXN3_C PEG_TXP3 [11]
L6 P_GFX_RXN[3] P_GFX_TXN[3] J2 C563 EV@0.22u/10V_4
[11] PEG_RXN3 PEG_TXN3 [11]

X8 : TYP1 (GEN3)
L10 P_GFX_RXP[4] P_GFX_TXP[4] J4 PEG_TXP4_C C572 EV_SP@0.22u/10V_4
[11] PEG_RXP4 L9 J3 PEG_TXN4_C PEG_TXP4 [11]
P_GFX_RXN[4] P_GFX_TXN[4] C573 EV_SP@0.22u/10V_4
[11] PEG_RXN4 PEG_TXN4 [11]
K6 P_GFX_RXP[5] P_GFX_TXP[5] H2 PEG_TXP5_C C562 EV_SP@0.22u/10V_4
[11] PEG_RXP5 K5 H1 PEG_TXN5_C PEG_TXP5 [11]
P_GFX_RXN[5] P_GFX_TXN[5] C561 EV_SP@0.22u/10V_4
C [11] PEG_RXN5 PEG_TXN5 [11] C
K9 P_GFX_RXP[6] P_GFX_TXP[6] G1 PEG_TXP6_C C574 EV_SP@0.22u/10V_4
[11] PEG_RXP6 K8 G2 PEG_TXN6_C PEG_TXP6 [11]
P_GFX_RXN[6] P_GFX_TXN[6] C575 EV_SP@0.22u/10V_4
[11] PEG_RXN6 PEG_TXN6 [11]
J7 P_GFX_RXP[7] P_GFX_TXP[7] G4 PEG_TXP7_C C559 EV_SP@0.22u/10V_4
[11] PEG_RXP7 PEG_TXN7_C PEG_TXP7 [11]
J6 P_GFX_RXN[7] P_GFX_TXN[7] G3 C560 EV_SP@0.22u/10V_4
[11] PEG_RXN7 PEG_TXN7 [11]

FP4 REV 0.93

SP@FP4
AC-coupling capactior(depend on GenX, not TYPE)
TYP1&3:(220nF)CH4222K9B04: Only Gen3 and Both of Gen2&3
TYP2 :(100nF)CH4103K1B08: Only Gen2

D D

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
FP4 PCIE I/F(1/7)
Date: Monday, February 15, 2016 Sheet 2 of 45
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

(CPU)
Channel A:CZ(TYP1) ONLY
U31A U31I
3
MEMORY A MEMORY B
[9] M_A_A[13:0] M_A_A0 AE28 H17 M_A_DQ0 M_A_DQ[0..63] [9] [10] M_B_A[13:0] M_B_A0 AG31 A25 M_B_DQ0 M_B_DQ[0..63] [10]
MA_ADD[0] MA_DATA[0] MB_ADD[0] MB_DATA[0]
M_A_A1 Y27 MA_ADD[1] MA_DATA[1] J17 M_A_DQ1 M_B_A1 AC30 MB_ADD[1] MB_DATA[1] C25 M_B_DQ1
M_A_A2 Y29 MA_ADD[2] MA_DATA[2] F20 M_A_DQ2 M_B_A2 AC31 MB_ADD[2] MB_DATA[2] C27 M_B_DQ2
M_A_A3 Y26 MA_ADD[3] MA_DATA[3] H20 M_A_DQ3 M_B_A3 AB32 MB_ADD[3] MB_DATA[3] D27 M_B_DQ3
A M_A_A4 W 28 MA_ADD[4] MA_DATA[4] E17 M_A_DQ4 M_B_A4 AA32 MB_ADD[4] MB_DATA[4] B24 M_B_DQ4 A
M_A_A5 W 29 MA_ADD[5] MA_DATA[5] F17 M_A_DQ5 M_B_A5 AA33 MB_ADD[5] MB_DATA[5] B25 M_B_DQ5
M_A_A6 W 26 MA_ADD[6] MA_DATA[6] K18 M_A_DQ6 M_B_A6 AA31 MB_ADD[6] MB_DATA[6] B27 M_B_DQ6
M_A_A7 U29 MA_ADD[7] MA_DATA[7] E20 M_A_DQ7 M_B_A7 Y33 MB_ADD[7] MB_DATA[7] A27 M_B_DQ7
M_A_A8 W 25 MA_ADD[8] M_B_A8 AA30 MB_ADD[8]
M_A_A9 U26 MA_ADD[9] MA_DATA[8] A21 M_A_DQ8 M_B_A9 W 32 MB_ADD[9] MB_DATA[8] A29 M_B_DQ8
M_A_A10 AG29 MA_ADD[10] MA_DATA[9] C21 M_A_DQ9 M_B_A10 AG32 MB_ADD[10] MB_DATA[9] C29 M_B_DQ9
M_A_A11 U27 MA_ADD[11] MA_DATA[10] C23 M_A_DQ10 M_B_A11 Y32 MB_ADD[11] MB_DATA[10] B32 M_B_DQ10
M_A_A12 T28 MA_ADD[12] MA_DATA[11] D23 M_A_DQ11 M_B_A12 W 33 MB_ADD[12] MB_DATA[11] D32 M_B_DQ11
M_A_A13 AK26 MA_ADD[13] MA_DATA[12] B20 M_A_DQ12 M_B_A13 AL31 MB_ADD[13] MB_DATA[12] B28 M_B_DQ12
T26 MA_ADD[14]/MA_BG[1] MA_DATA[13] B21 M_A_DQ13 W 30 MB_ADD[14]/MB_BG[1] MB_DATA[13] B29 M_B_DQ13
[9] M_MA_BG1 M_A_DQ14 [10] M_MB_BG1 M_B_DQ14
T25 MA_ADD[15]/MA_ACT_L MA_DATA[14] B23 V32 MB_ADD[15]/MB_ACT_L MB_DATA[14] A31
[9] MEM_MA_ACT# A23 M_A_DQ15 [10] MEM_MB_ACT# C31 M_B_DQ15
MA_DATA[15] MB_DATA[15]

MA_DATA[16] G22 M_A_DQ16 MB_DATA[16] E30 M_B_DQ16

M_A_BS#0 AG26 MA_BANK[0] MA_DATA[17] H22 M_A_DQ17 AH32 MB_BANK[0] MB_DATA[17] E31 M_B_DQ17
[9] M_A_BS#0 M_A_BS#1 AG27 E25 M_A_DQ18 [10] M_B_BS#0 AG33 G33 M_B_DQ18
MA_BANK[1] MA_DATA[18] MB_BANK[1] MB_DATA[18]
[9] M_A_BS#1 M_MA_BG0 T29 G25 M_A_DQ19 [10] M_B_BS#1 W 31 G32 M_B_DQ19
MA_BANK[2]/MA_BG[0] MA_DATA[19] MB_BANK[2]/MB_BG[0] MB_DATA[19]
[9] M_MA_BG0 J20 M_A_DQ20 [10] M_MB_BG0 C33 M_B_DQ20
MA_DATA[20] MB_DATA[20]
[9] M_A_DM[7..0] M_A_DM0 E19 E22 M_A_DQ21 [10] M_B_DM[7..0] M_B_DM0 D25 D33 M_B_DQ21
MA_DM[0] MA_DATA[21] MB_DM[0] MB_DATA[21]
M_A_DM1 D21 MA_DM[1] MA_DATA[22] H23 M_A_DQ22 M_B_DM1 D29 MB_DM[1] MB_DATA[22] G30 M_B_DQ22
M_A_DM2 K21 MA_DM[2] MA_DATA[23] J23 M_A_DQ23 M_B_DM2 E33 MB_DM[2] MB_DATA[23] G31 M_B_DQ23
M_A_DM3 F29 MA_DM[3] M_B_DM3 J33 MB_DM[3]
M_A_DM4 AP28 MA_DM[4] MA_DATA[24] F26 M_A_DQ24 M_B_DM4 AR30 MB_DM[4] MB_DATA[24] J30 M_B_DQ24
M_A_DM5 AV26 MA_DM[5] MA_DATA[25] E27 M_A_DQ25 M_B_DM5 AW 30 MB_DM[5] MB_DATA[25] J31 M_B_DQ25
M_A_DM6 AR22 MA_DM[6] MA_DATA[26] J26 M_A_DQ26 M_B_DM6 BC30 MB_DM[6] MB_DATA[26] L33 M_B_DQ26
M_A_DM7 BC22 MA_DM[7] MA_DATA[27] J27 M_A_DQ27 M_B_DM7 BC26 MB_DM[7] MB_DATA[27] L32 M_B_DQ27
K29 MA_DM[8] MA_DATA[28] H25 M_A_DQ28 N33 MB_DM[8] MB_DATA[28] H32 M_B_DQ28
MA_DATA[29] E26 M_A_DQ29 MB_DATA[29] H33 M_B_DQ29
H19 MA_DQS_H[0] MA_DATA[30] G28 M_A_DQ30 B26 MB_DQS_H[0] MB_DATA[30] L30 M_B_DQ30
B [9] M_A_DQS0 G19 G29 M_A_DQ31 [10] M_B_DQS0 A26 L31 M_B_DQ31 B
MA_DQS_L[0] MA_DATA[31] MB_DQS_L[0] MB_DATA[31]
[9] M_A_DQS#0 [10] M_B_DQS#0
B22 MA_DQS_H[1] B30 MB_DQS_H[1]
[9] M_A_DQS1 A22 AN26 M_A_DQ32 [10] M_B_DQS1 A30 AN31 M_B_DQ32
MA_DQS_L[1] MA_DATA[32] MB_DQS_L[1] MB_DATA[32]
[9] M_A_DQS#1 M_A_DQ33 [10] M_B_DQS#1 M_B_DQ33
F23 MA_DQS_H[2] MA_DATA[33] AP29 F32 MB_DQS_H[2] MB_DATA[33] AP32
[9] M_A_DQS2 M_A_DQ34 [10] M_B_DQS2 M_B_DQ34
E23 MA_DQS_L[2] MA_DATA[34] AR26 E32 MB_DQS_L[2] MB_DATA[34] AT32
[9] M_A_DQS#2 G27 AP24 M_A_DQ35 [10] M_B_DQS#2 K32 AU32 M_B_DQ35
MA_DQS_H[3] MA_DATA[35] MB_DQS_H[3] MB_DATA[35]
[9] M_A_DQS3 F27 AN29 M_A_DQ36 [10] M_B_DQS3 J32 AN33 M_B_DQ36
MA_DQS_L[3] MA_DATA[36] MB_DQS_L[3] MB_DATA[36]
[9] M_A_DQS#3 AP25 AN27 M_A_DQ37 [10] M_B_DQS#3 AR32 AN32 M_B_DQ37
MA_DQS_H[4] MA_DATA[37] MB_DQS_H[4] MB_DATA[37]
[9] M_A_DQS4 M_A_DQ38 [10] M_B_DQS4 M_B_DQ38
AP26 MA_DQS_L[4] MA_DATA[38] AR29 AR33 MB_DQS_L[4] MB_DATA[38] AR31
[9] M_A_DQS#4 AW 27 AR27 M_A_DQ39 [10] M_B_DQS#4 AW 32 AT33 M_B_DQ39
MA_DQS_H[5] MA_DATA[39] MB_DQS_H[5] MB_DATA[39]
[9] M_A_DQS5 AV27 [10] M_B_DQS5 AW 33
MA_DQS_L[5] MB_DQS_L[5]
[9] M_A_DQS#5 M_A_DQ40 [10] M_B_DQS#5 M_B_DQ40
AV22 MA_DQS_H[6] MA_DATA[40] AU26 BA29 MB_DQS_H[6] MB_DATA[40] AU30
[9] M_A_DQS6 AU22 AV29 M_A_DQ41 [10] M_B_DQS6 AY29 AV32 M_B_DQ41
MA_DQS_L[6] MA_DATA[41] MB_DQS_L[6] MB_DATA[41]
[9] M_A_DQS#6 BA21 AU25 M_A_DQ42 [10] M_B_DQS#6 BA25 BA33 M_B_DQ42
MA_DQS_H[7] MA_DATA[42] MB_DQS_H[7] MB_DATA[42]
[9] M_A_DQS7 M_A_DQ43 [10] M_B_DQS7 M_B_DQ43
AY21 MA_DQS_L[7] MA_DATA[43] AW 25 AY25 MB_DQS_L[7] MB_DATA[43] AY32
[9] M_A_DQS#7 L27 AU29 M_A_DQ44 [10] M_B_DQS#7 P32 AU33 M_B_DQ44
MA_DQS_H[8] MA_DATA[44] MB_DQS_H[8] MB_DATA[44]
L26 MA_DQS_L[8] MA_DATA[45] AU28 M_A_DQ45 N32 MB_DQS_L[8] MB_DATA[45] AU31 M_B_DQ45
MA_DATA[46] AW 26 M_A_DQ46 MB_DATA[46] AW 31 M_B_DQ46
AE25 MA_CLK_H[0] MA_DATA[47] AT25 M_A_DQ47 AE33 MB_CLK_H[0] MB_DATA[47] AY33 M_B_DQ47
[9] M_A_CLK0 [10] M_B_CLK0
AE26 MA_CLK_L[0] AE32 MB_CLK_L[0]
[9] M_A_CLK0# AD26 AV23 M_A_DQ48 [10] M_B_CLK0# AE30 BC31 M_B_DQ48
MA_CLK_H[1] MA_DATA[48] MB_CLK_H[1] MB_DATA[48]
[9] M_A_CLK1 M_A_DQ49 [10] M_B_CLK1 M_B_DQ49
AD27 MA_CLK_L[1] MA_DATA[49] AW 23 AE31 MB_CLK_L[1] MB_DATA[49] BB30
[9] M_A_CLK1# M_MA_CLK2_P AB28 AV20 M_A_DQ50 [10] M_B_CLK1# AD32 BB28 M_B_DQ50
MA_CLK_H[2] MA_DATA[50] MB_CLK_H[2] MB_DATA[50]
TP28 AB29 MA_CLK_L[2] MA_DATA[51] AW 20 M_A_DQ51 AD33 MB_CLK_L[2] MB_DATA[51] AY27 M_B_DQ51
M_MA_CLK3_P AB25 MA_CLK_H[3] MA_DATA[52] AR23 M_A_DQ52 AC33 MB_CLK_H[3] MB_DATA[52] BB32 M_B_DQ52
TP21 AB26 MA_CLK_L[3] MA_DATA[53] AT23 M_A_DQ53 AC32 MB_CLK_L[3] MB_DATA[53] BA31 M_B_DQ53
MA_DATA[54] AR20 M_A_DQ54 MB_DATA[54] BC29 M_B_DQ54
N29 MA_RESET_L MA_DATA[55] AT20 M_A_DQ55 T33 MB_RESET_L MB_DATA[55] BB29 M_B_DQ55
[9] M_A_RESET# [10] M_B_RESET#
AE29 MA_EVENT_L AG30 MB_EVENT_L
[9] M_A_EVENT# BB23 M_A_DQ56 [10] M_B_EVENT# BB27 M_B_DQ56
MA_DATA[56] MB_DATA[56]
C P27 MA_CKE0 MA_DATA[57] BB22 M_A_DQ57 U32 MB_CKE0 MB_DATA[57] BB26 M_B_DQ57 C
[9] M_A_CKE0 M_A_DQ58 [10] M_B_CKE0 M_B_DQ58
P29 MA_CKE1 MA_DATA[58] BB20 U33 MB_CKE1 MB_DATA[58] BB24
[9] M_A_CKE1 AY19 M_A_DQ59 [10] M_B_CKE1 AY23 M_B_DQ59
MA_DATA[59] MB_DATA[59]
MA_DATA[60] BA23 M_A_DQ60 MB_DATA[60] BA27 M_B_DQ60
MA_DATA[61] BC23 M_A_DQ61 MB_DATA[61] BC27 M_B_DQ61
AK27 MA0_ODT[0] MA_DATA[62] BC21 M_A_DQ62 AL30 MB0_ODT[0] MB_DATA[62] BC25 M_B_DQ62
[9] M_A_ODT0 M_A_DQ63 [10] M_B0_ODT0 M_B_DQ63
AL26 MA0_ODT[1] MA_DATA[63] BB21 AM32 MB0_ODT[1] MB_DATA[63] BB25
[9] M_A_ODT1 MEM_MA1_ODT0 AH25 [10] M_B0_ODT1 AJ32
MA1_ODT[0] MB1_ODT[0]
TP25 MEM_MA1_ODT1 AL25 MA1_ODT[1] MA_CHECK[0] K26 AM33 MB1_ODT[1] MB_CHECK[0] N30
TP26 MA_CHECK[1] K28 MB_CHECK[1] N31
AH26 MA0_CS_L[0] MA_CHECK[2] N26 AJ33 MB0_CS_L[0] MB_CHECK[2] R33
[9] M_A0_CS#0 AL29 N28 [10] M_B0_CS#0 AL32 R32
MA0_CS_L[1] MA_CHECK[3] MB0_CS_L[1] MB_CHECK[3]
[9] M_A0_CS#1 MEM_MA1_CS#0 AH29 J29 [10] M_B0_CS#1 AJ30 M32
MA1_CS_L[0] MA_CHECK[4] MB1_CS_L[0] MB_CHECK[4]
TP27 MEM_MA1_CS#1 AL28 MA1_CS_L[1] MA_CHECK[5] K25 AL33 MB1_CS_L[1] MB_CHECK[5] M33
TP29 MA_CHECK[6] L29 MB_CHECK[6] R30
MA_CHECK[7] N25 MB_CHECK[7] R31
AG24 MA_RAS_L/MA_RAS_L_ADD[16] AH33 MB_RAS_L/MB_RAS_L_ADD[16]
[9] M_A_RAS# AK29 [10] M_B_RAS# AK32
MA_CAS_L/MA_CAS_L_ADD[15] MB_CAS_L/MB_CAS_L_ADD[15]
[9] M_A_CAS# AH28 +1.2VSUS [10] M_B_CAS# AJ31 +1.2VSUS
MA_WE_L/MA_WE_L_ADD[14] MB_WE_L/MB_WE_L_ADD[14]
[9] M_A_WE# [10] M_B_WE#

APU_MA_VREFDQ B19 MA_VREFDQ MA_ZVDDIO_MEM_S AD29 MA_ZVDDIO R210 CZ@39.2/F_4 APU_MB_VREFDQ A19 MB_VREFDQ MB_ZVDDIO_MEM_S AF32 MB_ZVDDIO R643 39.2/F_4
TP57 APU_M_VREF_SUS T32 M_VREF TP56
TP64
FP4 REV 0.93 FP4 REV 0.93
SP@FP4 SP@FP4

+1.2VSUS R646 *1K/F_4

R648 *1K/F_4

routed near APU

D 2015-11-10 SCL v1.11 D

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
FP4 DDR I/F(2/7)
Date: Monday, February 15, 2016 Sheet 3 of 45
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

(CPU)
VDD_18

R633
R545
300_4
300_4
APU_PWRGD
APU_RST#
Soldermask openings for all bottom side vias/TPs under FP4
U31C

DISPLAY/SVI2/JTAG/TEST
33S0_18S0 +3V
4
B6 DP2_TXP[0] DP_ZVSS A9 DP_ZVSS R532 2K/F_4
[20] DP2_TX0
A6 DP2_TXN[0] DP_AUX_ZVSS B9 DP_AUX_ZVSS R533 150/F_4
[20] DP2_TX0#
VGA DP_BLON G5 TYP13 : 1.8V R517
APU_DISP_BLEN [18,33]

2
D7 DP2_TXP[1] DP_DIGON G6 APU_DIGON 10K/F_4
[20] DP2_TX1 CZL : 3.3V
C7 F11 APU_BLPWM
[20] DP2_TX1# DP2_TXN[1] DP_VARY_BL
APU_BLPWM 1 3
LCD 3.3V
APU_DISP_PWM [18]
A7 DP2_TXP[2] DP2 : Type 1 & 3 only
A A
B7 DP2_TXN[2] DP2_AUXP H9 DP2_AUX [20] Q36
DP2_AUXN G9 DP2_AUX# [20] PJA138K
D9 DP2_TXP[3] DP2_HPD E9
DP2_HPD [20] APU_DIGON
C9 DP2_TXN[3] CZ:1.8_S0 CZL:3V_S0 R467 *short_4
APU_DISP_ON [18]
DP1_AUXP F7 TYP13 : 1.8V
HDMI_DDCCLK_SW [19]
[19] INT_HDMITX2P A2 DP1_TXP[0] DP1_AUXN E7 EN:>1.5V
A3 DP1_TXN[0] (XX,PD) DP1_HPD F5
HDMI_DDCDATA_SW [19] CZL : 3.3V
[19] INT_HDMITX2N INT_HDMI_HPD [19]

[19] INT_HDMITX1P B4 DP1_TXP[1] DP0_AUXP F8 EDP_AUX [18]

[19] INT_HDMITX1N A4 DP1_TXN[1] DP0_AUXN E8 EDP_AUX# [18]
(XX,PD) G8 +3V
HDMI DP0_HPD
EDP_HPD [18]
[19] INT_HDMITX0P D5 DP1_TXP[2]

[19] INT_HDMITX0N C5 DP1_TXN[2] RSVD_1 K24 RSVD TP20

TEMPIN0 E15 APU_TEMPIN0 DP2_AUX# R237 *100K/F_4
TP15
A5 DP1_TXP[3] TEMPIN1 E14 APU_TEMPIN1 DP2_AUX R238 *100K/F_4
[19] INT_HDMICLK+ TP12
B5 DP1_TXN[3] CZ:1.8_S0 CZL:3V_S0 TEMPIN2 E12 APU_TEMPIN2

Serial VID [19] INT_HDMICLK-

[18] EDP_TX0 E2
E1
DP0_TXP[0]
TEMPINRETURN
TEST410
F14
AK24
AL24
APU_TEMPRETURN
APU_TEST410
APU_TEST411
TP19
TP10
R556 *0_4
DNI: VGA doesn't need it.
[18] EDP_TX0# DP0_TXN[0] TEST411
TP24
VDD_18 VDD_18 P24 APU_TEST4
eDP TEST4
APU_TEST5
TP23
[18] EDP_TX1 E3 DP0_TXP[1] TEST5 N24 TP22
[18] EDP_TX1# E4 DP0_TXN[1] TEST6 AN24
TEST9 AB8
[18] EDP_TXP2 D1 DP0_TXP[2] TEST10 Y9
R590 R575 R627 R578 R596 R605 R595 D2 DP0_TXN[2] TEST14 B10 APU_TEST14 R536 *1K/F_4
[18] EDP_TXN2
*1K/F_4 *1K/F_4 *2.2K_4 *1K/F_4 *CZ@1K/F_4 *CZ@1K/F_4 *CZ@1K/F_4 eDP 4k*2k TEST15 D11 APU_TEST15
TP48
C1 DP0_TXP[3] TEST16 A10 APU_TEST16 R537 *1K/F_4
[18] EDP_TXP3
APU_SVT GFX_SVT B1 DP0_TXN[3] TEST17 C11 APU_TEST17 R558 *1K/F_4
[18] EDP_TXN3
APU_SVC GFX_SVC TEST11 B11 APU_TEST11 R557 *CZ@1K/F_4
APU_SVD GFX_SVD *APU_SVT & GFX_SVT need 0R in power side C15 SVT0 TEST18 A14 APU_TEST18 R554 1K/F_4
APU_PWRGD_SVID_REG [38] APU_SVT APU_SVC_R APU_TEST19
R583 *short_4 D17 SVC0 TEST19 B14 R555 1K/F_4
[38] APU_SVC APU_SVD_R
R572 *short_4 D19 SVD0
[38] APU_SVD
R592 R601
B R586 R576 R617 *CZ@220_4 *CZ@220_4 B15 A13 APU_TEST28_H B
SVT1 TEST28_H
TP54
[39] GFX_SVT
*220_4 *220_4 *220_4 R588 *shortCZ@0_4 GFX_SVC_R B16 SVC1 TEST28_L B13 APU_TEST28_L
TP51
[39] GFX_SVC
R591 *shortCZ@0_4 GFX_SVD_R A18 SVD1 TEST31 P26 APU_TEST31 R649 *39.2/F_4 VDD_18
M_TEST CONNECTION TBD
[39] GFX_SVD DP_STEREOSYNC
DP_STEREOSYNC/TEST36 E11 R647 *39.2/F_4
APU_SIC B18 SIC CZL:3V_S0 TEST37 A17 APU_TEST37 R561 1K/F_4 PU ->enable HDMI video/audio
33S0_18S0 PD->Disable HDMI audio
APU_SID C17 SID CZL:3V_S0 R560 *1K/F_4
R607 *CZ@1K/F_4 VDD_18
APU_RST# D15 RESET_L R608 *CZ@1K/F_4
R616 *short_4 APU_PWRGD C19 PWROK
[38,39] APU_PWRGD_SVID_REG TP53
APU_PWRGD_D R626 HDT@0_4 TP50
APU_PROCHOT# A15 CZ:1.8_S0 CZL:3V_S0
VFIX MODE VID Override table (VDD) APU_ALERT# B17
PROCHOT_L
CZL:3V_S0
TP49
ALERT_L TP30
APU_PWRGD VDDCR_GFX_SENSE H11
APU_RST# APU_TDI APU_VDDGFX_RUN_FB_H [39]
SVC SVD Boot Voltage H15 TDI VDDCR_NB_SENSE J12
APU_TDO APU_VDDNB_RUN_FB_H [38]
H14 TDO VDDCR_CPU_SENSE G12
APU_TCK APU_VDD_RUN_FB_H [38]
D13 AY18
0 0 1.1V C703 C663 APU_TMS G15
TCK
TMS
VDDP_SENSE
R527 *short_4
APU_VDDP_RUN_FB_H [36]
APU_TRST# APU_VDD_RUN_FB_L [38]
*27p/50V_4 *27p/50V_4 J14 H12 APU_VSS_SENSE R550 *shortCZ@0_4 (APU_VDD_RUN_FB_L = APU_VDDNB_RUN_FB_L)
0 1 1.0V APU_DBRDY C13
TRST_L
DBRDY
VSS_SENSE
R573 *0_4
APU_VDDGFX_RUN_FB_L [39]
APU_DBREQ# APU_VDDP_RUN_FB_L [36]
A11
1 0 0.9V DBREQ_L
CRB CLOSE TO APU

1 1 0.8V FOR DEBUG, PLACE THESE CAPS CLOSE TO APU

FP4 REV 0.93

SP@FP4

+3V 33S0_18S0

33S0_18S0

C HDT(Hardware Debug Tool ) Connector VDD_18

3V_S0
R635
10K/F_4 5
Q41 R639
R641
R638
1K/F_4
1K/F_4
1K/F_4
APU_SIC
APU_SID
APU_ALERT#
C

3 4 APU_PROCHOT# R636 1K/F_4 APU_PROCHOT#

[33,34,38,39] CORE_PWM_PROCHOT#
C719
HDT@0.1U/16V/X7R_4 5V_S0 2
VDD_18 R642 *short_4 33S0_18S0
6 1 APU_ALERT#
U33 [31] THERM_ALERT#
APU_RST# 1 6 APU_RST_L_BUF
1A 1Y PJT138K
2 5
GND VCC
APU_PWRGD_D 3 4 APU_PWROK_BUF
2A 2Y

HDT@SN74LVC2G07DCKR
SMBUS (Internal Thermal sensor)
VDD_18 VDD_18 VDD_18
PLACE HDT+ HEADER ON TOP 33S0_18S0

CN7
R160 1 2 APU_TCK R562 HDT@1K/F_4 Q43
CPU_VDDIO CPU_TCK
HDT@1K/F_4 3 4 APU_TMS R563 HDT@1K/F_4 5
GND CPU_TMS
5 6 HDT_APU_TDI R564 HDT@0_4 APU_TDI HDT@1K/F_4
GND CPU_TDI
7 8 APU_TDO R565 3 4 APU_SIC
GND CPU_TDO [12,33] 2ND_MBCLK
APU_TRST# R161 HDT@33_4 HDT_TRST# 9 10 APU_PWROK_BUF R566 HDT@1K/F_4
CPU_TRST_L CPU_PWROK_BUF
R162 HDT@10K/F_4 11 12 APU_RST_L_BUF R567 HDT@1K/F_4 3V_S5
CPU_DBRDY3 CPU_RST_L_BUF
R163 HDT@10K/F_4 13 14 APU_DBRDY 2
C218 R164 HDT@10K/F_4 15
CPU_DBRDY2 CPU_DBRDY0
16 HDT_DBREQ# R569 HDT@33_4 APU_DBREQ#
(PU in EC side )
CPU_DBRDY1 CPU_DBREQ_L
HDT@0.01u/50V_4 17 18 APU_TEST19 R568 HDT@1K/F_4 6 1 APU_SID
GND CPU_PLLTEST0 [12,33] 2ND_MBDATA
19 20 APU_TEST18
CPU_VDDIO CPU_PLLTEST1
D D
*HDT@HDT PJT138K
C674 C675
*HDT@0.01u/50V_4 HDT@0.01u/50V_4

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
FP4 DISPLAY/MISC(3/7)
Date: Thursday, March 03, 2016 Sheet 4 of 45
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

(CPU)
VDD_18_S5

(CZ,CZL)
U31D
5
R418
15K/F_4 C669 150P/50V_4 ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
R553 33_4 LPC_RST#_R BB12 LPC_RST_L 3V_S5? S0? (PD,PU) 3V_S0 SD0_WP/EGPIO101 BB2
[22,25,33] PLTRST# DGPU_RST_L [11]
R478 33_4 PCIE_RST# AN7 PCIE_RST_L/EGPIO26 3V_S5 3V_S0 SD0_PWR_CTRL/AGPIO102 BB5
[11,18,21,22,23] PCIERST# ODD_PLUGIN# [26]
C643 150P/50V_4 (PU,PU) CZ:3V_S5 CZL:3V_S0 SD0_CD/AGPIO25 BC2
D11 RB500V-40 PCH_RSMRST#_R AE4 RSMRST_L 1.8V_S5 (PD,PU) SD0_CLK/EGPIO95 BB4 BOARD_ID4
[33] RSMRST# BOARD_ID5 BOARD_ID4 [18]
(PD,PU) SD0_CMD/EGPIO96 AY5
10ms RC-delay AE1 PWR_BTN_L/AGPIO0 3V_S5 (PU,PU)
A [33] DNBSWON# SYS_PWRGD
A
BC9 PWR_GOOD CZ:3V_S0 CZL:1.8V_S0
C602 SYS_RST# AF2 SYS_RESET_L/AGPIO1 (PU,PU)
0.1u/16V_4 R433 *short_4 PCIE_WAKE# AG2 WAKE_L/AGPIO2 (PU,PU) (PD,PU) SD0_DATA0/EGPIO97 BC3 BOARD_ID0
[12,21,22] PCIE_LAN_WAKE# BOARD_ID1
C615 *EV@100P/50V_4 (PD,PU) 3.3V_S0 SD0_DATA1/EGPIO98 BA3
AK7 SLP_S3_L (PD,PU) SD0_DATA2/EGPIO99 BC5 BOARD_ID2
+3V_S5 [33] SUSB# BOARD_ID3
AH5 SLP_S5_L (PD,PU) SD0_DATA3/EGPIO100 BA5
[33] SUSC# DGPU_PWREN_A
(PD,) SD0_LED/EGPIO93 BB6
R434 NAC@10K/F_4 PCIE_WAKE# S0A3 AE8 S0A3_GPIO/AGPIO10 3V_S5
[43] APU_S5_MUX_CTRL AH8 S5_MUX_CTRL/EGPIO42 CZ ONLY (PU,) SCL0/I2C2_SCL/EGPIO113 BA15
CLK_SCLK [9,10,20,25]
(PU,) SDA0/I2C2_SDA/EGPIO114 AY17
LR_LED_L APU_TEST0 CLK_SDATA [9,10,20,25]
R82 10K/F_4 AH6 TEST0 (,PD)
R83 10K/F_4 S0A3 APU_TEST1 AK8 TEST1/TMS (,PD) (PU,) SCL1/I2C3_SCL/AGPIO19 AG5 SCL1
APU_TEST2 TP3
R81 10K/F_4 DNBSWON# AE3 TEST2 (,PD) (PU,) SDA1/I2C3_SDA/AGPIO20 AG4 SDA1
USB_OC1# TP2
R436 10K/F_4
R442 10K/F_4 USB_OC2# AY15 ESPI_RESET_L/KBRST_L/AGPIO129 3V_S0 (PU,PU)
USB_OC3# [33] SIO_RCIN#
R104 10K/F_4 BC19 GA20IN/AGPIO126 3V_S0 (PU,PU)
[33] SIO_A20GATE
AD7 LPC_PME_L/AGPIO22 3V_S5 (PU,PU) (PU,PU) AGPIO3 AL5 GEVENT2# GEVENT2# [6]
[33] SIO_EXT_SCI# SIO_EXT_SMI# BB13 LPC_SMI_L/AGPIO86 3V_S0 (PU,PU) (PD,) AGPIO4 AL6 AGPIO4
TP52 TP4
R80 10K/F_4 AGPIO8 3.3V_S5 AGPIO5 AJ1
S3_resume PCH_ODD_EN [26]
R100 *10K/F_4 AG3 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 CZ ONLY (PU,PU) (PD,PU) AGPIO6/LDT_RST AJ3
[34] ACPRESENT ACCEL_INTA [25]
AD5 IR_TX0/USB_OC5_L/AGPIO13 (PU,) (PD,PU) AGPIO7/LDT_PWROK AH1
[28] APU_TypeC_UFP#
AL8 IR_TX1/USB_OC6_L/AGPIO14 (PU,PU) AGPIO8 AJ4 AGPIO8
+3V AN8 IR_RX1/AGPIO15 3V_S5 (PU,PU) (PD,PU) AGPIO9 AK5
LR_LED_L AE2 IR_LED_L/LLB_L/AGPIO12 (PU,PU) VDDGFX_PD/AGPIO39 AD8 2015.10.20 SCL v1.10 & DG v1.08
CLK_SCLK S3_resume VDDGFX_PD [33] TYP1: No connect (**)
R603 2.2K_4 BC15 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 (,PU) AGPIO40 AG8 R99 10K/F_4
CLK_SDATA [21] PCIE_REQ_LAN#
R589 2.2K_4 BB17 CLK_REQ1_L/AGPIO115 (PU,PU) (PD,PU) AGPIO64 AW15 AGPIO64 S3 resume time measure point
CLK_REQ3_L [22] PCIE_CLKREQ_WLAN# TP7
R602 10K/F_4 TP55 BC17 CLK_REQ2_L/AGPIO116 (PU,PU) (PD,PU) AGPIO65 AU15
R598 10K/F_4 PCIE_REQ_GPU#_R CLK_REQ3_L BB18 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 3V_S0 (,PU)
R597 *EV@0_4 PCIE_REQ_GPU#_R BB16 (,PU) (PD,PU) AT15 AGPIO66
[12] PCIE_REQ_GPU#
AH9
CLK_REQG_L/OSCIN/EGPIO132
(PU,) (PD,PU)
AGPIO66/SHUTDOWN_L
AU12
TP11 Type 3 no these agpio pins,
USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK
R156 10K/F_4 AGPIO69
[28] CC_OC#
AG1 USB_OC1_L/TDI/AGPIO17 (PU,PU) (,PU) 3.3V_S0 AGPIO69/SGPIO_LOAD AT14 AGPIO69
TP9 only for type 1 & 2 !!!
[27] USB_OC1#
AH2 USB_OC2_L/TCK/AGPIO18 3V_S5 (PU,PU) (PD,PU) AGPIO71/SGPIO_DATAOUT AR14
[27] USB_OC2# TP18
AL9 USB_OC3_L/TDO/AGPIO24 (PU,PU) (PD,) AGPIO72/SGPIO_DATAIN BC13
B [27] USB_OC3# TP16 B
R541 33_4 ACZ_BCLK_R AU6 AZ_BITCLK/I2S_BCLK_MIC SPKR/AGPIO91 BA17
[24] PCH_AZ_CODEC_BITCLK SPKR [24]
+3V_S5 R429 *10K/F_4 AR8 AZ_SDIN0/I2S_DATA_MIC[0] (,PD)
[24] PCH_AZ_CODEC_SDIN0 AZ_SDIN1 AP6 AZ_SDIN1/I2S_LR_PLAYBACK (,PD) (PU,PU) CZ:3V_S5 CZL:3V_S0 BLINK/USB_OC7_L/AGPIO11 AN5
SYS_RST# AZ_SDIN2 AGPIO11 [6]
J1 1 2 AR5 AZ_SDIN2/I2S_DATA_MIC[1] S5 (,PD) (PD,)
SYS_RST# internal R525 33_4 ACZ_RST#_R AU9 AZ_RST_L/I2S_LR_MIC (PU,PU) GENINT1_L/AGPIO89 BB14 TP17 BB14 AMD change pin name to HVBEN_L : default NC
[24] PCH_AZ_CODEC_RST# ACZ_SYNC_R
*SHORT_PAD 40K pull up R530 33_4 AT9 AZ_SYNC/I2S_BCLK_PLAYBACK (PU,PU) GENINT2_L/AGPIO90 BA19
[24] PCH_AZ_CODEC_SYNC ACZ_SDOUT_R PE_PWRGD [42]
R542 33_4 AR7 AZ_SDOUT/I2S_DATA_PLAYBACK 3.3V_S0
[24] PCH_AZ_CODEC_SDOUT +3V
(PU,) FANIN0/AGPIO84 BC18
ACZ_RST#_R APU_TP_INT# [18]
R159 CZ@1K/F_4 BB10 I2C0_SCL/EGPIO145 (PU,) FANOUT0/AGPIO85 BB19
ACZ_BCLK_R [30] I2C_SCL_TP APU_I2C_INT# [30]
R544 CZ@1K/F_4 BB9 I2C0_SDA/EGPIO146
ACZ_SYNC_R [30] I2C_SDA_TP
R529 CZ@1K/F_4 BB7 I2C1_SCL/EGPIO147 TPE13:1.8V_S0 CZL:3V UART0_CTS_L/EGPIO135 AY9
ACZ_SDOUT_R [18] I2C_SCL_TS
R528 CZ@1K/F_4 BC7 I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AW8 R181
PCH_AZ_CODEC_SDIN0 [18] I2C_SDA_TS
R531 *10K/F_4 1.8V_S0 UART0_RTS_L/EGPIO137 AV5 *EV@100K/F_6
R121 10K/F_4 AZ_SDIN1 AG7 RTCCLK 3V_S5 (PU,) UART0_TXD/EGPIO138 AV8
AZ_SDIN2 [6] RTC_CLK
R126 10K/F_4 R112 *33_4 UART0_INTR/AGPIO139 AW9 CZ : mount R1
ACZ_BCLK_R [22] SUS_CLK
R540 *10K/F_4 2015-11-10 SCL v1.11 R1
18p/50V_4 C636 32K_X1 AT1 X32K_X1 1.8V_S0 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 AV11 R178 *shortEV@0_4
CZ:1.8V_S0 CZL:1.8V_S5 UART1_RXD/BT_I2S_SDI/EGPIO141 AU7
1

1.8V_S0 UART1_RTS_L/EGPIO142 AT11 D1

1.8V_S0 UART1_TXD/BT_I2S_SDO/EGPIO143 AR11
VDD_18 32K_X2 AT2 X32K_X2 (,PD) CZ:1.8V_S0 CZL:1.8V_S5 UART1_INTR/BT_I2S_LRCLK/AGPIO144 AP9 D3 DGPU_PWREN_A
[42] DGPU_PWREN
Y4 R473
I2C_SCL_TP FP4 REV 0.93
R609 2.2K_4 32.768KHZ 20M_4 *EV_SP@RB500V-40
R610 2.2K_4 I2C_SDA_TP SP@FP4
C258 R182
2

R495 SP@10K/F_4 I2C_SCL_TS 18p/50V_4 C637 EV@0.1u/16V_4 *EV@1M/F_4

R488 SP@10K/F_4 I2C_SDA_TS

TYP13 :
I2C Touch interface:2.2K(CS22202JB18) +3V >1 mS delay is required between all MXM power rail stable
None I2C interface:10k(CS31002FB26)
CZL:NC
SYS PWRGD and MXM_PWREN(enables the module internal power)
C C
R463 DGPU_PWREN_A >1mS
4.7K_4
DGPU_PWREN
D13 1N4148WS SYS_PWRGD_R R457 *short_4 SYS_PWRGD
[33] EC_PWROK
D12 *1N4148WS
[6] SYS_RST#
C625 ZYV
SUSB# D14 *1N4148WS
+3V_S5
0.22u/10V_4 BOARD ID BOARD_ID4 Depend on cable => always PU, PD DNI
Touch cable PIN2 => NC
non-Touch cable PIN2 => GND
+3V

Test mode setting (Follow AMD's suggestion) R458 R120 SP@10K/F_4 BOARD_ID0 R119 SP@10K/F_4
R110 SP@10K/F_4 BOARD_ID1 R113 SP@10K/F_4
100K/F_4 R115 SP@10K/F_4 BOARD_ID2 R114 SP@10K/F_4
+3V_S5 R107 IOAC@10K/F_4BOARD_ID3 R109 NAC@10K/F_4
NC,no install by default R484 10K/F_4 BOARD_ID4 R483 *10K/F_4
APU_TEST0 [33] HWPG
R101 *2.2K_4 R102 15K/F_4 R122 SP17@10K/F_4BOARD_ID5 R125 SP15@10K/F_4
5

6
R93 *1K/F_4 APU_TEST1 R106 15K/F_4

R426 *2.2K_4 APU_TEST2 R423 15K/F_4 Q33

GPIO High Low
2N7002DW
BOARD_ID0 dTPM iTPM
TEST2 TEST1 TEST0 Description BOARD_ID1 dGPU UMA
4

FCH TAP accessible from APU when TAPEN is asserted

BOARD_ID2 non-G sensor G sensor
0 0 0
FCH JTAG pins are overloaded for multiple BOARD_ID3 IOAC non-IOAC
functions, in this configuration the FCH JTAG are D15 *CZ@RB500V-40
used as non-JTAG pins
R447 CZ@47K_4
BOARD_ID4 Touch non-Touch
D [33,38] VRON VDDGFX_EN [39] D
BOARD_ID5 17" 15"
3

0 0 1 Reserved
C620
Q34 *CZ@1U/6.3V_4
0 1 X Reserved VDDGFX_PD R435 **CZ@10K/F_4 2

FCH JTAG multi-function pins are configured as C616

1 TMS 0 JTAG pins, in this configuration the FCH TAP **CZ@2N7002K
can be accessed from FCH JTAG pins **CZ@1000P/50V_4 Quanta Computer Inc.
1

Use on ATE only PROJECT : ZAB

1 TMS 1 Yuba JTAG enabled 2015.10.20 SCL v1.10 & DG v1.08
TYP1: No connect (**) Size Document Number Rev
1A
FP4 GPIO/AZ/I2C/SD/UARTS(4/7)
Date: Thursday, March 03, 2016 Sheet 5 of 45
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

(CPU)
[26] SATA_TXP0
AU3
AU4
SATA_TX0P
SATA_TX0N
U31E

CLK/SATA/USB/SPI/LPC
(PD,) USBCLK/25M_48M_OSC AP8 TP5
R629 *short_4
6
[26] SATA_TXN0 VDD_18 33S5_18S0
AP5 USB_ZVSS R480 11.8K/F_4
HDD AV1 SATA_RX0N
USB_ZVSS

[26] SATA_RXN0
AV2 SATA_RX0P USB_HSD0P AR2
[26] SATA_RXP0 USBP0+ [27] 33S5_18S0
USB_HSD0N AR1 USB2.0/DB
USBP0- [27] 33S5_18S0
AY2 SATA_TX1P
[26] SATA_TXP1
AY1 SATA_TX1N USB_HSD1P AR3
[26] SATA_TXN1 USBP1+ [27]
AR4 USB2.0/DB
ODD AW4 SATA_RX1N
USB_HSD1N
USBP1- [27]
R615
A [26] SATA_RXN1 A
AW3 SATA_RX1P USB_HSD2P AN2 C701
[26] SATA_RXP1 USBP2+ [22]
USB_HSD2N AN1 WLAN/BT 10K/F_4
SATA_ZVSS USBP2- [22]
R472 1K/F_4 AW1 SATA_ZVSS R618 0.1u/16V_4
R476 1K/F_4 SATA_ZVDD AW2 SATA_ZVDDP USB_HSD3P AN3 U32 10K/F_4
VDDP_0.95V USBP3+ [32]
DEVSLP_HDD AT17 DEVSLP[0]/EGPIO67 3V_S0 USB_HSD3N AN4 POA SPI_CS# R623 33_4 SPI_CS_A 1 8
[26] DEVSLP_HDD USBP3- [32] CE# VDD
R152 10K/F_4 DEVSLP_ODD AT12 DEVSLP[1]/EGPIO70 3V_S0 SPI_CLK R606 33_4 SPI_SCK_A 6
+3V SCK
R154 10K/F_4 AGPIO130 BB15 SATA_ACT_L/AGPIO130 3V_S0 USB_HSD4P AM1 5
USBP4+ [18] SI SPI_HOLD#
USB_HSD4N AM2 CCD C691 *22P/50V_4 2 7
USBP4- [18] SO HOLD#
AU2 SATA_X1 1.8V_S0 SPI EMI
USB_HSD5P AL2 SPI_SI R600 33_4 SPI_SDI_A 3 4
USBP5+ [27] SPI_SO SPI_SDO_A WP# VSS
R148 10K/F_4 USB_HSD5N AL1 USB3 (Charger) R611 33_4
USBP5- [27]
33S5_18S0 R599 10K/F_4 W25Q64FWSSIG
AU1 SATA_X2 1.8V_S0 USB_HSD6P AL3
USBP6+ [27] SPI_WP SPI_WP_R
USB_HSD6N AL4 USB3.0 R604 *short_4
USBP6- [27]
R446 *shortEV@0_4 CLK_PCIE_VGAP_C U4 GFX_CLKP USB_HSD7P AK2
[11] CLK_PCIE_VGAP USBP7+ [28]
R445 *shortEV@0_4 CLK_PCIE_VGAN_C U3 AJ2 Type-C
[11] CLK_PCIE_VGAN GFX_CLKN USB_HSD7N
USBP7- [28] SP@ socket P/N: DFHS08FS023 only for A-TEST
R462 *short_4 CLK_PCIE_LANP_R U1 GPP_CLK0P
[21] CLK_PCIE_LANP
R461 *short_4 CLK_PCIE_LANN_R U2 SPI ROM
[21] CLK_PCIE_LANN GPP_CLK0N
Vender Size Quanta P/N Vender P/N
R453 *short_4 CLK_PCIE_WLANP_C W4
[22] CLK_PCIE_WLANP
R454 *short_4 CLK_PCIE_WLANN_C W3
GPP_CLK1P WND 8M AKE5EZN0N00 W25Q64FWSSIG
[22] CLK_PCIE_WLANN GPP_CLK1N TYP13
R451 *short_4 CLK_PCIE_SSDP_C W1 1.8V GGD 8M AKE5EG-0Q00 GD25LQ64CSIGR
[23] CLK_PCIE_SSDP GPP_CLK2P
R452 *short_4 CLK_PCIE_SSDN_C W2
[23] CLK_PCIE_SSDN GPP_CLK2N EON 8M
Y2 GPP_CLK3P
TP6
Y1 GPP_CLK3N

C623 5.6p/50V_4 TP8 BC10 X25M_48M_OSC CZ:3V_S0 CZL:3V_S5 (PD,)

USB_SS_ZVSS AD2 USBSS_CALP R470 1K/F_4
2

USB_SS_ZVDDP AD1 USBSS_CALN R471 1K/F_4

B VDDP_0.95V_S5 B
Y3 R468 48M_X1 T2 X48M_X1
48MHz USB_SS_0TXP AA3
1M/F_4 USB_SS_0TXN AA4
4

C624 5.6p/50V_4 48M_X2 T1 X48M_X2 USB_SS_0RXP W9

USB_SS_0RXN W8
Port 0 & 1 : TYP13 Only
R570 22_4 LPCCLK0 AW14 LPCCLK0/EGPIO74 CZ:3V_S0 CZL:3V_S5 USB_SS_1TXP AA2
[33] CLK_PCI_EC USB30_TX1+ [27]
R612 22_4 LPCCLK1 AY13 LPCCLK1/EGPIO75 CZ:3V_S0 CZL:3V_S5 USB_SS_1TXN AA1
[25] PCLK_TPM USB30_TX1- [27]
R594 22_4
[22] CLK_LPC_DEBUG
BB11 LAD0 (PD,) USB_SS_1RXP W5 USB3 (Charger)
[22,25,33] LPC_LAD0 USB30_RX1+ [27]
BA11 LAD1 (PD,) USB_SS_1RXN W6
[22,25,33] LPC_LAD1 USB30_RX1- [27]
AY11 LAD2 (PD,)
[22,25,33] LPC_LAD2
BA13 LAD3 CZ:3V_S0 CZL:3V_S5 (PD,) USB_SS_2TXP AC1
[22,25,33] LPC_LAD3 USB30_TX2+ [27]
AV14 LFRAME_L USB_SS_2TXN AC2
[22,25,33] LPC_LFRAME# USB30_TX2- [27]
TP44 BA1 ESPI_ALERT_L/LDRQ0_L (PD,) USB3.0
BC14 SERIRQ/AGPIO87 3V_S0 (PU,PU) USB_SS_2RXP Y6
[25,33] SERIRQ USB30_RX2+ [27]
R543 *short_4 LPC_CLKRUN#_R BC11 LPC_CLKRUN_L/AGPIO88 3V_S0 (,PU) USB_SS_2RXN Y7
[25,33] CLKRUN# USB30_RX2- [27]
AE9 LPC_PD_L/AGPIO21 3V_S5
[25] LPCPD#
USB_SS_3TXP AC4
USB30_TX3+ [28]
USB_SS_3TXN AC3
SPI_CLK USB30_TX3- [28]
BC6 SPI_CLK/ESPI_CLK/EGPIO117 (PD,) Type-C
SPI_CS# BB8 SPI_CS1_L/EGPIO118 USB_SS_3RXP AB5
USB30_RX3+ [28]
R146 10K/F_4 EGPIO119 AW7 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN AB6
CLK_LPC_DEBUG SPI_SO USB30_RX3- [28]
C688 *15P/50V_4 BA9 SPI_DI/ESPI_DATA/EGPIO120 CZ:1.8V_S0 CZL:1.8V_S5 (PD,)
C700 *15P/50V_4 PCLK_TPM SPI_SI AY7 SPI_DO/EGPIO121 (PD,)
C677 15P/50V_4 CLK_PCI_EC SPI_WP AW11 SPI_WP_L/EGPIO122 (PD,)
SPI_HOLD# BA7 SPI_HOLD_L/EGPIO133 (PD,)
20160205_EMI R173 10K/F_4 AGPIO76 AW12 SPI_TPM_CS_L/AGPIO76 CZ:3V_S0 CZL:3V_S5
FP4 REV 0.93

SP@FP4

C C

STRAPS PINS
+3V +3V +3V +3V_S5 +3V_S5 +3V_S5 +3V_S5

R581 R593 R613 R117 R98 R430 R105

*10K/F_4 10K/F_4 10K/F_4 10K/F_4 10K/F_4 10K/F_4 10K/F_4
Int pull-up Int pull-up Int pull-up Int pull-up

LPC_CLK0 LPC_CLK1 LFRAME# RTC_CLK GEVENT2# (AGPIO3) SYS_RST# AGPIO11(BLINK)

LPCCLK0
CZ-L TYP13
LPCCLK1

LPC_LFRAME# BOOT Fail Timer Internal CLKGEN SPI ROM Coin battery 1.8V SPI ROM Enhanced Reset logic normal reset mode LDT_RST#/LDT_PWRGD
PU ENABLE is on board. output to APU
[5] RTC_CLK
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
[5] GEVENT2#
BOOT Fail Timer External CLKGEN LPC ROM Coin battery 3.3V SPI ROM Traditional Reset logic
[5] SYS_RST# PD DISABLE isn't on board. short reset mode LDT_RST#/LDT_PWRGD
output to Pads
[5] AGPIO11
DEFAULT DEFAULT

R587 R559 R614 R116 R103 R431 R108

2K/F_4 *2K/F_4 *2K/F_4 *2K/F_4 *2K/F_4 *2K/F_4 *2K/F_4

D D

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
FP4 SATA/USB/LPC/SPI(5/7)
Date: Thursday, March 03, 2016 Sheet 6 of 45
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

(CPU) +1.2VSUS

P25
P28
T24
VDDIO_MEM_S3_1
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
U31F

POWER
VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
U8
W7
W12
VDDCR_CPU

Place under APU

22 uF * 9
0.22 uF * 8
7
C295 C291 C292 C296 C293 C294 C313 C330 T27 VDDIO_MEM_S3_4 VDDCR_CPU_4 W15 C248 C267 C268 C269 C249 180 pF * 1
22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 U25 VDDIO_MEM_S3_5 VDDCR_CPU_5 W18 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 47U/6.3V_8 47U/6.3V_8
U28 VDDIO_MEM_S3_6 VDDCR_CPU_6 W21
V30 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y8
V33 Y10
22 uF * 8 for EMI reserve W24
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDCR_CPU_8
VDDCR_CPU_9 Y13
0.22 uF * 6 W27
Y25
VDDIO_MEM_S3_10 VDDCR_CPU_10 Y16
Y19
180 pF * 1 Y28
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDCR_CPU_11
VDDCR_CPU_12 Y22
C300 C727 C297 C314 C322 C315 C728 C729 C329 C299 C730 Y30 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB7 C251 C234 C232 C236
A A
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 AB24 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB9 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6
AB27 VDDIO_MEM_S3_15 VDDCR_CPU_15 AB12
AB30 VDDIO_MEM_S3_16 VDDCR_CPU_16 AB15
AB33 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB18
AD25 VDDIO_MEM_S3_18 VDDCR_CPU_18 AB21
AD28 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD6
VDDP_0.95V AD30 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD10
AE24 VDDIO_MEM_S3_21 VDDCR_CPU_21 AD13
AE27 VDDIO_MEM_S3_22 VDDCR_CPU_22 AD16 C217 C221 C219 C210 C209
AF30 AD19 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4
10 uF * 4 AF33
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDCR_CPU_23
VDDCR_CPU_24 AD22
0.22 uF * 6 C692
22u/6.3V_6
C704
22u/6.3V_6
C705
22u/6.3V_6
C706
22u/6.3V_6
C285
10u/6.3V_4
C275
10u/6.3V_4
C311
0.22u/10V_4
C319
0.22u/10V_4
C287
0.22u/10V_4
C290
0.22u/10V_4
C289
180P/50V_4
AG25
AG28
VDDIO_MEM_S3_25 VDDCR_CPU_25 AE7
AE12
180 pF * 1 AH24
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDCR_CPU_26
VDDCR_CPU_42 AK9
AH27 VDDIO_MEM_S3_28 VDDCR_CPU_31 AG10
TYP1 UMA & DIS tied to VDDP. (Stuff R1,C1,C2) AH30 VDDIO_MEM_S3_29 VDDCR_CPU_43 AK10
VDDP_0.95V TYP3: Left unconencted. (DNI R1, R2, C1, C2) AK25 VDDIO_MEM_S3_30 VDDCR_CPU_32 AG13
R1 AK28 VDDIO_MEM_S3_31 VDDCR_CPU_44 AK13 C233 C220 C206 C242
R59 CZ@0_8 VDDP_GFX 1.5A AK30 VDDIO_MEM_S3_32 VDDCR_CPU_33 AG16 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 180P/50V_4
AK33 VDDIO_MEM_S3_33 VDDCR_CPU_45 AK16
R2 C1 C2 AL27 VDDIO_MEM_S3_34 VDDCR_CPU_34 AG19
R61 C106 C183 AM30 VDDIO_MEM_S3_35 VDDCR_CPU_46 AK19
R634 *short_4 +VDDIO_AZ R213 *short_4 200mA *SP@0_4 CZ@10U/6.3V_4 CZ@0.22u/10V_4 VDDCR_CPU_35 AG22
+1.5V +3V +VDDIO_AZ AR19 VDDIO_AUDIO VDDCR_CPU_47 AK22
200mA VDDCR_CPU_36 AH7
C709 C708 C298 C324 AE6 VDDP_GFX_2 VDDCR_CPU_28 AE18
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_4 AE5 VDDP_GFX_1 VDDCR_CPU_29 AE21
VDDCR_CPU_40 AH21
AP19 VDD_33_1 VDDCR_CPU_30 AG6
VDD_18 VDD_33 AP21 VDD_33_2 VDDCR_CPU_37 AH12
VDDCR_CPU_49 AN6
1.5A AP16 VDD_18_1 VDDCR_CPU_38 AH15
AP18 VDD_18_2 VDDCR_CPU_39 AH18
VDDCR_CPU_48 AL7
C265 C260 500mA AP10 VDD_18_S5_1 VDDCR_CPU_41 AK6
10U/6.3V_4 0.22u/10V_4 AR9 VDD_18_S5_2 VDDCR_CPU_27 AE15
VDDCR_GFX
B 200mA AP15 VDD_33_S5_1 Place under APU B
AR15 L8
VDD_33_S5_2 VDDCR_GFX_14
VDDCR_GFX_15 L13 22 uF * 9
800mA AN12
AP12
VDDP_S5_1 VDDCR_GFX_16 L16
L19 C271 C235 C239 C252
0.22 uF * 9
VDDP_S5_2 VDDCR_GFX_17
VDDCR_FCH_S5 VDDCR_FCH_ALW VDDCR_GFX_18 L22 CZ@47U/6.3V_8 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@47U/6.3V_8 180 pF * 1
VDD_18_S5 +3V_S5 VDDP_0.95V_S5 AP13 VDDCR_FCH_S5_1 VDDCR_GFX_19 N7
R142 *0_4 AR12 VDDCR_FCH_S5_2 VDDCR_GFX_20 N12
VDDCR_GFX_21 N15
C240 C230 C241 AW19 VDDP_6 VDDCR_GFX_22 N18
VDDP_0.95V AU17 VDDP_1 VDDCR_GFX_23 N21
C203 C202 C254 C256 C211 C215 22u/6.3V_6 22u/6.3V_6 0.22u/10V_4 AU19 VDDP_2 VDDCR_GFX_24 P8
10U/6.3V_4 0.22u/10V_4 10U/6.3V_4 0.22u/10V_4 22u/6.3V_6 0.22u/10V_4 7A AV17 VDDP_3 VDDCR_GFX_25 P13
AV19 VDDP_4 VDDCR_GFX_26 P16 C253 C255 C270 C266 C195
AW17 VDDP_5 VDDCR_GFX_27 P19 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@22U/6.3V_6
VDDCR_GFX_28 P22
AL12 VDDCR_NB_1 VDDCR_GFX_29 T7
VDDCR_NB AL13 VDDCR_NB_2 Type 1 only VDDCR_GFX_1 F12
Place under APU AL15 VDDCR_NB_3 VDDCR_GFX_2 F15
AL18 VDDCR_NB_4 VDDCR_GFX_3 G11
AL21 VDDCR_NB_5 VDDCR_GFX_4 G14
AN13 J8
22 uF * 4 C71 C187 C283 C250 C191 C262 AN16
VDDCR_NB_6
VDDCR_NB_7
VDDCR_GFX_5
VDDCR_GFX_6 J9 C196 C197 C198 C199 C200
0.22 uF * 8 0.22u/10V_4 0.22u/10V_4 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 AN19
AN22
VDDCR_NB_8 VDDCR_GFX_7 J11
K7
CZ@0.22u/10V_4 CZ@0.22u/10V_4 CZ@0.22u/10V_4 CZ@0.22u/10V_4 CZ@0.22u/10V_4

180 pF * 1 VDDCR_NB_9 VDDCR_GFX_8

VDDCR_GFX_9 K12
VDDCR_GFX_10 K13
AR17 VDDBT_RTC_G VDDCR_GFX_11 K15
VDDCR_GFX_12 K16
VDDCR_GFX_30 T12
C243 VDDCR_GFX_31 T15
C308 C274 C259 C284 C288 C245 C312 0.22u/10V_4 VDDCR_GFX_32 T18 C227 C228 C226 C238 C304
180P/50V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 VDDCR_GFX_33 T21 CZ@0.22u/10V_4 CZ@0.22u/10V_4 CZ@0.22u/10V_4 CZ@0.22u/10V_4 CZ@180P/50V_4
VDDCR_GFX_34 U13
VDDCR_GFX_35 U16
VDDCR_GFX_36 U19
VDDCR_GFX_37 U22
VDDCR_GFX_13 K19
C C
FP4 REV 0.93

SP@FP4

+1.2VSUS DECOUPLING BETWEEN PROCESSOR AND DIMMs Q27

ACROSS VDDIO AND VSS SPLIT AP2138N-1.5TRG1
RTC (RTC) +3VRTC
+3VPCU_R R344 *short_4
C725 C717 C301 C318 C380 C302 20MIL R330 1K/F_4 +1.5V_RTC 1 3
+3VPCU
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 180P/50V_4 180P/50V_4 +VCCRTC_2
20MIL 20MIL
+1.5V_RTC_RST#

D9
C482 BAT54CW 20MIL
1U/6.3V_4

2
C481
1

4x0.22UF (0402)+2x180PF(0402) 1U/6.3V_4 R345

1K/F_4

G1

+BAT
2

VDDCR_NB *SHORT_PAD
3

For EC reset RTC

[33] CLR_CMOS
2 20MIL
C188 C122 C190 C96 C77
0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 0.22u/10V_4 Q26
R348 2N7002K

1
100K/F_4
1

ACROSS VDDNB AND VSS SPLIT

RTC CR2032 Coin Battery CN1
RTC_2032
DBV: AHL03003057
VDE: AHL03003003

2
JHT: AHL03003035

D D

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
FP4 POWER(6/7)
Date: Thursday, March 03, 2016 Sheet 7 of 45
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

(CPU)
U31G U31H
8
U31J
GND GND
A8 VSS_1 VSS_63 L28 AE10 VSS_125 VSS_187 AV30
A A12 M4 AE13 AV33 U30 RSVD_2
A
VSS_2 VSS_64 VSS_126 VSS_188
A16 VSS_3 VSS_65 M30 AE16 VSS_127 VSS_189 AW22 U31 RSVD_3
A20 VSS_4 VSS_66 N10 AE19 VSS_128 VSS_190 AY4 AN30 RSVD_4
A24 VSS_5 VSS_67 N13 AE22 VSS_129 VSS_191 AY6
A28 VSS_6 VSS_68 N16 AF1 VSS_130 VSS_192 AY8
A32 VSS_7 VSS_69 N19 AF4 VSS_131 VSS_193 AY10
B2 VSS_8 VSS_70 N22 AG9 VSS_132 VSS_194 AY12
B8 VSS_9 VSS_71 N27 AG12 VSS_133 VSS_195 AY14
B12 VSS_10 VSS_72 P1 AG15 VSS_134 VSS_196 AY16
B33 VSS_11 VSS_73 P2 AG18 VSS_135 VSS_197 AY20
C3 VSS_12 VSS_74 P4 AG21 VSS_136 VSS_198 AY22 FP4 REV 0.93
D4 VSS_13 VSS_75 P5 AH4 VSS_137 VSS_199 AY24
D6 VSS_14 VSS_76 P12 AH10 VSS_138 VSS_200 AY26 SP@FP4
D8 VSS_15 VSS_77 P15 AH13 VSS_139 VSS_201 AY28
D10 VSS_16 VSS_78 P18 AH16 VSS_140 VSS_202 AY30
D12 VSS_17 VSS_79 P21 AH19 VSS_141 VSS_203 BB1
D14 VSS_18 VSS_80 P30 AH22 VSS_142 VSS_204 BB33
D16 VSS_19 VSS_81 P33 AK1 VSS_143 VSS_205 BC4
D18 VSS_20 VSS_82 T4 AK4 VSS_144 VSS_206 BC8
D20 VSS_21 VSS_83 T10 AK12 VSS_145 VSS_207 BC12
D22 VSS_22 VSS_84 T13 AK15 VSS_146 VSS_208 BC16
D24 VSS_23 VSS_85 T16 AK18 VSS_147 VSS_209 BC20
D26 VSS_24 VSS_86 T19 AL16 VSS_148 VSS_210 BC24
D28 VSS_25 VSS_87 T22 AL19 VSS_149 VSS_211 BC28
B B
D30 VSS_26 VSS_88 T30 AL22 VSS_150 VSS_212 BC32
F1 VSS_27 VSS_89 U5 AM4 VSS_151
F2 VSS_28 VSS_90 U12 AN9 VSS_152
F4 VSS_29 VSS_91 U15 AN10 VSS_153
F9 VSS_30 VSS_92 U18 AN15 VSS_154
F19 VSS_31 VSS_93 U21 AN18 VSS_155
F22 VSS_32 VSS_94 U24 AN21 VSS_156
F25 VSS_33 VSS_95 V1 AN25 VSS_157
F30 VSS_34 VSS_96 V2 AN28 VSS_158
F33 VSS_35 VSS_97 V4 AP1 VSS_159
G7 VSS_36 VSS_98 W10 AP2 VSS_160
G17 VSS_37 VSS_99 W13 AP4 VSS_161
G20 VSS_38 VSS_100 W16 AP7 VSS_162
G23 VSS_39 VSS_101 W19 AP22 VSS_163
G26 VSS_40 VSS_102 W22 AP27 VSS_164
H4 VSS_41 VSS_103 Y4 AP30 VSS_165
H30 VSS_42 VSS_104 Y5 AP33 VSS_166
J5 VSS_43 VSS_105 Y12 AR6 VSS_167
J15 VSS_44 VSS_106 Y15 AR25 VSS_168
J19 VSS_45 VSS_107 Y18 AR28 VSS_169
J22 VSS_46 VSS_108 Y21 AT4 VSS_170
J25 VSS_47 VSS_109 Y24 AT19 VSS_171
J28 VSS_48 VSS_110 AB1 AT22 VSS_172
C K1 VSS_49 VSS_111 AB2 AT30 VSS_173 C
K2 VSS_50 VSS_112 AB4 AU5 VSS_174
K4 VSS_51 VSS_113 AB10 AU8 VSS_175
K10 VSS_52 VSS_114 AB13 AU11 VSS_176
K22 VSS_53 VSS_115 AB16 AU14 VSS_177
K27 VSS_54 VSS_116 AB19 AU20 VSS_178
K30 VSS_55 VSS_117 AB22 AU23 VSS_179
K33 VSS_56 VSS_118 AD4 AU27 VSS_180
L5 VSS_57 VSS_119 AD9 AV4 VSS_181
L12 VSS_58 VSS_120 AD12 AV7 VSS_182
L15 VSS_59 VSS_121 AD15 AV9 VSS_183
L18 VSS_60 VSS_122 AD18 AV12 VSS_184 VSS_213 L24
L21 VSS_61 VSS_123 AD21 AV15 VSS_185 VSS_215 AL10
L25 VSS_62 VSS_124 AD24 AV25 VSS_186 VSS_214 AK21

FP4 REV 0.93 FP4 REV 0.93

SP@FP4 SP@FP4

D D

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
FP4 GND(7/7)
Date: Monday, February 15, 2016 Sheet 8 of 45
1 2 3 4 5 6 7 8
 5 4 3 2 1

SODIMM (SDM)
[3] M_A_A[13:0]
M_A_A0 144
JDIM1A
8 M_A_DQ0
M_A_DQ[63:0] [3] +1.2VSUS
JDIM1B
+3V

R236
*shortCZ@0_4
9
M_A_A1 133 A0 DQ0 7 M_A_DQ1 111
M_A_A2 132 A1 DQ1 20 M_A_DQ2 2250mA 112 VDD1
M_A_A3 131 A2 DQ2 21 M_A_DQ3 117 VDD2
M_A_A4 128 A3 DQ3 4 M_A_DQ4 0-7 118 VDD3 255 C384 CZ@1U/6.3V_4
M_A_A5 126 A4 DQ4 3 M_A_DQ5 123 VDD4 VDDSPD
M_A_A6 127 A5 DQ5 16 M_A_DQ6 124 VDD5
M_A_A7 122 A6 DQ6 17 M_A_DQ7 129 VDD6 257
A7 DQ7 VDD7 VPP1 +2.5VSUS
M_A_A8 125 28 M_A_DQ8 130 259 (+2.5V_SUS)
M_A_A9 A8 DQ8 M_A_DQ9 VDD8 VPP2 C775 CZ@1U/6.3V_4
121
A9 DQ9
29 135
VDD9
0.5A
M_A_A10 146 41 M_A_DQ10 136
D M_A_A11 120 A10/AP DQ10 42 M_A_DQ11 8-15 141 VDD10 258 D
M_A_A12 119 A11 DQ11 24 M_A_DQ12 142 VDD11 VTT +SMDDR_VTT 0.6A
M_A_A13 158 A12 DQ12 25 M_A_DQ13 147 VDD12
151 A13 DQ13 38 M_A_DQ14 148 VDD13
[3] M_A_WE# A14/WE# DQ14 M_A_DQ15 VDD14 +VREF_CA_A0
156 37 153 164
[3] M_A_CAS# A15/CAS# DQ15 M_A_DQ16 VDD15 VREF_CA
152 50 154
[3] M_A_RAS# A16/RAS# DQ16 49 M_A_DQ17 159 VDD16
162 DQ17 62 M_A_DQ18 160 VDD17 C410
TP41 165 S2#/C0 DQ18 63 M_A_DQ19 16-23 163 VDD18
TP40 S3#/C1 DQ19 VDD19 CZ@1000p/50V_4
+1.2VSUS 46 M_A_DQ20
DQ20 45 M_A_DQ21
[3] MEM_MA_ACT#

DDR4 SODIMM 260 PIN

114 DQ21 58 M_A_DQ22 1 2
R251 CZ@1K/F_4 M_A_ALERT# R678 *shortCZ@0_4 M_A_PARITY 143 ACT# DQ22 59 M_A_DQ23 5 VSS1 VSS48 6
M_A_ALERT# 116 PARITY DQ23 70 M_A_DQ24 9 VSS2 VSS49 10
R252 CZ@1K/F_4 M_A_EVENT# M_A_EVENT# 134 ALERT# DQ24 71 M_A_DQ25 15 VSS3 VSS50 14
[3] M_A_EVENT# 108 EVENT# DQ25 83 M_A_DQ26 19 VSS4 VSS51 18
[3] M_A_RESET# RESET# DQ26 84 M_A_DQ27 24-31 23 VSS5 VSS52 22

DDR4 SODIMM 260 PIN

DQ27 66 M_A_DQ28 27 VSS6 VSS53 26
DQ28 67 M_A_DQ29 31 VSS7 VSS54 30
DQ29 79 M_A_DQ30 35 VSS8 VSS55 36
DQ30 80 M_A_DQ31 39 VSS9 VSS56 40
DQ31 174 M_A_DQ32 43 VSS10 VSS57 44
DQ32 173 M_A_DQ33 47 VSS11 VSS58 48
DQ33 187 M_A_DQ34 51 VSS12 VSS59 52
DQ34 186 M_A_DQ35 57 VSS13 VSS60 56
DQ35 170 M_A_DQ36 33-39 61 VSS14 VSS61 60
DQ36 169 M_A_DQ37 65 VSS15 VSS62 64

(260P)
DQ37 183 M_A_DQ38 69 VSS16 VSS63 68
DQ38 182 M_A_DQ39 73 VSS17 VSS64 72
DQ39 195 M_A_DQ40 77 VSS18 VSS65 78
150 DQ40 194 M_A_DQ41 81 VSS19 VSS66 82
[3] M_A_BS#0 145 BA0 DQ41 207 M_A_DQ42 85 VSS20 VSS67 86
[3] M_A_BS#1 BA1 DQ42 M_A_DQ43 VSS21 VSS68
115 208 89 90

(260P)
[3] M_MA_BG0 113 BG0 DQ43 191 M_A_DQ44 40-47 93 VSS22 VSS69 94
[3] M_MA_BG1 BG1 DQ44 M_A_DQ45 VSS23 VSS70
190 99 98
149 DQ45 203 M_A_DQ46 103 VSS24 VSS71 102
[3] M_A0_CS#0 157 S0# DQ46 204 M_A_DQ47 107 VSS25 VSS72 106
[3] M_A0_CS#1 S1# DQ47 M_A_DQ48 VSS26 VSS73
C 109 216 167 168 C
[3] M_A_CKE0 110 CKE0 DQ48 215 M_A_DQ49 171 VSS27 VSS74 172
[3] M_A_CKE1 CKE1 DQ49 M_A_DQ50 VSS28 VSS75
228 175 176
137 DQ50 229 M_A_DQ51 48-55 181 VSS29 VSS76 180
[3] M_A_CLK0 139 CK0 DQ51 211 M_A_DQ52 185 VSS30 VSS77 184
[3] M_A_CLK0# CK0# DQ52 M_A_DQ53 VSS31 VSS78
138 212 189 188
[3] M_A_CLK1 140 CK1 DQ53 224 M_A_DQ54 193 VSS32 VSS79 192
[3] M_A_CLK1# CK1# DQ54 M_A_DQ55 VSS33 VSS80
225 197 196
155 DQ55 237 M_A_DQ56 201 VSS34 VSS81 202
[3] M_A_ODT0 161 ODT0 DQ56 236 M_A_DQ57 205 VSS35 VSS82 206
[3] M_A_ODT1 ODT1 DQ57 M_A_DQ58 VSS36 VSS83
249 209 210
253 DQ58 250 M_A_DQ59 213 VSS37 VSS84 214
[5,10,20,25] CLK_SCLK SCL DQ59 M_A_DQ60 56-63 VSS38 VSS85
254 232 217 218
[5,10,20,25] CLK_SDATA SDA DQ60 M_A_DQ61 VSS39 VSS86
233 223 222
256 DQ61 245 M_A_DQ62 227 VSS40 VSS87 226
260 SA0 DQ62 246 M_A_DQ63 231 VSS41 VSS88 230
166 SA1 DQ63 235 VSS42 VSS89 234
SA2 M_A_DQS0 M_A_DQS[7:0] [3] VSS43 VSS90
13 239 238
92 DQS0 34 M_A_DQS1 243 VSS44 VSS91 244
91 CB0 DQS1 55 M_A_DQS2 247 VSS45 VSS92 248
101 CB1 DQS2 76 M_A_DQS3 251 VSS46 VSS93 252
105 CB2 DQS3 179 M_A_DQS4 VSS47 VSS94
88 CB3 DQS4 200 M_A_DQS5
87 CB4 DQS5 221 M_A_DQS6
100 CB5 DQS6 242 M_A_DQS7 261
104 CB6 DQS7 97 GND 262
CB7 DQS8 GND
[3] M_A_DM[7..0] M_A_DM0 M_A_DQS#0 M_A_DQS#[7:0] [3]
12 11
M_A_DM1 33 DM0 DQS#0 32 M_A_DQS#1 CZ@DDR4-DIMM1_H=5.2_RVS
M_A_DM2 54 DM1 DQS#1 53 M_A_DQS#2
M_A_DM3 75 DM2 DQS#2 74 M_A_DQS#3
M_A_DM4 178 DM3 DQS#3 177 M_A_DQS#4
M_A_DM5 199 DM4 DQS#4 198 M_A_DQS#5
M_A_DM6 220 DM5 DQS#5 219 M_A_DQS#6
M_A_DM7 241 DM6 DQS#6 240 M_A_DQS#7
96 DM7 DQS#7 95
DM8 DQS#8
CZ@DDR4-DIMM1_H=5.2_RVS
B B

ADDRESS A0

+1.2VSUS +1.2VSUS
Place these Caps near So-Dimm A +SMDDR_VTT

C417 C418
From Power Chip (+0.6V) R263
C377 C378 C379 C381 C376 C367 CZ@1K/F_4
CZ@0.1u/16V_4 CZ@0.1u/16V_4 CZ@0.1u/16V_4 CZ@0.1u/16V_4 CZ@0.1u/16V_4 CZ@0.1u/16V_4 CZ@4.7U/6.3V_4 CZ@0.1u/16V_4 +SMDDR_VREF

R270 *CZ@0_6 +VREF_CA_A0

3mA
+1.2VSUS R264
+2.5VSUS C412 C411
(+MEM_VPP) CZ@1K/F_4
CZ@0.1u/16V_4 CZ@0.1u/16V_4

A C409 C776 C774 A

C402 C401 C773 C404 C405 C406
*CZ@0.1u/16V_4 *CZ@0.1u/16V_4 *CZ@0.1u/16V_4 *CZ@0.1u/16V_4 *CZ@0.1u/16V_4 *CZ@0.1u/16V_4 CZ@180P/50V_4 CZ@0.1u/16V_4 CZ@0.1u/16V_4

+1.2VSUS

C403 C327 C328 C917 C918 C919 C920 C921 Quanta Computer Inc.
CZ@180P/50V_4 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@22U/6.3V_6 CZ@22U/6.3V_6
PROJECT : ZAB
Size Document Number Rev
1A
DDR4 DIMM A0
Date: Friday, March 04, 2016 Sheet 9 of 45
5 4 3 2 1
 5 4 3 2 1

SODIMM (SDM)
[3] M_B_A[13:0]
M_B_A0 144
JDIM2A
8 M_B_DQ0
M_B_DQ[63:0] [3] +1.2VSUS
JDIM2B
+3V

R289
*short_4
10
M_B_A1 133 A0 DQ0 7 M_B_DQ1 111
M_B_A2 132 A1 DQ1 20 M_B_DQ2 2250mA 112 VDD1
M_B_A3 131 A2 DQ2 21 M_B_DQ3 117 VDD2
M_B_A4 128 A3 DQ3 4 M_B_DQ4 118 VDD3 255 C433 1U/6.3V_4
A4 DQ4
0-7 VDD4 VDDSPD
M_B_A5 126 3 M_B_DQ5 123
M_B_A6 127 A5 DQ5 16 M_B_DQ6 124 VDD5
M_B_A7 122 A6 DQ6 17 M_B_DQ7 129 VDD6 257
A7 DQ7 VDD7 VPP1 +2.5VSUS
M_B_A8 125 28 M_B_DQ8 130 259 (+2.5V_SUS)
M_B_A9 A8 DQ8 M_B_DQ9 VDD8 VPP2 C429 1U/6.3V_4
121
A9 DQ9
29 135
VDD9
0.5A
M_B_A10 146 41 M_B_DQ10 136
D M_B_A11 120 A10/AP DQ10 42 M_B_DQ11 141 VDD10 258 D
A11 DQ11
8-15 VDD11 VTT +SMDDR_VTT 0.6A
M_B_A12 119 24 M_B_DQ12 142
M_B_A13 158 A12 DQ12 25 M_B_DQ13 147 VDD12
151 A13 DQ13 38 M_B_DQ14 148 VDD13
[3] M_B_WE# A14/WE# DQ14 M_B_DQ15 VDD14 +VREF_CA_B0
156 37 153 164
[3] M_B_CAS# A15/CAS# DQ15 M_B_DQ16 VDD15 VREF_CA
152 50 154
[3] M_B_RAS# A16/RAS# DQ16 49 M_B_DQ17 159 VDD16 C818
162 DQ17 62 M_B_DQ18 160 VDD17
TP81 165 S2#/C0 DQ18 63 M_B_DQ19 163 VDD18
16-23 1000p/50V_4
+1.2VSUS TP43 S3#/C1 DQ19 M_B_DQ20 VDD19
46
DQ20 45 M_B_DQ21
[3] MEM_MB_ACT#

DDR4 SODIMM 260 PIN

114 DQ21 58 M_B_DQ22 1 2
R760 1K/F_4 M_B_ALERT# R312 *short_4 M_B_PARITY 143 ACT# DQ22 59 M_B_DQ23 5 VSS1 VSS48 6
M_B_ALERT# 116 PARITY DQ23 70 M_B_DQ24 9 VSS2 VSS49 10
R761 1K/F_4 M_B_EVENT# M_B_EVENT# 134 ALERT# DQ24 71 M_B_DQ25 15 VSS3 VSS50 14
[3] M_B_EVENT# 108 EVENT# DQ25 83 M_B_DQ26 19 VSS4 VSS51 18
[3] M_B_RESET# RESET# DQ26 84 M_B_DQ27 23 VSS5 VSS52 22
24-31

DDR4 SODIMM 260 PIN

DQ27 66 M_B_DQ28 27 VSS6 VSS53 26
DQ28 67 M_B_DQ29 31 VSS7 VSS54 30
DQ29 79 M_B_DQ30 35 VSS8 VSS55 36
DQ30 80 M_B_DQ31 39 VSS9 VSS56 40
DQ31 174 M_B_DQ32 43 VSS10 VSS57 44
DQ32 173 M_B_DQ33 47 VSS11 VSS58 48
DQ33 187 M_B_DQ34 51 VSS12 VSS59 52
DQ34 186 M_B_DQ35 57 VSS13 VSS60 56
DQ35 170 M_B_DQ36 61 VSS14 VSS61 60
DQ36
33-39 VSS15 VSS62
169 M_B_DQ37 65 64

(260P)
DQ37 183 M_B_DQ38 69 VSS16 VSS63 68
DQ38 182 M_B_DQ39 73 VSS17 VSS64 72
DQ39 195 M_B_DQ40 77 VSS18 VSS65 78
150 DQ40 194 M_B_DQ41 81 VSS19 VSS66 82
[3] M_B_BS#0 145 BA0 DQ41 207 M_B_DQ42 85 VSS20 VSS67 86
[3] M_B_BS#1 BA1 DQ42 M_B_DQ43 VSS21 VSS68
115 208 89 90

(260P)
[3] M_MB_BG0 113 BG0 DQ43 191 M_B_DQ44 93 VSS22 VSS69 94
[3] M_MB_BG1 BG1 DQ44
40-47 VSS23 VSS70
190 M_B_DQ45 99 98
149 DQ45 203 M_B_DQ46 103 VSS24 VSS71 102
[3] M_B0_CS#0 157 S0# DQ46 204 M_B_DQ47 107 VSS25 VSS72 106
[3] M_B0_CS#1 S1# DQ47 M_B_DQ48 VSS26 VSS73
C 109 216 167 168 C
[3] M_B_CKE0 110 CKE0 DQ48 215 M_B_DQ49 171 VSS27 VSS74 172
[3] M_B_CKE1 CKE1 DQ49 M_B_DQ50 VSS28 VSS75
228 175 176
137 DQ50 229 M_B_DQ51 181 VSS29 VSS76 180
[3] M_B_CLK0 CK0 DQ51
48-55 VSS30 VSS77
139 211 M_B_DQ52 185 184
[3] M_B_CLK0# CK0# DQ52 M_B_DQ53 VSS31 VSS78
138 212 189 188
[3] M_B_CLK1 140 CK1 DQ53 224 M_B_DQ54 193 VSS32 VSS79 192
[3] M_B_CLK1# CK1# DQ54 M_B_DQ55 VSS33 VSS80
225 197 196
155 DQ55 237 M_B_DQ56 201 VSS34 VSS81 202
[3] M_B0_ODT0 161 ODT0 DQ56 236 M_B_DQ57 205 VSS35 VSS82 206
[3] M_B0_ODT1 ODT1 DQ57 M_B_DQ58 VSS36 VSS83
249 209 210
253 DQ58 250 M_B_DQ59 213 VSS37 VSS84 214
[5,9,20,25] CLK_SCLK SCL DQ59 M_B_DQ60 VSS38 VSS85
254 232 56-63 217 218
[5,9,20,25] CLK_SDATA SDA DQ60 M_B_DQ61 VSS39 VSS86
233 223 222
R764 4.7K_4 M_B0_SA0 256 DQ61 245 M_B_DQ62 227 VSS40 VSS87 226
+3V SA0 DQ62 M_B_DQ63 VSS41 VSS88
260 246 231 230
166 SA1 DQ63 235 VSS42 VSS89 234
SA2 M_B_DQS0 M_B_DQS[7:0] [3] VSS43 VSS90
13 239 238
92 DQS0 34 M_B_DQS1 243 VSS44 VSS91 244
91 CB0 DQS1 55 M_B_DQS2 247 VSS45 VSS92 248
101 CB1 DQS2 76 M_B_DQS3 251 VSS46 VSS93 252
105 CB2 DQS3 179 M_B_DQS4 VSS47 VSS94
88 CB3 DQS4 200 M_B_DQS5
87 CB4 DQS5 221 M_B_DQS6
100 CB5 DQS6 242 M_B_DQS7 261
104 CB6 DQS7 97 GND 262
CB7 DQS8 GND
[3] M_B_DM[7..0] M_B_DM0 M_B_DQS#0 M_B_DQS#[7:0] [3]
12 11
M_B_DM1 33 DM0 DQS#0 32 M_B_DQS#1 DDR4-DIMM2_H=5.2_STD
M_B_DM2 54 DM1 DQS#1 53 M_B_DQS#2
M_B_DM3 75 DM2 DQS#2 74 M_B_DQS#3
M_B_DM4 178 DM3 DQS#3 177 M_B_DQS#4
M_B_DM5 199 DM4 DQS#4 198 M_B_DQS#5
M_B_DM6 220 DM5 DQS#5 219 M_B_DQS#6
M_B_DM7 241 DM6 DQS#6 240 M_B_DQS#7
96 DM7 DQS#7 95
DM8 DQS#8
DDR4-DIMM2_H=5.2_STD
B B

ADDRESS A2

+1.2VSUS +1.2VSUS
Place these Caps near So-Dimm B +SMDDR_VTT

C464 C465
From Power Chip R313
C453 C452 C455 C456 C454 C389 1K/F_4
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 4.7U/6.3V_4 0.1u/16V_4 +SMDDR_VREF

R315 *0_6 +VREF_CA_B0

3mA
+1.2VSUS R314
+2.5VSUS 1K/F_4 C462 C817
0.1u/16V_4 0.1u/16V_4

A A
C424 C428 C427
C458 C457 C816 C459 C388 C815
*0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 180P/50V_4 0.1u/16V_4 0.1u/16V_4

+1.2VSUS

C814 C325 C326 C922 C923 C924 C925 C926

Quanta Computer Inc.
180P/50V_4 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 PROJECT : ZAB
Size Document Number Rev
1A
DDR4 DIMM B0
Date: Thursday, March 03, 2016 Sheet 10 of 45
5 4 3 2 1
 5 4 3 2 1

(VGA)
U25A
11
AF30 AH30 PEG_RXP0_C C619 EV@0.22u/10V_4
D [2] PEG_TXP0 PCIE_RX0P PCIE_TX0P PEG_RXN0_C PEG_RXP0 [2] D
AE31 AG31 C618 EV@0.22u/10V_4
[2] PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 [2]

X4 : TYP3 (GEN3)
X4 : TYP2 (GEN2)
X4 : TYP3 (GEN3)
X4 : TYP2 (GEN2)

AE29 AG29 PEG_RXP1_C C612 EV@0.22u/10V_4

[2] PEG_TXP1 PCIE_RX1P PCIE_TX1P PEG_RXN1_C PEG_RXP1 [2]
AD28 AF28 C613 EV@0.22u/10V_4
[2] PEG_TXN1 PCIE_RX1N PCIE_TX1N PEG_RXN1 [2]

AD30 AF27 PEG_RXP2_C C614 EV@0.22u/10V_4

[2] PEG_TXP2 PCIE_RX2P PCIE_TX2P PEG_RXN2_C PEG_RXP2 [2]
AC31 AF26 C617 EV@0.22u/10V_4
[2] PEG_TXN2 PCIE_RX2N PCIE_TX2N PEG_RXN2 [2]

X8 : TYP1 (GEN3)
AC29 AD27 PEG_RXP3_C C589 EV@0.22u/10V_4
[2] PEG_TXP3 PCIE_RX3P PCIE_TX3P PEG_RXP3 [2]
X8 : TYP1 (GEN3)

AB28 AD26 PEG_RXN3_C C592 EV@0.22u/10V_4

[2] PEG_TXN3 PCIE_RX3N PCIE_TX3N PEG_RXN3 [2]

AB30 AC25 PEG_RXP4_C C593 EV_SP@0.22u/10V_4

[2] PEG_TXP4 PCIE_RX4P PCIE_TX4P PEG_RXN4_C PEG_RXP4 [2]
AA31 AB25 C590 EV_SP@0.22u/10V_4
[2] PEG_TXN4 PCIE_RX4N PCIE_TX4N PEG_RXN4 [2]

AA29 Y23 PEG_RXP5_C C585 EV_SP@0.22u/10V_4

[2] PEG_TXP5 PCIE_RX5P PCIE_TX5P PEG_RXP5 [2]

PCI EXPRESS INTERFACE

Y28 Y24 PEG_RXN5_C C582 EV_SP@0.22u/10V_4
[2] PEG_TXN5 PCIE_RX5N PCIE_TX5N PEG_RXN5 [2]

Y30 AB27 PEG_RXP6_C C583 EV_SP@0.22u/10V_4

C [2] PEG_TXP6 PCIE_RX6P PCIE_TX6P PEG_RXN6_C PEG_RXP6 [2] C
W31 AB26 C586 EV_SP@0.22u/10V_4
[2] PEG_TXN6 PCIE_RX6N PCIE_TX6N PEG_RXN6 [2]

W29 Y27 PEG_RXP7_C C580 EV_SP@0.22u/10V_4

[2] PEG_TXP7 PCIE_RX7P PCIE_TX7P PEG_RXN7_C PEG_RXP7 [2]
V28 Y26 C577 EV_SP@0.22u/10V_4
[2] PEG_TXN7 PCIE_RX7N PCIE_TX7N PEG_RXN7 [2]

V30 W24
U31 NC#V30 NC#W24 W23 AC-coupling capactior(depend on GenX, not TYPE)
NC#U31 NC#W23 TYP1&3:(220nF)CH4222K9B04: Only Gen3 and Both of Gen2&3
TYP2 :(100nF)CH4103K1B08: Only Gen2
U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26 +3V_GFX

P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

B P30 T24 C644 B

N31 NC#P30 NC#T24 T23
NC#N31 NC#T23 EV@0.1u/16V_4
GPU RESET

5
N29 P27 U26
M28 NC#N29 NC#P27 P26 2
NC#M28 NC#P26 [5] DGPU_RST_L
4 PERST#_BUF
PERST#_BUF [12]
[5,18,21,22,23] PCIERST# 1
M30 P24
L31 NC#M30 NC#P24 P23 EV@TC7SH08FU R479

3
NC#L31 NC#P23
*EV@100K/F_4
L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26

CLOCK
[6] CLK_PCIE_VGAP AK30
AK32 PCIE_REFCLKP
[6] CLK_PCIE_VGAN PCIE_REFCLKN

CALIBRATION
Y22 PCIE_CALR_TX R37 EV@1.69K/F_4
A PCIE_CALR_TX A
R124 EV@1K/F_4 TEST_PG N10 AA22 PCIE_CALR_RX R36 EV@1K/F_4 +PCIE_VDDC_GFX
TEST_PG PCIE_CALR_RX

PERST#_BUF AL27
PERSTB
Quanta Computer Inc.
EV_SP@R16-M1-70/30_S3 PROJECT :ZAB
Size Document Number Rev
1A
R16-M1-70/-30_S3_PCIE(1/7)
Date: Friday, March 18, 2016 Sheet 11 of 45
5 4 3 2 1
 5 4 3 2 1

(VGA)
The SMBus slave ID is default 0x41
Meso SCL/SDA PU : 47k ohm (CS34702JB21)
DP_VDDR
12
Exo SCL/SDA PU: 45.3kohm (CS34532FB18)
+3V_GFX EXO MESO
10u X1 10u X1 U25G

+3V_GFX U25B
1u X1 1u X1 DP POWER NC/DP POWER
R166 0.1u X1
*EV@4.7K_4 AG15 AE11
AG16 NC_DP_VDDR#1
NC_DP_VDDR#2
NC#AE11
NC#AF11
AF11 EXTERNAL THERMAL SENSOR
R155 *shortEV@0_4 R167 AF2 AF16 AE13
[11] PERST#_BUF NC#AF2 AF4 AG17 NC_DP_VDDR#3 NC#AE13 AF13
EV_SP@45.3K/F_4 DVO +3V_GFX
NC#AF4 NC_DP_VDDR#4 NC#AF13

2
+1.8V_GFX AG18 AG8
N9 AG3 AG19 NC_DP_VDDR#5 NC#AG8 AG10
6 1 DGPUT_DATA L9 DBG_DATA16 NC#AG3 AG5 AF14 NC_DP_VDDR#6 NC#AG10
[4,33] 2ND_MBDATA DBG_DATA15 DPA NC#AG5 DP_PVDD
AE9
Q7A Y11 DBG_DATA14 AH3
D DBG_DATA13 NC#AH3 D
EV@2N7002KDW AE8 AH1 C153 C132 C139 C668
+3V_GFX AD9 DBG_DATA12 NC#AH1 EV@10U/6.3V_4 EV@1U/6.3V_4 Exo@0.1U/16V_4X
DBG_DATA11 *EV@0.1u/16V_4
AC10 AK3 U30
AD7 DBG_DATA10 NC#AK3 AK1 AG20 AF6
AC8 DBG_DATA9 NC#AK1 AG21 NC_DP_VDDC#1 NC#AF6 AF7 DGPUT_CLK 8 1 GPU_D+
R149 AC7 DBG_DATA8 AK5 +PCIE_VDDC_GFX AF22 NC_DP_VDDC#2 NC#AF7 AF8 SCLK VCC
EV_SP@45.3K/F_4 AB9 DBG_DATA7 NC#AK5 AM3 AG22 NC_DP_VDDC#3 NC#AF8 AF9 DGPUT_DATA 7 2
DBG_DATA6 NC#AM3 NC_DP_VDDC#4 NC#AF9 SDA DXP
5

Q7B AB8 AD14 C661

AB7 DBG_DATA5 AK6 DP_VDDC VGA_ALERT 6 3
3 4 DGPUT_CLK AB4 DBG_DATA4 NC#AK6 AM5 ALERT# DXN *EV@2200p/50V_4
[4,33] 2ND_MBCLK DBG_DATA3 NC#AM5
AB2 DPB C61 C127 C128 4 5
EV@2N7002KDW Y8 DBG_DATA2 AJ7 Exo@10U/6.3V_4 EV@1U/6.3V_4 EV@0.1u/16V_4 AG14 AE1 OVERT# GND GPU_D-
Y7 DBG_DATA1 NC#AJ7 AH6 AH14 NC_DP_VSSR#1 NC#AE1 AE3
R621 *EV@0_4 DGPU_OPP# DBG_DATA0 NC#AH6 AM14 NC_DP_VSSR#2 NC#AE3 AG1 *EV@G781P8
[34] GPU_THROTTING# AK8 AM16 NC_DP_VSSR#3 NC#AG1 AG6
NC#AK8 AL7 AM18 NC_DP_VSSR#4 NC#AG6 AH5
PU/PD NC#AL7 DP_VDDC AF23 NC_DP_VSSR#5
NC_DP_VSSR#6
NC#AH5
NC#AF10
AF10

3
+3V_GFX Q39 AG23 AG9
EV@2N7002K W6 DPC
EXO MESO AM20 NC_DP_VSSR#7 NC#AG9 AH8
V6 NC#W6 AM22 NC_DP_VSSR#8 NC#AH8 AM6
NC#V6 10u X1 1u X1 NC_DP_VSSR#9 NC#AM6
R620 EV@10K/F_4 DGPU_OPP# R619 *EV@10K/F_4 DGPU_OPP 2 V4 AM24 AM8
[33] DGPU_OPP NC#V4 U5
1u X1 0.1u X1 AF19 NC_DP_VSSR#10 NC#AM8 AG7
R518 *EV@10K/F_4 GPU_PWM_PROCHOT# AC5 NC#U5 0.1u X1 AF20 NC_DP_VSSR#11 NC#AG7 AG11
AC6 NC#AC5 AE14 NC_DP_VSSR#12 NC#AG11
R504 *EV@10K/F_4 DGPU_TDI N#CAC6 V2 DP_VSSR

1
NC#V2
R505 *EV@10K/F_4 DGPU_TMS Y4
AA5 NC#Y4 W5
R507 *EV@10K/F_4 DGPU_TDO AA6 NC#AA5 NC#W5 AF17 AE10
AMD GAE:Debug port TDO left as floating. NC#AA6 NC_UPHYAB_DP_CALR NC#AE10
R506 *EV@10K/F_4 DGPU_TRSTB Y2
NC#Y2 J8
R640 *EV@10K/F_4 PEX_CLKREQ# R497 Meso@10K/F_4 U1 NC#J8 EV_SP@R16-M1-70/30_S3
ZYV doesn't PU PEX_CLKREQ# +1.8V_GFX NC#U1/BP_0 AA1
NC#AA1/PLL_ANALOG_IN TP46
R551 EV@10K/F_4 VGA_ALERT R519 Meso@10K/F_4 U3 AA3
R123 Y6 NC#U3/BP_1 NC#AA3/PLL_ANALOG_OUT
R143 *EV@5.1K/F_4 TESTEN NC#Y6
R127 SVC SVD Output Voltage
EV@1K/F_4 *Meso@16.2K/F_4

R622 EV@10K/F_4 TEMP_FAIL R524 *EV@10K/F_4 R1 PLL_ANALOG_OUT: Provide a pull-down 0 0 1.1 Volts
ZYV doesn't PD TEMP_FAIL +3V_GFX
R501 *EV@10K/F_4 R3 SCL
I2C resistor on the PCB (DNI).FOR TOPAZ ONLY
R515 *EV@10K/F_4 DGPU_TCK SDA
AM26 Debug port for the die 0 1 1.0 Volts
GENERAL PURPOSE I/O DCM/NC_R AK26 +3V_GFX
U6 NC_AVSSN#AK26
GPIO_0 AL25 R417 PCIeR Optimized Buffer Flush/Fill (OBFF)
C NC_G 1 0 0.9 Volts Exo Boot C
AJ25 *MESO@10K/F_4on WAKEB FOR TOPAZ ONLY
DGPUT_DATA U8 NC_AVSSN#AJ25
DGPUT_CLK U7 SMBDATA AH24
Peak Current Control (PCC) GPIO_6. DGPU_OPP# SMBCLK NC_B 1 1 0.8 Volts
T9 AG25 R403
GPIO_5_AC_BATT NC_AVSSN#AG25

2
FOR MESO ONLY [41] GPU_PWM_PROCHOT#
R509 *EV@1K/F_4 GPU_GPIO6 T8
PCC/GPIO_6 EV@4.7K_4
T7 DAC1 AH26 Q31
P10 NC_GPIO_7 NC_HSYNC AJ27 PCIE_WAKE#_GPU 1 3 PCIE_LAN_WAKE#
to power IC GPIO_8_ROMSO NC_VSYNC/WAKEb PCIE_LAN_WAKE# [5,21,22]
C647 P4
*EV@0.1u/16V_4 P2 GPIO_9_ROMSI *EV@ME2N7002DS-G_300MA
AMD GAE:GPIO_6 keep as unconnected, don’t stuff N6 GPIO_10_ROMSCK AD22
NC_GPIO_11 NC_RSET
the components on this relative circuitry N5
N3 NC_GPIO_12 AG24
R402
NC_GPIO_13 NC_AVDD *EV@10K/F_4
AE22
[33,35,40] SYS_SHDN# GPU_GPIO15 N1
GPIO_15_PWRCNTL_0
NC_AVSSQ EXO Level Shift
3

to power IC Q38 M4 AE23 +3V_GFX

*EV@ME2N7002DS-G_300MA VGA_ALERT R6 GPIO_16 NC_VDD1DI AD23 +1.8V_GFX +1.8V_GFX +1.8V_GFX
GPIO_17_THERMAL_INT NC_VSS1DI U4 +3V_GFX
2 TEMP_FAIL M2
GPU_GPIO20 P8 GPIO_19_CTF AM12 C150 1 6
P7 GPIO_20_PWRCNTL_1 NC VCCA VCCB R523 R87
+3V_GFX N8 GPIO_21 Exo@0.1U/16V_4X R63 R84 *Exo@10K/F_4
GPIO_22_ROMCSB Exo@10K/F_4
AK10 AK12 R498 Meso@0_4 GPU_SVD_R *Meso@10K/F_4 Meso@10K/F_4 GPU_SVD_R 3 4 GPU_GPIO15
1

AM10 GPIO_29 NC_SVI2#1/GPIO_SVD AL11 GPU_SVT A B +1.8V_GFX

PEX_CLKREQ# N7 GPIO_30 NC_SVI2#2/GPIO_SVT AJ11 R500 Meso@0_4 GPU_SVC_R GPU_GPIO15
PERST#_BUF D16 *EV@1N4148WS TEMP_FAIL DGPU_TRSTB L6 CLKREQB NC_SVI2#3/GPIO_SVC GPU_SVD_R 2 5 R70 Exo@10K/F_4
JTAG_TRSTB GPU_SVC_R GND OE
2

GPU_GPIO20
DGPU_TDI L5 AL13 Exo@G2129TL1U
3 1 DGPU_TCK L3 JTAG_TDI NC_GENLK_CLK AJ13 +1.8V_GFX U5 +3V_GFX
[5] PCIE_REQ_GPU# DGPU_TMS JTAG_TCK NC_GENLK_VSYNC +3V_GFX
L1 R503 R79
Q42 DGPU_TDO K4 JTAG_TMS R62 R90 1 6 Exo@10K/F_4
JTAG_TDO VCCA VCCB *Exo@10K/F_4
*EV@ME2N7002DS-G_300MA TESTEN K7 DAC2 Meso@10K/F_4 *Meso@10K/F_4
AF24 TESTEN AG13 C124
AMD GAE:CLKRFQ keep this pin as floating. NC#AF24 NC_SWAPLOCKA AH12 GPU_SVC_R 3 4 GPU_GPIO20
NC_SWAPLOCKB Exo@0.1U/16V_4X A B

W8 2 5 GPU_SVT R499 Meso@0_4

NC_GENERICB AC19 PS_0 GND OE GPU_SVD_R GPU_SVT_R [41]
PS_0 GPU_SVC_R GPU_SVD_R [41]
W7
NC_GENERICD PS_1 GPU_SVC_R [41]
AD10 AD19 Exo@G2129TL1U
GPIO_11, 12, and 13 FOR MESO ONLY, AJ9 NC_GENERICE_HPD4 PS_1
to power IC
EXO become NC AL9 NC#AJ9 AE17 PS_2
DBG_CNTL0 PS_2
AE20 PS_3
PS_3
AB16 AE19 EXO MESO PS_3[3:1] Vendor/Total Size Type Vendor P/N QCI STN B/S Rpu Rpd
TP1 PX_EN TS_A
B B
R65 (M1-30) (M1-70) 000 Hynix / 2G 256Mx16 *4,1000Mhz H5TC4G63CFR-N0C AKD5PZDTW03 NC 4.75K
AC16 *EV@0_4
C597 EV@8.2P/50V_4C EVGA-XTALI NC_DBG_VREFG
PS0[5:1] 11001 11001 001 Hynix / 4G 256Mx16 *8,1000Mhz H5TC4G63CFR-N0C AKD5PZDTW03 8.45K 2K
DDC/AUX 010 Samsung / 2G 256Mx16 *4,1000Mhz K4W4G1646E-BC1A AKD5PGDT504 4.53K 2K
AE6 PS1[5:1] 11001 11001
NC_DDC1CLK
2
1

PLL/CLOCK AE5 011 Samsung / 4G 256Mx16 *8,1000Mhz K4W4G1646E-BC1A AKD5PGDT504 6.98K 4.99K
R415 NC_DDC1DATA
Y2 EV@1M/F_4 AD2 PS2[5:1] 11000 11000 100 4.53K 4.99K
EV@27MHZ_10 NC_AUX1P AD4
NC_AUX1N
101 3.24K 5.62K
3
4

EVGA-XTALI AM28 PS3[5:1] 11xxx 11xxx

EVGA-XTALO AK28 XTALIN
C600 EV@8.2P/50V_4C EVGA-XTALO XTALOUT
AD13
R47 EV@10K/F_4 AC22 NC_AUX2P AD11
R48 EV@10K/F_4 AB22 XO_IN NC_AUX2N +1.8V_GFX +1.8V_GFX +1.8V_GFX
XO_IN2 BIT[5:4] C(nF)

00 680
Ra AE16
GPU_D+ T4 NC#AE16 AD16 R56 R67 R75
+3V_GFX R522 *Exo@10K/F_4 GPU_D- T2 DPLUS
DMINUS
THERMAL NC#AD16 EV@8.45K/F_4 R1 EV@8.45K/F_4 *EV@0_4 01 82
AC1
NC_DDCVGACLK AC3 TP47 PS_0 PS_1 PS_2
Rb GPU_GPIO28 NC_DDCVGADATA TP45
R502 Exo@10K/F_4 R5 10 10
L2 EV@BLM15AG121SN1D(120/0.5)_4 +1.8V_TSVDD AD17 GPIO28_FDO
+1.8V_GFX TSVDD
AC17
TSVSS R57 C98 R68 C117 R76 C126
1.8V(5mA TSVDD) 11 NC
C151 C138 EV@2K/F_4 *EV@0.01U/50V_4X R2 EV@2K/F_4 *EV@0.01U/50V_4X EV@4.75K/F_4 *EV@0.01U/50V_4X
C155
Exo@10U/6.3V_4 EV@1U/6.3V_4 Exo@0.1U/16V_4X
BIT[3:1] Rpu Rpd
EXO MLPS setting PD EV_SP@R16-M1-70/30_S3
GEN3(TYP1&3) : 000 NC 4750
MEXO no mount DP_VDDC R1 8.45K(CS28452FB12)
R2 2K(CS22002FB19)
EXO ONLY: stuff Ra=> disable MLPS
EXO MESO 001 8450 2000
+1.8V_GFX GEN2(CZL):
120R beed x1 1u X1 R1 NC
stuff Rb=> enable MLPS 10u X1 R2 4.75K(CS24752FB12)
1u X1 010 4530 2000
0.1u X1
Rpu R50 011 6980 4990
EV_SP@8.45K/F_4
A A
PS_3 PS_3 [5,4] should be 11 due to this is no output/audio design 100 4530 4990

R51 Quanta P/N====> 101 3240 5620

Rpd EV_SP@2K/F_4 C93 4.53K: CS24532FB08 4.99K: CS24992FB26
*EV@680n/6.3V_4
6.98K: CS26982FB01 3.24K: CS23242FB17 110 3400 10000
5.62K: CS25622FB18 8.45K: CS28452FB12
4.75K: CS24752FB12 2K: CS22002FB19 111 4750 NC

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
R16-M1-70/-30_S3_Main(2/7)
Date: Friday, March 18, 2016 Sheet 12 of 45
5 4 3 2 1
 5 4 3 2 1

(VGA)
U25E

U25F
13
AA27 A3
AB24 PCIE_VSS#1 GND#1 A30
AB32 PCIE_VSS#2 GND#2 AA13
D AC24 PCIE_VSS#3 GND#3 AA16 LVDS CONTROL D
AC26 PCIE_VSS#4 GND#4 AB10
AC27
AD25
PCIE_VSS#5
PCIE_VSS#6
GND#5
GND#6
AB15
AB6
All the ASIC supplies must reach their respective
AD32
AE27
PCIE_VSS#7
PCIE_VSS#8
GND#7
GND#8
AC9
AD6
nominal voltages within 20 ms of the start of the
AF32
AG27
PCIE_VSS#9
PCIE_VSS#10
GND#9
GND#10
AD8
AE7 NC_UPHYAB_TMDPA_TX0N
AL15
AK14
ramp-up sequence, though a shorter ramp-up
AH32
K28
PCIE_VSS#11
PCIE_VSS#12
GND#11
GND#12
AG12
AH10
NC_UPHYAB_TMDPA_TX0P
AH16
duration is preferred. The maximum slew rate on
PCIE_VSS#13 GND#13 NC_UPHYAB_TMDPA_TX1N
K32
L27 PCIE_VSS#14 GND#14
AH28
B10 NC_UPHYAB_TMDPA_TX1P
AJ15 all rails is 50 mV/µs.
M32 PCIE_VSS#15 GND#15 B12 AL17
N25 PCIE_VSS#16 GND#16 B14 NC_UPHYAB_TMDPA_TX2N AK16
N27
P25
PCIE_VSS#17
PCIE_VSS#18
GND#17
GND#18
B16
B18
NC_UPHYAB_TMDPA_TX2P
AH18
It is recommended that the 3.3-V rail ramp up first
P32 PCIE_VSS#19 GND#19 B20 NC_UPHYAB_TMDPA_TX3N AJ17
R27
T25
PCIE_VSS#20
PCIE_VSS#21
GND#20
GND#21
B22
B24
NC_UPHYAB_TMDPA_TX3P
AL19
The 3.3-V, 1.8-V, and 0.95-V rails must reach their
T32
U25
PCIE_VSS#22
PCIE_VSS#23
GND#22
GND#23
B26
B6
NC_TXOUT_L3P
NC_TXOUT_L3N
AK18 ready state at least 10 µs before VDDC, VDDCI,
U27
V32
PCIE_VSS#24
PCIE_VSS#25
GND#24
GND#25
B8
C1 TMDP
and VMEMIO start to ramp up.
W25 PCIE_VSS#26 GND#26 C32
C
W26
W27
PCIE_VSS#27
PCIE_VSS#28
GND#27
GND#28
E28
F10 NC_UPHYAB_TMDPB_TX0N
AH20
AJ19
For power down, reversing the ramp-up sequence is C

Y25
Y32
PCIE_VSS#29
PCIE_VSS#30
GND#29
GND#30
F12
F14
NC_UPHYAB_TMDPB_TX0P
AL21
recommended.
PCIE_VSS#31 GND#31 F16 NC_UPHYAB_TMDPB_TX1N AK20
GND#32 F18 NC_UPHYAB_TMDPB_TX1P
GND#33 F2 AH22
GND#34 F20 NC_UPHYAB_TMDPB_TX2N AJ21
M6 GND#35 F22 NC_UPHYAB_TMDPB_TX2P
N11 GND#56 GND#36 F24 AL23
GND#57 GND#37 F26 NC_UPHYAB_TMDPB_TX3N AK22
N13
N16 GND#58
GND#38
GND#39
F6
F8
NC_UPHYAB_TMDPB_TX3P
AK24
Power Up/Down Sequence
N18
N21
GND#59
GND#60
GND#61
GND GND#40
GND#41
GND#42
G10
G27
NC_TXOUT_U3P
NC_TXOUT_U3N
AJ23

P6 G31
P9 GND#62 GND#43 G8
R12 GND#63 GND#44 H14
R15 GND#64 GND#45 H17 EV_SP@R16-M1-70/30_S3
R17 GND#65 GND#46 H2
R20 GND#66 GND#47 H20
VDDR3
T13 GND#67 GND#48 H6 3.3V
T16 GND#68 GND#49 J27
T18 GND#69 GND#50 J31
B B
T21 GND#70 GND#51 K11
T6 GND#71 GND#52 K2
+1.8V_VGA
U15 GND#72 GND#53 K22
U17 GND#73 GND#54 K6
GND#74 GND#55 10us
U20 T11
U9 GND#75 GND#84 R11
V13 GND#76 GND#85
V16 GND#77 +PCIE_VDDC_GFX (0.95V)
V18 GND#78
Y10 GND#79
Y15 GND#80
Y17 GND#81 A32
+1.5V_GFX
Y20 GND#82 VSS_MECH#1 AM1
AA11 GND#83 VSS_MECH#2 AM32
M12 GND#86 VSS_MECH#3
V11 GND#87
GND#88
+VGA_CORE

EV_SP@R16-M1-70/30_S3 20ms
20ms

A A

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
R16-M1-70/-30_S3_GND/LVDS/Strap(3/7)
Date: Friday, March 18, 2016 Sheet 13 of 45
5 4 3 2 1
 5 4 3 2 1

(VGA)
14

D D

VDDR1 PCIE_PVDD
EXO MESO
EXO MESO 10u X1 10u X1
1u X1 1u X1
10u X1 0.1u X1
10u X3 2.2u X5
2.2u X5 0.01u X1
0.1u X1
0.1u X6 0.01u X1
U25D +1.8V_GFX
+1.5V_GFX PCIE_VDDR : 1.8V @ 100mA
MESO Power VMEMIO MEM I/O
PCIE_PVDD
PCIE
AM30
1.35V ( DDR3, MVDDQ = 1.35V@1.2A)
H13 AB23
H16 VDDR1#1 NC#AB23 AC23 C83 C84 C91 C85
H19 VDDR1#2 NC#AC23 AD24 Exo@0.1U/16V_4X EV@1U/6.3V_4 EV@10U/6.3V_4 Exo@0.01u/50V_4
C145 C53 C54 C140 C69 C159 C108 C135 J10 VDDR1#3 NC#AD24 AE24
Exo@10U/6.3V_4 Exo@10U/6.3V_4 EV@10U/6.3V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 J23
J24
VDDR1#4
VDDR1#5
NC#AE24
NC#AE25
AE25
AE26
PCIE_VDDC
J9 VDDR1#6 NC#AE26 AF25
EXO MESO
K10 VDDR1#7 NC#AF25 AG26
VDDR1#8 NC#AG26 +PCIE_VDDC_GFX
10u X2 10u X1
K23
K24 VDDR1#9
PCIE_VDDC : 0.95V @ 2.5A (GEN3.0)
1u X7 1u X6
K9 VDDR1#10 L23
C120 C118 C116 C134 C109 C92 C125 L11 VDDR1#11 PCIE_VDDC#1 L24
Meso@0.01u/50V_4 Exo@0.1U/16V_4X Exo@0.1U/16V_4X Exo@0.1U/16V_4X Exo@0.1U/16V_4X Exo@0.1U/16V_4X EV@0.1u/16V_4 L12 VDDR1#12 PCIE_VDDC#2 L25
L13 VDDR1#13 PCIE_VDDC#3 L26 C76 C75 C68 C67 C88 C79 C78 C80 C73
L20 VDDR1#14 PCIE_VDDC#4 M22 Exo@1U/6.3V_4 EV@1U/6.3V_4 EV@1U/6.3V_4 EV@1U/6.3V_4 EV@1U/6.3V_4 EV@1U/6.3V_4 EV@1U/6.3V_4 EV@10U/6.3V_4 Exo@10U/6.3V_4
L21 VDDR1#15 PCIE_VDDC#5 N22
L22 VDDR1#16 PCIE_VDDC#6 N23
VDDR1#17 PCIE_VDDC#7 N24
C C
Meso Power VDD_GPIO18 PCIE_VDDC#8
PCIE_VDDC#9
R22
T22
VDDC
+1.8V_GFX LEVEL PCIE_VDDC#10 U22 MESO Power VDDC EXO MESO
VDD_CT VDD_GPIO18 @13mA
AA20
TRANSLATION PCIE_VDDC#11
PCIE_VDDC#12
V22
+VGPU_CORE
10u X4 10u X6
EXO MESO AA21 VDD_CT#1
VDDC+VDDCI:0.85~1.1V(14.2A peak )( Ripple < 87.2mV)
1u X30 2.2u X16
AB20 VDD_CT#2 AA15
bead 120 X1 1u X1 VDD_CT#3 VDDC#1
C81 C86 C63 AB21 CORE N15
10u X1 Exo@10U/6.3V_4 Exo@0.1U/16V_4X EV@1U/6.3V_4 VDD_CT#4 VDDC#2 N17
1u X1 VDDC#3 R13 C143 C144 C123 C141 C111 C97 C129 C142
VDDC#4

POWER
0.1u X1 I/O R16 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4
AA17 VDDC#5 R18
+3V_GFX AA18 VDDR3#1 VDDC#6 Y21
AB17 VDDR3#2 VDDC#7 T12
VDD_GPIO33@25mA
Meso Power VDD_GPIO33 AB18 VDDR3#3
VDDR3#4
VDDC#8
VDDC#9
T15
T17

MPLL_PVDD VDDR3 V12

Y12 NC_VDDR4#1
VDDC#10
VDDC#11
T20
U13
C171 C107 C113 C110
EXO MESO Exo@10U/6.3V_4 Exo@1U/6.3V_4 Exo@1U/6.3V_4 EV@1U/6.3V_4 U12 NC_VDDR4#2 VDDC#12 U16
EXO MESO NC_VDDR4#3 VDDC#13 U18
bead 120 X1 1u X1 VDDC#14
bead 220 X1 bead 220 X1 V21
10u X1 VDDC#15 V15 C154 C95 C130 C89 C90 C119 C156 C136
10u X1 10u X2 1u X3 VDDC#16 V17 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 EV@2.2U/10V_4 Meso@2.2U/10V_4
1u X1 1u X1 VDDC#17 V20
VDDC#18 Y13
0.1u X1 VDDC#20 Y16
VDDC#21 Y18
L3 EV@PBY160808T-221Y-N_6 MPV18 VDDC#22 AA12
+1.8V_GFX VDDC#23 M11
VDDC#24 N12
Memory Phase Lock Loop Power :
SPLL_PVDD 1.8V @ 90mA C158 C166 C182 C174 VDDC#25
VDDC#26
U11
EV@1U/6.3V_4 Exo@0.1U/16V_4X EV@10U/6.3V_4 Meso@10U/6.3V_4 AB11 C169 C170 C133 C157 C163 C177
EXO MESO VDDC/VARY_BL AB12 EV@10U/6.3V_4 EV@10U/6.3V_4 EV@10U/6.3V_4 EV@10U/6.3V_4 Meso@10U/6.3V_4 Meso@10U/6.3V_4
VDDC/DIGON AB13
bead 120 X1 bead 120 X1 VDDC/GENERICA W9
10u X1 1u X1 PLL VDDC/GENERICC AC11
1u X1 10u X1 VDDC/DDC2CLK AC13
B VDDC/DDC2DATA AC14 B
0.1u X1 VDDC/HPD1 U10
+1.8V_GFX
L1 EV@BLM15AG121SN1D(120/0.5)_4 SPV18 MPV18 L8
MPLL_PVDD
VDDC/GPIO_1
VDDC/GPIO_2
T10
W10
VDDCI
Engine Phase Lock Loop Power :
VDDC/GPIO_18 Y9
EXO MESO
C161 C162 C160 VDDC/GPIO_14_HPD2
analog power pin for engine PLL 10u X1 10u X2
1.8V @ 75mA Exo@0.1U/16V_4X EV@1U/6.3V_4 EV@10U/6.3V_4 R21
SPV18 H7 BIF_VDDC_1 U21 1u X3 1u X3
SPLL_PVDD BIF_VDDC_2 +PCIE_VDDC_GFX +VGPU_CORE 0.1u X3 0.1u X2
M13 0.95V~1.1V(2A VDDCI)
ISOLATED VDDCI#1 M15
CORE I/O VDDCI#2 M16
L4 EV@BLM15AG121SN1D(120/0.5)_4 +0.95V_VGA_SPV10 H8 VDDCI#3 M17
+PCIE_VDDC_GFX SPLL_VDDC VDDCI#4 M18 C131 C115 C114 C121 C112 C137 C176 C193
VDDCI#5 M20 Exo@0.1U/16V_4X EV@0.1u/16V_4 EV@0.1u/16V_4 EV@1U/6.3V_4 EV@1U/6.3V_4 EV@1U/6.3V_4 EV@10U/6.3V_4 Meso@10U/6.3V_4
Engine Phase Lock Loop Power : VDDCI#6
digital power pin for engine PLL C189 C181 C175 J7 M21
Exo@10U/6.3V_4 EV@0.1u/16V_4 EV@1U/6.3V_4 SPLL_PVSS VDDCI#7 N20
0.95V @ 100mA VDDCI#8
W1 R131 Meso@0_4
NC#W1/FB_VDDCI +VGPU_CORE
W3 R496 Meso@0_4
SPLL_VDDC NC#W3/FB_VSS
AC20 GPUVDDC_SENSE_R R401 Meso@0_4
EXO MESO NC#FB_VDDC AD20 GPUVSS_SENSE_R R400 Meso@0_4
GPUVDDC_SENSE [41]
NC#FB_VSS GPUVSS_SENSE [41]
bead 120 X1 bead 120 X1
EV_SP@R16-M1-70/30_S3
10u X1 1u X1
1u X1 0.1u X1 EXO doesn't support this function
0.1u X1 (refer to GPU SCL)

A A

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
R16-M1-70/-30_S3_Power(4/7)
Date: Friday, March 18, 2016 Sheet 14 of 45
5 4 3 2 1
 5 4 3 2 1

U25C

(VGA)
[16,17] VMA_ODT0
[16,17] VMA_ODT1
VMA_ODT0
VMA_ODT1
VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
VMA_DQ4
K27
J29
H30
H32
G29
DQA0_0
DQA0_1
DQA0_2
DQA0_3
MAA0_0
MAA0_1
MAA0_2
MAA0_3
K17
J20
H23
G23
G24
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
15
VMA_DQ5 F28 DQA0_4 MAA0_4 H24 VMA_MA5
VMA_RAS0# VMA_DQ6 F32 DQA0_5 MAA0_5 J19 VMA_MA6
[16,17] VMA_RAS0# DQA0_6 MAA0_6
VMA_RAS1# VMA_DQ7 F30 K19 VMA_MA7
D [16,17] VMA_RAS1# DQA0_7 MAA0_7 D
VMA_DQ8 C30 G20 VMA_MA13
VMA_CAS0# VMA_DQ9 F27 DQA0_8 MAA0_8 L17 VMA_MA15
[16,17] VMA_CAS0#

MEMORY INTERFACE
VMA_CAS1# VMA_DQ10 A28 DQA0_9 MAA0_9
[16,17] VMA_CAS1# DQA0_10
VMA_DQ11 C28 J14 VMA_MA8
VMA_WE0# VMA_DQ12 E27 DQA0_11 MAA1_0 K14 VMA_MA9
[16,17] VMA_WE0# DQA0_12 MAA1_1
VMA_WE1# VMA_DQ13 G26 J11 VMA_MA10
[16,17] VMA_WE1# DQA0_13 MAA1_2
VMA_DQ14 D26 J13 VMA_MA11
VMA_CS0#_0 VMA_DQ15 F25 DQA0_14 MAA1_3 H11 VMA_MA12
[16,17] VMA_CS0#_0

From GPU
VMA_CS0#_1 VMA_DQ16 A25 DQA0_15 MAA1_4 G11 VMA_BA2
[17] VMA_CS0#_1 DQA0_16 MAA1_5
VMA_DQ17 C25 J16 VMA_BA0
VMA_CS1#_0 VMA_DQ18 E25 DQA0_17 MAA1_6 L15 VMA_BA1 25mm (max) 5mm (max) 25mm (max)
[16,17] VMA_CS1#_0 DQA0_18 MAA1_7
VMA_CS1#_1 VMA_DQ19 D24 G14 VMA_MA14
[17] VMA_CS1#_1 DQA0_19 MMA1_8
VMA_DQ20 E23 L16
VMA_CKE0 VMA_DQ21 F23 DQA0_20 MAA1_9 DRAM_RST R96 EV@10_4 R97 EV@51_4
[16,17] VMA_CKE0 DQA0_21 DRAM_RST_M [16,17]
VMA_CKE1 VMA_DQ22 D22 E32 VMA_DM0
[16,17] VMA_CKE1 DQA0_22 WCKA0_0
VMA_DQ23 F21 E30 VMA_DM1
VMA_CLK0 VMA_DQ24 E21 DQA0_23 WCKA0B_0 A21 VMA_DM2
[16,17] VMA_CLK0 DQA0_24 WCKA0_1
VMA_CLK0# VMA_DQ25 D20 C21 VMA_DM3 R95 C152
[16,17] VMA_CLK0# DQA0_25 WCKA0B_1
VMA_DQ26 F19 E13 VMA_DM4 EV@4.99K/F_4 EV@120P/50V_4N
VMA_CLK1 VMA_DQ27 A19 DQA0_26 WCKA1_0 D12 VMA_DM5
[16,17] VMA_CLK1 DQA0_27 WCKA1B_0
VMA_CLK1# VMA_DQ28 D18 E3 VMA_DM6
[16,17] VMA_CLK1# DQA0_28 WCKA1_1
VMA_DQ29 F17 F4 VMA_DM7
VMA_WDQS[7..0] VMA_DQ30 A17 DQA0_29 WCKA1B_1
[16,17] VMA_WDQS[7..0] VMA_DQ31 DQA0_30 VMA_RDQS0
C17 H28
C VMA_RDQS[7..0] DQA0_31 EDCA0_0 C
VMA_DQ32 E17 C27 VMA_RDQS1
[16,17] VMA_RDQS[7..0] VMA_DQ33 DQA1_0 EDCA0_1 VMA_RDQS2
D16 A23
VMA_DM[7..0] VMA_DQ34 F15 DQA1_1 EDCA0_2 E19 VMA_RDQS3
[16,17] VMA_DM[7..0] DQA1_2 EDCA0_3
VMA_DQ35 A15 E15 VMA_RDQS4 Place all these components very close to GPU (Within
VMA_DQ[63..0] VMA_DQ36 D14 DQA1_3 EDCA1_0 D10 VMA_RDQS5
[16,17] VMA_DQ[63..0] VMA_DQ37 F13 DQA1_4 EDCA1_1 D6 VMA_RDQS6 25mm) and keep all component close to each Other (within
VMA_MA[15..0] VMA_DQ38 A13 DQA1_5 EDCA1_2 G5 VMA_RDQS7 5mm) except Rser2
[16,17] VMA_MA[15..0] DQA1_6 EDCA1_3
VMA_DQ39 C13
VMA_DQ40 E11 DQA1_7 H27 VMA_WDQS0 This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
VMA_BA0 VMA_DQ41 A11 DQA1_8 DDBIA0_0 A27 VMA_WDQS1
[16,17] VMA_BA0 DQA1_9 DDBIA0_1
Capacitors and Resistor values are an example only. The Series R and
VMA_BA1 VMA_DQ42 C11 C23 VMA_WDQS2 || Cap values will depend on the DRAM load and will have to be
[16,17] VMA_BA1 DQA1_10 DDBIA0_2
VMA_BA2 VMA_DQ43 F11 C19 VMA_WDQS3 calculated for different Memory ,DRAM Load and board to pass Reset
[16,17] VMA_BA2 DQA1_11 DDBIA0_3
VMA_DQ44 A9 C15 VMA_WDQS4
VMA_DQ45 C9 DQA1_12 DDBIA1_0 E9 VMA_WDQS5
Signal Spec.
VMA_DQ46 F9 DQA1_13 DDBIA1_1 C5 VMA_WDQS6
To support 2/4 Gbits VRAM, DQA1_14 DDBIA1_2
dual Rank VMA_DQ47 D8 H4 VMA_WDQS7
VMA_DQ48 E7 DQA1_15 DDBIA1_3
(256 Mbits X 16 x 4/8 pcs) DQA1_16
VMA_DQ49 A7 L18 VMA_ODT0
+1.5V_GFX VMA_DQ50 C7 DQA1_17 ADBIAO K16 VMA_ODT1
VMA_DQ51 F7 DQA1_18 ADBIA1
Place these DQA1_19
VMA_DQ52 A5 H26 VMA_CLK0
dividers and Caps DQA1_20 CLKA0
VMA_DQ53 E5 H25 VMA_CLK0#
close to ASIC VMA_DQ54 C3 DQA1_21 CLKA0B
C60 VMA_DQ55 E1 DQA1_22 G9 VMA_CLK1
B B
R30 *EV@1U/6.3V_4 VMA_DQ56 G7 DQA1_23 CLKA1 H9 VMA_CLK1#
EV@40.2/F_4 VMA_DQ57 G6 DQA1_24 CLKA1B
VMA_DQ58 G1 DQA1_25 G22 VMA_RAS0#
VMA_DQ59 G3 DQA1_26 RASA0B G17 VMA_RAS1#
VMA_DQ60 J6 DQA1_27 RASA1B
VMA_DQ61 J1 DQA1_28 G19 VMA_CAS0#
C64 VMA_DQ62 J3 DQA1_29 CASA0B G16 VMA_CAS1#
R39 EV@1U/6.3V_4 VMA_DQ63 J5 DQA1_30 CASA1B
EV@100/F_4 DQA1_31 H22 VMA_CS0#_0
MVREFDA K26 CSA0B_0 J22 VMA_CS0#_1
MVREFSA J26 MVREFDA CSA0B_1
MVREFSA G13 VMA_CS1#_0
J25 CSA1B_0 K13 VMA_CS1#_1
R38 EV@120/F_4 K25 NC CSA1B_1
+1.5V_GFX MEM_CALRP0 K20 VMA_CKE0
Rd CKEA0 J17 VMA_CKE1
Place these CKEA1
dividers and Caps
G25 VMA_WE0#
close to ASIC DRAM_RST L10 WEA0B H10 VMA_WE1#
C59 DRAM_RST WEA1B
R31 *EV@1U/6.3V_4 CLKTESTA K8
EV@40.2/F_4 CLKTESTB L7 CLKTESTA
CLKTESTB
A C316 C201 A
*EV@0.1u/16V_4 *EV@0.1u/16V_4 EV_SP@R16-M1-70/30_S3

C65
R40
EV@100/F_4
EV@1U/6.3V_4X R204
*EV@51.1/F_4
R135
*EV@51.1/F_4
Quanta Computer Inc.
PROJECT : ZAB
Size Document Number Rev
1A
R16-M1-70/-30_S3_MEM(5/7)
route 50ohms single-ended/100ohms diff and keep short Date: Friday, March 18, 2016 Sheet 15 of 45
5 4 3 2 1
 5 4 3 2 1

(VGA)
[15,17]
[15,17]
[15,17]
VMA_DQ[63..0]
VMA_WDQS[7..0]
VMA_RDQS[7..0]
VMA_DQ[63..0]
VMA_WDQS[7..0]
VMA_RDQS[7..0]
VMA_MA[15..0]
Channel A, RANK 0: 2Gb/4Gb gDDR3 16
[15,17] VMA_MA[15..0] VMA_DM[7..0] U28 U27
[15,17] VMA_DM[7..0]
U3 U2 VREFC_VMA3 M8 E3 VMA_DQ58 VREFC_VMA4 M8 E3 VMA_DQ33
VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ63 Byte 7 VREFD_VMA4 H1 VREFCA DQL0 F7 VMA_DQ36 Byte 4
VREFC_VMA1 M8 E3 VMA_DQ12 VREFC_VMA2 M8 E3 VMA_DQ29 VREFDQ DQL1 F2 VMA_DQ59 VREFDQ DQL1 F2 VMA_DQ32
VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ11 Byte 1 VREFD_VMA2 H1 VREFCA DQL0 F7 VMA_DQ27 Byte 3 VMA_MA0 N3 DQL2 F8 VMA_DQ60 VMA_MA0 N3 DQL2 F8 VMA_DQ39
VREFDQ DQL1 F2 VMA_DQ14 VREFDQ DQL1 F2 VMA_DQ30 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ57 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ35
VMA_MA0 N3 DQL2 F8 VMA_DQ8 VMA_MA0 N3 DQL2 F8 VMA_DQ25 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ62 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ37
VMA_MA1 P7 A0 DQL3 H3 VMA_DQ15 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ31 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ56 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ34
VMA_MA2 P3 A1 DQL4 H8 VMA_DQ9 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ24 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ61 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ38
VMA_MA3 N2 A2 DQL5 G2 VMA_DQ13 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ28 VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7
VMA_MA4 P8 A3 DQL6 H7 VMA_DQ10 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ26 VMA_MA6 R8 A5 VMA_MA6 R8 A5
VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7 VMA_MA7 R2 A6 D7 VMA_DQ47 VMA_MA7 R2 A6 D7 VMA_DQ52
VMA_MA6 R8 A5 VMA_MA6 R8 A5 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ42 Byte 5 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ48 Byte 6
VMA_MA7 R2 A6 D7 VMA_DQ18 VMA_MA7 R2 A6 D7 VMA_DQ3 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ46 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ51
D VMA_MA8 T8 A7 DQU0 C3 VMA_DQ22 Byte 2 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ7 Byte 0 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ43 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ49 D
VMA_MA9 R3 A8 DQU1 C8 VMA_DQ17 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ0 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ44 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ53
VMA_MA10 L7 A9 DQU2 C2 VMA_DQ20 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ6 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ40 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ50
VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ19 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ1 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ45 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ55
VMA_MA12 N7 A11 DQU4 A2 VMA_DQ21 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ5 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ41 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ54
VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ16 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ2 VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7
VMA_MA14 T7 A13 DQU6 A3 VMA_DQ23 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ4 A15 +1.5V_GFX A15 +1.5V_GFX
VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7
A15 +1.5V_GFX A15 +1.5V_GFX VMA_BA0 M2 B2 VMA_BA0 M2 B2
VMA_BA1 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA2 M3 BA1 VDD#D9 G7 VMA_BA2 M3 BA1 VDD#D9 G7
[15,17] VMA_BA0 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2 BA2 VDD#G7 BA2 VDD#G7
N8 D9 N8 D9 K2 K2
[15,17] VMA_BA1 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9 VDD#K2 VDD#K2
M3 G7 M3 G7 K8 K8
[15,17] VMA_BA2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 VDD#K8 N1 VDD#K8 N1
VDD#K2 K8 VDD#K2 K8 VMA_CLK1 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
VDD#K8 VDD#K8 VMA_CLK1# CK VDD#N9 [15,17] VMA_CLK1 VMA_CLK1# CK VDD#N9
N1 N1 K7 R1 K7 R1
VMA_CLK0 VDD#N1 VMA_CLK0 VDD#N1 VMA_CKE1 CK VDD#R1 [15,17] VMA_CLK1# VMA_CKE1 CK VDD#R1
J7 N9 J7 N9 K9 R9 K9 R9
[15,17] VMA_CLK0 VMA_CLK0# K7 CK VDD#N9 VMA_CLK0# CK VDD#N9 CKE VDD#R9 +1.5V_GFX [15,17] VMA_CKE1 CKE VDD#R9 +1.5V_GFX
R1 K7 R1
[15,17] VMA_CLK0# VMA_CKE0 K9 CK VDD#R1 R9 VMA_CKE0 K9 CK VDD#R1 R9
[15,17] VMA_CKE0 CKE VDD#R9 +1.5V_GFX CKE VDD#R9 +1.5V_GFX VMA_ODT1 K1 A1 VMA_ODT1 K1 A1
VMA_CS1#_0 ODT VDDQ#A1 [15,17] VMA_ODT1 VMA_CS1#_0 ODT VDDQ#A1
L2 A8 L2 A8
VMA_ODT0 VMA_ODT0 VMA_RAS1# CS VDDQ#A8 [15,17] VMA_CS1#_0 VMA_RAS1# CS VDDQ#A8
K1 A1 K1 A1 J3 C1 J3 C1
[15,17] VMA_ODT0 VMA_CS0#_0 ODT VDDQ#A1 VMA_CS0#_0 ODT VDDQ#A1 VMA_CAS1# RAS VDDQ#C1 [15,17] VMA_RAS1# VMA_CAS1# RAS VDDQ#C1
L2 A8 L2 A8 K3 C9 K3 C9
[15,17] VMA_CS0#_0 VMA_RAS0# J3 CS VDDQ#A8 C1 VMA_RAS0# J3 CS VDDQ#A8 C1 VMA_WE1# L3 CAS VDDQ#C9 D2 [15,17] VMA_CAS1# VMA_WE1# L3 CAS VDDQ#C9 D2
[15,17] VMA_RAS0# VMA_CAS0# K3 RAS VDDQ#C1 C9 VMA_CAS0# K3 RAS VDDQ#C1 C9 WE VDDQ#D2 E9 [15,17] VMA_WE1# WE VDDQ#D2 E9
[15,17] VMA_CAS0# VMA_WE0# CAS VDDQ#C9 VMA_WE0# CAS VDDQ#C9 VDDQ#E9 VDDQ#E9
L3 D2 L3 D2 F1 F1
[15,17] VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 VMA_RDQS7 VDDQ#F1 VMA_RDQS4 VDDQ#F1
E9 E9 F3 H2 F3 H2
VDDQ#E9 F1 VDDQ#E9 F1 VMA_WDQS7 G3 DQSL VDDQ#H2 H9 VMA_WDQS4 G3 DQSL VDDQ#H2 H9
VMA_RDQS1 F3 VDDQ#F1 H2 VMA_RDQS3 F3 VDDQ#F1 H2 DQSL VDDQ#H9 DQSL VDDQ#H9
VMA_WDQS1 G3 DQSL VDDQ#H2 H9 VMA_WDQS3 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 VMA_DM7 E7 A9 VMA_DM4 E7 A9
VMA_DM5 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3
VMA_DM1 E7 A9 VMA_DM3 E7 A9 DMU VSS#B3 E1 DMU VSS#B3 E1
VMA_DM2 D3 DML VSS#A9 B3 VMA_DM0 D3 DML VSS#A9 B3 VSS#E1 G8 VSS#E1 G8
DMU VSS#B3 E1 DMU VSS#B3 E1 VMA_RDQS5 C7 VSS#G8 J2 VMA_RDQS6 C7 VSS#G8 J2
VSS#E1 G8 VSS#E1 G8 VMA_WDQS5 B7 DQSU VSS#J2 J8 VMA_WDQS6 B7 DQSU VSS#J2 J8
VMA_RDQS2 C7 VSS#G8 J2 VMA_RDQS0 C7 VSS#G8 J2 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VMA_WDQS2 B7 DQSU VSS#J2 J8 VMA_WDQS0 B7 DQSU VSS#J2 J8 VSS#M1 M9 VSS#M1 M9
DQSU VSS#J8 M1 DQSU VSS#J8 M1 VSS#M9 P1 VSS#M9 P1
VSS#M1 M9 VSS#M1 M9 DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9
VSS#M9 P1 VSS#M9 P1 RESET VSS#P9 T1 RESET VSS#P9 T1
DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 VMA_ZQ4 L8 VSS#T1 T9 VMA_ZQ3 L8 VSS#T1 T9
[15,17] DRAM_RST_M RESET VSS#P9 RESET VSS#P9 ZQ VSS#T9 ZQ VSS#T9
T1 T1
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9
B1 B1 R490 VSSQ#B9 D1 R477 VSSQ#B9 D1
VSSQ#B1 VSSQ#B1 VSSQ#D1 Should be 240 VSSQ#D1
C B9 B9 Should be 240 EV@243/F_4 D8 Ohms +-1% EV@243/F_4 D8 C
R34 VSSQ#B9 D1 R46 VSSQ#B9 D1 VSSQ#D8 E2 VSSQ#D8 E2
Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Ohms +-1% VSSQ#E2 VSSQ#E2
Ohms +-1% EV@243/F_4 D8 Ohms +-1% EV@243/F_4 D8 J1 E8 J1 E8
VSSQ#D8 E2 VSSQ#D8 E2 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 96-BALL 96-BALL
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 SDRAM DDR3 SDRAM DDR3
96-BALL 96-BALL EV_SP@H5TC4G63CFR-N0C EV_SP@H5TC4G63CFR-N0C
SDRAM DDR3 SDRAM DDR3
EV_SP@H5TC4G63CFR-N0C EV_SP@H5TC4G63CFR-N0C

MEM Reference Voltage 1 MEM Reference Voltage 2 MEM Reference Voltage 3 MEM Reference Voltage 4
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

R44 R25 R52 R54 R481 R582 R474 R489

EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4

R42 C66 R26 C51 R49 C74 R53 C94 R485 C646 R571 C671 R475 C641 R512 C648
EV@4.99K/F_4 EV@0.1u/16V_4 EV@4.99K/F_4 EV@0.1u/16V_4 EV@4.99K/F_4 EV@0.1u/16V_4 EV@4.99K/F_4 EV@0.1u/16V_4 EV@4.99K/F_4 EV@0.1u/16V_4 EV@4.99K/F_4 EV@0.1u/16V_4 EV@4.99K/F_4 EV@0.1u/16V_4 EV@4.99K/F_4 EV@0.1u/16V_4

VRAM De-Coupling CLK-A0 Termination VRAM De-Coupling

+1.5V_GFX
1uF x 16 8*0.1uF, 8*1uF, 1*10uF/per VRAM VMA_CLK0
+1.5V_GFX
1uF x 16 8*0.1uF, 8*1uF, 1*10uF/per VRAM
R405
C601 C686 C681 C598 C635 C684 C99 C604 C631 C544 C550 C542 C546 C554 C633 C556
B B
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@80.6/F_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
C567
Dual Rank :80.6R VMA_CLK0_COM1
(CS08062FB19) +1.5V_GFX
+1.5V_GFX Single Rank :40.2R
EV@0.01u/50V_4
(CS04022FB28) R406

EV@80.6/F_4
C537 C552 C533 C535 C610 C548 C57 C62
C699 C649 C638 C640 C665 C695 C673 C697 VMA_CLK0# EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4

CLK-A1 Termination +1.5V_GFX

VMA_CLK1 0.1uF x 16
+1.5V_GFX 0.1uF x 16
R526
C543 C547 C545 C551 C630 C632 C558 C555
EV@80.6/F_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4
C659
C605 C634 C670 C683 C685 C687 C594 C599
EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 VMA_CLK1_COM1
Dual Rank :80.6R
Single Rank :40.2R +1.5V_GFX
R516 EV@0.01u/50V_4
+1.5V_GFX
EV@80.6/F_4

VMA_CLK1# C536 C534 C553 C609 C549 C591 C538 C58

EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4
C676 C694 C696 C698 C639 C653 C642 C656
EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4

For dual rank design: +1.5V_GFX

10uF x 2
+1.5V_GFX 10uF x 2 Stuff the terminator 80.6R for clk
even 4 pcs single rank only
C532 C531
EV@10U/6.3V_4 EV@10U/6.3V_4

C693 C680
EV@10U/6.3V_4 EV@10U/6.3V_4

A A

Stitching Caps(0.1uF x 5)
+1.5V_GFX

Stitching Caps(0.1uF x 5) C539 C607 C608 C541 C540

EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4
+1.5V_GFX

C660 C678 C682 C689 C679

EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 EV@0.1u/16V_4 Quanta Computer Inc.
PROJECT : ZAB
Size Document Number Rev
1A
R16-M1-70/-30_S3_VRAM_DDR3 BGA(6/7)
Date: Friday, January 29, 2016 Sheet 16 of 45
5 4 3 2 1
 5 4 3 2 1

(VGA)
[15,16] VMA_DQ[63..0]
[15,16] VMA_WDQS[7..0]
VMA_DQ[63..0]
VMA_WDQS[7..0]
VMA_RDQS[7..0]
Channel A, RANK 1 : 2Gb/4Gb gDDR3 Stuff when 8 pcs(4G) 17
[15,16] VMA_RDQS[7..0] VMA_MA[15..0]
[15,16] VMA_MA[15..0] VMA_DM[7..0] U7 U6
[15,16] VMA_DM[7..0]
U24 U23 VREFC_VMA7 M8 E3 VMA_DQ63 VREFC_VMA8 M8 E3 VMA_DQ36
VREFD_VMA7 H1 VREFCA DQL0 F7 VMA_DQ58 Byte 7 VREFD_VMA8 H1 VREFCA DQL0 F7 VMA_DQ33 Byte 4
VREFC_VMA5 M8 E3 VMA_DQ11 VREFC_VMA6 M8 E3 VMA_DQ27 VREFDQ DQL1 F2 VMA_DQ60 VREFDQ DQL1 F2 VMA_DQ39
VREFD_VMA5 H1 VREFCA DQL0 F7 VMA_DQ12 Byte 1 VREFD_VMA6 H1 VREFCA DQL0 F7 VMA_DQ29 Byte 3 VMA_MA0 N3 DQL2 F8 VMA_DQ59 VMA_MA0 N3 DQL2 F8 VMA_DQ32
VREFDQ DQL1 F2 VMA_DQ8 VREFDQ DQL1 F2 VMA_DQ25 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ61 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ38
VMA_MA0 N3 DQL2 F8 VMA_DQ14 VMA_MA0 N3 DQL2 F8 VMA_DQ30 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ56 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ34
VMA_MA1 P7 A0 DQL3 H3 VMA_DQ10 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ26 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ62 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ37
VMA_MA2 P3 A1 DQL4 H8 VMA_DQ13 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ28 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ57 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ35
VMA_MA3 N2 A2 DQL5 G2 VMA_DQ9 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ24 VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7
VMA_MA4 P8 A3 DQL6 H7 VMA_DQ15 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ31 VMA_MA6 R8 A5 VMA_MA6 R8 A5
VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7 VMA_MA7 R2 A6 D7 VMA_DQ42 VMA_MA7 R2 A6 D7 VMA_DQ48
VMA_MA6 R8 A5 VMA_MA6 R8 A5 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ47 Byte 5 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ52 Byte 6
VMA_MA7 R2 A6 D7 VMA_DQ22 VMA_MA7 R2 A6 D7 VMA_DQ7 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ43 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ49
VMA_MA8 T8 A7 DQU0 C3 VMA_DQ18 Byte 2 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ3 Byte 0 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ46 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ51
VMA_MA9 R3 A8 DQU1 C8 VMA_DQ20 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ6 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ41 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ54
VMA_MA10 L7 A9 DQU2 C2 VMA_DQ17 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ0 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ45 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ55
D A10/AP DQU3 A10/AP DQU3 A12/BC DQU5 A12/BC DQU5 D
VMA_MA11 R7 A7 VMA_DQ23 VMA_MA11 R7 A7 VMA_DQ5 VMA_MA13 T3 B8 VMA_DQ40 VMA_MA13 T3 B8 VMA_DQ50
VMA_MA12 N7 A11 DQU4 A2 VMA_DQ16 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ2 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ44 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ53
VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ21 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ4 VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7
VMA_MA14 T7 A13 DQU6 A3 VMA_DQ19 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ1 A15 +1.5V_GFX A15 +1.5V_GFX
VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7
A15 +1.5V_GFX A15 +1.5V_GFX VMA_BA0 M2 B2 VMA_BA0 M2 B2
VMA_BA1 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA2 M3 BA1 VDD#D9 G7 VMA_BA2 M3 BA1 VDD#D9 G7
[15,16] VMA_BA0 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2 BA2 VDD#G7 BA2 VDD#G7
N8 D9 N8 D9 K2 K2
[15,16] VMA_BA1 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9 VDD#K2 VDD#K2
M3 G7 M3 G7 K8 K8
[15,16] VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 VDD#K8 VDD#K8
K2 K2 N1 N1
VDD#K2 K8 VDD#K2 K8 VMA_CLK1 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
VDD#K8 VDD#K8 VMA_CLK1# CK VDD#N9 [15,16] VMA_CLK1 VMA_CLK1# CK VDD#N9
N1 N1 K7 R1 K7 R1
VMA_CLK0 VDD#N1 VMA_CLK0 VDD#N1 VMA_CKE1 CK VDD#R1 [15,16] VMA_CLK1# VMA_CKE1 CK VDD#R1
J7 N9 J7 N9 K9 R9 K9 R9
[15,16] VMA_CLK0 VMA_CLK0# CK VDD#N9 VMA_CLK0# CK VDD#N9 CKE VDD#R9 +1.5V_GFX [15,16] VMA_CKE1 CKE VDD#R9 +1.5V_GFX
K7 R1 K7 R1
[15,16] VMA_CLK0# VMA_CKE0 CK VDD#R1 VMA_CKE0 CK VDD#R1
K9 R9 K9 R9
[15,16] VMA_CKE0 CKE VDD#R9 +1.5V_GFX CKE VDD#R9 +1.5V_GFX VMA_ODT1 VMA_ODT1
K1 A1 K1 A1
VMA_CS1#_1 ODT VDDQ#A1 [15,16] VMA_ODT1 VMA_CS1#_1 ODT VDDQ#A1
L2 A8 L2 A8
VMA_ODT0 VMA_ODT0 VMA_RAS1# CS VDDQ#A8 [15] VMA_CS1#_1 VMA_RAS1# CS VDDQ#A8
K1 A1 K1 A1 J3 C1 J3 C1
[15,16] VMA_ODT0 VMA_CS0#_1 ODT VDDQ#A1 VMA_CS0#_1 ODT VDDQ#A1 VMA_CAS1# RAS VDDQ#C1 [15,16] VMA_RAS1# VMA_CAS1# RAS VDDQ#C1
L2 A8 L2 A8 K3 C9 K3 C9
[15] VMA_CS0#_1 VMA_RAS0# CS VDDQ#A8 VMA_RAS0# CS VDDQ#A8 VMA_WE1# CAS VDDQ#C9 [15,16] VMA_CAS1# VMA_WE1# CAS VDDQ#C9
J3 C1 J3 C1 L3 D2 L3 D2
[15,16] VMA_RAS0# VMA_CAS0# RAS VDDQ#C1 VMA_CAS0# RAS VDDQ#C1 WE VDDQ#D2 [15,16] VMA_WE1# WE VDDQ#D2
K3 C9 K3 C9 E9 E9
[15,16] VMA_CAS0# VMA_WE0# CAS VDDQ#C9 VMA_WE0# CAS VDDQ#C9 VDDQ#E9 VDDQ#E9
L3 D2 L3 D2 F1 F1
[15,16] VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 VMA_RDQS7 VDDQ#F1 VMA_RDQS4 VDDQ#F1
E9 E9 F3 H2 F3 H2
VDDQ#E9 F1 VDDQ#E9 F1 VMA_WDQS7 G3 DQSL VDDQ#H2 H9 VMA_WDQS4 G3 DQSL VDDQ#H2 H9
VMA_RDQS1 F3 VDDQ#F1 H2 VMA_RDQS3 F3 VDDQ#F1 H2 DQSL VDDQ#H9 DQSL VDDQ#H9
VMA_WDQS1 G3 DQSL VDDQ#H2 H9 VMA_WDQS3 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 VMA_DM7 E7 A9 VMA_DM4 E7 A9
VMA_DM5 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3
VMA_DM1 E7 A9 VMA_DM3 E7 A9 DMU VSS#B3 E1 DMU VSS#B3 E1
VMA_DM2 D3 DML VSS#A9 B3 VMA_DM0 D3 DML VSS#A9 B3 VSS#E1 G8 VSS#E1 G8
DMU VSS#B3 E1 DMU VSS#B3 E1 VMA_RDQS5 C7 VSS#G8 J2 VMA_RDQS6 C7 VSS#G8 J2
VSS#E1 G8 VSS#E1 G8 VMA_WDQS5 B7 DQSU VSS#J2 J8 VMA_WDQS6 B7 DQSU VSS#J2 J8
VMA_RDQS2 C7 VSS#G8 J2 VMA_RDQS0 C7 VSS#G8 J2 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VMA_WDQS2 B7 DQSU VSS#J2 J8 VMA_WDQS0 B7 DQSU VSS#J2 J8 VSS#M1 M9 VSS#M1 M9
DQSU VSS#J8 M1 DQSU VSS#J8 M1 VSS#M9 P1 VSS#M9 P1
VSS#M1 M9 VSS#M1 M9 DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9
VSS#M9 P1 VSS#M9 P1 RESET VSS#P9 T1 RESET VSS#P9 T1
DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 VMA_ZQ7 L8 VSS#T1 T9 VMA_ZQ8 L8 VSS#T1 T9
[15,16] DRAM_RST_M RESET VSS#P9 RESET VSS#P9 ZQ VSS#T9 ZQ VSS#T9
T1 T1
VMA_ZQ5 L8 VSS#T1 T9 VMA_ZQ6 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9
B1 B1 R469 VSSQ#B9 D1 R128 VSSQ#B9 D1
VSSQ#B1 VSSQ#B1 VSSQ#D1 Should be 240 VSSQ#D1 D8
B9 B9 Should be 240 EV_4G@243/F_4 D8 Ohms +-1% EV_4G@243/F_4
R412 VSSQ#B9 D1 R419 VSSQ#B9 D1 VSSQ#D8 E2 VSSQ#D8 E2
Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Ohms +-1% VSSQ#E2 VSSQ#E2 E8
Ohms +-1% EV_4G@243/F_4 D8 Ohms +-1% EV_4G@243/F_4 D8 J1 E8 J1
VSSQ#D8 E2 VSSQ#D8 E2 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 96-BALL 96-BALL
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 SDRAM DDR3 SDRAM DDR3
96-BALL 96-BALL EV_SP@H5TC4G63CFR-N0C EV_SP@H5TC4G63CFR-N0C
C SDRAM DDR3 SDRAM DDR3 C
EV_SP@H5TC4G63CFR-N0C EV_SP@H5TC4G63CFR-N0C

MEM Reference Voltage 5 MEM Reference Voltage 6 MEM Reference Voltage 7 MEM Reference Voltage 8
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

R416 R404 R420 R394 R111 R140 R129 R188

EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4

VREFC_VMA5 VREFD_VMA5 VREFC_VMA6 VREFD_VMA6 VREFC_VMA7 VREFD_VMA7 VREFC_VMA8 VREFD_VMA8

R414 C596 R407 C576 R421 C603 R397 C557 R118 C180 R144 C212 R130 C186 R177 C247
EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4
EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4 EV_4G@4.99K/F_4

VRAM De-Coupling CLK-A0 Termination VRAM De-Coupling

8*0.1uF, 8*1uF, 1*10uF/per VRAM 8*0.1uF, 8*1uF, 1*10uF/per VRAM
+1.5V_GFX VMA_CLK0
1uF x 16 +1.5V_GFX
1uF x 16
R28
EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4
C104 C306 C165 C286 C47 C309 C184 C179 EV@80.6/F_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4
C56
EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 C22 C28 C24 C26 C31 C49 C52 C33
VMA_CLK0_COM2 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4
Dual Rank :80.6R
Single Rank :40.2R
+1.5V_GFX R29 EV@0.01u/50V_4
+1.5V_GFX
EV@80.6/F_4

EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 VMA_CLK0#

C281 C192 C167 C277 C231 C279 C246 C178 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4
EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 C581 C42 C70 C82 C45 C35 C587 C46
EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4 EV_4G@1u/6.3V_4
CLK-A1 Termination
VMA_CLK1

+1.5V_GFX 0.1uF x 16
B R158 +1.5V_GFX 0.1uF x 16 B

EV@80.6/F_4
C224
EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4
C173 C185 C105 C168 C307 C303 C310 C194 VMA_CLK1_COM2 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4
EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4
Dual Rank :80.6R C27 C50 C55 C29 C34 C32 C23 C25
Single Rank :40.2R EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4
R151 EV@0.01u/50V_4

+1.5V_GFX EV@80.6/F_4
+1.5V_GFX
VMA_CLK1#

EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4

C278 C280 C282 C244 C172 C225 C164 C216 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4
EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 C48 C72 C87 C36 C588 C584 C43 C44
EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4
For dual rank design:
+1.5V_GFX 10uF x 2 Stuff the terminator 80.6R for clk
even 4 pcs single rank only
+1.5V_GFX 10uF x 2
C305 C276
EV_4G@10U/6.3V_4 EV_4G@10U/6.3V_4
C21 C30
EV_4G@10U/6.3V_4 EV_4G@10U/6.3V_4

+1.5V_GFX +1.5V_GFX Stitching Caps(0.1uF x 5)

Stitching Caps(0.1uF x 5)

C100 C606 C148 C146 C103 C149 C147 C611 C102 C101
EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4 EV_4G@0.1u/16V_4

+1.5V_GFX
+1.5V_GFX
A A
+1.5V_GFX +1.5V_GFX R85 EV@100/F_4 VMA_BA0 R450 EV@100/F_4
R91 EV@100/F_4 VMA_BA1 R465 EV@100/F_4 R32 EV@100/F_4 VMA_RAS0# R408 EV@100/F_4
R66 EV@100/F_4 VMA_MA0 R432 EV@100/F_4 R78 EV@100/F_4 VMA_MA8 R449 EV@100/F_4 R89 EV@100/F_4 VMA_BA2 R456 EV@100/F_4 R145 EV@100/F_4 VMA_RAS1# R508 EV@100/F_4
R74 EV@100/F_4 VMA_MA1 R443 EV@100/F_4 R92 EV@100/F_4 VMA_MA9 R460 EV@100/F_4
R64 EV@100/F_4 VMA_MA2 R428 EV@100/F_4 R86 EV@100/F_4 VMA_MA10 R459 EV@100/F_4
R58 EV@100/F_4 VMA_MA3 R422 EV@100/F_4 R88 EV@100/F_4 VMA_MA11 R455 EV@100/F_4 R35 EV@100/F_4 VMA_CKE0 R410 EV@100/F_4 R33 EV@100/F_4 VMA_CAS0# R409 EV@100/F_4
R55 EV@100/F_4 VMA_MA4 R424 EV@100/F_4 R94 EV@100/F_4 VMA_MA12 R464 EV@100/F_4 R486 EV@100/F_4 VMA_CKE1 R133 EV@100/F_4 R141 EV@100/F_4 VMA_CAS1# R493 EV@100/F_4
R73 EV@100/F_4 VMA_MA5 R444 EV@100/F_4 R60 EV@100/F_4 VMA_MA13 R425 EV@100/F_4
R69 EV@100/F_4 VMA_MA6 R438 EV@100/F_4 R77 EV@100/F_4 VMA_MA14 R448 EV@100/F_4
R71 EV@100/F_4 VMA_MA7 R437 EV@100/F_4 R72 EV@100/F_4 VMA_MA15 R441 EV@100/F_4 R399 EV@100/F_4 VMA_ODT0 R27 EV@100/F_4 R41 EV@100/F_4 VMA_WE0# R411 EV@100/F_4
R134 EV@100/F_4 VMA_ODT1 R487 EV@100/F_4 R132 EV@100/F_4 VMA_WE1# R482 EV@100/F_4

+1.5V_GFX

VMA_CS0#_0 R43 EV@100/F_4 VMA_CS0#_0 R398 EV@100/F_4

[15,16] VMA_CS0#_0 VMA_CS1#_0 VMA_CS1#_0
R169 EV@100/F_4 R547 EV@100/F_4
[15,16] VMA_CS1#_0
Quanta Computer Inc.
R45 EV@100/F_4 VMA_CS0#_1 R413 EV@100/F_4
2015.11.09 Add that GAE suggest & SCL R552 EV@100/F_4 VMA_CS1#_1 R170 EV@100/F_4
PROJECT : ZAB
Size Document Number Rev
1A
R16-M1-70/-30_S3_VRAM_DDR3 BGA(7/7)
Date: Friday, January 29, 2016 Sheet 17 of 45
5 4 3 2 1
 1 2 3 4 5 6 7 8

LCD (LDS) +3V

R389
*1K/F_4
LCD Power (LDS)
+3V
18
VIN +3V +5V
1u/6.3V_4
EDP_HPD C40 U1
[4] EDP_HPD 5 1 LCDVCC
C17 C16 C15 C14 IN OUT
R387 C529 C530 2
0.1u/16V_4 0.1u/16V_4 GND C20 C38 C19 C37 C39
4.7u/25V_8 1000p/50V_4 1000p/50V_4 1000p/50V_4 4 3 *0.1u/16V_4 *2.2u/16V_6 0.1u/16V_4 0.01u/50V_4 22U/6.3V_6
[4] APU_DISP_ON EN /OC
100K/F_4
G524B1T11U
A A

R24
100K/F_4
+3V
Enable:High Active /2.5A
R19 *100K/F_4 EDP_AUX_C R21 *100K/F_4 GMT: AL000524004
R18 *100K/F_4 EDP_AUX#_C R22 *100K/F_4 BCD : AL022802000

LVDS_CONN

G_5
R391 *short_8 V_BLIGHT
VIN 40
39
Front Camera (FCM) LCDVCC R23 *short_6 LCDVCC_R
38
37
36
R383 *short_4 USBP4+_R 35
CCD [6] USBP4+ 34
R381 *short_4 USBP4-_R C928 *22U/6.3V_6
[6] USBP4- CCD_PWR 33
CCD +3V R20 *short_6
R17 *0_4 32
+3V TPA_PWR 31 G_4
Touch panel +5V R15 *short_6
R390 I2CT@0_4 TP_RST# 30
[5,11,21,22,23] PCIERST# 29
R388 *short_4 BRIGHT 28
[4] APU_DISP_PWM BL_ON 27
EDP_HPD R386 33_4 EDP_HPD_R 26
C528 180P/50V_4 25
C527 0.1u/16V_4 EDP_AUX_C 24
TOUCH Screen (TSN) [4] EDP_AUX
[4] EDP_AUX#
C526 0.1u/16V_4 EDP_AUX#_C 23
22
Backlight Control (LDS)
C525 0.1u/16V_4 EDP_TX1_C 21
[4] EDP_TX1 EDP_TX1#_C 20
C524 0.1u/16V_4
[4] EDP_TX1# 19
C523 0.1u/16V_4 EDP_TX0_C 18
[4] EDP_TX0 EDP_TX0#_C 17
C522 0.1u/16V_4
[4] EDP_TX0# 16
I2C_SCL_TS_R R12 I2CT@0_4 USBP4+_R 15
B B
I2C_SDA_TS_R R11 I2CT@0_4 USBP4-_R 14 +3VPCU
13
USBP2+_R/TP_CLK 12
USBP2-_R/TP_DATA 11
10 G_1 R16
EDP_TXP2 C521 0.1U/16V_4 EDP_TXP2_C 9 *100K/F_4
[4] EDP_TXP2 EDP_TXN2 EDP_TXN2_C 8
C520 0.1U/16V_4
[4] EDP_TXN2 7 +3V +3V
eDP 4k*2k +3VPCU LID# LID# [33]
[33] TS_EN_R EDP_TXP3 EDP_TXP3_C 6
C519 0.1U/16V_4
[4] EDP_TXP3 EDP_TXN3 EDP_TXN3_C 5
C518 0.1U/16V_4 LID591#,HALL intrnal PU
[4] EDP_TXN3 4
R376 33_4 3 D1
[5] BOARD_ID4 TP_INT# 2 R13 1N4148WS
1

G_0
For Touch or None-Touch
C517 CN5 R14 R10 10K/F_4
180P/50V_4 BL_ON
10K/F_4 *10K/F_4

3
BL# 2 2
EC_FPBACK# [33]
Q5 Q4
2N7002K DTC144EU

1
3
+3V

1
R395 *I2CT@0_4 +5V R7 2.2K_4 APU_BLEN_R 2
VDD_18 [4,33] APU_DISP_BLEN
R396 I2CT@0_4 +3V
Q3

1
R8 MMBT3904-7-F
R9 R393 R392 100K/F_4
*I2CT@10K/F_4 Q6 I2CT@2.2K_4 I2CT@2.2K_4
5
2

4 3 I2C_SCL_TS_R
TP_INT# [5] I2C_SCL_TS
3 1
[5] APU_TP_INT#
Q14 2
C C
*I2CT@2N7002K 1.8V_S0
1 6 I2C_SDA_TS_R
[5] I2C_SDA_TS
R212 I2CT@0_4

I2CT@PJT138K

Lid Switch (HSR)

AL008251000 -- YBT
AL008132004 -- ANC
+3VPCU

C515 1U/6.3V_4
1

2 LID#
1

MR1
APX9132H_AI-TRG D10
3

*TVS/6pF_4
2

D D

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
EDP/LID/CCD
Date: Thursday, March 03, 2016 Sheet 18 of 45
1 2 3 4 5 6 7 8
 5 4 3 2 1

4Kx2K (HDM)
+3V_HDMI +3V_HDMI

19

HDMI_DDCDATA_MB1
HDMI_DDCCLK_MB1
HDMI_MB_HPD_RP
+3V +3V_HDMI
C446 C445 Co-Layout
R249 *RP@0_6 Add it when using HDMI level shifter RP@0.1U/16V_4 RP@0.1U/16V_4
HDMI_MB_HPD_RP R848 *RP@0_4 HDMI_MB_HPD

D
+3V_HDMI D

C450 C449 C415 C414 C447 C448 Co-Layout To Choke

24
23
22
21
20
19
18
17
U17
RP@0.1u/16V_4 RP@0.1u/16V_4 RP@0.1u/16V_4 RP@0.1u/16V_4 RP@0.01u/50V_4 RP@0.01u/50V_4

GND
TERM_EN
DDC_EN

VDD
OE_N
HPD_SNK
SDA_SNK
SCL_SNK
HDMI_DDCCLK_MB1 R303 *RP@0_4 HDMI_DDCCLK_MB
From APU Co-Layout HDMI_DDCDATA_MB1 R304 *RP@0_4 HDMI_DDCDATA_MB

C443 *RP@0.1u/16V_4 INT_HDMITX0P_C_R 25 16 INT_HDMITX0P_C1 R301 *RP@0_4 INT_HDMITX0P_C

[4] INT_HDMITX0P INT_HDMITX0N_C_R IN_D1- OUT_D1- INT_HDMITX0N_C1 INT_HDMITX0N_C
C441 *RP@0.1u/16V_4 26 15 R296 *RP@0_4
[4] INT_HDMITX0N INT_HDMITX1P_C_R IN_D1+ OUT_D1+ INT_HDMITX1P_C1 INT_HDMITX1P_C
C436 *RP@0.1u/16V_4 27 14 R288 *RP@0_4
[4] INT_HDMITX1P INT_HDMITX1N_C_R IN_D2- OUT_D2- INT_HDMITX1N_C1 INT_HDMITX1N_C
C434 *RP@0.1u/16V_4 28 13 R284 *RP@0_4
HDMI_EQ1 [4] INT_HDMITX1N INT_HDMITX2P_C_R IN_D2+ OUT_D2+ INT_HDMITX2P_C1 INT_HDMITX2P_C
R250 RP@10K/F_4 +3V C431 *RP@0.1u/16V_4 29 12 R281 *RP@0_4
[4] INT_HDMITX2P INT_HDMITX2N_C_R IN_D3- OUT_D3- INT_HDMITX2N_C1 INT_HDMITX2N_C
C425 *RP@0.1u/16V_4 30 11 R276 *RP@0_4
[4] INT_HDMITX2N INT_HDMICLK+_C_R IN_D3+ OUT_D3+ INT_HDMICLK+_C1 INT_HDMICLK+_C
R260 *RP@0_4 C421 *RP@0.1u/16V_4 31 10 R273 *RP@0_4
[4] INT_HDMICLK+ INT_HDMICLK-_C_R IN_D4- OUT_D4- INT_HDMICLK-_C1 INT_HDMICLK-_C
C419 *RP@0.1u/16V_4 32 9 R267 *RP@0_4
[4] INT_HDMICLK- IN_D4+ OUT_D4+
33 37

HPD_SRC
SDA_SRC
SCL_SRC
HDMI_EQ0 R248 *RP@10K/F_4 +3V R257 *RP@0_4 HDMI_DDCCLK_SW1 CEN_PAD GND 36
[4] HDMI_DDCCLK_SW HDMI_DDCDATA_SW1 GND 35

REXT
R258 *RP@0_4

GND
VDD
[4] HDMI_DDCDATA_SW

EQ1

EQ0
R256 RP@0_4 GND 34
GND
RP@PTN3366BS

1
2
3
4
INT_HDMI_HPD_RP 5
HDMI_DDCDATA_SW16
HDMI_DDCCLK_SW1 7
8
+3V_HDMI

Co-Layout

RP@12.4K/F_4
R851 *RP@0_4 INT_HDMI_HPD_RP C413
[4,19] INT_HDMI_HPD

HDMI_EQ1

HDMI_EQ0
RP@0.1U/16V_4

C C

R259
Normal Rout
HDMI DDC (HDM)
+3V
+3V
Normal Rout
R244
HDMI-detect (HDM)
2.2K_4 Q22
2

NRD@2N7002K
**Share with normal rout
HDMI_DDCCLK_SW R253 *shortNRD@0_4 HDMI_DDCCLK_COM1 3 R306 *shortNRD@0_4 HDMI_DDCCLK_MB +3V +5V

+HDMI_5V
R850 R309
NRD@10K/F_4 NRD@10K/F_4
HDMI_DDCCLK_MB R310 2.2K_4 1 2
Co-Layout Co-Layout D6 RB501V-40

+3V +3V *shortNRD@0_4 R308 HDMI_HPD_R *shortNRD@0_4 R847 HDMI_MB_HPD HDMI_DDCDATA_MB R311 2.2K_4 1 2
[4,19] INT_HDMI_HPD
D7 RB501V-40

5
R245 R305
2

2.2K_4 Q23 Q21 NRD@100K/F_4

B
NRD@2N7002K B
HDMI_DDCDATA_SW R254 *shortNRD@0_4 HDMI_DDCDATA_COM
1 3 R307 *shortNRD@0_4 HDMI_DDCDATA_MB NRD@2N7002DW

4
Co-Layout Co-Layout

HDMI(HDM) Normal Rout

+5V +HDMI_5V

*CM1225-04DE
EMI
INT_HDMITX2P_C 5 6 INT_HDMITX2P_C Q16 CN14 INT_HDMITX2P_C
Co-Layout INT_HDMITX2N_C 4 5 6 7 INT_HDMITX2N_C 3 1 20
From APU Co-Layout To Choke 3 4 7 IN OUT 2 INT_HDMITX2P_C 1 SHELL1 R299 *120/F_4
INT_HDMITX1P_C 2 GND_3/8 9 INT_HDMITX1P_C GND 2 D2+
INT_HDMITX2P C432 NRD@0.1u/16V_4 INT_HDMITX2P_R3 R280 *shortNRD@0_4 INT_HDMITX2P_C INT_HDMITX1N_C 1 2 9 10 INT_HDMITX1N_C AP2802NTR-G1-01 C408 D5 INT_HDMITX2N_C 3 D2 Shield INT_HDMITX2N_C
INT_HDMITX2N C426 NRD@0.1u/16V_4 INT_HDMITX2N_R3 R275 *shortNRD@0_4 INT_HDMITX2N_C 1 10 *220p/50V_4 *EGA_4 INT_HDMITX1P_C 4 D2-
ESD4 BCD : AL002802002 5 D1+ INT_HDMITX1P_C
INT_HDMITX1P C437 NRD@0.1u/16V_4 INT_HDMITX1P_R3 R287 *shortNRD@0_4 INT_HDMITX1P_C *CM1225-04DE GMT : AL005250003 INT_HDMITX1N_C 6 D1 Shield
INT_HDMITX1N C435 NRD@0.1u/16V_4 INT_HDMITX1N_R3 R283 *shortNRD@0_4 INT_HDMITX1N_C INT_HDMITX0P_C 5 6 INT_HDMITX0P_C INT_HDMITX0P_C 7 D1- R286 *120/F_4
INT_HDMITX0N_C 4 5 6 7 INT_HDMITX0N_C 8 D0+
3 4 7 INT_HDMITX0N_C 9 D0 Shield 23 INT_HDMITX1N_C
INT_HDMICLK+_C 2 GND_3/8 9 INT_HDMICLK+_C INT_HDMICLK+_C 10 D0- GND
INT_HDMITX0P C442 NRD@0.1u/16V_4 INT_HDMITX0P_R3 R300 *shortNRD@0_4 INT_HDMITX0P_C INT_HDMICLK-_C 1 2 9 10 INT_HDMICLK-_C 11 CK+ 22 INT_HDMITX0P_C
INT_HDMITX0N C444 NRD@0.1u/16V_4 INT_HDMITX0N_R3 R295 *shortNRD@0_4 INT_HDMITX0N_C 1 10 INT_HDMICLK-_C 12 CK Shield GND
ESD3 13 CK- R279 *120/F_4
INT_HDMICLK+ C422 NRD@0.1u/16V_4 INT_HDMICLK+_R3 R272 *shortNRD@0_4 INT_HDMICLK+_C 14 CE Remote
INT_HDMICLK- C420 NRD@0.1u/16V_4 INT_HDMICLK-_R3 R266 *shortNRD@0_4 INT_HDMICLK-_C R265 R274 R277 R282 R285 R291 R298 R302 HDMI_DDCCLK_MB 15 NC INT_HDMITX0N_C
499_4 499_4 499_4 499_4 499_4 499_4 499_4 499_4 HDMI_DDCDATA_MB 16 DDC CLK
17 DDC DATA INT_HDMICLK+_C
18 GND
A Close to Choke HDMI_MB_HPD R246 *short_4
+HDMI_5V
HP_DET_CN 19 +5V R271 *120/F_4
A
HP DET 21
SHELL2
3

INT_HDMICLK-_C
HDMI_CONN
Q17 D23 D25 D4
+5V R255 *short_4 2 *EGA_4 *EGA_4 *EGA_4

2N7002K
R247 Quanta Computer Inc.
1

100K/F_4
PROJECT : ZAB
Size Document Number Rev
1A
De-Mux (PS8339B )/HDMI
Date: Friday, March 04, 2016 Sheet 19 of 45
5 4 3 2 1
 5 4 3 2 1

DP TO VGA (CRT)

[5,9,10,25] CLK_SDATA
R240
R241
*0_4
*0_4
20
[5,9,10,25] CLK_SCLK
C398
Power
0.1U/16V_4

CIIC_SDA
CIIC_SCL
DP_HPD
D +3V D

+3V
L9 AVCC33 VCCK_V12
BLM15BB470SN1D(47/0.3)_4
C397 C395

33

32

31

30

29

28

27

26

25
L18 VDD_DAC_33 U16
BLM15BB470SN1D(47/0.3)_4 0.1U/16V_4 2.2U/10V_4

XI
EXT1.2V_CTRL

SMB_SCL

PVCC_33

VCCK_12
SMB_SDA

LDO_RSTB
EPAD

HPD
AVCC33 1 24
AVCC_33 GND
AUX_CH_P 2 23 CRT_RED
R242 *short_4 DP_HPD AUX_P RED_P
[4] DP2_HPD AUX_CH_N CRT_GRE
3 22
AUX_N GREEN_P
R243
100K/F_4
C382
VCCK_V12

LANE0_P
4

5
AVCC_12

LANE0_P
RTD2166 VDD_DAC_33
BLUE_P
21

20
CRT_BLU

VDD_DAC_33

0.1U/16V_4 LANE0_N 6 19 HSYNC C779

LANE0_N HSYNC
LANE1_P 7 18 VSYNC +5V 0.1U/16V_4
LANE1_P VSYNC
LANE1_N 8 17
Note:

POL1/SPI_CEB
C393 0.1U/16V_4 AUX_CH_N LANE1_N HVSYNC_PW R
[4] DP2_AUX#
C365 C364
1- Caps should be placed close to chip

VGA_SDA
VGA_SCL
C C

SPI_CLK
AUX_CH_P

VCC_33
C394 0.1U/16V_4

SPI_SO
[4] DP2_AUX 2- Pin 9's Cap shold be X5R material

SPI_SI
0.1U/16V_4 4.7U/6.3V_4

POL2
C385 0.1U/16V_4 LANE0_P 3- R,G,B's R should be 75 ohm with +/-1%
[4] DP2_TX0
RTD2166CG 4- Suggest to connect Pin 29 and Pin 30 to PCH SMBUS for debug purpose.

10

11

12

13

14

15

16
C375 0.1U/16V_4 LANE0_N +3V
[4] DP2_TX0#
5- This configuration is for internal ROM mode and using embedded LDO mode.

4.7K_4

4.7K_4
*4.7K_4
LANE1_P Slave Address:

DDCDAT
DDCCLK
C371 0.1U/16V_4 R230 4.7K_4
[4] DP2_TX1 0x64/0x65 and 0x68/0x69

TP37
LANE1_N

+3V
C368 0.1U/16V_4
[4] DP2_TX1#

R229

R853

R854
+3V

RTD2166 integrate 5V HSYNC/VSYNC buffer inside IC

Reserved for debug ESD2
CRT_R1 5 6 CRT_R1 CRTVDD5 R217 2.2K_4 DDCCLK
CRT_G1 4 5 6 7 CRT_G1 R220 2.2K_4 DDCDAT
B
3 4 7 BCD : AL002802002 B
+5V CRT_B1 2 GND_3/8 9 CRT_B1 GMT : AL005250003
U36 CRTVDD5 1 2 9 10 CRTVDD5 Q15
1 10 3 1 CRTVDD5
+5V IN OUT
1 5 C741 *0.1u/16V_4 *CM1225-04DE 2
OE# VCC GND C334 0.1u/16V_4 CN13

16
ESD1 AP2802NTR-G1-01
HSYNC R671 *0_4 2 4 R667 *33_4 CRTHSYNC DDCDAT 5 6 DDCDAT Close to RT2166
A Y CRTHSYNC 4 5 6 7 CRTHSYNC 6
3 4 7 CRT_RED L8 BLM15BB470SN1D(47/0.3)_4 CRT_R1 1 11 CRT_11
GND_3/8 TP35
3 CRTVSYNC 2 9 CRTVSYNC 7
GND DDCCLK 1 2 9 10 DDCCLK CRT_GRE L7 BLM15BB470SN1D(47/0.3)_4 CRT_G1 2 12 DDCDAT
1 10 8
*74AHCT1G125GW *CM1225-04DE CRT_BLU L6 BLM15BB470SN1D(47/0.3)_4 CRT_B1 3 13 CRTHSYNC
R670 *short_4 R666 47/F_4 9
4 14 CRTVSYNC
C360 C354 C345 C344 C353 C359 10
R225 R224 R221 5 15 DDCCLK
C336 0.22u/10V_4 CRTVDD5 75/F_4 75/F_4 75/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4

+5V C332 *220p/50V_4 CRT_CONN

17
U34
C333 0.1u/16V_4
1 5 C750 *0.1u/16V_4
OE# VCC C338 2.2P/50V_4 CRTVSYNC
vendor test report
VSYNC R654 *0_4 2 4 R663 *33_4 CRTVSYNC C339 2.2P/50V_4 CRTHSYNC
A Y
A C337 1n/50V_4 DDCCLK A
3
GND C341 1n/50V_4 DDCDAT vendor projector result
*74AHCT1G125GW
R661 *short_4 R662 47/F_4
Quanta Computer Inc.
PROJECT : ZAB
Co-Layout Size Document Number Rev
1A
CRT/DP2VGA(RTD2166)
Date: Monday, March 07, 2016 Sheet 20 of 45
5 4 3 2 1
 5 4 3 2 1

LAN & Card reader Combo (LAN)

10p/50V_4 C348 LAN_XTALI

Tramsformer
21
2
1
SP8 All termination trace > 30 mils
Y1
25MHZ C352 *10P/50V_4 U35
1 24 LAN_MCT0

4
3
LAN_XTAL2 TP36 MDI_0+ 2 TCT1 MCT1 23 LAN_MX0+
10p/50V_4 C347 MDI_0- 3 TD1+ MX1+ 22 LAN_MX0-
PCIE_LAN_WAKE#_R TD1- MX1-
4 21 LAN_MCT1
TCT2 MCT2

TP31

TP33
MDI_1+ 5 20 LAN_MX1+
TP34 MDI_1- 6 TD2+ MX2+ 19 LAN_MX1-
VDD10 TD2- MX2-
D D
TP32 7 18 LAN_MCT2
R223 2.49K/F_4 RSET MDI_2+ 8 TCT3 MCT3 17 LAN_MX2+
C351 *10P/50V_4 MDI_2- 9 TD3+ MX3+ 16 LAN_MX2-
10 mils TD3- MX3-
+LANVCC LAN_MCT3
10 15
MDI_3+ 11 TCT4 MCT4 14 LAN_MX3+

GND
MDI_3- 12 TD4+ MX4+ 13 LAN_MX3-

48
47
46
45
44
43
42
41
40
39
38
37
U15 TD4- MX4-

75/F_8

75/F_8

75/F_8

75/F_8
TRANSFORMER

HV_GIGA

CKXTAL2
CKXTAL1
MS_CD#
SD_CD#
LED0

LANWAKEB
LED1/GPO
LED2
RSET
LV_CEN

LED_CR

25
49
E_PAD C331
0.01U/50V/X7R_4
+3V

R219

R218

R216

R215
REGOUT
VDDREG
MDI_0+ 1 36
MDI_0- 2 MDIP0 REG_OUT 35 R227 *short_8 R232
MDIN0 VDDREG +LANVCC
VDD10
3 34 ENSWREG R226 *short_4 1K/F_4
AVDD10 ENSWREG

TERM9
MDI_1+ 4 33
MDI_1- MDIP1 VDD1 VDD10
5 32 R228 *short_4 +LANVCC
MDI_2+ 6 MDIN1 VD33 31 ISOLATEB
MDI_2- 7 MDIP2 RTL8411B-CG ISOLATEBPIN 30 PERSTBPIN
8 MDIN2 PERSTBPIN 29 PCIE_REQ_LAN#_R C714
VDD10 MDI_3+ AVDD10 CLKREQBPIN
9 28 SP7 R231 1000P/3KV_1808
MDI_3- 10 MDIP3 QFN48 MS_BS/SD_WP# 27 VDD33/18
11 MDIN3 DV33_18 26 PCIE_RXN0_C2 C387 0.1u/16V_4 15K/F_4
+LANVCC HV_GIGA HSON PCIE_RXP0_C2 PCIE_RXN0 [2]
12 25 C392 0.1u/16V_4
+3V VDD3 HSOP PCIE_RXP0 [2]
SD_CMD/MS_D2

C374
SD_CLK/MS_D0

SD_D2/MS_CLK
SD_D0/MS_D1

SD_D3/MS_D3

0.1U/16V_4
REFCLK_N
CARD_3V3

REFCLK_P
VDDTX
SD_D1

RJ45 Connector
HSIN
HSIP

R234 NAC@0_4
13
14
15
16
17
18
19
20
21
22
23
24

PCIERST# [5,11,18,22,23]
CN10

LAN_MX0+ 1 12
+CARD_3V3 LAN_MX0- 0+ G
R233 IOAC@0_4 2 11
C IOAC_RST# [22,33] LAN_MX1+ 0- G C
C390 3
SP1 LAN_MX2+ 4 1+
0.1U/16V_4 SP2 CLK_PCIE_LANN [6] LAN_MX2- 5 2+
SP3 CLK_PCIE_LANP [6] LAN_MX1- 6 2-
SP4 PCIE_TXN0 [2] LAN_MX3+ 7 1- 10
PCIE_TXP0 [2] LAN_MX3- 3+ G
SP5 8 9
3- G
SP6

CONN_RJ45_SINK
EVDD10

For RTL8111H
Place 0.1 uF close to each pin 11, 32,48
+LANVCC
40 mils (Iout=1A)
RTL8111H (LDO mode) close to each VDD10 pin-- 3, 8, 33, 46 close to each VDD10 pin-- 46 Crad Reader Connector
REGOUT (reserve)
VDD10
C349 C355 C373 C342 C346 40 mils (Iout=1A) 40 mils (Iout=1A)
R222 *short_8 EMI CN2
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 4.7U/6.3V_4 4.7U/6.3V_4
SP7 11
C356 C343 C396 C366 C350 C362 C363 SP8 10 WP 16
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 *1U/6.3V_4 *0.1u/16V_4 SP6 R365 *short_4 9 CD NC 17
For RTL8111H SP1 R362 *short_4 8 DATA2 NC
Place 4.7 uF close to each pin 12,35 SP2 R363 *short_4 7 DATA1
6 DATA0
SP3 R364 *short_4 SD_CLK_R 5 VSS2
R359 *short_4 +VCC_XD 4 CLK
+CARD_3V3 VDD
3
SP4 R360 *short_4 2 VSS1

GND
GND
GND
GND
SP5 R361 *short_4 1 CMD
CD/DATA3
SD-CARD

12
13
14
15
VDD10 EVDD10 VDDREG R855 C508
B 30 mils 40 mils C502
B
10 mils *2K/F_4 4.7u/6.3V_4 0.1u/16V_4
R239 *short_6
VDD33/18 10 mils
C391 C386 C361 C357
Close to CONN
C372 C369
1U/6.3V_4 0.1U/16V_4 *4.7U/6.3V_4 0.1U/16V_4
*4.7U/6.3V_4 0.1U/16V_4
EMI
SP1
SP2
Place close to pin 27 SP3
SP4
Close to Pin20 Place connect to Pin35 SP5
SP6

C505 C506 C507 C503 C504 C509

*10p/50V_4 *10p/50V_4 *10p/50V_4 *10p/50V_4 *10p/50V_4 *10p/50V_4

Leakage circuit IOAC

+3V +3V +3V

R292 R235
Share Pin
10K/F_4 *10K/F_4 +3VPCU +LANVCC +3V_S5 SP1 SD_D1
2

3V_S0 MAIN POWER(3V_S0) Q20 SP2 SD_D0 MS_D1

IOAC@AO3413 SP3 SD_CLK MS_D0
1 3 PCIE_REQ_LAN#_R SP4 SD_CMD MS_D2
[5] PCIE_REQ_LAN# +3V_LAN
1 3 R261 IOAC@0_8 R262 NAC@0_8 SP5 SD_D3 MS_D3
Q18 SP6 SD_D2 MS_CLK
*2N7002K C440 SP7 SD_WP MS_BS
R268 *short_4 R294 C400 C383 C370 C399 SP8 SD_CD#
2

*IOAC@0.1U/16V_4 *IOAC@100K/F_4 10U/6.3V_4 0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 SP9 MS_INS#

+LANVCC
A A
[33] LANPWR# R293
IOAC@10K/F_4 C439

R290 *IOAC@1000p/50V_4
IOAC@10K/F_4
2

EC_PCU LANVCC
R269 IOAC@0_4 3 1 PCIE_LAN_WAKE#_R
[33] IOAC_LAN_WAKE#
Q19
IOAC@2N7002K
[5,12,22] PCIE_LAN_WAKE#
R297 NAC@0_4
Quanta Computer Inc.
APU 3V_S5(Ext PU) PROJECT : ZAB
Size Document Number Rev
1A
LAN-CR COMBO
Date: Thursday, March 03, 2016 Sheet 21 of 45
5 4 3 2 1
 5 4 3 2 1

NGFF_M.2 WiFi & BT (NGF)

CN3
+W L_VDD
22
+W L_VDD
1
NGFF 2
3 GND 3.3Vaux 4
[6] USBP2+ 5 USB_D+ 3.3Vaux 6 C11 10U/6.3V_4
[6] USBP2- 7 USB_D- LED#1 8 C5 0.1u/16V_4
9 GND PCM_CLK 10 C6 0.1u/16V_4
11 SDIO CLK(O) PCM_SYNC 12 C13 0.1u/16V_4
D SDIO CMDIO) PCM_IN D
13 14 C12 0.1u/16V_4
15 SDIO DAT0(IO) PCM_OUT 16
17 SDIO DAT1(IO) LED#2 18
19 SDIO DAT2(IO) GND 20
21 SDIO DAT3(IO) UART Wake 22
23 SDIO Wake(I) UART Rx 24
25 SDIO Reset Key 5 26
27 KEY1 Key 6 28
29 KEY2 Key 7 30
31 KEY3 Key 8 32
33 KEY4 UART Tx 34
35 GND UART CTS 36
[2] PCIE_TXP1 PETp0 UART RTS
37 38
[2] PCIE_TXN1 PETn0 Clink RESET
39 40
41 GND CLink DATA 42
[2] PCIE_RXP1 PERp0 CLink CLK
43 44
[2] PCIE_RXN1 PERn0 COEX3
45 46
47 GND COEX2 48 R374 NAC@0_4
[6] CLK_PCIE_W LANP REFCLKP0 COEX1 PCIERST# [5,11,18,21,23] WIFI card reset (non-IOAC)
49 50 SUSCLK R377 IOAC@0_4
[6] CLK_PCIE_W LANN REFCLKN0 SUSCLK(32KHz) W LAN_RST# IOAC_RST# [21,33] WIFI card reset (IOAC)
51 52 R375 *0_4
CLKREQ_W LAN# GND PERST0# BT_EN PLTRST# [5,25,33] Debug card reset
53 54
W AKE_W LAN# CLKREQ0# W_DISABLE#2 RF_EN BT_EN [33]
55 56
PEWake0# W_DISABLE#1 RF_EN [33]
57 58
59 GND NFC I2C SM DATA 60
61 PETp1 NFC I2C SM CLK 62
63 PETn1 NFC I2C IRQ 64 A_LAD0_R R378 *short_4
GND NFC Reset# A_LAD1_R LPC_LAD0 [6,25,33]
65 66 R379 *short_4
PERp1 RESERVED3 A_LAD2_R LPC_LAD1 [6,25,33]
67 68 R380 *short_4
PERn1 RESERVED4 A_LAD3_R LPC_LAD2 [6,25,33]
69 70 R382 *short_4
CLK_LPC_DEBUG_C GND RESERVED5 LPC_LAD3 [6,25,33]
R384 *0_4 71 72
[6] CLK_LPC_DEBUG LPC_LFRAME#_C Reserved1 3.3Vaux +W L_VDD
R385 *0_4 73 74
C [6,25,33] LPC_LFRAME# Reserved2 3.3Vaux C
75
FOR Debug card, MP remove them. GND

W LAN_NGFF_CONN_E_KEY

Leakage circuit
Keep 0 Ohm +3V +W L_VDD
(don't change to short pad)
Q1 IOAC@AO3413 +W L_VDD +3V

1 3+3V_W LAN R2 R373 R367

+3VPCU IOAC@0_8 R1 NAC@0_8
*4.7K_4 IOAC@4.7K_4

2
C7
R4 C4 C1 C3 C2 1 3 CLKREQ_W LAN#
2

[5] PCIE_CLKREQ_W LAN#

*IOAC@0.1U/16V_4 *IOAC@100K/F_4 *10U/6.3V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4
APU 3V_S0(Int PU) Q30 IOAC 3V_S0
IOAC@2N7002K
R3
[33] W LANPW R# R370 NAC@0_4
IOAC@10K/F_4 C9

B *IOAC@1000p/50V_4 B
+W L_VDD

Low M2 card power enable

R371
High M2 card power disable IOAC@4.7K_4

2
EC PCU
R366 IOAC@0_4 3 1 W AKE_W LAN#
[33] IOAC_W LAN_W AKE#
R369 *0_4 Q28 IOAC 3V_S0
[5,12,21] PCIE_LAN_W AKE#
IOAC@2N7002K
***ZRZ reserved for 1.5V's module (doesn't use) APU 3V_S5(Ext PU)

Q2 *IOAC@AO3413
+W L_VDD
1 3+3V_W LAN
+1.5VSUS
C8
R6
2

*IOAC@0.1U/16V_4 *IOAC@100K/F_4 R372

2
*10K/F_4

W LANPW R# R5 3 1 SUSCLK
[5] SUS_CLK
*IOAC@10K/F_4 C10 APU 3V_S5(Ext PU) Q29 +WL_VDD
*2N7002K C516
*IOAC@1000p/50V_4 *22P/50V_4
A R368 *0_4 A

Quanta Computer Inc.

PROJECT :ZAB
Size Document Number Rev
1A
NGFF(WiFi&BT combo)
Date: Thursday, March 03, 2016 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

PCIE to SATA III (HDD)

Power up sequence
AKE35ZN0N00 (1 Mb)...EC
AKE37FN0N05 (4 Mb)..SSD
refer to support list

+3.3V_10048 +3.3V_10048
SPI ROM
23
+3.3V & +1.2V R679
90% *SSD@4.7K_4
+3.3V_10048
+3.3V_10048
U38
SPI_CS_10048 1 8
PERST SPI_DI_10048 CE# VDD HOLD#_10048
2 7
WP#_10048 3 SO HOLD# 6 SPI_CLK_10048
4 WP# SCK 5 SPI_DO_10048 R687 **SSD@4.7K_4 R674 *shortSSD@0_4
VSS SI PCIERST# [5,11,18,21,22]

TP69
D
*SSD@W25X40CLSNIG SPI_DO D
C777 0: Spin up by H/W Close to IC
*SSD@0.1u/16V_4 1: Spin up by S/W +3V +3.3V_10048
HOLD#- R673 SSD@12.1K/F_4
T>0ms 0:Operation Lock H/W Strapping
refer to datasheet:

PERST_10048
R653 *shortSSD@0_4

SPI_CLK_10048
1:Normal Operation

PREXT_10048
SPI_CS_10048
SPI_DO_10048
+3.3V_10048
+1.2V_10048

SPI_DI_10048
+1.2V_10048
+1.2V_10048
>40mil Frequency Tolerance: +/-30PPM 2nd source:
L17 SSD@4.7uH/1A_2X2

49
48
47
46
45
44
43
42
41
40
39
38
37
+1.2V_L10048 EXTL_10048
CL: 20pf TXC:BG620000040 U37
HHE:BG620000039

SPI_DO

PREXT
LED
GND4
VCC12_4

PERST#
VCC33_2
VCC12_3
GND3
SPI_DI
SPI_CS#
TESTMODE

SPI_CK
L and C close to pin2 1 36 +3.3V_10048
C759 C765 XO_10048 EXTL_10048 2 VSSPWM VCC33P 35 PTXN_10049 C762 SSD@0.1U/16V/X7R_4
+3.3V_10048 R672 EXTL PTXN PTXP_10048 PCIE_RXN2 [2]
SSD@0.1u/16V_4 SSD@10u/6.3V_4 *shortSSD@0_4 VCC33IN4 3 34 C760 SSD@0.1U/16V/X7R_4
VCC33IN PTXP PCIE_RXP2 [2]

3
4
low ESR TP68 GPIO0_I2C_CLK4 4 33
Y5 TP67 GPIO1_I2C_DATA4 5 GPIO0 GNDA3 32
GPIO1 PRXN PCIE_TXN2 [2]
close to pin 1 XTAL-CAP=NPO type C756 SSD@20MHz C761 TP66 6 31
+1.2V_10048 GPIO2 PRXP +1.2V_10048 PCIE_TXP2 [2]
SSD@15P/50V_4 SSD@10u/6.3V_4 TP65 7 30
8 VCC12_1 VDD12P 29 XI_10048

1
2
close to +3.3V_10048 9 GND1 XI 28 XO_10048
Internal 1.25V voltage Cout is mandatory. VCC33_1 XO
XI_10048 pin3/pin 1 10 27
+1.2V_10048 GND2 PECLKN CLK_PCIE_SSDN [6]
11 26
CLK_PCIE_SSDP [6]

SRXN_B

SRXN_A
VCC12_2 PECLKP

SRXP_B

SRXP_A
STXN_B

VCC33S

STXN_A
STXP_B

STXP_A
+1.2V_10048 12 25 +1.2V_10048

GNDA1

GNDA2
Cin is mandatory.

SREXT
VDD12S_1 VDD12S_2
XI & XO follow differential layout rule for Min. jitter
+1.2V_10048
SSD@ASM1061

13
14
15
16
17
18
19
20
21
22
23
24
C771 SSD@0.1u/16V_4

C766 SSD@0.1u/16V_4

+3.3V_10048

STXN_A_10048

SRXN_A_10048
SRXP_A_10048
STXP_A_10048
C749 SSD@0.1u/16V_4 +1.2V_10048 +3.3V_10048

SREXT_10048
+3.3V_10048
C758 SSD@0.1u/16V_4 C763 SSD@0.1u/16V_4

C
C755 SSD@0.1u/16V_4 C768 SSD@0.1u/16V_4 C

C754 SSD@0.1u/16V_4 C748 SSD@0.1u/16V_4

Vendor suggest: AL902525001(RT9025-25GSP)
C769 SSD@0.1u/16V_4 C757 SSD@0.1u/16V_4

Delete... C770 SSD@0.1u/16V_4

R657
Just choose one of external 1.25V regulator C767 SSD@0.1u/16V_4 SSD@12.1K/F_4

or IC internal regulator (@Pin 2). C772 SSD@0.1u/16V_4 Close to IC

Close to ASM1061

Option; refer to datasheet or contact FAE

NGFF_M.2 SSD (NGF)

+3V +3V_SATA +3V_SATA
Close SSD CONN
1.5A
R650 *shortSSD@0_8 +3V_SATA

C718 C716 C726 C720 C715

6/25 Add R580/R581 by Kingston SSD. CN12 C738 C739
+3V_SATA SSD@10u/6.3V_4 SSD@0.1U/16V_4 SSD@0.1U/16V_4 SSD@0.1U/16V_4 SSD@0.1U/16V_4
*SSD@0.1u/10V_4 *SSD@10u/6.3V_4
R628 *shortSSD@0_4 SSD_PRESENCE 1
NGFF 2
3 GND 3.3V 4
5 GND 3.3V 6
7 PERn3 NC 8
rating = 1000mA @ 128G
9 PERp3 NC 10 DAS TP61
11 GND DAS 12
13 PETn3 NOTCH/3.3V 14
B PETp3/NOTCH NOTCH/3.3V B
15 16
17 GND/NOTCH NOTCH/3.3V 18
19 PERn2/NOTCH NOTCH/3.3V 20
21 PERp2/NOTCH NC 22
23 GND/CONFIG_0 NC 24
25 PETn2 NC 26
PETp2 NC pin Type Description
27 28
29 GND NC 30
31 PERn1 NC 32
33 PERp1 NC 34 +3V_SATA
GND NC
This pin is grounded on the SSD. May be used by host to
35 36 determine if slot is empty or populated
From ASM1061 37 PETn1 NC 38 DEVSLP R644 *SSD@10K/F_4
1 PRESENCE
39 PETp1 DEVSLP 40 R645 SSD@1K/F_4
SRXP_A_10048 C724 SSD@0.01u/50V_4 SATA_RXP_SSD_C 41 GND NC 42
SRXN_A_10048 C723 SSD@0.01u/50V_4 SATA_RXN_SSD#_C 43 PERn0/SATA-B+ NC 44
PERp0/SATA-B- NC 10 DAS# Device Activity Signal
45 46
STXN_A_10048 C722 SSD@0.01u/50V_4 SATA_TXN_SSD#_C 47 GND NC 48
STXP_A_10048 C721 SSD@0.01u/50V_4 SATA_TXP_SSD_C 49 PETn0/SATA-A- NC 50 SSD_PLTRST# TP60
51 PETp0/SATA-A+ PERST# 52
GND CLKREQ# 21 WWAN/SSDIND_N This pin connect to Ground
53 54
55 REFCLKn PEWake# 56 TP63
57 REFCLKp N/C 58 TP62
59 GND N/C 60
NOTCH NOTCH 38 Device Sleep Signal If system didn't support DEVSLP, set DEVSLP Sleep Signal pin
61 62 power high and keep (from power on), device will ignore.
63 NOTCH NOTCH 64
NOTCH NOTCH If system support DEVSLP, set DEVSLP Sleep Signal pin power low
65 66 (from power on) device, device will support DEVSLP function.
RESET_C 67 NOTCH NOTCH 68 PCH_SUSCLK TP59
TP58
SSD_PEDET NC SUSCLK(32KHz) Device Sleep Signal H: SSD enter sleep model.
69 70
71 PEDET 3.3V 72
Device Sleep Signal L: SSD exit sleep model.
73 GND 3.3V 74
R632 75 GND 3.3V
53 REFCLKN no connect on SSD
GND
GND

GND
*shortSSD@0_4

SSD@SSD_NGFF_CONN_M_KEY
76
77

55 REFCLKP no connect on SSD

56 MFG1 Manufacturing pin. Use determined by vendor.

Must be a noconnect on the host board

58 MFG2 Manufacturing pin. Use determined by vendor.

Card pin69 = Ground (SATA card) Must be a noconnect on the host board

A A
68 SUSCLK no connect on SSD

69 IFDET This pin connect to Ground

Quanta Computer Inc.

PROJECT :ZAB
Size Document Number Rev
1A
M.2 SSD/ASM1061
Date: Friday, March 04, 2016 Sheet 23 of 45
5 4 3 2 1
 5 4 3 2 1

Codec(ADO)
HP-R2

HP-L2
DC-DET circuit(ADO) +15V to VIN

VIN
+5V
R742

3
*short_6

1 PVDD
24
+5V C807 Q49
LINE1-VREFO-L R752 *10u/6.3V_4 *AO3404

2
*1M_6
LINE1-VREFO-R

MIC2-VREFO
R750

3
*100K/F_4
CODEC_VREF C856 2.2U/10V_4 ADOGND
DC-DET R758 *0_4 2 Q51
INT_AMIC-VREFO C851 10u/6.3V_4 *DTC144EU
ADOGND +5VA

C853

C852

C854
R782 100K/F_4

1
10u/6.3V_4

1U/6.3V_4

1U/6.3V_4
C858
D D
C855
0.1u/16V_4 10u/6.3V_4
+AZA_VDD
Place next to pin 26

36

35

34

33

32

31

30

29

28

27

26

25
+1.5VA
U44
ADOGND HEADPHONE/MIC/LINE combo (ADO)

CPVDD

CBN

HP-OUT-R

LINE1-VREFO-R
CPVEE

LDO1-CAP
VREF
HP-OUT-L

LINE1-VREFO-L

MIC2-VREFO

AVDD1

AVSS1
C843
C846
10u/6.3V_4 0.1u/16V_4 MIC2-VREFO R818 2.2K_4
ADOGND 37 24
CBP LINE2-L R827 2.2K_4
38 23
ADOGND AVSS2 LINE2-R SLEEVE R819 *short_4
39 22 SLEEVE_R [27]
Place next to pin 40 C850 10u/6.3V_4 LINE1-L
LDO2-CAP LINE1-L RING2 R828 *short_4
RING2_R [27]
Analog 40 21 LINE1-R
AVDD2 LINE1-R HP-L2 R835 62_4
+5V_PVDD HP-L3 [27]
Digital L21 41 20 R343 *short_6
PVDD PVDD1 NC +3VPCU
PBY160808T-600Y-N_60_3A_6 analog digital HP-R2 R839 62_4
L_SPK+ 42 19 HP-R3 [27]
C840 10u/6.3V_4 ADOGND
C839 C837 SPK-L+ MIC-CAP HP_JD#

10u/6.3V_4 0.1u/16V_4
L_SPK- 43
SPK-L-
ALC255-CG MIC2-R/SLEEVE
18 SLEEVE trace width of SLEEVE & RING2
R834 R838
HP_JD# [27]

R_SPK- 44 17 RING2 are required at least 40mil and LINE1-L C874 4.7U/6.3V_4 *10K/F_4 *10K/F_4 C876 C883 C885 C887
SPK-R- MIC2-L/RING2 its length should be asshort as possible
R_SPK+ 45 16 LINE1-VREFO-L R810 4.7K_4 100p/50V_4 100p/50V_4 100p/50V_4 100p/50V_4
Low is power down SPK-R+ MONO-OUT
amplifier output 46 15 LINE1-VREFO-R R809 4.7K_4
PVDD2 SPDIFO/FRONT JD
GPIO0/DMIC-DATA

PD# 47 GPIO1/DMIC-CLK 14 Placement near Audio Codec LINE1-R C873 4.7U/6.3V_4 ADOGND
C833 C836 PDB MIC2/LIN2 JD
48 13 SENSEA R778 200K/F_4 HP_JD#

SDATA-OUT
TP85 SPDIF-OUT HP/LINE1 JD

LDO3-CAP
10u/6.3V_4 0.1u/16V_4

SDATA-IN

DVDD-IO

PCBEEP
RESETB
BIT-CLK
R775 100K/F_4 +3V
DVDD

SYNC
DVSS

49
DGND
Analog
Digital
D-Mic (MIC) A-test
1

10

11

12
+3V +3V_DMIC
DMIC_DAT

C825

R214 *short_4
1st: AL403010A00/ KMM40301026-18DS only stuff Single MIC
DC-DET
DMIC_CLK

1.6Vrms
+AZA_VDD BEEP_1
2nd: AL403010000/ KMM40301026-18DZ
R766

+3V R316 *short_6 PCBEEP C826 0.1u/16V_4 R759 22K_4 D37 1N4148WS
SPKR [5]
* : dual
10u/6.3V_4

+3V_DMIC
C D36 1N4148WS C
C827 R768
PCBEEP_EC [33]
C732 10u/6.3V_4
**: DNI
*short_4

C822 C823 100p/50V_4 10K/F_4 C733 0.1u/16V_4

0.1u/16V_4 10u/6.3V_4 C731 10p/50V_4
+3V +1.5V
U14
DMIC_CLK_L R660 *short_4 DMIC_CLK_L1 3 1
CLK VDD
PCH_AZ_CODEC_RST# [5] DMIC_DAT_L DMIC_DAT_L1
R317 *0_4 R659 *short_4 4 2
DMIC_DAT_L R756 *short_4 PCH_AZ_CODEC_SYNC [5]
APU 1.5V 7
DATA LR
5 Left

*TVS/6pF_4

*TVS/6pF_4
DMIC_CLK_L R757 22_4 DVDD_IO R318 *short_4 8 GND GND 6
Tied at one point only under

*10p/50V_4

*10p/50V_4
GND GND
the codec or near the codec
KMM40301026-18DS

1
R840 *0_4 C812 ACZ_SDIN R767 33_4 C478 C477
PCH_AZ_CODEC_SDIN0 [5]
R784 *0_4 10p/50V_4 Single DMIC
R771 *0_4 0.1u/16V_4 10u/6.3V_4
R785 *0_4
PCH_AZ_CODEC_BITCLK [5] DUAL MAIN

D19

D18
C747

C746
2

2
R779 *0_4 C824 *22p/50V_4
R342 *short_4 +3V_DMIC
C875 *1000p/50V_4 PCH_AZ_CODEC_SDOUT [5] Place next to pin 9
C743 **SP17@10u/6.3V_4
C847 0.1u/16V_4 C742 **SP17@0.1u/16V_4
C744 **SP17@10p/50V_4

ADOGND
U12
Cap need near AVDD1 and AVDD2
power source input
DMIC_CLK_L

DMIC_DAT_L
R669

R668
*SP17@0_4

*SP17@0_4
DMIC_CLK_L2

DMIC_DAT_L2
3

4
CLK VDD
1

2
17" Right
7
DATA

GND
LR

GND
5
SP17@: 17" only

**SP17@10p/50V_4

**SP17@TVS/6pF_4
**SP17@10p/50V_4

**SP17@TVS/6pF_4
8 6
GND GND
*SP17@KMM40301026-18DS

1
DUAL SECOND

D22

D21
CO-LAYOUT Stuff when dual MIC

C752

C751
2

2
+3V_DMIC

C735 **SP15@10u/6.3V_4
C736 **SP15@0.1u/16V_4
B B
C737 **SP15@10p/50V_4

U13
DMIC_CLK_L

DMIC_DAT_L
R656

R655
*SP15@0_4

*SP15@0_4
DMIC_CLK_L3

DMIC_DAT_L3
3

4
CLK VDD
1

2
15" Right
7
DATA

GND
LR

GND
5
SP15@: 15" only

**SP15@10p/50V_4

**SP15@TVS/6pF_4
**SP15@10p/50V_4

**SP15@TVS/6pF_4
8 6
GND GND
*SP15@KMM40301026-18DS

1
DUAL SECOND

D20

D17
Stuff when dual MIC

C740

C745
2

2
Codec PWR 5V(ADO) Mute(ADO) Codec PWR 1.5V(ADO)
+AZA_VDD +1.5V

R754
1K/F_4
2

DIGITAL ANALOG
L24 HCB2012KF220T60/6A/22ohm_8 PD# D34 *RB500V-40 3 1 PCH_AZ_CODEC_RST#
+5V +5VA +1.5VA
U47 R762
3 4 *10K/F_4 C820 Q50 DIGITAL ANALOG
IN OUT *PJA138K
*1U/6.3V_4
2
GND C862 C866 D33 RB500V-40 L23 BLM15AG121SN1D(120/0.5)_4
AMP_MUTE# [33] +1.5V
A 1 5 R798 *29.4K/F_4 A
SHDN SET *10U/6.3V_4 *0.1u/16V_4 C861
*G923-330T1UF
C867 C863 R800 1U/6.3V_4
*10K/F_4
*0.1u/16V_4 *10U/6.3V_4

R796 *0_4
ADOGND
Internal Speaker(ADO)
close pin3
ADOGND 4 ohm : 40mil for each signal CN22
R_SPK+ R817 *short_6 R_SPK+_1
R_SPK- R816 *short_6 R_SPK-_1 1
L_SPK- R815 *short_6 L_SPK-_1 2
L_SPK+ R814 *short_6 L_SPK+_1 3 5
4 6
SPK_CONN_4P
C881 C880 C879 C878 Quanta Computer Inc.
1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4
PROJECT : ZAB
Size Document Number Rev
Place these EMI components next to codec 1A
Codec(AL255) / HP / SPK / DMIC
Date: Friday, March 04, 2016 Sheet 24 of 45
5 4 3 2 1
 5 4 3 2 1

G-sensor (H3D)
R769 *shortGS@0_6 +3V
25
+G_SEN_PW

D C810 C828 U42 D

1 2
GS@0.1U/16V_4 GS@10U/6.3V_4 14 Vdd_IO NC 3
VDD NC

C821 GS@22P/50V_4
10
D35 GS@RB500V-40 ACCEL_INTA_R 11 RESERVED 15
[5] ACCEL_INTA ACCEL_INT2_R 9 INT1 RESERVED
D31 *GS@RB500V-40
[26] ACCEL_INT2 INT2
R739 *shortGS@0_4 7
R738 *shortGS@0_4 G_MBDATA_R 6 SA0 5
[5,9,10,20] CLK_SDATA SDA GND
[5,9,10,20] CLK_SCLK R747 *shortGS@0_4 G_MBCLK_R 4 12
SCL GND 13
PU on CPU side 8 GND 16
+G_SEN_PW CS GND
CLK_SDATA C806 GS@33P/50V_4
GS@LIS3DHTR
CLK_SCLK C808 GS@33P/50V_4

C C

R737 *GS@4.7K_4 G_MBDATA_R

+G_SEN_PW
R749 *GS@4.7K_4 G_MBCLK_R

TPM (TPM) +TPM_VDD

R700 *shortTPM@0_4 +TPM_VSB

DECOUPLING CAPACITORS
22 NOTE:
14
8

1
U41 Place 0.1 uF capacitors as close as
SERIRQ: R714 possible to the device power pins.

VSB
VDD3
VDD2
PU 10k on EC side (reserved) *TPM@10K/F_4 VDD1
+3V_S5 +TPM_VSB

15 4 R696 *shortTPM@0_4
[6,22,33] LPC_LAD3 LAD3 PP TP71
B 18 3 B
[6,22,33] LPC_LAD2 LAD2/SPI_IRQ GPX/GPIO2 TP70
[6,22,33] LPC_LAD1 21 30
24 LAD1/MOSI GPIO1 TP72
[6,22,33] LPC_LAD0 C785 C787
20 LAD0/MISO 29 TPM@10U/6.3V_4 TPM@0.1U/16V_4
[6,22,33] LPC_LFRAME# LFRAME/SCS GPIO0/XOR_OUT TP73
[6,33] SERIRQ R729 *shortTPM@0_4 SERIRQ_R 27 6 R695 *TPM@10K/F_4
R730 *shortTPM@0_4 PCLK_TPM_R 19 SERIRQ GPIO3/BADD 5
[6] PCLK_TPM LCLK/SCLK TEST
CLKRUN#: R712 LPC_CLKRUN#_D 13
*shortTPM@0_4 2 +3V +TPM_VDD
[6,33] CLKRUN# CLKRUN/GPIO04 NC1
PU 8.2 K on EC side PLTRST#_R 17 7
D27 TPM@RB500V-40 LPCPD#_R 28 LRESET/SPI_RST NC2 10 R694 TPM@2.2/F_6
[5,22,33] PLTRST# LPCPD NC3 11
26 NC4 12
+3V 31 NC7 NC5 25 C783 C800 C784 C797
NC8 NC6
GND1
GND2
GND3
GND4

TPM@10U/6.3V_4 TPM@0.1U/16V_4 TPM@0.1U/16V_4 TPM@0.1U/16V_4

B.M.

R727 TPM@NPCT650ABAYX_QFN32
33

9
16
23
32

*10K/F_4

[6] LPCPD# D24 TPM@RB500V-40

R728 This module is LPC interface

A SP@10K/F_4 IF SPI interface , reset need link PCIERST# A

w/o TPM: Stuff

with TPM: DNI
Quanta Computer Inc.
PROJECT : ZAB
Size Document Number Rev
1A
TPM (NPCT650)
Date: Thursday, March 03, 2016 Sheet 25 of 45
5 4 3 2 1
 5 4 3 2 1

SATA HDD (HDD)

SATA REDRIVER (HDD)
+601_VCC
EQ2
H - 14dB
X - 0dB
L - 7dB
DE1
H - -2dB
X - -4dB
L - 0dB
26
+3V +601_VCC R706 *SRD@4.7K_4 EQ2 R705 *SRD@4.7K_4 EQ1 DE2
R707 *SRD@4.7K_4 EQ1 R708 *SRD@4.7K_4 H - 14dB H - -2dB
R709 *SRD@4.7K_4 DEW1 R710 *SRD@4.7K_4 X - 0dB X - -4dB
R711 *SRD@0_4 L - 7dB L - 0dB
D D

C789 C778 C780 C790 C407 R682 *SRD@4.7K_4 DE1 R677 *SRD@4.7K_4
R681 *SRD@4.7K_4 DE2 R676 *SRD@4.7K_4 DEW1 DEW2
SRD@10U/6.3V_4 SRD@1U/6.3V_4 SRD@1U/6.3V_4 SRD@0.1u/10V_4 SRD@0.1u/10V_4 R683 *SRD@4.7K_4 DEW2 R686 *SRD@4.7K_4 H - Long Duration H - Long Duration
X - NC (Long) X - NC (Long)
L - Short Duration L - Short Duration
R680 *SRD@4.7K_4 EN R675 SRD@4.7K_4

SW7 - EN
H - Enabled
L - Standby Mode

DEW1
EQ2

EQ1
+601_VCC

20
19
18
17
16
U39

EQ2

EQ1
DEW1
VCC

GND
21
C788 *SRD@0.01u/50V_4 SATA_TXN0C 1 PPAD
[6] SATA_TXN0 SATA_TXP0C RX1P SATA_TXN0_PS SATA_TXN0_PS_R
C786 *SRD@0.01u/50V_4 2 15 R701 *SRD@0_4 CN15
[6] SATA_TXP0 RX1N TX1P SATA_TXP0_PS SATA_TXP0_PS_R
3 14 R697 *SRD@0_4 23
C782 *SRD@0.01u/50V_4 SATA_RXP0C 4 GND TX1N 13 GND23
[6] SATA_RXP0 TX2N GND
C781 *SRD@0.01u/50V_4 SATA_RXN0C 5 12 SATA_RXP0_PS R691 *SRD@0_4 SATA_RXP0_PS_R 1
[6] SATA_RXN0 TX2P RX2N GND1
11 SATA_RXN0_PS R688 *SRD@0_4 SATA_RXN0_PS_R SATA_TXP0_PS_R 0.01u/50V_4 C835 SATA_TXP0_C 2
DEW2 6 RX2P SATA_TXN0_PS_R 0.01u/50V_4 C832 SATA_TXN0_C 3 RXP
EN 7 DEW2 22 4 RXN
DE2 8 EN GND 23 SATA_RXN0_PS_R 0.01u/50V_4 C831 SATA_RXN0_C 5 GND2
DE1 9 DE2 GND 24 SATA_RXP0_PS_R 0.01u/50V_4 C829 SATA_RXP0_C 6 TXN
10 DE1 GND 25 7 TXP
C +601_VCC VCC GND GND3 C
26
GND
8
9 3.3V
*SRD@SN75LVCP601RTJR R735 *0_4 10 3.3V
+5V [6] DEVSLP_HDD 3.3V
11
12 GND
60mil 13 GND
R715 *short_8 +5V_HDD 14 GND
15 5V
C796 + 16 5V
C791 C798 C792 C793 C799 17 5V
*100u/6.3V_3528 4.7U/6.3V_4 *0.1u/16V_4 *0.1u/16V_4 0.01u/50V_4 0.01u/50V_4 18 GND
19 RSVD
20 GND
21 12V
22 12V
Co-Layout R704 *0_4 12V
[25] ACCEL_INT2
24
GND24
HDD_CONN(on-board)
SATA_TXP0 R699 *short_4 SATA_TXP0_R R698 *short_4 SATA_TXP0_PS_R
SATA_TXN0 R703 *short_4 SATA_TXN0_R R702 *short_4 SATA_TXN0_PS_R

SATA_RXN0 R690 *short_4 SATA_RXN0_R R689 *short_4 SATA_RXN0_PS_R

SATA_RXP0 R693 *short_4 SATA_RXP0_R R692 *short_4 SATA_RXP0_PS_R

B B

SATA ODD (ODD) IOAC power

+15V to VIN
CN11 +3VPCU
14 VIN +5V +5V_ODD +5V
GND14

1
1 6
GND1 2 SATA_TXP1_C C712 0.01u/50V_4 R211 5 4 R196 NAC@0_8
RXP SATA_TXP1 [6]
3 SATA_TXN1_C C711 0.01u/50V_4 IOAC@100K/F_4 2 Q12
RXN SATA_TXN1 [6]
4 1 IOAC@AO6402A R192
GND2 5 SATA_RXN1_C C710 0.01u/50V_4 IOAC@22_8

2
TXN SATA_RXP1_C SATA_RXN1 [6]
6 C707 0.01u/50V_4 R208

3
TXP SATA_RXP1 [6] ODD_EN_Q
7 2 1

MOD_EN_5V
GND3 C702 180P/50V_4 +5V_ODD

3
R630 33_4 IOAC@100K/F_4
8 SATA_DP ODD_PLUGIN# [5]
R631 10K/F_4 +3V
DP 9 +5V_ODD_R R190 *short_8 R206 IOAC@0_4 ODD_EN
+5V [33] ODD_POWER
10 ODD_EN_Q 2
1

6
+5V 11 C320 C272 C273 C321 C317 C690 R205 *IOAC@0_4 C323
+

RSVD [5] PCH_ODD_EN

12 Q10
GND 13 0.01u/50V_4 0.01u/50V_4 *0.1u/16V_4 *0.1u/16V_4 10U/6.3V_4 *100u/6.3V_3528 R207 IOAC@0.1u/16V_4 IOAC@2N7002K
GND *IOAC@100K/F_4 Q13

1
15
2

GND15 IOAC@2N7002DW
ODD_CONN
EC_ODD_EJ# [33]
4

R637 10K/F_4 +3V

A A

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
HDD/REDRIVER/ODD
Date: Friday, March 04, 2016 Sheet 26 of 45
5 4 3 2 1
 5 4 3 2 1

USB Charger to 3.0 (UBC)

+5VPCU
80 mils (Iout=2A)

C499
1
U21

IN OUT
12

15 ILIM_LO (RILIM_LO 1.2A)

80 mils (Iout=2A)
+USBPWR0

SDP
CTL1

1
CTL2

1
CTL3

1
ILIM_SEL

0
27
ILIM_LO 16 ILIM_HI

+
1U/6.3V_4 ILIM_HI C497 C511
(RILIM_HI 2.3A) C510
9
STATUS 17
R356 R355
39K/F_4
100u/6.3V_1206
470P/50V_4 0.1u/16V_4 CDP 1 1 1 1
20K/F_4
13 GND_PAD
[5] USB_OC1# FAULT
4 14
[33] USB_BC_ON ILIM_SEL GND DCP 0 1 1 X
5 11 USBP5-_C iPAD charging current is about 2.1A so set on 2.3A
[33] USB_CHARGE_ON EN DM_IN USBP5+_C 1.2A current limit of USB 3.0 SDP mode
R329 100K/F_4 10
6 DP_IN
D D
[33] USB_CTL1 CTL1
R328 10K/F_4 CTL2 7 2
CTL2 DM_OUT USBP5- [6]
+5VPCU R327 10K/F_4 CTL3 8 3
CTL3 DP_OUT USBP5+ [6]
SLGC55544VTR RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
1. ILIM_SEL is always set high
2. Load Detection - Port Power Management is not used
3. Mouse / Keyboard wake function is not used
GMT:AL003703000(G3703)_X If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
RILIM_LO < 80.6 kΩ.
TI:AL002544001(TPS2544) The following equation programs the typical current limit:
Silergy:AL055544000(SLGC55544VTR) (1) IOS_typ(mA) = 50,250/{RILIM_XX(KΩ)+0.1}
RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.

USB 3.0 redriver (UB3) TP95

USBP5-_C
TP99 USB 3.0 Connector (UB3)
USBP5+_C
TP94 TP101
USB30_RX1-_R
TP97 TP90
VDD_18_S5 +USB_RE_PWR 2015-11-16_Change to NXP TP96
USB30_RX1+_R
TP91
USB30_TX1-_R USBP5-_C
TP98 TP93

12 36001_C1
R338 *URD@0_6 USBP5+_C
USB30_TX1+_R
+USB_RE_PWR TP100 TP92 with charger
+USBPWR0
U20 CN19 +USBPWR0
12/25 Add for ESD USB3.0_CONN
C1

C486 *URD@0.1u/10V_4 USB3_TXP1_C 11 1 USB3_TXP1_RE_C C484 *URD@0.1u/16V_4 USB30_TX1+_C 1 U22

[6] USB30_TX1+ AIN+ AOUT+ 1 VBUS USB30_TX1-_R
C501 *1.6P/50V_4 R358 *short_4 2 1
USB3_TXN1_C USB3_TXN1_RE_C USB30_TX1-_C 2 D- I/O 1 USB30_TX1+_R
C491 *URD@0.1u/10V_4 10 2 C489 *URD@0.1u/16V_4 3 10
[6] USB30_TX1- AIN- AOUT- 3 D+ I/O 6
4 2
9 3 USB30_RX1-_C USB30_RX1-_R 5 4 GND VDD 9
GND VDD(1V8) USB30_RX1+_C USB30_RX1+_R 6 5 SSRX- C513 3 GND_2
C493 *URD@0.1u/10V_4 USB3_RXP1_C 8 4 USB3_RXP1_RE R341 *URD@0_4 USB30_RX1+_C 7 6 SSRX+ 0.1u/16V_4 NC_1 8
C [6] USB30_RX1+ BOUT+ BIN+ 7 GND USBP5+_C NC_2 C
8 4
C495 *URD@0.1u/10V_4 USB3_RXN1_C 7 5 USB3_RXN1_RE R350 *URD@0_4 USB30_RX1-_C C498 *1.6P/50V_4 R357 *short_4 9 8 SSTX- I/O 2 7 USBP5-_C
[6] USB30_RX1- BOUT- BIN- 9 SSTX+ USB30_RX1-_R I/O 5
5
C2

GND_1
13
12
11
10
I/O 3 6 USB30_RX1+_R
URD@PTN36001 C490 R347 *short_4 I/O 4
6

13
12
11
10
URD@0.1u/10V_4

11
36001_C2

USB30_TX1-_C USB30_TX1-_R
USB30_TX1+_C USB30_TX1+_R
USB30_ESD_AZ1065-06F.R7G

R339 *short_4 C514 C512 USB protection diodes for ESD.

*1.6P/50V_4 *1.6P/50V_4
as close as possible to USB connector pins.

USB30_TX1- R334 *short_4 USB3_TXN1_NRD C488 0.1U/16V/X7R_4 USB30_TX1-_C

USB30_TX1+ R332 *short_4 USB3_TXP1_NRD C483 0.1U/16V/X7R_4 USB30_TX1+_C

USB30_RX1- R346 *short_4 USB3_RXN1_NRD R349 *short_4 USB30_RX1-_C

USB30_RX1+ R337 *short_4 USB3_RXP1_NRD R340 *short_4 USB30_RX1+_C

Co layout Co layout
R324 *short_4

USBP6-_R
[6] USBP6- USBP6+_R
[6] USBP6+

+USB_RE_PWR R331 *short_4 +USBPWR1

+USBPWR1
CN16 U19
R325 *URD@10K/F_4 36001_C1 R326 *URD@10K/F_4 USB3.0_CONN USB30_TX2-_R 1
1 I/O 1 10 USB30_TX2+_R
1 VBUS I/O 6
R335 *short_4 2 2
2 D- VDD
C492 *1.6P/50V_4 3 9
R353 *URD@10K/F_4 36001_C2 R352 *URD@10K/F_4 4 3 D+ C485 3 GND_2
USB30_RX2-_R 5 4 GND 0.1u/16V_4 NC_1 8
[6] USB30_RX2- USB30_RX2+_R 5 SSRX- USBP6-_R NC_2
6 4
[6] USB30_RX2+ 6 SSRX+ I/O 2 USBP6+_R
B fine tune re-driver setting 7 7 B
C487 *1.6P/50V_4 8 7 GND USB30_RX2-_R 5 I/O 5

GND_1
R333 *short_4 9 8 SSTX- I/O 3 6 USB30_RX2+_R
9 SSTX+ I/O 4

13
12
11
10
13
12
11
10

11
R323 *short_4

USB30_ESD_AZ1065-06F.R7G
C475 0.1U/16V_4 USB30_TX2-_C USB30_TX2-_R
[6] USB30_TX2-
[6] USB30_TX2+
C471 0.1U/16V_4 USB30_TX2+_C USB30_TX2+_R USB protection diodes for ESD.
as close as possible to USB connector pins.
R321 *short_4 C480 C472
*1.6P/50V_4 *1.6P/50V_4

USBP6-_R
TP107 TP111
+5V_S5 USBP6+_R
TP106 TP113
USB30_RX2-_R
TP109 TP102
USB30_RX2+_R
C460 +USBPWR1 TP108 TP103
U18
1u/6.3V_4 Close to CONN USB30_TX2-_R
TP110 TP105
DB 5
IN OUT
1
TP112
USB30_TX2+_R
TP104
+USBPWR3
USB2.0 (UB2) 1
CN18

USBON# 4
GND
2

3 C468 C470 C461

[33] USBON# /EN /OC
2 470P/50V_4 0.1u/16V_4 100U/6.3V_1206
3 12/25 Add for ESD
4 G524B2T11U
Enable: Low Active /2.5A 5
+5V_S5 GMT: AL000524007 6
[5] USB_OC2#
EMS: AL005203001 [6] USBP1+
7
Enable: Low Active /2.5A
BCD: AL002822000 8
+USBPWR3 [6] USBP1-
9 GMT:AL000524007
1u/6.3V_4 U45 10 EMS:AL005203001
C849 5 1 11
IN OUT [6] USBP0+
12
BCD:AL002822000
A [6] USBP0- A
2 C857 13
GND C868 C848 C864 14
[24] HP_JD#
USBON# 4 3 470P/50V_4 0.1u/16V_4 10U/6.3V_4 *100U/6.3V_1206 15
/EN /OC 16
G524B2T11U 17
[24] SLEEVE_R
18
[5] USB_OC3#
19
20
[24] RING2_R
21
22
23
[24] HP-L3
24
25 27
[24] HP-R3
26 28 Quanta Computer Inc.
DB_CONN PROJECT : ZAB
ADOGND Size Document Number Rev
1A
USB3/CHARGER
Date: Friday, March 04, 2016 Sheet 27 of 45
5 4 3 2 1
 5 4 3 2 1

USB Type C (UTC)

28
USB 3.0 redriver
Close to connector
VDD_18_S5 +USB_RE_PWR_C Type-C MUX USB2.0 ESD R179 *shortTYP_C@0_4

R157 *CRD@0_6 +3V_S5 +MUX_PWR

12 36001_CC1
USB2_TYPC_7P_C
[6] USBP7+ USB2_TYPC_7N_C
R180 *shortTYP_C@0_6 [6] USBP7-
D +USB_RE_PWR_C D
C667 C645 C662 C651
R187 *shortTYP_C@0_4
U29 TYP_C@0.1u/16V_4 TYP_C@0.1u/16V_4 TYP_C@0.1u/16V_4 TYP_C@0.1u/16V_4

Type C1_HSIO_ ESD

C1
C664 *CRD@0.1u/16V_4 USB3_TXP3_C 11 1 USB3_TXP3_RE_C R549 *CRD@0_4 USB3_TXP3_RE_C2
[6] USB30_TX3+ AIN+ AOUT+
C657 *CRD@0.1u/16V_4 USB3_TXN3_C 10 2 USB3_TXN3_RE_C R539 *CRD@0_4 USB3_TXN3_RE_C2 USB3_TXP3_B0+ USB3_TXP3_B0+_C R168 *shortTYP_C@0_4 USB3_TXP3_B0+_R
[6] USB30_TX3- AIN- AOUT- C229 TYP_C@0.1u/16V_4
9 3
GND VDD(1V8)
C654 *CRD@0.1u/16V_4 USB3_RXP3_C 8 4 USB3_RXP3_RE_C R514 *CRD@0_4 USB3_RXP3_RE_C2 +MUX_PWR U8
[6] USB30_RX3+ BOUT+ BIN+
C650 *CRD@0.1u/16V_4 USB3_RXN3_C 7 5 USB3_RXN3_RE_C R492 *CRD@0_4 USB3_RXN3_RE_C2 1 19 USB3_TXP3_B0+
[6] USB30_RX3- BOUT- BIN- VDD01 B0_P USB3_TXN3_B0- USB3_TXN3_B0- USB3_TXN3_B0-_C USB3_TXN3_B0-_R
6 18 R165 *shortTYP_C@0_4

C2
10 VDD06 B0_N C222 TYP_C@0.1u/16V_4
CRD@PTN36001 C655 VDD10 17 USB3_RXP3_B1+

6
B1_P 16 USB3_RXN3_B1- USB3_RXP3_B1+ R534 *shortTYP_C@0_4 USB3_RXP3_B1+_R
+MUX_PWR USB3_TXP3_RE_C2 3 B1_N

36001_CC2
CRD@0.1u/16V_4
USB3_TXN3_RE_C2 4 A0_P 15 USB3_TXP3_C0+
A0_N C0_P 14 USB3_TXN3_C0-
USB3_RXP3_RE_C2 7 C0_N
R175 USB3_RXN3_RE_C2 8 A1_P 13 USB3_RXP3_C1+
A1_N C1_P 12 USB3_RXN3_C1-
TYP_C@10K/F_4 C1_N
R174 *TYP_C@0_4 USB3_RXN3_B1- R520 *shortTYP_C@0_4 USB3_RXN3_B1-_R
5
CBTL02043A_XSD 2 VSS05 11
USB30_TX3- R535 *shortCRD@0_4 USB3_TXN3_NRD R538 *shortCRD@0_4 USB3_TXN3_RE_C2 XSD VSS11 20
VSS20

3
USB30_TX3+ R546 *shortCRD@0_4 USB3_TXP3_NRD R548 *shortCRD@0_4 USB3_TXP3_RE_C2 USB3_TXP3_C0+ USB3_TXP3_C0+_C R153 *shortTYP_C@0_4 USB3_TXP3_C0+_R
25810_POL# R137 *shortTYP_C@0_4CBTL02043A_SEL 9 21 C214 TYP_C@0.1u/16V_4
USB30_RX3- R510 *shortCRD@0_4 USB3_RXN3_NRD R491 *shortCRD@0_4 USB3_RXN3_RE_C2 SEL TAB
USB30_RX3+ R521 *shortCRD@0_4 USB3_RXP3_NRD R513 *shortCRD@0_4 USB3_RXP3_RE_C2 25810_EN 2
From CC Ctrl TYP_C@CBTL02043ABQ
Q8
Co layout Co layout TYP_C@2N7002K
USB3_TXN3_C0- USB3_TXN3_C0-_C R147 *shortTYP_C@0_4 USB3_TXN3_C0-_R
CBTL02043ABQ_SEL CBTL02043ABQ_XSD:

1
C207 TYP_C@0.1u/16V_4
Active-low chip enable
Low Port A to Port B L: Normal operation
USB3_RXP3_C1+ USB3_RXP3_C1+_R
H: Shutdown R511 *shortTYP_C@0_4

+USB_RE_PWR_C Hi Port A to Port C

C C
R171 *CRD@10K/F_4 36001_CC1 R172 *CRD@10K/F_4

USB3_RXN3_C1- R494 *shortTYP_C@0_4 USB3_RXN3_C1-_R

R138 *CRD@10K/F_4 36001_CC2 R139 *CRD@10K/F_4

fine tune re-driver setting

+TYPEC_VBUS

C666 TYP_C@0.1U/25V_4

2
+5V_S5 +CC_PWR C237 TYP_C@0.1U/25V_4
D2
R194 *shortTYP_C@0_8 TYP_C@TVS-AZ5725-01F_4
R195 *shortTYP_C@0_8 Type-C CC

1
CN9
A1 B12
GND GND
Q9 USB3_TXP3_C0+_R A2 B11 USB3_RXP3_C1+_R
Vendor suggest input cap 120u +TYPEC_VBUS_C TYP_C@AON7401 +TYPEC_VBUS TX1+ RX1+
USB3_TXN3_C0-_R A3 B10 USB3_RXN3_C1-_R
+CC_PWR 1 TX1- RX1-
+TYPEC_VBUS_C 5 2 C208 TYP_C@0.47u/25V_6 +TYPEC_VBUS A4 B9 +TYPEC_VBUS C658 TYP_C@0.47u/25V_6
C713 TYP_C@150U/6.3V_3528 U11 TYP_C@TPS25810RVCR(QFN) 3 VBUS VBUS
25810_CC1 A5 B8 TYPEC_SBU2
+

+5V_S5 CC1 SBU2 TP14

C264 TYP_C@10U/6.3V_4 2 15 C257 TYP_C@10U/6.3V_4
C263 TYP_C@10U/6.3V_4 3 IN1 OUT 14 USB2_TYPC_7P_C A6 B7 USB2_TYPC_7N_C

4
4 IN1 OUT 25810_UFP#_G2 D+ D-
B B
5 IN2 11 25810_CC1 R209 R191 TYP_C@100K/F_4 R189 USB2_TYPC_7N_C A7 B6 USB2_TYPC_7P_C
VAUX TI CC1 25810_CC2 D- D+
13 TYP_C@10K/F_4 C261 TYP_C@10K/F_4
CC2

3
R185 *shortTYP_C@0_4 25810_EN 6 TPS25810RVC TYP_C@0.1U/25V_4 TYPEC_SBU1 A8 B5 25810_CC2
[33] EC_TypeC_EN EN 25810_FAULT# TP13 SBU1 CC2
1 R203 *shortTYP_C@0_4
TYPEC_CHG FAULT# 25810_LD_DET# CC_OC# [5] +TYPEC_VBUS +TYPEC_VBUS
7 20 Q11 C223 TYP_C@0.47u/25V_6 A9 B4 C652 TYP_C@0.47u/25V_6
R176 *shortTYP_C@0_4TYPEC_CHG_HI 8 CHG LD_DET# 19 25810_UFP# R199 *shortTYP_C@0_4 25810_UFP#_G1 2 VBUS VBUS
[33] EC_TypeC_CHG_HI CHG_HI UFP# 25810_POL# APU_TypeC_UFP# [5] USB3_RXN3_B1-_R USB3_TXN3_B0-_R
18 A10 B3
25810_REF POL# 25810_AUO# 25810_POL# [33] TYP_C@2N7002K RX2- TX2-
10 17
REF AUDIO#
3

16 25810_DBG# USB3_RXP3_B1+_R A11 B2 USB3_TXP3_B0+_R

R186 TYP_C@100K/F_4 25810_REF_RTN 9 DEBUG# RX2+ TX2+

1
12 REF_RTN 21 Q40 A12 B1

G1
G2
G3
G4
GND
GND
GND
GND
GND
GND

GND PwPd 25810_UFP# 2 GND GND

TYP_C@USB_Type_C_CONN
TYP_C@2N7002K

1
2
3
4
22
23
24
25
26
27

U9 U10
USB3_TXP3_B0+_R 1 9 USB3_TXN3_B0-_R USB2_TYPC_7P_C 1 9 USB2_TYPC_7N_C
USB3_RXP3_B1+_R 2 LINE-1 LINE-2 8 USB3_RXN3_B1-_R 2 LINE-1 LINE-2 8
LINE-3 LINE-4 LINE-3 LINE-4
+3V_S5 3 3
GND GND
USB3_TXP3_C0+_R 4 7 USB3_TXN3_C0-_R TYPEC_SBU1 4 7 TYPEC_SBU2
25810_FAULT# R202 TYP_C@10K/F_4 USB3_RXP3_C1+_R 5 LINE-6 LINE-5 6 USB3_RXN3_C1-_R 25810_CC1 5 LINE-6 LINE-5 6 25810_CC2
25810_UFP# R200 TYP_C@10K/F_4 LINE-8 LINE-7 LINE-8 LINE-7
25810_EN R580 *TYP_C@10K/F_4 TYP_C@AZ1043-08F TYP_C@AZ1045-08F

Test Only
Quanta P/NAMAZING P/NUSD保保保保
25810_AUO# R197 TYP_C@10K/F_4 BC104308Z00, AZ1043-08F.R7G0.08TX RX ( USB3.0 GEN1 5G )
25810_DBG# R193 TYP_C@10K/F_4
BC104508Z00, AZ1045-08F.R7G0.08D+ D- SBU1 SBU2 CC1 CC2
BC005725Z00, AZ5725-01F.R7G0.009 PD 5V ( follow ZAA)
A A
R201 *TYP_C@0_4 25810_LD_DET# R625 TYP_C@10K/F_4
R624 *TYP_C@0_4 25810_POL# R198 TYP_C@10K/F_4

R184 *TYP_C@0_4 TYPEC_CHG R579 TYP_C@10K/F_4

R183 *TYP_C@0_4 TYPEC_CHG_HI R574 *TYP_C@10K/F_4

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
USB Type-C
Date: Saturday, March 05, 2016 Sheet 28 of 45
5 4 3 2 1
 5 4 3 2 1

LED(UIF)

R822 *1M/F_4 +3VPCU

Stich cap
+5V +3VPCU +1.2VSUS
29
C844 C335 C463 C494 C18 C764 C423 C466 C438
R826 *1M/F_4 +3V 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4
D D
R813 *1M/F_4 +3VPCU
+3VPCU

Power LED Blue VIN +3VPCU

R821 47/F_4 2 3 VIN
[33] PWRLED#
R812 124/F_4 1
[33] SUSLED#
C41 C473 C416 C340 C500 C842 C358

1
LED1 0.1u/25V_4 0.1u/25V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/25V_4
D45
*MLVS0402K11 D44 Amber +3VPCU
*MLVS0402K11

2
+5V +5V
C884
39P/50V_4

for ESD
R831 *1M/F_4 +3VPCU
C C
R825 *1M/F_4
+3VPCU
Battery Blue SPAD3 SPAD1 SPAD6 SPAD7 SPAD11 SPAD8 SPAD13
*SPAD-ZAB-1NP *SPAD-ZAB-2NP *SPAD-ZAB-3NP *SPAD-RE157X488NP *SPAD-RE157X1282NP *SPAD-RE157X491NP *SPAD-C197NP
R830 47/F_4 2 3
[33] BATLED0#
R829 124/F_4 1
[33] BATLED1#

1
LED2
1

D47 D46 Amber

*MLVS0402K11 *MLVS0402K11
SPAD12 SPAD10 SPAD5 SPAD4 SPAD2 SPAD9 SPAD14
2

*SPAD-RE157X1267NP *SPAD-C276NP *SPAD-C298NP *SPAD-C298NP *SPAD-RE531X205NP *SPAD-RE157X315NP *O-ZAB-1

1
B
HOLE(OTH) B
HOLE5 HOLE4
*H-ZAB-6 *H-ZAB-2
Layout set on Bottom Layout set on BOT
H-TC217IC197BC197D126P2 H-C236I180D140P2 H-C236I180D140P2 H-C256D161P2 H-C256D161P2 H-C256D161P2
HOLE18 HOLE21 HOLE19 HOLE8 HOLE9 HOLE11 HOLE22 HOLE20 HOLE23 HOLE6 HOLE10

1
WLAN_MBZAA002010 EV@MBZRQ001010 EV@MBZRQ001010 SSD@MBZAA001010 SSD@MBZAA001010 SSD@MBZAA001010 *H-C236D161P2 *H-C236D161P2 *H-C236D161P2 *H-C87D87N *H-O146X87D146X87N
1

1
HOLE25
*H-C217D217N

1
HOLE13 HOLE14 HOLE16 HOLE7 HOLE15 HOLE17 HOLE2 HOLE1 HOLE3 HOLE12
*HG-C315D134P2 *HG-C315D134P2 *HG-C354D134P2 *HG-C354D134P2 *HG-C354D134P2 *HG-C354D134P2 *HG-TC354IC236BC236D118P2 *O-ZAB-2 *H-ZAB-5 *O-ZAA-1
7 6 7 6 7 6 7 6 7 6 7 6 7 6 1 6
A 8 5 8 5 8 5 8 5 8 5 8 5 8 5 2 5 A
9 4 9 4 9 4 9 4 9 4 9 4 9 4 3 4

Quanta Computer Inc.

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
PROJECT :ZAB
Size Document Number Rev
1A
LED/HOLE/EMI
Date: Tuesday, February 16, 2016 Sheet 29 of 45
5 4 3 2 1
 5 4 3 2 1

TOUCH PAD(TPD)
30
TP_PWR
D D
VDD_18
+3V +3V TP_PWR

R832 R811
Q55 2.2K_4 2.2K_4
R836 R824 5
10K/F_4 10K/F_4

2
4 3 I2C_SCL_TP_R
[5] I2C_SCL_TP
1 3 I2C_INT#_TP
[5] APU_I2C_INT# 1.8V_S0 2 +3V_S5
Q56
2N7002K 1 6 I2C_SDA_TP_R
[5] I2C_SDA_TP
*0_4 R833
PJT138K

R823 *0_4
TP_PWR
C Q57 C

R820 *short_4 1 3
+3V_S5 +3V VIN TP_PWR
C877 AO3413
C882 C870

2
*0.1u/16V_4 0.22u/10V_4 0.1u/16V_4
TP_PWR R777 R783
R837 R772 *1M_6 *22_8
*10K/F_4
[33] PTP_PWR_EN#
10K/F_4

3
R793 R792 C886

3
*1000p/50V_4
10K/F_4 10K/F_4 CN20
8 PTP_PWR_EN# 2 2 2
R801 *short_4 TPCLK_CN 7
[33] TPCLK TPDATA_CN 6
R802 *short_4 R781 Q54
[33] TPDATA 5 *1M_6 *2N7002K

1
I2C_SDA_TP_R R807 *short_4 CLK_SDATA_R 4 Q53 Q52

1
C871 C872 I2C_SCL_TP_R R808 *short_4 CLK_SCLK_R 3 *DTC144EU *DTC144EU
I2C_INT#_TP R805 *short_4 2 9
10p/50V_4 10p/50V_4 1 10
B [33] TPD_INT# B
TP_CONN
[33] TPD_EN

20160205_EMI

A A

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
Touch Pad
Date: Thursday, March 03, 2016 Sheet 30 of 45
5 4 3 2 1
 5 4 3 2 1

KEYBOARD (KBC)
CN17
1
2
3
MX0
MX1
MX2
MX0
MX1
[33]
[33]
CN23
1
2
3
4
MX0
MX1
MX2
MX3 MX4
<EMI>

C893 *220p/50V_4
CPU FAN CTRL(THM)
31
4 MX2 [33] 5
MX3 MX4 MX5 C894 *220p/50V_4
MX3 [33]
5 MX4 6 MX5 MX6 C895 *220p/50V_4
6 MX5
MX4 [33] 7 MX6 MX7 C896 *220p/50V_4 2015-12-07_ B changes from PWM to DAC
D MX5 [33] D
7 MX6 8 MX7 MY3 C897 *220p/50V_4 +3V
8 MX6 [33] 9
MX7 MY17 MY2 C898 *220p/50V_4
9 MX7 [33] 10
MY17 MY16 MY1 C899 *220p/50V_4
MY17 [33] +5V
10 MY16 11 MY15 MY0 C900 *220p/50V_4 20160205_EMI
11 MY16 [33] 12
MY15 MY14 MY7 C901 *220p/50V_4 C929 1000P/50V_4 R841
MY15 [33]
12 MY14 13 MY13 MY6 C902 *220p/50V_4 10K/F_4
13 MY14 [33] 14
MY13 MY12 MY5 C903 *220p/50V_4 C892 0.01u/50V_4
14 MY13 [33] 15
MY12 MY11 MY4 C904 *220p/50V_4
MY12 [33]
15 MY11 16 MY10 MY11 C905 *220p/50V_4 C890
16 MY11 [33] 17 [33] FAN1_RPM
MY10 MY9 MY10 C906 *220p/50V_4
MY10 [33]
17 MY9 18 MY8 MY9 C907 *220p/50V_4 2.2U/10V_4 U48 30mils CN8
18 MY9 [33] 19 2 3 TH_FAN_POWER
MY8 MY7 MY8 C908 *220p/50V_4
19 MY8 [33] 20 VIN VO 5 1 4
MY7 MY6 MX0 C909 *220p/50V_4
MY7 [33] GND 2
20 MY6 21 MY5 MX1 C910 *220p/50V_4 R842 1
*short_4 6
21 MY6 [33] 22 [4] THERM_ALERT# /FON GND 7 3 5
MY5 MY4 MX2 C911 *220p/50V_4 C891 C889
MY5 [33] GND
22 MY4 23 MY3 MX3 C912 *220p/50V_4 4 8 FAN_3P
23 MY4 [33] 24 [33] FAN1_DAC VSET GND
MY3 MY2 MY15 C913 *220p/50V_4 2.2U/10V_4 0.01u/50V_4
24 MY3 [33] 25
MY2 MY1 MY14 C914 *220p/50V_4 APL5606AKI
MY2 [33]
25 MY1 26 MY0 MY13 C915 *220p/50V_4
26 MY1 [33] 27 NBSWON#_R
MY0 MY12 C916 *220p/50V_4
27
MY0 [33]
28 FANPWR = 1.6*VSET
28 NBSWON#_R R791 33_4
NBSWON# [33] 29
1

29 30
C C
30 D43 C865
*AZ5725-01F_4 180P/50V_4 SP15@KB_CONN
SP17@KB_CONN
2

SP15@
SP17@ 15" Only
17" Only +3VPCU

+3V_LDO_EC RP5
10 1 MX0
MX7 9 2 MX1
MX6 8 3 MX2
R773 reserve switch for test MX5 7 4 MX3
10K/F_4(MP remove) MX4 6 5

SW3 *10K_10P8R
*POWER_SW
NBSWON# 1 3
2 4

C834
5

0.1u/16V_4
B B

KB_BL LED (KBL)

+5V +5V

C595 *KBL@2.2u/16V_6
1

R466
Q32
KBL@10K/F_4
KBL@AO3413
2
CN4
3

1
20mil 20mil
3

2 +5V_KB R427 *shortKBL@0_4 +5V_KB_R 2 5

[33] KB_BL_LED 3 6
A 4 A
Q35 C578 C579
KBL@DTC144EU
KBL@KB_backlight
1

KBL@4.7u/6.3V_4 KBL@0.01u/50V_4
Quanta Computer Inc.
PROJECT : ZAB
Size Document Number Rev
1A
KB/FAN
Date: Thursday, March 03, 2016 Sheet 31 of 45
5 4 3 2 1
 5 4 3 2 1

POA(FPD) or PBA
Don't change to short pad
+3V_LDO_EC R859 FPD@0_4
+POA_PWR
change from +3V_LDO_EC to +POA_PWR
+POA_PWR

C476 *FPD@2.2u/16V_6
32
D D
D49 *FPD@D5V0X1B2LP-7B
R860 *FPD@0_4 1 2 USBP3+_R
+3VPCU

1
+3V R865 *FPD@0_4
Q24 D50 *FPD@D5V0X1B2LP-7B
FPD@AO3413 R866 1 2 USBP3-_R
R336 FPD@10K/F_4 2 *FPD@0_4
[33] POA_FP_PWREN#

C927
20mil CN21
20mil

3
*FPD@1000p/50V_4 +POA_PWR_Q R806 *shortFPD@0_4 +POA_PWR_R 1 10
USBP3+_R 2 9
C496 C869 USBP3-_R 3
FPD@4.7u/6.3V_4 FPD@0.01u/50V_4 4
R861 FPD@0_4 5
[33] POA_EN#
R862 FPD@0_4 6
[33] POA_PWR_INT#
C R863 FPD@0_4 7 C
[33] POA_AUTH_ERR
R864 FPD@0_4 8
[33] POA_POWERREQ
FPD@CONN_AOP
Don't change to short pad
Co-Layout
USBP3+ R790 FPD@0_4 R804 FPD@0_4 USBP3+_R
USBP3- R795 FPD@0_4 R803 FPD@0_4 USBP3-_R

U46

+3VPCU R789 *FPD@0_4 USBP3+_U 1 4 TP89

[6] USBP3+ Y+ M-
R794 *FPD@0_4 USBP3-_U 2 5 TP88
[6] USBP3- Y- M+ USBP3-_R2 R799
3 6 *FPD@0_4 USBP3-_R
B
R788 *FPD@0_4 R787 *FPD@100/F_4 9 GND D- 7 USBP3+_R2 R797 *FPD@0_4 USBP3+_R B
10 VCC D+ 8 R786 *FPD@0_4
[33,35,37,40] MAINON SEL OE#
C860 C859

*FPD@0.01u/50V_4 *FPD@0.1u/16V_4 *FPD@PI3USB103ZLEX

20160205_DNI because PBA doesn't have leakage issue

SEL OE# Y+ Y-
X H Hi-Z Hi-Z
A A
L L M+ M- Quanta Computer Inc.
H L D+ D- PROJECT :ZAB
Size Document Number Rev
1A
Spec define: High Active POA
Date: Friday, March 04, 2016 Sheet 32 of 45
5 4 3 2 1
 5 4 3 2 1

L22 BLM15AG121SN1D(120/0.5)_4 +A3VPCU +3VPCU_ECPLL L19 BLM15AG121SN1D(120/0.5)_4 +3V_LDO_EC

33
+3VPCU_EC
EC(KBC) C830 C803 (For PLL Power) S5_ON R731 10K/F_4
0.1u/16V_4
0.1u/16V_4
ECAGND +3V_S5
[34] D/C# SB_ACDC [34]
1 2
12 mils +3VPCU_EC POA_EN# [32] SIO_EXT_SCI#
+3V_LDO_EC R770 *10K/F_4
+VSTBY_FSPI BT_EN [22]
R278 2.2/F_6
C430 C451 C845 C801 C474 C479
POA_PWR_INT# [32]
+3V

0.1u/16V_4
POA_POWERREQ [32]
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 Layout put in device side
SIO_A20GATE R726 *10K/F_4
USBON# [27] SIO_RCIN#
R740 33_4 R744 10K/F_4
+VSTBY_FSPI TPD_EN [30]
SERIRQ R746 *10K/F_4
1 2 +3V_EC USB_BC_ON [27]
+3V USB_CHARGE_ON [27]

C888
+3V_LDO_EC R718 2.2/F_6 R320 2.2/F_6 C805
D CLKRUN# [6,25] D
C469 R748 8.2K_4 180P/50V_4 SUSON R724 100K/F_4
1 2 +3V
+3V_S5 R717 *2.2/F_6 Reserved for EC debug +3V_S5 MAINON R774 100K/F_4
R319 *2.2/F_6 0.1u/16V_4 VRON R776 100K/F_4

114
121
106

127
PLTRST# R765 100K/F_4

11
26
50
92

74

84
83
82

19
20

99
98
97
96
93
3
U43 RSMRST# R734 *10K/F_4 ITE suggest RSMRST# PD
10 110 CPU_ID R725 *SP@0_4

GPH7
VCC

VSTBY_FSPI

AVCC

EGCLK/WUI27/GPE3(Dn)
EGCS#/WUI26/GPE2(Dn)
EGAD/WUI25/GPE1(Dn)

L80HLAT/BAO/WUI24/GPE0(Dn)
L80LLAT/WUI7/GPE7(Up)

WUI42/GPH6/ID6(Dn)
WUI41/GPH5/ID5(Dn)
WUI40/GPH4/ID4(Dn)
WUI19/GPH3/ID3(Dn)
CLKRUN#/WUI16/GPH0/ID0(Dn)
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY

VSTBY
[6,22,25] LPC_LAD0 9 LAD0/GPM0(X) SMCLK0/GPB3(X) 111 MBCLK [34]
[6,22,25] LPC_LAD1 MBDATA [34]
CPU_ID:
8 LAD1/GPM1(X) SMDAT0/GPB4(X) 115 CZ@: Internal PU
[6,22,25] LPC_LAD2
[6,22,25] LPC_LAD3
7 LAD2/GPM2(X)
LAD3/GPM3(X)
VSTBY SMCLK1/GPC1(X)
SMDAT1/GPC2(X)
116
2ND_MBCLK [4,12]
2ND_MBDATA [4,12] TYP3@: External PD ???
22 VCC 117
+3V_LDO_EC [5,22,25] PLTRST# LPCRST#/WUI4/GPD2(Up) PECI/SMCLK2/WUI22/GPF6(Up) LID#_R TP78
13 VSTBY 118 R723 33_4

SM BUS
[6] CLK_PCI_EC 6 LPCCLK/GPM4(X) VCC SMDAT2/WUI23/GPF7(Up) LID# [18]
C802 180P/50V_4
CLK_PCI_EC [6,22,25] LPC_LFRAME# LFRAME#/GPM5(X) VSTBY 85
PROCHOT_EC 17
LPCPD#/WUI6/GPE6(Dn)
PS2CLK0/TMB0/CEC/GPF0(Up)
PS2DAT0/TMB1/GPF1(Up)
86 IOAC_RST# [21,22]
EC_FPBACK# [18]
SM BUS PU(KBC)
2

89
PS2CLK2/WUI20/GPF4(Up) TPCLK [30]
D8 126 90
[5] SIO_A20GATE 5 GA20/GPB5(X) VSTBY PS2DAT2/WUI21/GPF5(Up) TPDATA [30]
R753 R322

PS/2
RB500V-40 [6,25] SERIRQ SERIRQ/GPM6(X)

1
100K/F_4 15 VCC +3V_LDO_EC
[28] 25810_POL# 23 ECSMI#/GPD4(Up) VSTBY VSTBY VSTBY
*22_4 D48 Layout put in device side
[5] SIO_EXT_SCI# ECSCI#/GPD3(Up) LPC VSTBY
1

WRST# 14 GPIO TVM0G5R5M220R MBCLK R719 4.7K_4

R743 *short_4 4 WRST# VSTBY Closed to EC MBDATA R720 4.7K_4
[5] SIO_RCIN#

2
16 KBRST#/GPB6(X) VSTBY
[22] IOAC_WLAN_WAKE# PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT VSTBY
C813 C467
*10p/50V_4 1u/6.3V_4 24 Change EC SMBus PU voltage from
PWM0/GPA0(Up) PWRLED# [29] +3V_GFX to +3V_S5 due to it also
25 +3V_S5

Layout put in device side(ESD)

[31] KB_BL_LED
[5] DNBSWON#
113
123 CRX0/GPC0(Dn)
CTX0/TMA0/GPB2(Dn) CIR
IT8987E/BX PWM1/GPA1(Up)
PWM2/GPA2(Up)
PWM3/GPA3(Up)
PWM4/GPA4(Up)
28
29
30
BATLED1# [29]
SUSLED# [29]
BATLED0# [29]
MAINON [32,35,37,40]
2ND_MBCLK
2ND_MBDATA
R721
R722
4.7K_4
4.7K_4
connect to CPU(SIC/SID) and GPU.
EC need read CPU temperature even
in UMA mode or GPU off mode
VSTBY 31
TS_EN PWM5/GPA5(Up) USB_CTL1 [27]
R755 33_4
[18] TS_EN_R
80
PWM
[28] EC_TypeC_EN DAC4/DCD0#/GPJ4(X)
C819 119 47
[5] SUSB# 33 DSR0#/GPG6(X) VSTBY TACH0A/GPD6(Dn) 48 FAN1_RPM [31]
180P/50V_4
[5] EC_PWROK GINT/CTS0#/GPD5(Up) TACH1A/TMA1/GPD7(Dn) POA_AUTH_ERR [32] CORE_PWM_PROCHOT# [4,34,38,39]
R751 *short_4 88
[4,18] APU_DISP_BLEN

3
81 PS2DAT1/RTS0#/GPF3(Up) 120
[31] FAN1_DAC 87 DAC5/RIG0#/GPJ5(X) TMRI0/WUI2/GPC4(Dn) 124 CPU_ID SUSON [37,40]
Q48
[21] IOAC_LAN_WAKE# PS2CLK1/DTR0#/GPF2(Up) TMRI1/WUI3/GPC6(Dn)
C TP80 109 C
108 TXD/SOUT0/GPB1(Up) PROCHOT_EC 2
[24] AMP_MUTE# RXD/SIN0/GPB0(Up)
71 VSTBY 107
ODD_POWER [26] 72 ADC5/DCD1#/WUI29/GPI5(X) PWRSW/GPE4(Up) 18 NBSWON# [31]
UART port R741 2N7002K
[34] ACIN ADC6/DSR1#/WUI30/GPI6(X) RI1#/WUI0/GPD0(Up) SUSC# [5]
73 21 HWPG

1
[34] TEMP_MBAT# 35 ADC7/CTS1#/WUI31/GPI7(X) RI2#/WUI1/GPD1(Up)
Layout put in device side(ESD) [22] WLANPWR# WAKE UP 100K/F_4
34 RTS1#/WUI5/GPE5(Dn)
[24] PCBEEP_EC PWM7/RIG1#/GPA7(Up)
R745 33_4 122 112 RSMRST#
[26] EC_ODD_EJ# [37] DDR4_SUSON_2V5 95 DTR1#/SBUSY/GPG1/ID7(Dn) RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn) RSMRST# [5]
[34] AC_Protect
Layout put in device side(ESD)
C809 180P/50V_4 94 CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn) R780 33_4
CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn) RF_EN [22]
EC_SPI_SCK 105 C841 180P/50V_4
EC_SPI_CS0# 101 FSCK/GPG7 +3V_LDO_EC
EC_SPI_SDI
EC_SPI_SDO
102
103
FSCE#/GPG3
FMOSI/GPG4 EXTERNAL SERIAL FLASH
66
ICMNT [34]
SPI NOR FLASH(128KB) (KBC)
FMISO/GPG5 ADC0/GPI0(X) 67 C838 10U/6.3V_4 ECAGND +3V_LDO_EC
56 ADC1/GPI1(X) 68
[31] MY16 KSO16/SMOSI/GPC3(Dn) ADC2/GPI2(X) DGPU_OPP [12]
57 69 25mA U40 R684
[31] MY17 TS_EN 32 KSO17/SMISO/GPC5(Dn) ADC3/GPI3(X) 70 VRON [5,38] 8 5 EC_SPI_SDI 10K/F_4
PWM6/SSCK/GPA6(Up) ADC4/WUI28/GPI4(X) LANPWR# [21] +3V_LDO_EC VCC SPI_SI EC_SPI_SDO
2
100 SPI_SO 1 EC_SPI_CS0#
[35,36,40] S5_ON SSCE0#/GPG2(X) A/DAVCC
D/A EC_SPI_WP# CS# EC_SPI_SCK
125 SPI ENABLE 3 6
[30] PTP_PWR_EN# SSCE1#/GPG0(X) POA_FP_PWREN# [32] WP# SPI_SCK
76 R685 10K/F_4
36 TACH2/GPJ0(X) 77 SYS_HWPG_R R852 *short_4 SYS_HWPG
[31] MY0 KSO0/PD0 GPJ1(X) EC_SPI_HOLD# 7
37 78 4 C794
[31] MY1 38 KSO1/PD1 DAC2/TACH0B/GPJ2(X) 79 EC_TypeC_CHG_HI [28] SPI_HOLD GND
R713 10K/F_4 *10P/50V_4
EC_SPI_SDI [31] MY2 KSO2/PD2 DAC3/TACH1B/GPJ3(X) CLR_CMOS [7]
R732 *10K/F_4 39 W25X10CLSNIG
EC_SPI_SDO [31] MY3 KSO3/PD3
R733 *10K/F_4 40 KBMX VSTBY
[31] MY4 41 KSO4/PD4
[31] MY5
EC requirement
42 KSO5/PD5
[31] MY6 43 KSO6/PD6
Please do not place any [31] MY7 KSO7/PD7
44
pull-up resistor [31] MY8
45 KSO8/ACK#
on GPG0, GPG2, and GPG6 [31] MY9 46 KSO9/BUSY
(Reserved [31]
[31]
MY10
MY11
51 KSO10/PE 2
SYS_SHDN# [12,35,40]
HWPG(KBC) +3V
KSI3/SLIN#

KSO11/ERR# GPJ7
KSI1/AFD#
KSI0/STB#

KSI2/INIT#

hardware strapping). 52 128 R736 33_4

[31] MY12 KSO12/SLCT GPJ6 TPD_INT# [30]
53
VCORE

B [31] MY13 KSO13 B

AVSS

54
KSI4
KSI5
KSI6
KSI7

VSS

VSS
VSS
VSS
VSS

[31] MY14 55 KSO14 C804 R763

[31] MY15 KSO15 180P/50V_4 10K/F_4
SM BUS ARRANGEMENT TABLE IT8987E/BX
58
59
60
61
62
63
64
65

27
49
91
104

75

12

D32 *1N4148WS HWPG

[40] HWPG_0.775VS5 HWPG [5]
SM Bus 1 Battery
Layout put in device side(ESD) D29 *1N4148WS
[31] MX0 [40] HWPG_1.8VS5
C811
[31] MX1
D38 1N4148WS
ECAGND

SM Bus 2 PCH/VGA [31] MX2 [38] VRM_PWRGD

0.1u/16V_4
[31] MX3
D41 *1N4148WS
[31] MX4 [37] HWPG_VDDR
SM Bus 3 N/A [31] MX5
D26 *1N4148WS
[31] MX6 [36] HWPG_0.95VS5
L20 BLM15AG121SN1D(120/0.5)_4
[31] MX7
SM Bus 4 N/A D40 *1N4148WS
[35] SYS_HWPG

D28 *1N4148WS
[40] HWPG_1.5V
Power sequence Battery B/I SW (SYP) [37] HWPG_2.5V
D42 *1N4148WS

R658 *0_4 +3VRTC D30 *1N4148WS

[40] HWPG_1.5VSUS

R664 *0_4 +3VPCU

1 3D39 *CZ@1N4148WS
NBSWON# TP42
BATT Detect SW [39] GFX_PWRGD
R665 Q46
DNBSWON# TP79 *10K/F_4 *CZ@2N7002K

2
SW2 +3VRTC R716 *CZ@100K/F_4
+3V
SUSON TP74 WRST#

3
3 2
1

SUSB# 4 1 C795
TP75 [34] BI
R652 C753 *CZ@0.22U/10V_4
3

EC_PWROK 100K/F_4 *0.1u/16V_4 2

TP87 [5] VDDGFX_PD
BATT_Switch Vgs = 1.5V
A PLTRST# TP84 Q47 A
2

2 BI_GATE **CZ@2N7002K
HWPG TP83 Vgs = 1.5V

1
5

SW1
3
4

MAINON PJA138K C734 BI_SW

TP86
R651 *SP@0_4 Q44 *0.1u/16V_4 6 2015.10.20 SCL v1.10 & DG v1.08
1

RSMRST# TYP1: No connect (**)

TP77
S5_ON Q45
TP76
Just for A 5 *PJ4N3KDW

Quanta Computer Inc.

4

1
1
2

PROJECT : ZAB
Size Document Number Rev
1A
EC (ITE8987E/BX)
Date: Friday, March 04, 2016 Sheet 33 of 45
5 4 3 2 1
 5 4 3 2 1

15-12-10 SMT ME request:

change FP & pin order
PJ1
4
VA1

1
2
3
PQ30
TPCA8109

5
VA2
PD6
SV1040
1

2
3 1
PR199
0.02/F_0612

2
VIN
1
2
3
PQ3
TPCA8109

5
34
3 PR197

1
2 *short_4
1 PC1 PC21 PR37 24737_ACN PC161 PC162 PR65

4
Power_conn 0.1u/25V_4 0.1u/25V_4 220K/F_4 0.1u/25V_4 2200p/50V_4 33K/F_4
50320-0040n-001-4p-l-smt PD7
P4SMAFJ20A 24737_ACP

2
D D

PC3 PC2 PR198

0.1u/25V_4 2200p/50V_4 1 6 *short_4

PD1 PR43 2 5 PR70

D/C# [33]
1N4148WS 220K/F_4 10K/F_4
recommend 200mA at least. 3 4 PR34
*short_4
PQ1

3
IMD2AT108

2
24737_ACP
PQ33
2N7002K
24737_ACN

1
PC5 PC9 PC4
0.1u/25V_4 0.1u/25V_4 0.1u/25V_4

PR20
+3VPCU 63.4K/F_4

1
VIN
PR23 PC20

ACP

ACN
11K/F_4 1u/16V_4
24737_ACDET 6 16 24737_REGN
C
ACDET REGN C
PR51 PR50 PR47 PC25
*10K/F_4 100K/F_4 100K/F_4 0.1u/25V_4 PD2 PC152 PC157
24737_VCC 20 RB500V-40 2200p/50V_4 10u/25V_8
VCC PR29
PR17 *short_6
20_1206 PC8 17 24737_BST
[33] ACIN

5
0.47u/25V_6 BTST PQ31
PC14 AON7410
47n/50V_6
[5] ACPRESENT
PR52 18 24737_DH 4
6

*0_4 5 HIDRV
[33] SB_ACDC ACOK#
PR53 *short_4
19 24737_LX

3
2
1
PHASE PR213
0.01/F_0612
MBDATA 8 PU1 PL2
PQ2 PR27 *short_4 SDA BQ24737RGRR 6.8uH_7X7X3
2N7002DW 15 24737_DL 1 2 BAT-V
1

LCDRV
MBCLK 9

5
PR32 *short_4 SCL PQ32
+3VPCU AON7410
14 PR30
PGND *4.7_6
PC37 if no external switch control=> stuff PR64 10K/F_4 24737_BM# 11 4 PR216 PR215
0.1u/25V_4 BM# *short_4 *short_4
if has external switch control=> DNI
BAT-V PC30
PR67 10K/F_4 24737_CMPOUT 3 PR46 0.1u/25V_4
BI [33]

3
2
1
B CMPOUT 13 10_4 24737_SRP 24737_SRP PC28 PC177 PC172
B
SRP PC24 2200p/50V_4 10U/25V_8 10U/25V_8
PR58 PR41 316K/F_4 24737_ILIM 10 PC38 *680p/50V_6 24737_SRN
PJ2 *0_4 ILIM 0.1u/25V_4
TEMP_MBAT# [33]
PR45
9 8 PC171 PR59 PR44 24737_CMPIN 4 12 7.5_6 24737_SRN
7 CMPIN SRN
6
*100p/50V_4 100/F_4 1M/F_4
PC29 ／SRN
SRP／

IOUT

GND
GND
GND
GND
GND
5 +3VPCU
PR73 PR36 0.1u/25V_4
4 *100K/F_4 100K/F_4 PR14
3 100K/F_4 4-Cells Others

21
22
23
24
25
3

2
10 1
BATT_CONN R2 bq24707A ／0
0／ ／7.5
10／
50458-00801-v02-8p-l PR57 PR56 24737_BM# 2 PC19
100/F_4 100/F_4 0.01u/50V_4
PQ5
*2N7002K bq24737 ／7.5
10／ ／7.5
10／
1
1

PC31 PC40 PR16

REGN MAX voltage 6.5V
*47p/50V_4 *47p/50V_4 PR15
R1 SP@162K/F_4
*0_4
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
CORE_PWM_PROCHOT# [4,33,38,39]
2

=0.793V for 3.965A current limit

3
[33] ICMNT
PD3 PD4 PU to +3V_GFX in GPU side
PDZ5.6B PDZ5.6B
MBCLK [33] 24737_CMPOUT 2
GPU_THROTTING# [12] Pin10 ILIM=0.793V

3
A
R1 R2 Rsr = 0.01ohm A
MBDATA [33] PC16 PQ4
45W 100p/50V_4 2N7002K
ZRZL UMA PR69 24737_CMPOUT 2
51K 100K

1
*short_4
CS35102FB04 PQ6
65W *EV@2N7002K
ZAB UMA 115K 100K Quanta Computer Inc.

1
[33] AC_Protect
CS41152FB08
78W
PROJECT : ZAB
ZAB DIS For BATT Only Size Document Number Rev
162K 100K 1A
CS41622FB11 Charger (BQ24737RGRR)
Date: Saturday, March 05, 2016 Sheet 34 of 45
5 4 3 2 1
 5 4 3 2 1

SYS_SHDN#
SYS_SHDN# [12,33,40]

+3VPCU VL 3V_LDO
PR297
35
10K/F_4
[33] SYS_HWPG
VIN VIN
SYS_SHDN#

0.1u/25V_4
10U/6.3V_4

4.7u/6.3V_4
1
D D
+
PC236 PC245 PC248 PC241 PC240
*33u/25V_6x4.5 10u/25V_8 2200p/50V_4 PR173 2200p/50V_4 10u/25V_8
2 *short_4 PR165

PC127

PC242
10K/F_4

51225_VIN

PC243
+5VPCU

5
PQ52 +3VPCU
PR300 AON7410 +3VPCU
+5VPCU 100K/F_4 3.3 Volt +/- 5%
5 Volt +/- 5% PQ54

13

12
TDC : 8.4A

3
AON6978 4
TDC : 10.35A PEAK : 11.2A

VREG5

VIN

VREG3
2
PEAK : 13.8A 7 6 51225_EN1 OCP : 14A

D1
D1
D1

3
2
1
PGOOD EN2
OCP : 17A 51225_EN1 20 10 51225_DH2 Width : 340mil
Width : 420mil EN1 DRVH2 PR163 PC126
PL16 G1 1 51225_DH1 16 9 51225_VBST2 PL15
2.2uH_7X7X3 PC131 PR172 DRVH1 VBST2 2.2uH_7X7X3
51225_SW1 9 S1/D2 51225_VBST1 17 8 51225_SW2 1/F_4 0.1u/25V_4
VBST1 PU11 SW 2
0.1u/25V_4 1/F_4 51225_SW1 18 TPS51225RUKR 11 51225_DL2
SW 1 DRVL2

5
G2 8 PR299
+ PR301 51225_DL1 15 4 51225_FB2 6.49K/F_4 +
PC252 PC137 15.8K/F_4 DRVL1 VFB2 PC244
C C
220u/6.3V_6X4.2 0.1u/25V_4 51225_FB1 2 21 PR167 220u/6.3V_6X4.2

S2
S2
S2
PR303 VFB1 GND 4 *4.7_6
*4.7_6 14 22

5
6
7
VO1 GND PC246

VCLK
OCP:17A

GND

GND

GND

GND
CS1

CS2
PQ53 0.1u/25V_4

3
2
1
L(ripple current) AON7752 PC128
PR170 *680p/50V_6 PR169
=(9-5)*5/(1u*0.3M*9)

19

26

25

24

23
10K/F_4 PC247 RDSon=4.9mohm 9.31K/F_4
=7.407A

150K/F_4
*680p/50V_6

63.4K/F_4
PR302
RDSon=14.5mohm
Iocp=17-(7.407/2)=13.296A *short_6
Vth=(13.296A*4.9mOhm)+1mV
=66.151mV
R(Ilim)=(66.151mV*8)/10uA
OCP:14A
~52.92K L(ripple current)
=(9-3.3)*3.3/(2.2u*0.355M*9)

PR171

PR166
~2.676A
+5VPCU Iocp=14-(2.676/2)=13.162A
+5VPCU Vth=(12.662A*14.5mOhm)+1mV +3VPCU +3VPCU

TDC : 5.25A =184.599mV TDC : 3.9A

PEAK : 7A TDC : 3.6A R(Ilim)=(184.599mV*8)/10uA TDC : 2.38A
PEAK : 5.2A
PEAK : 4.8A =147.68K PEAK : 3.17A
Width : 220mil Width : 160mil
B PC143 PC148 Width : 160mil Width : 100mil PC132 PC133 B
+5V_S5 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 +3V
1

7
+5V +3V_S5
VIN1

VIN1

VIN2

VIN2

VIN1

VIN1

VIN2

VIN2
13 8 13 8
14 VOUT1 OUT2 9 14 VOUT1 OUT2 9
VOUT1 OUT2 VOUT1 OUT2
PC144 PC142 PC149 PC147 PC254 PC138 PC139 PC253
10U/6.3V_4 0.1U/16V_4 11 0.1U/16V_4 10U/6.3V_4 +5VPCU 10U/6.3V_4 0.1U/16V_4 11 0.1U/16V_4 10U/6.3V_4
+5VPCU PU13 GND PU17 GND
APL3523A 15 APL3523A 15
4 GND 4 GND
PC259 VBIAS PC136 VBIAS

PR313 PR184
0.1U/16V_4 *short_4 0.1U/16V_4 *short_4
S5_ON 3 5 MAINON S5_ON 3 5 MAINON
[33,36,40] S5_ON ON1 ON2 ON1 ON2
CT1

CT2

CT1

CT2
MAINON [32,33,37,40]
PR310 PR183
*short_4 PC256 PC263 +3V_LDO_EC *short_4 PC134 PC135
12

10

12

10
*0.1U/16V_4 *0.1U/16V_4 *0.1U/16V_4 *0.1U/16V_4
PR176 0_4
PC257 PC262
3V_LDO +3V_LDO_EC PC140 PC141
1000P/50V_4 1000P/50V_4 +3VPCU PR181 *0_4 TDC : 100MA 1000P/50V_4 1000P/50V_4

A
Soft-Start For EC power auto recovery Soft-Start A
Don't change to short pad

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
SYSTEM 5V/3V (RT6575AGQW)
Date: Tuesday, March 29, 2016 Sheet 35 of 45
5 4 3 2 1
 5 4 3 2 1

36
D D

VIN

PU2000
8
IN
VDDP_0.95V_S5

2200p/50V_4

10u/25V_8
9

*0.1U/25V_4
IN
0.95 Volt +/- 5%

PC2001

PC2002

PC2000
7 22
+5VPCU PR2001 NC IN TDC : 7.56A
10_4 24
G5335-VCC-1 21 IN Fsw=550KHz PEAK : 10A
VCC
Width : 320mil
G5335QT2U PR2000 PC2004
PC2003 73.2K/F_4 *0.01U/25V_4 AMD requirements (depends on OPN)
+3V 10U/6.3V_4 6 G5335-TON-1
TON Refer to datasheet...SR: 55366 / BR:53557 VDDP_0.95V_S5
1.05V: 2.49K ohm, CS22492FB22
0.95V: 0 ohm, CS00002JB38
PR2002 20 G5335-BST-1
100K/F_4 BST
PR2003 PC2005
2.2/F_6 0.1U/25V_4 PL2000
PR2004 *short_4G5335-PWRGD-1 1 0.68uH_7X7X3
[33] HWPG_0.95VS5 PGOOD 10 G5335-LX-1 1 2
+5VPCU LX 11
C LX C
16
LX 17

22U/6.3V_6

22U/6.3V_6

22U/6.3V_6

0.1U/16V_4

22U/6.3V_6

22U/6.3V_6
*22U/6.3V_6

*22U/6.3V_6
PR2005 *0_4
LX

PC2008

PC2009

PC2010

PC2011

PC2012

PC2013

PC2006

PC2007
18
PR2006 *short_4 G5335-PFM-1 3 LX 25
G5335-AGND-1 PFM LX PR2007
Pulse-Skipping mode *4.7_6 PR316 PC2014
SP@0_4 *1000P/50V_4

PC2015 R1
PR2009 *short_4 G5335-EN-1 2 *680p/50V_6
[33,35,40] S5_ON EN 12
PGND PR2008
PC2016 13 3.83K/F_4
*0.047U/16V_4 PGND
14
PGND
G5335-AGND-1 15
PGND
19
G5335-SS-1 23 PGND
SS PR2010
20K/F_4 PR317
4 *100/F_4
AGND G5335-AGND-1
PC2017
APU_VDDP_RUN_FB_H [4]
0.047U/16V_4 R2
B
5 G5335-FB-1 VFB=0.8V APU_VDDP_RUN_FB_L [4] B

G5335-AGND-1 FB PR311
*0_4
PR314
*short_4
PR2011 *short_4 Vo=0.8*(R1+R2)/R2
=0.95V
G5335-AGND-1
G5335-AGND-1

VDDP_0.95V_S5

5
MAIND 4 PQ16
[37,40] MAIND
AON6752
A +0.95V A

1
2
3
TDC : 6.38A
PEAK : 8.5A
VDDP_0.95V Width : 260mil Quanta Computer Inc.
PROJECT : ZAB
Size Document Number Rev
1A
VDDP_0.95V_S5 (G5335QT2U)
Date: Saturday, March 05, 2016 Sheet 36 of 45
5 4 3 2 1
 5 4 3 2 1

PR2016
100K/F_4
+3V

37
PR2017 *short_4 [18,24,26,29,30,34,35,36,38,39,40,41,42,43] VIN
[33] HWPG_VDDR
[27,28,35,38,39,41,43] +5V_S5
[9,10] +SMDDR_VTT
PR2018 *short_4 [9,10] +SMDDR_VREF
[33,40] SUSON
[3,7,9,10,29] +1.2VSUS
D PC2021 D
*0.1U/16V_4 Ilimit=10A
+1.2VSUS
VIN
PR2019 1.2 Volt +/- 5%

1P35V_PGOOD
249K/F_4 Fsw=500KHz
[32,33,35,40] MAINON
PR2020 *short_4 TDC : 6A

1P35V_CS
1P35V_S3

1P35V_S5
PC2022 PR2021 PEAK : 8A
*0.1U/16V_4 1P35V_TON OCP : 10A

10u/25V_8

10u/25V_8

2200P/50V_4
0.1U/25V_4

0.1U/25V_4
Width : 240mil

PC2023

PC2027

PC2024

PC2028

PC2025
499K/F_4

10

13
7

9
TDC : 0.38A

5
PQ2005 +1.2VSUS

CS
PGOOD

TON
S3

S5
PEAK : 0.5A +SMDDR_VTT AON7410

Width : 20mil 20
VTT 17 1P35V_UGATE 4
2 UGATE
PC2026 VTTSNS PC2029
10U/6.3V_4 18 1P35V_BOOT PR2022
TDC : 0.45A

3
2
1
1 BOOT1 PL2001
VTTGND 2.2/F_6
PEAK : 0.6A +SMDDR_VREF
PU2001 16 1P35V_PHASE
0.1u/25V_4 1uH_7X7X3

Width : 20mil PHASE

*330u/2.5V_6X4.2
RT8231BGQW
PR2023

5
1P35V_LGATE

0.1U/16V_4

22U/6.3V_6

22U/6.3V_6

22U/6.3V_6

22U/6.3V_6
4 15
VTTREF LGATE

PC2031

PC2035

PC2032

PC2036

PC2037

PC2033
100/F_4 +
19 12 +5V_S5 PR2025
PC2034 PC2030 VLDOIN VDD *4.7_6
*10U/6.3V_4
PC2038

0.1U/16V_4 0.033U/10V_4 4

PC2040 PR2026

PGND

VDDQ
1U/6.3V_4 PQ2006 PC2039 *short_4

GND

PAD

3
2
1
VID
AON7752 *680p/50V_6

FB
C +1.2VSUS C

11

14

21
1P35V_VID

1P35V_FB
1P35V_S3 PR2027 *0_4 1P35V_S5 Rds(on)=14.5mohm
1P35V_VDDQ
+5V_S5
PR2030 *short_4
PR2032
PR2031 *0_4
7.87K/F_4

VID Ref. Voltage PR2033

10K/F_4
High 0.675V

Low 0.75V
S3 S5 VDDQ VTTREF VTT
OCP=10A
L ripple current S0 1 1 ON ON ON
=(19-1.2)*1.2/(1u*500k*19)
=2.248A S3 (mainon off) 0 1 ON ON OFF
Vtrip=10-(2.248/2)*14.5mohm DDR=1.2V
=128.702mV PR2032=7.87K/F_4 S4/S5 0 0 OFF OFF OFF
Rlimit=128.702mV/5uA*10=257.4Kohm PR2033=10K/F_4
B B

+2.5VSUS
2.5Volt +/- 5%
+2.5VSUS Power Rail For DDR4 TDC : 0.78A
Chechk PU high with HW
+3V +3V_S5 PEAK : 1.04A 10/27 Reserve +2.5V for DDR4 VDDSPD
Width : 40mil
+2.5VSUS
PR321 PR323 +2.5VSUS
100K/F_4 PC260 *short_6

3
4.7U/6.3V_4
4

PR322 PU18
*short_4
VIN

[33] HWPG_2.5V PL17

5 3 MAIND 2
PG LX [36,40] MAIND
2.2uH/1.85A_2.5X2X1.2
PQ22
*AO3404
SUSON PR306 1 2 PR320

1
*10K/F_4 EN GND 47.5K/F_4 R1 +2.5V
PC249
FB

PR307 PC258 10U/6.3V_4

[33] DDR4_SUSON_2V5 +2.5V [40]
*short_4 0.47uF/6.3V_2 G5719BTB1U
6

Chechk Enable Sequence with HW PC250 PC251 TDC : 0.03A

A Vo=(0.6(R1+R2)/R2) *10U/6.3V_4 0.1U/16V_4 PEAK : 0.04A A

PR315 R2 Width : 20mil

15K/F_4

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
DDR4_+1.2VSUS (RT8231BGQW)
Date: Saturday, March 05, 2016 Sheet 37 of 45
5 4 3 2 1
 5 4 3 2 1

PR28
10_4
VDDCR_NB

PC13
330p/50V_4
38
PR236 Load line setting
*short_4 PR54
[4] APU_VDDNB_RUN_FB_H 2.2/F_6 VIN
BOOT_NB
PR25

10u/25V_8

10u/25V_8
0.1u/25V_4

2200p/50V_4
1.87K/F_4

PC66

PC51

PC52

PC61
Close to the RC time PC22

2
CPU side. constant 0.22u/25V_6
PC15 PR22

D1
D1
D1
D +5V_S5 UGATE_NB D
1000p/50V_4 300_4 VSUMG+

PC10 PR18 PR1 1 G1 PL5

680p/50V_4 2K/F_4 2.61K/F_4 0.36uH_7X7X4 DCR=1.4mOhm

47n/16V_4
0.1u/16V_4
PHASE_NB 9 PHASE_NB 1 2

PC6
S1/D2

PC12
VDDCR_NB
PR66

PR13
11K/F_4
PR35 PC18 PR33 1/F_4 Close with

4
8 G2

PR74
33K/F_4 390p/50V_4 133K/F_4 PHASE_NB inductor

2.2/F_6

330u/2V_7343

*220u/2V_7343
+

0.1u/16V_4

10U/6.3V_4
LGATE_NB +

PC73
PR214

PC183

PC182

PC181
PC17 PR21 10K/F_4_3435NTC

S2
S2
S2
PC33 1U/6.3V_4

PC32 1U/6.3V_4
62771_VSEN_NB
68p/50V_4 549/F_4 PQ7

1n/50V_4
62771_FB_NB VSUMG-

PC43
AON6998

7
6
5
OCP

ISUMN_NB
PC11
62771_COMP_NB 0.1u/16V_4

+3V
+VDDCR_NB
VSUMG+ PR3 3.65K/F_4 TDC : 15.75A

36

37

38

25

26

40

39
PEAK : 21A

VDD
COMP_NB

FB_NB

VSEN_NB

VDDP

ISUMP_NB

ISUMN_NB
PR42
10K/F_4 VSUMG- PR12 1/F_4 OCP : 26.5A
PR40
*short_4 Width : 600mil
LGATE_NB
35
PGOOD_NB LGATE_NB
34
Load Line = -4mV/A
VRM_PWRGD 20 33 PHASE_NB
[33] VRM_PWRGD PGOOD PHASE_NB

PR10 *short_4 62771_SVC 3 32 UGATE_NB

[4] APU_SVC SVC UGATE_NB

C PR8 *short_4 62771_VRHOT 4 31 BOOT_NB PR60 C

[4,33,34,39] CORE_PWM_PROCHOT# VR_HOT_L BOOT_NB 2.2/F_6 VIN
BOOT_2

*33u/25V_6x4.5
1
PR7 *short_4 62771_SVD 5 30 BOOT_2

10u/25V_8

10u/25V_8
0.1u/25V_4

2200p/50V_4
[4] APU_SVD SVD BOOT2 +

PC47

PC48

PC231
PC35

PC46

PC49
2
PR9 *short_4 62771_VDDIO 6 29 UGATE_2 0.22u/25V_6
VDD_18

2
VDDIO UGATE2

D1
D1
D1
PU2 UGATE_2
PR5 *short_4 62771_SVT 7 ISL62771HRTZ-TS2775 28 PHASE_2
[4] APU_SVT SVT PHASE2
1 G1 PL8
62771_EN PR4 *short_4 62771_EN 8 27 LGATE_2 0.36uH_10X10X4
[5,33] VRON ENABLE LGATE2 PHASE_2 S1/D2 9 PHASE_2 1 2
DCR=1.1mOhm
VDDCR_CPU
PR201 PR6 *short_4 62771_PWROK 9 24 LGATE_1

PR83

4
[4,39] APU_PWRGD_SVID_REG PWROK LGATE1 8 G2

2.2/F_6
*100K/F_4

330u/2V_7343
*220u/2V_7343
NTC_NB 1 23 PHASE_1 LGATE_2 + +

PC188
0.1u/16V_4

10U/6.3V_4
NTC_NB PHASE1

PC60
S2
S2
S2
PQ38

PC71

PC69
1n/50V_4
NTC 11 22 UGATE_1

PC59
AON6998

7
6
5
NTC UGATE1
27.4K/F_4

27.4K/F_4
470K_4_4700NTC

470K_4_4700NTC

IMON_NB 2 21 BOOT_1
PR87

PR84
PR229

PR230

IMON_NB BOOT1

IMON 10 41 VSUM+ PR31 3.65K/F_4

IMON EP
1000p/50V_4

1000p/50V_4

ISUMN

ISUMP
COMP

ISEN1

ISEN2
VSEN
PC7

PC154
133K/F_4

133K/F_4

RTN
PR2

ISEN2 PR19 10K/F_4

PR200

Add 9 GND VIAs

FB
10K/F_4

10K/F_4

PR24
PR90

PR91

for thermal pad *10K/F_4

VDDCR_CPU
19

18

16

17

15

14

13

12

VSUM- PR49 1/F_4 ISEN1

TDC : 33.75A
ISEN2
PEAK : 45A
62771_VSEN

62771_RTN

B B
62771_FB

ISUMN

Place NTC close to the Place NTC close to the 62771_COMP PC153 OCP : 68A
VDDNB Hot-Spot.
OCP=100'C
VDDCORE Hot-Spot.
OCP=100'C PC23
0.22u/25V_6 Width : 1600mil
VIN
100p/50V_4 VSUM-
Load Line = -2.1mV/A
PR62
PR206 PC163 PR207 PC155 2.2/F_6
200K/F_4 390p/50V_4 133K/F_4 0.22u/25V_6 BOOT_1
ISEN1

10u/25V_8

10u/25V_8
0.1u/25V_4

2200p/50V_4
PC160 PR205 PC36

PC41
PC169
2
680p/50V_4 2K/F_4 0.22u/25V_6

PC42
PC165
VSUM+

D1
D1
D1
UGATE_1

PC158 PR204
1000p/50V_4 300_4 PR39 1 G1 PL9
VDDCR_CPU 2.61K/F_4 0.36uH_10X10X4 DCR=1.1mOhm
47n/16V_4
0.15u/10V_4

PHASE_1 S1/D2 9 PHASE_1 1 2

PC26

PC27

PR48
11K/F_4

VDDCR_CPU
PC156 PR203
330p/50V_4 2.1K/F_4

PR75

4
PR232 Close with 8 G2

1n/50V_4 2.2/F_6

330u/2V_7343
10_4 PR226 phase1 inductor
PR235 Load line setting PR38 10K/F_4_3435NTC LGATE_1 +

PC189
0.1u/16V_4

10U/6.3V_4
*short_4 549/F_4

S2
S2
S2
[4] APU_VDD_RUN_FB_H VSUM- PQ35

PC53

PC70

PC72
AON6998

7
6
5
OCP
PC166
[4] APU_VDD_RUN_FB_L RC time 0.1u/16V_4
constant
PR234
*short_4 VSUM+ PR26 3.65K/F_4
PR231
10_4
Parallel
A
PC159
0.01u/50V_4 AMD CZ/Bristol/Stoney 35W - SVI2 ISEN1 PR202 10K/F_4
PR11
*10K/F_4
A

VSUM- PR63 1/F_4 ISEN2

Close to the
GPU side.
+VDDCR_NB +VDDCR_CPU +VDDCR_GFX
TDC : 15.75A TDC : 33.75A TDC : 30A
PEAK : 21A PEAK : 45A PEAK : 40A
OCP : 26.5A OCP : 68A OCP : 56A Quanta Computer Inc.
Width : 600mil Width : 1600mil Width : 1200mil PROJECT : ZAB
Load Line = -4mV/A Load Line = -2.1mV/A Load Line = -2.1mV/A Size Document Number Rev
1A
VDDCR_CPU / NB (SL62771HRTZ)
Date: Saturday, March 05, 2016 Sheet 38 of 45
5 4 3 2 1
 5 4 3 2 1

39
+5V_S5

PR120
CZ@1/F_4
D D

PC213 PC103
CZ@1U/6.3V_4 CZ@1U/6.3V_4

+3V

36

37

38

25

26

40

39
VIN

COMP_NB

FB_NB

VSEN_NB

VDDP

ISUMP_NB

ISUMN_NB
VDD
PR248
CZ@10K/F_4 PR121
CZ@2.2/F_6
BOOT_GFX2
35 34 PR257 CZ@10K/F_4

CZ@10u/25V_8

CZ@10u/25V_8
CZ@0.1u/25V_4

CZ@2200p/50V_4
PGOOD_NB LGATE_NB

PC97
PC206

PC100

PC209
PC105

2
GFX_PWRGD 20 33 CZ@0.22u/25V_6
[33] GFX_PWRGD PGOOD PHASE_NB

D1
D1
D1
UGATE_GFX2
PR148 62771_SVC_GFX
*shortCZ@0_4 3 32 PR252 CZ@10K/F_4
[4] GFX_SVC SVC UGATE_NB
1 G1 PL12
PR149 62771_VRHOT_GFX 4
*shortCZ@0_4 31 PR127 *shortCZ@0_4 CZ@0.24uH_7X7X4DCR=1mOhm
[4,33,34,38] CORE_PWM_PROCHOT# VR_HOT_L BOOT_NB +5V_S5
PHASE_GFX2 S1/D2 9 PHASE_GFX2 1 2
C VDDCR_GFX C
PR144 62771_SVD_GFX
*shortCZ@0_4 5 30 BOOT_GFX2
[4] GFX_SVD

4
SVD BOOT2 8 G2

PR115
CZ@2.2/F_6

CZ@0.1u/16V_4

CZ@330u/2V_7343
CZ@10U/6.3V_4

CZ@330u/2.5V_6X4.2
PC200

PC198
PR145 62771_VDDIO_GFX 6
*shortCZ@0_4 29 UGATE_GFX2 LGATE_GFX2 +

PC196

PC190
+
VDD_18 VDDIO UGATE2

S2
S2
S2
PU7 PQ48

CZ@1n/50V_4
62771_SVT_GFX 7 28 PHASE_GFX2

PC92
PR146 *shortCZ@0_4 CZ@ISL62771HRTZ-TS2775 CZ@AON6998

7
6
5
[4] GFX_SVT SVT PHASE2

62771_EN_GFX PR147 62771_EN_GFX

*shortCZ@0_4 8 27 LGATE_GFX2
[5] VDDGFX_EN ENABLE LGATE2

PR267 PR142 62771_PWROK_GFX9

*shortCZ@0_4 24 LGATE_GFX1 VSUM+_GFX PR131 CZ@3.65K/F_4
[4,38] APU_PWRGD_SVID_REG PWROK LGATE1
*CZ@100K/F_4
NTC_NB_GFX 1 23 PHASE_GFX1 ISEN2_GFX PR138 CZ@10K/F_4
NTC_NB PHASE1 PR258
*CZ@10K/F_4
NTC_GFX 11 22 UGATE_GFX1 VSUM-_GFX PR259 CZ@1/F_4 ISEN1_GFX
NTC UGATE1 VDDCR_GFX
TDC : 30A
CZ@100K/F_4

CZ@100K/F_4

CZ@27.4K/F_4
CZ@470K_4_4700NTC

IMON_NB_GFX 2 21 BOOT_GFX1
PR271

PR269

PR244

PR243

IMON_NB BOOT1
PEAK : 40A
IMON_GFX 10 41
IMON EP OCP : 56A
ISUMN
CZ@1000p/50V_4

ISUMP
*CZ@0.1u/16V_4

COMP

ISEN1

ISEN2
VSEN

Width : 1200mil
PC227

PC226
CZ@100K/F_4

CZ@133K/F_4

RTN
PR270

PR268

Add 9 GND VIAs

FB
CZ@100K/F_4

CZ@10K/F_4

VIN
Load Line = -2.1mV/A
PR272

PR111

for thermal pad PR122

19

18

62771_VSEN_GFX 16

17

15

14

13

12
CZ@2.2/F_6
BOOT_GFX1
62771_RTN_GFX

B B

CZ@10u/25V_8

CZ@10u/25V_8
CZ@0.1u/25V_4

CZ@2200p/50V_4
62771_FB_GFX

ISUMN_GFX

ISEN2_GFX

PC98
PC207

PC101

PC210
PC106

2
CZ@0.22u/25V_6
Place NTC close to the Place NTC close to the 62771_COMP_GFX PC225

D1
D1
D1
UGATE_GFX1
VDDNB Hot-Spot. VDDCORE Hot-Spot. CZ@0.22u/25V_6
OCP=100'C OCP=100'C PC112
CZ@100p/50V_4 VSUM-_GFX
1 G1 PL13
CZ@0.24uH_7X7X4DCR=1mOhm
PR249 PC109 PR128 PC221 PHASE_GFX1 S1/D2 9 PHASE_GFX1 1 2 VDDCR_GFX
CZ@200K/F_4 CZ@390p/50V_4 CZ@133K/F_4 CZ@0.22u/25V_6
ISEN1_GFX

4
8 G2

PR114
CZ@2.2/F_6

CZ@0.1u/16V_4

CZ@10U/6.3V_4

*CZ@220u/2V_7343
*CZ@330u/2V_5x4.2
PC214 PR254

PC199

PC197
LGATE_GFX1

PC81
PC202
CZ@680p/50V_4 CZ@2K/F_4 + +
VSUM+_GFX

S2
S2
S2
PQ49

CZ@1n/50V_4
PC94
CZ@AON6998

7
6
5
PC216 PR247
CZ@1000p/50V_4 CZ@300_4 PR123
VDDCR_GFX CZ@2.61K/F_4
CZ@22n/25V_4
CZ@0.15u/10V_4
PC110

PC114

PR134
CZ@11K/F_4

PR256
CZ@1.87K/F_4 VSUM+_GFX PR253 CZ@3.65K/F_4
PR245 PC219 Close with
CZ@10_4 CZ@330p/50V_4 PR246 phase1 inductor
PR110 Load line setting PR133 CZ@10K/F_4_3435NTC ISEN1_GFX PR255 CZ@10K/F_4
*shortCZ@0_4 CZ@475/F_4 PR280
[4] APU_VDDGFX_RUN_FB_H VSUM-_GFX *CZ@10K/F_4
VSUM-_GFX PR279 CZ@1/F_4 ISEN2_GFX
OCP
PC222
A [4] APU_VDDGFX_RUN_FB_L RC time CZ@0.1u/16V_4 A
constant
PR109
*shortCZ@0_4
PR242 PC217
CZ@10_4 CZ@0.01u/50V_4
Parallel

Quanta Computer Inc.

Close to the
GPU side. PROJECT : ZAB
Size Document Number Rev
1A
VDDCR_GFX (ISL62771HRTZ)
Date: Saturday, March 05, 2016 Sheet 39 of 45
5 4 3 2 1
 5 4 3 2 1

40
VIN

+3VPCU VDD_18_S5 VDD_18_S5

PD5
DA2J10100L

3
PU4 RT8068AZQW PL6
1uH_7X7X3
9 1 554LX_1.8V MAIND 2
PVIN NC PR164
10 2 1M_6
PVIN LX

1
D PC54 PC187 PC186 PQ9 D
0.01U/50V_4 PR86 3 PR217 PC68 0.1u/16V_4 22U/6.3V_6 AO3404 PQ20

1
+3V 10_4 8 LX *2.2/F_6 *22P/50V_4
SVIN AO3409
2
4 VDD_18
PC57
10U/6.3V_4 PC64 PG 6
FB

3
PR77 1U/6.3V_4 PC178 R1 PR92
100K/F_4 5 *2200P/50V_4 20K/F_4 VDD_18_S5 TDC : 1.13A

GND

3
EN
1.8 Volt +/- 5% PEAK : 1.5A S5_ON 2

NC
PR78
*short_4
554PG_1.8V 554FB_1.8V TDC : 2A Width : 60mil

11

7
[33] HWPG_1.8VS5 PQ21 PR168
PEAK : 2.67A

1
S5_ON 554EN_1.8V DTC144EU *short_6
[33,35,36] S5_ON R2 PR89 Width : 80mil Thermal Protection
PR76 10K/F_4
*short_4 PC45 PC65 Vo=0.6*(R1+R2)/R2 VL VL
*0.1u/16V_4 *68P/50V_4
(1) Need fine tune SYS_SHDN# [12,33,35]

for thermal protect point

(2) Note placement position
PR179 PC129 PR174
(3) Thermal protection setting = 92'C PR177 200K/F_4 0.1u/25V_4 200K/F_4

3
1.2K/F_4

8
VDDP_0.95V_S5 PQ10 VDDCR_FCH_S5 PR233
AO3404 10K/F_4_3435NTC 2.469V 3
+ 1 2
3 1 2
+3V +5VPCU - PQ24

3
PU12A 2N7002K

4
AS393MTR-E1 PC130

1
PC80 PC79 PC74 PC75 0.1u/25V_4
PR104 10U/6.3V_4 0.1u/16V_4 10U/6.3V_4 10U/6.3V_4 S5_ON 2
100K/F_4 PC77 PU6 PR178
C 0.1u/16V_4 G9336TB1U PR94 VDDCR_FCH_S5 PQ43 200K/F_4 C
1
VCC
56/F_4 Rg 0.775 Volt +/- 5% 2N7002K

TDC : 0.68A

1
[33] HWPG_0.775VS5 3 6
PGD DRV
S5_ON 4 5 PEAK : 0.9A
EN FB PR96 Vout = (1+Rg/Rh)*0.5 Width : 40mil
GND

PR105 47/F_4
*short_4 5
+ 7
2

PC82 PR101 6
*0.1u/16V_4 100/F_4 -
PC78 Rh PU12B
33n/10V_4 AS393MTR-E1

For EC control thermal protection (output 3.3V)

+3V +3VPCU
+1.5VSUS Reserve for +1.5V Wifi Card
PC228
4.7U/6.3V_4
PR277 +1.5VSUS
100K/F_4 +1.5V +1.5V 1.5Volt +/- 5%
1.5Volt +/- 5% TDC : 1.65A
4

PU9
TDC : 0.57A +3V +3VPCU
PEAK : 2.2A
VIN

[33] HWPG_1.5V PL1

PR278 *short_4 5 3
PG LX 2.2uH/1.85A_2.5X2X1.2
PEAK : 0.76A PC179 Width : 80mil
Width : 40mil *4.7U/6.3V_4
PR224
B MAINON PR153 10K/F_4 1 2 *100K/F_4 JP13 +1.5VSUS B
EN GND *0.001/F_3720
0.47uF/6.3V_2

4
PR285 PC123
PC122

PU15
FB

22.6K/F_4 10U/6.3V_4

VIN
[33] HWPG_1.5VSUS PL3
G5719BTB1U R1 PR221 *0_4 5 3 1 2
6

PG LX *2.2uH/1.85A_2.5X2X1.2

PC120 PC125
R2 *10U/6.3V_4 0.1U/16V_4 PR211 *10K/F_4 1 2
Vo=(0.6(R1+R2)/R2) [33,37] SUSON EN GND

*0.47uF/6.3V_2
PR286 PR219 PC170

PC176

FB
15K/F_4 *22.6K/F_4 *0.1U/16V_4
*G5719BTB1U

6
R1
PC167 PC164
*10U/6.3V_4 *10U/6.3V_4
R2
Vo=(0.6(R1+R2)/R2) PR220
VIN +3V +5V VDD_18 +2.5V VDDP_0.95V VIN *15K/F_4

PR327 PR186 PR185 PR180 PR175 PR189 PR196

1M_6 22_8 *220_8 22_8 *22_8 22_8 1M_6

MAINON_ON_G MAIND
MAIND [36,37]
Thermal protection
3

3
3

PR902 *22K/F_4
PR328 PU901
2 PQ57 1M_6 2 2 2 2 2 2 VL PR901 *150/F_4 5 1 PR903 *24K/F_4
A [32,33,35,37] MAINON DTC144EU PC150 VCC SET A
PQ27 PQ26 PQ25 PQ23 PQ28 PQ29 *2200p/50V_4 PC901 2 Rset(Kohm)=0.0012T*T-0.9308T+96.147
2N7002K *2N7002K 2N7002K *2N7002K 2N7002K 2N7002K *0.1U/16V_4 GND
HYST=VCC for 10 degree Hys.
1

PR325 HYST=GND for 30 degree Hys.

1

*100K/F_6 4 3 SYS_SHDN#
HYST OT#
*TMP708AIDBVR
Need fine tune
for thermal protect point
Note placement position
Quanta Computer Inc.
TEMP=85'C PROJECT : ZAB
Size Document Number Rev
1A
+1.8V/+0.775V/+1.5V/Thermal
Date: Friday, March 18, 2016 Sheet 40 of 45
5 4 3 2 1
 5 4 3 2 1

Interface SVI2 41
+5V_S5 R16M-M2-50 (37W)
TDC : 45A
PEAK : 60A
PR124
D EV@1/F_4 OCP : 75A D

Width : 1600mil
Load Line = -1mV/A
PC218 PC211
EV@1U/6.3V_4 EV@1U/6.3V_4

PR126
EV@2.2/F_6

36

37

38

25

26

40

39
+3V_GFX BOOT_GPU2 VIN

*EV@33U/25V_6x4.5
EV@10u/25V_8

EV@10u/25V_8
EV@0.1u/25V_4

EV@2200p/50V_4
VDD
COMP_NB

FB_NB

VSEN_NB

VDDP

ISUMP_NB

ISUMN_NB

1
5

PC212

PC204

PC208

PC215

PC229
PC108 +
EV@0.22u/25V_6
PR129

2
EV@10K/F_4 35 34 PR265 EV@10K/F_4 UGATE_GPU2 4
PGOOD_NB LGATE_NB

1
2
3
[42] GPU_PG_EN
20 33 PQ47 PL11
PGOOD PHASE_NB EV@AON6414AL EV@0.24uH_7X7X4
PHASE_GPU2 1 2
DCR=1mOhm
62771_SVC_GPU +VGPU_CORE
PR155 *shortEV@0_4 3 32 PR264 EV@10K/F_4
[12] GPU_SVC_R SVC UGATE_NB

EV@1n/50V_4EV@2.2/F_6

*EV@330u/2V_7343
3

4
PR113

EV@0.1u/16V_4

EV@10U/6.3V_4
PR156 62771_VRHOT_GPU
*shortEV@0_4 4 31 PR130 *shortEV@0_4
[12] GPU_PWM_PROCHOT# VR_HOT_L BOOT_NB +5V_S5 LGATE_GPU2

PC195

PC194

PC193
4 +
C C
PR161 62771_SVD_GPU
*shortEV@0_4 5 30 BOOT_GPU2

1
2
3
[12] GPU_SVD_R SVD BOOT2

PC93
PQ45
EV@AON6752
PR157 62771_VDDIO_GPU
*shortEV@0_4 6 29 UGATE_GPU2
+1.8V_GFX VDDIO UGATE2
[11,12,14,42] +3V_GFX PR158 *EV@0_4
PU8
PR159 62771_SVT_GPU
*shortEV@0_4 7 EV@ISL62771HRTZ-TS2775 28 PHASE_GPU2
[12] GPU_SVT_R SVT PHASE2 VSUM+_GPU PR292 EV@3.65K/F_4

62771_EN_GPU PR160 62771_EN_GPU

*shortEV@0_4 8 27 LGATE_GPU2
[42] 0.95_GFX_EN ENABLE LGATE2 ISEN2_GPU PR295 EV@10K/F_4
PR294
PR288 GPU_PG_EN PR154 62771_PWROK_GPU 9
*shortEV@0_4 24 LGATE_GPU1 *EV@10K/F_4
PC234 EV@0.1u/16V_4 PWROK LGATE1 VSUM-_GPU PR143 EV@1/F_4 ISEN1_GPU
EV@100K/F_4
NTC_NB_GPU 1 23 PHASE_GPU1
NTC_NB PHASE1

NTC_GPU 11 22 UGATE_GPU1
NTC UGATE1
EV@100K/F_4

EV@100K/F_4

EV@27.4K/F_4
EV@470K_4_4700NTC

IMON_NB_GPU 2 BOOT_GPU1
PR276

PR291

PR241

PR107

21
IMON_NB BOOT1
VIN
IMON_GPU 10 41 PR125
IMON EP
EV@1000p/50V_4

EV@2.2/F_6

ISUMN

ISUMP
COMP

ISEN1

ISEN2
BOOT_GPU1
VSEN
EV@100K/F_4

EV@133K/F_4
*EV@0.1u/16V_4

RTN
PR290

PC235

PR287

PC233
EV@100K/F_4

EV@10u/25V_8

EV@10u/25V_8
EV@0.1u/25V_4

EV@2200p/50V_4
Add 9 GND VIAs
FB
EV@10K/F_4
PR289

PR108

for thermal pad

PC205

PC203

PC102

PC104
PC107
19

18

62771_VSEN_GPU 16

17

15

14

13

12
EV@0.22u/25V_6
B B
62771_RTN_GPU

UGATE_GPU1 4
62771_FB_GPU

ISUMN_GPU

ISEN2_GPU

1
2
3
PQ46 PL10 DCR=1.1mOhm
Place NTC close to the Place NTC close to the PC121 EV@AON6414AL EV@0.24uH_7X7X4
62771_COMP_GPU EV@0.22u/25V_6 PHASE_GPU1 1 2
VDDNB Hot-Spot. VDDCORE Hot-Spot. +VGPU_CORE
OCP=100'C OCP=100'C VSUM-_GPU
PC115 EV@220p/50V_4

EV@1n/50V_4EV@2.2/F_6
3

4
5

PR119

EV@0.1u/16V_4

EV@330u/2V_7343

EV@330u/2V_7343
EV@10U/6.3V_4
PR261 PC113 PR136

PC89

PC88

PC191

PC192
*EV@0_4 EV@390p/50V_4 EV@47.5K/F_4 PC119 + +
EV@0.22u/25V_6 LGATE_GPU1 4
ISEN1_GPU

PC99
PC111 PR135

1
2
3
EV@680p/50V_4 EV@2K/F_4 PQ44
EV@AON6752
VSUM+_GPU
PC117 PR132
EV@1000p/50V_4 EV@300_4
VSUM+_GPU PR282 EV@3.65K/F_4
EV@47n/16V_4

PR262
EV@0.22u/10V_4

+VGPU_CORE
EV@11K/F_4

EV@2.61K/F_4
ISEN1_GPU
PC224

PC230

PR266

PR137 EV@1.33K/F_4 PR283 EV@10K/F_4

PR152
Load line setting *EV@10K/F_4
PC232 Close with VSUM-_GPU PR151 EV@1/F_4 ISEN2_GPU
PR239 EV@330p/50V_4 PR240 phase1 inductor
PR238 EV@10_4 PR141 EV@10K/F_4_3435NTC
*shortEV@0_4 EV@634/F_4
[14] GPUVDDC_SENSE VSUM-_GPU

A A
OCP
PC118
[14] GPUVSS_SENSE RC time EV@0.1u/16V_4
constant
PR237
*shortEV@0_4
PR275 PC223
EV@10_4 EV@0.01u/50V_4
Parallel Quanta Computer Inc.
PROJECT : ZAB
Close to the Size Document Number Rev
1A
GPU side. +VGPU CORE (SL62771HRTZ)
Date: Saturday, March 05, 2016 Sheet 41 of 45
5 4 3 2 1
 5 4 3 2 1

+3VPCU +PCIE_VDDC_GFX

+0.95V
VDDP_0.95V_S5
42
0.95 Volt +/- 5%

5
PU5 EV@RT8068AZQW TDC : 1.58A
PL7
EV@1uH_7X7X3
PEAK : 2.1A
9
PVIN NC
1 554LX_0.95V Width : 80mil 1.8GFXD 4
PQ8
10 2 *EV@MDV1528Q
PC55 PVIN LX PC185 PC184

3
2
1
D EV@0.01U/50V_4 PR85 3 PR80 PC67 EV@0.1u/16V_4 EV@22U/6.3V_6 D
+3V_GFX EV@10_4 8 LX *EV@2.2/F_6 *EV@22P/50V_4
SVIN
+PCIE_VDDC_GFX
PC58 4
EV@10U/6.3V_4 PC63 PG 6 PR93
PR79 EV@1U/6.3V_4 FB PC50 R1 EV@6.49K/F_4 +0.95V
EV@10K/F_4 5 *EV@2200P/50V_4 0.95 Volt +/- 5%

GND
PR81 EN

NC
*shortEV@0_4 TDC : 1.58A
554PG_0.95V 554FB_0.95V
PEAK : 2.1A

11

7
[41] 0.95_GFX_EN
+3V_GFX
554EN_0.95V
R2 Width : 80mil
PR88
PR82 EV@11K/F_4
*shortEV@0_4 PC56 PC62
V0=0.6*(R1+R2)/R2
*EV@0.1u/16V_4 *EV@68P/50V_4

PQ18 VIN +3V_GFX +1.8V_GFX VIN VDD_18_S5

EV@AO3413
1 3
+3V +3V_GFX TDC : 0.04A
PC96 PEAK : 0.05A PR227 PR222

3
+3V *EV@0.1u/16V_4 EV@1M_6 PR218 PR225 EV@1M_6
Width : 20mil
2

PC91 EV@22_8 EV@22_8

CZ : DNI EV@0.1u/16V_4
CZL: mount PR116 EV@100K/F_4 1.8GFXD 2
PR112
3

3
*EV@10K/F_4 PQ37
EV@AO3404
PR228

1
PR118 EV@20K/F_4 2 0.95_GFX_EN 2 EV@1M_6 2 2 2 PC180
[5] DGPU_PWREN
EV@2200p/50V_4
C PC95 PQ19 PQ40 PQ39 PQ41 PQ42 C
PR117 EV@0.22U/10V_4 EV@2N7002K EV@2N7002K EV@2N7002K EV@2N7002K EV@2N7002K
+1.8V_GFX
*EV@100K/F_6
1

1
TDC : 0.38A
CZ : 20K (CS32002FB29)
CZ : 0.22uF(CH4222K9B04)
CZL: 0.1uF (CH4103K1B08)
PEAK : 0.5A
CZL: 10K (CS31002FB26) Width : 20mil

VIN

PU2003
8
IN
9

EV@10u/25V_8
EV@2200p/50V_4
*EV@0.1U/25V_4
IN

PC2046

PC2047

PC2048
7 22
+5VPCU PR2043 NC IN +1.5V_GFX
EV@10_4
G5335-VCC 21 IN
24 Fsw=550KHz 1.5 Volt +/- 5%
VCC TDC : 3.66A
PR2044 PC2050
PC2049
EV@G5335QT2U
EV@73.2K/F_4 *EV@0.01U/25V_4
PEAK : 4.88A
+3V_GFX EV@10U/6.3V_4
TON
6 G5335-TON Width : 160mil

PR2045 20 G5335-BST +1.5V_GFX

EV@100K/F_4 BST
B PR2047 PR2046 PC2051 B
*shortEV@0_4 EV@2.2/F_6 EV@0.1U/25V_4 PL2003
G5335-PWRGD 1 EV@0.68uH_7X7X3
[5] PE_PWRGD PGOOD 10 G5335-LX 1 2
+5VPCU LX 11
LX 16
PR2048 *EV@0_4 LX 17 EV@22U/6.3V_6

EV@22U/6.3V_6

EV@22U/6.3V_6

EV@22U/6.3V_6

EV@22U/6.3V_6

EV@0.1U/16V_4
*EV@22U/6.3V_6

*EV@22U/6.3V_6
LX 18
PC2052

PC2053

PC2054

PC2055

PC2056

PC2057

PC2058

PC2059
PR2049 *shortEV@0_4 G5335-PFM 3 LX 25
G5335-AGND PFM LX R1
PR2050
Pulse-Skipping mode *EV@4.7_6

PR2051 PC2060
EV@10K/F_4 *EV@1000P/50V_4
PC2061
GPU_PG_EN PR2052 *shortEV@0_4 G5335-EN 2 *EV@680p/50V_6
[41] GPU_PG_EN EN 12
PGND
PC2062 13
*EV@0.047U/16V_4 PGND
14
R2
PGND
G5335-AGND 15 PR2053 Vo=0.8*(R1+R2)/R2
PGND
19
EV@11K/F_4 =1.5V
G5335-SS 23 PGND
SS

4 G5335-AGND G5335-AGND
PC2063 AGND
EV@0.047U/16V_4

5 G5335-FB VFB=0.8V
G5335-AGND FB

A PR2054 *shortEV@0_4 A

G5335-AGND

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
1A
GPU_POWER/VDDC_GFX
Date: Saturday, March 05, 2016 Sheet 42 of 45
5 4 3 2 1
 5 4 3 2 1

For Type 1 & 3 43

D D

+5V_S5 +5V_S5 VDDCR_NB PQ13 PQ15

AO3416 AO3416 VDDCR_FCH_ALW
+3V_S5 VIN VDDCR_FCH_S5 VDDCR_NB 3 1 1 3
0.775~1.2 Volt +/- 5%
TDC : 0.15A
PR103 PC83
PEAK : 0.2A

2
8
1K/F_4 *0.1u/16V_4 Width : 20mil

3
PR98 PR97 3
100K/F_4 1M_6 + 1 COMP_OUT1
PR102 2 VDDCR_FCH_ALW
2 *0_4 - PU16A
AS393MTR-E1

4
C PQ12 C
3

2N7002K PR106
+5V_S5 VDDCR_FCH_S5 PQ14 PQ17 *short_6

1
FCH_PC AO3416 AO3416
[5] APU_S5_MUX_CTRL 2
3 1 1 3
PQ11
2N7002K PR95 PC76
100K/F_4 *0.1u/16V_4 PR100 PC84
1

2
1K/F_4 *0.1u/16V_4 PC87
PR99 5 0.1u/16V_4
*0_4 + 7
6
- PU16B PC86 PC85
AS393MTR-E1 22u/6.3V_6 22u/6.3V_6
COMP_OUT1

B B

A A
Quanta Computer Inc.
PROJECT : ZAB
Size Document Number Rev
1A
VDDCR_FCH_ALW
Date: Saturday, March 05, 2016 Sheet 43 of 45
5 4 3 2 1
 5 4 3 2 1

Model ZAB M/B

MODEL REV Change List Page From To
2015-11-03 1
ZAB M/B A Change DP to VGA IC from IT6516 to RTD2166 (cost) 2
3
D
First Release 4 D
5
2015-xx-xx 6
B Add 7
8
9
10
11
12
13
14
15
16
17
18
C 19 C

20
21
22
23
24
25
26
27
28
29
30
31
32
33
B
34 B

35
36
37
38
39
40
41

A A

Quanta Computer Inc.

PROJECT : ZAB
Size Document Number Rev
CHANGE LIST 1A

Date: Friday, January 29, 2016 Sheet 44 of 45

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A
Quanta Computer Inc.
PROJECT : ZAB
Size Document Number Rev
POWER STATUS 1A

Date: Friday, January 29, 2016 Sheet 45 of 45

5 4 3 2 1