Chapter 6

Effect of Electron-Hole Puddles on the Performance of

Graphene Antidot Field Effect Transistor

6.1 INTRODUCTION

For a disorder free pure graphene layer, the Fermi energy lies at the charge
neutrality point (CNP) or Dirac point (DP), where the density of states disappears.
However, in the unavoidable presence of disorder which is due to ripples associated with
intrinsic structural wrinkles or the substrate interface roughness or charged impurities
there would be charge inhomogeneity (equally probable regions of hole-rich and
electron-rich puddles) which will emerge in graphene. The graphene’s non-zero minimal
conductivity at DP could be interpreted by these puddles (Martin et al., 2007; Decker et
al., 2011). At low density, the puddles control transport phenomena not only in three
dimensional doped semiconductors and other two dimensional semiconductors
(Shklovskii and Efros, 1984) but also in graphene.

The quality of a device built using graphene strongly depends on the interaction
between the supported substrate and graphene layer. The SiO2, SiC substrates, or high-k
gate dielectrics which are most commonly used in devices limit the mobility of electron
and holes by introducing scattering from remote impurities, charged surface states,
substrate roughness and remote surface optical phonons (Decker et al., 2011).
Temperature dependence of electron hole puddle in graphene has been showing a kind of
long range columbic interaction, which is responsible for scattering of electrons in
channel region of the device (Vincent et al., 2010). One promising substrate or dielectric
for potential integration with graphene is h-BN, because it has an atomically smooth
surface which is relatively free from charge traps and dangling bonds (Bresnehan et al.,
2012).

The use of graphene in logic device applications is restricted because of its lack of
energy band gap. To overcome this problem, various methods have been proposed in
literature. One such method is etching periodic nanoholes called antidots into graphene

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(i.e., etching nanomesh into graphene) (Bai et al., 2010; Palla and Raina 2010). Though
formation of band gap in graphene by creating a periodic nanohole significantly improves
the performance (ION/IOFF ratio) of the device, the substrate induced inhomogeneous
puddles are still there to lower the performance in small gate voltage region. Magneto
conduction oscillation is a direct evidence of puddle formation in GAL (Andreas et al.,
2015). In this chapter, the effect of inhomogeneous electron-hole puddles on carrier
transport of back gated GALFET due to SiO2 and h-BN substrates will be demonstrated.
Comparison of device performance due to these substrates on the basis of shifting rate of
CNP and insulating behavior near CNP for different drain voltages has been done. In
order to know the effect of puddles on device characteristics at different channel lengths,
studies have been performed at micron and nanometer channel lengths.

6.2 RESULTS AND DISCUSSION

6.2.1 MICRON RANGE LONG CHANNEL N-TYPE AND P-TYPE GALFETS

Figure 6.1 (a) Atomistic model of a GAL [also called Nano Perforated Graphene Lattice (NPGL)]
(computational unit cell is enclosed by blue line).The parameters of the unit cell are R= 0.369 nm, W=
0.738 nm, P≈ 1.107 nm, = 6 atoms, 𝑎 = 72 atoms. (b) Atomistic model of GAL (computational
unit cell is enclosed by blue line).The parameters of the unit cell are R= 5 nm, W= 6.33 nm, P ≈ 16.3 nm,
= 2400 atoms, total = 8711 atoms. (c) Schematic diagram of a GALFET. (d) Conduction band
profile of GALFET at -0.2V, 0.0 V and 0.2V drain bias and 2.0V gate bias conditions. The effective mass
(m*) and band gap (EG), LC and WC of the channel are 0.149mo and 642meV, 1.0 m x 1.0 m respectively.

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 Here, numerical simulation package, ATK-15.1(Atomistix), with Hancock
(Hancock et al., 2008) parameters are used for finding material parameters like band gap
(EG), effective mass (m*), permittivity (ℇ) (Rene Petersen, 2009) for graphene antidot
with different neck-width (W) ranging from 1.72 nm to 7nm. Here, various sized unit
cells are used for GAL material parameters extraction. An example of an atomistic model
of GAL is shown in Fig.6.1b (computational unit cell is enclosed by blue line). A typical
GAL is characterized by hole radius(R), neck-width (W) and periodicity (p) as shown in
Fig.6.1b.

For a unit cell with R= 0.369 nm, W= 0.738 nm, ≈ . , number of atoms
removed, = 6 atoms, total number of atoms in a unit cell, 𝑎 = 72 atoms.
Similarly for 𝑎 = 4607 atoms, = 2400 atoms, = . energy gap
EG=20.5 meV, effective mass of electron me* = 0.780mo, effective mass of hole mh*
=0.395mo and permittivity 4.75. Some of the material parameters extracted for GAL are
shown in Table 6.1.

Table 6.1 Material parameters of GAL

Total Removed Neck- EG Effective Effective Permittivity

No Atoms Width (meV) mass of mass of
atoms (nm) e- h+

4607 2400 1.72 20.5 0.780 0.395 4.75

6497 2400 3.93 15.5 0.297 0.168 3.64
7199 2400 4.67 14.8 0.245 0.132 4.80

Snake state is a very important parameter to find the electron-hole puddle effect
on graphene device performance. The appearance of snake state is possible only when
cyclotron radius is equal to width of device. Cyclotron diameter can be modified by
changing magnetic field strength or by changing carrier concentration (Milovanović et
al., 2016). For GAL with hole diameter, d, the Fermi wavelength and cyclotron radius is
denoted as = − and 𝐶 = ⁄ respectively. For GAL with hole diameter, d, the
carrier density, 𝑠 , is estimated (Zhang et al., 2013) as, 𝑠 = 𝜋⁄ − , 𝑠 = . ×
−
for neck width p - d=6.33 nm; similarly for neckwidth 0.369 nm, 𝑠 = . ×

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 −
. The relaxation time is 𝒯 = ⁄ =16.3 fs for = . and = ×
6
/ and similarly 𝒯=1.107fs, for p=1.107 nm. Now the mobility is estimated
∗ ∗
using = 𝒯⁄ , for = . ° , 𝒯=16.33fs, =1148.89 / . . Similarly
∗
for = . °, 𝒯=1.107 fs, =13.0 / . . Mean free path in terms of neck-width
and mobility is estimated as 𝑝 = ћ⁄ 𝜋⁄ − = for neck-width

(p - d) = 6.33 nm and   1148 .89 cm 2 V  s ; similarly, as 𝑝 = for neck-width

(p - d) = 0.369 nm and   13 cm 2 V  s . Diffusion coefficient in terms of thermal velocity at

room temperature and mean free path is estimated as = 𝑝 ⁄ =58.5 ⁄ for

2 K BT 
VT  , where m  0.149 mo .
m *

Parameters for GALs of different neck-widths (w) ranging from 1.72nm to 7nm
are extracted the corresponding transport parameters such as mobility, carrier
concentration, mean free path etc. are calculated as explained above. The above material
parameters are used in ATLAS (ATLAS 2015) device simulator for studying device
electrical characteristics. The schematic diagram of simulated back gate GALFET is
shown in Fig.6.1b. Here, drift-diffusion mode space (DD_MS) mainly for micron size
channel length and Non-Equilibrium Green’s Function formalism with Mode Space
approach (NEGF_MS) for nano-scale channel length are separately solved self-
consistently with 2D-possion equation within effective mass Hamiltonian. For micron
size channel length Non-Equilibrium Green’s Function formalism with Tight Binding
(TB-NEGF) Hamiltonian is solved self- consistently with 2D-possion equation in order to
compare results with experimental values separately.

Here, two unit cells of different sizes are used for GAL material parameters
extraction for micron channel GALFETs. As shown in Fig. 6.1(a) and 6.1(b), two
atomistic models of GALs (computational unit cells are enclosed by blue line) are
considered for computation. The parameters of the unit cell shown in (a) are R= 0.369
nm, W= 0.738 nm, P ≈ 1.107 nm, = 6 atoms, 𝑎 = 72 atoms. (b) The
parameters of the unit cell shown in (b) are R= 5 nm, W= 6.33 nm, P ≈ 16.3 nm,
removed = 2400 atoms and 𝑎 = 8711 atoms.

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 The size of the GAL shown in unit cell of Fig. 6.1(b), is compared with an
experimentally fabricated one. The radius (R), neck-width (W) and Periodicity (P) are
same as the experimentally reported readings as mentioned in (Bai, et al. 2010). First, the
simulation has been performed using DD_MS approach within ATLAS device frame
work by making use of parameters mentioned for unit cell shown in Fig. 6.1(a). The
GALFET device dimensions (in x and y directions) used for simulation are1.5 m x
1.0 m respectively. The LC and WC are 1.0 m x 1.0 m (channel length x width)
respectively. The Au/Ti materials are used on top of pristine graphene to make electrodes
at device ends. The channel material is a band gap engineered semiconducting graphene
with periodic nanoscale pores. The channel material is placed on top of SiO 2 with 300 nm
thickness. The I-V characteristics of n- type- GALFET with material (EG= 642meV and
m*=0.149mo) and device dimensions mentioned above are shown in Fig. 6.2(a) (drain
characteristics) and 6.2(b) (transfer characteristics) respectively. In this case, where
Vds=0.5V, the device has shown good saturation and achieved an ION/IOFF ratio of 1589.4.

Figure 6.2 I-V characteristics of n-type GALFET (a) Drain characteristics (b) Transfer characteristics. The
GAL channel with EG=642 meV and m*=0.149mo is used for simulation. The DD_MS method is used for
numerical simulation.

Second, the simulation has been performed using DD_MS approach within
ATLAS device frame work by making use of parameters mentioned for unit cell 6.1(b).

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 The GALFET device dimensions (in x and y directions) used for simulation are
same as the first one. The LC and WC are 1.0 m x 2.0 m respectively. The Au/Ti
materials are used on top of pristine graphene to make electrodes at device ends. Again
the channel material is a band gap engineered semiconducting graphene with periodic
nanoscale holes. The channel material is placed on top of SiO 2 with 300 nm thickness.
The I-V characteristics of p- type GALFET with material (EG= 13.33meV and
m*=0.025mo) and device dimensions mentioned above are shown in Fig. 6.3(a) (drain
characteristics) and 6.3(b) (drain characteristics) respectively. In Fig. 6.3(a), the DD_MS
simulations are compared with experimental results (Bai, et al. 2010), which show good
agreement with each other. In Fig. 6.3(b), TB-NEGF simulations are compared with same
experimental results (Fig. 6.3(a)) which also show good agreement with each other. Even
though the shape and exact size of the pores have not been reported experimentally,
obviously which is a difficult task at atomic level, our above simulations confirm the
shape and size of the pores (holes) and neck-width between pores by comparing I-V
characteristics of both experiments and simulations. After having a detailed study with
various shapes, sizes and neck-widths it has been confirmed that, the experimentally
fabricated semiconducting GAL sheet is of hexagonal shape pores.

Figure 6.3 I-V characteristics of P-GALFET (a) Drain characteristics. The experimental results (Bai, et al.
2010) are compared with DD_MS numerical simulation (b) Drain characteristics. Here experimental results
(Bai, et al. 2010) are compared with TB-NEGF numerical simulation. The GAL channel with EG=
13.33meV and m*=0.025mo are used for simulation.

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 The ID -VG characteristics with various VDS values are shown in Fig.6.4 for one
micron channel length p-GALFET. The simulation results using DD_MS approach are
compared with experimental results (Bai et al., 2010). The simulation results have a good
agreement with experimental results and I ON/IOFF ratio has been compared with
experimental result. Band bending occurs from graphene to GAL region, which is due to
localized density of state at the edge of graphene nanohole. The band bending from
graphene to GAL is responsible for the formation of Schottkey barrier. Hence, this
simulated device has used Schottkey barrier junction formation at source-channel and
drain-channel interfaces in its calculation.

Figure 6.4 ID-VGS characteristics using DD_MS method at different VDS has been compared with
experimental P-type GALFET with 1micrometer channel length, with GAL neck width = 7nm,
EG=13.3meV.

6.2.2 NANO SCALE N-CHANNEL GALFETS

Simulated, one of the hexagonal unit cells is displayed in Fig.6.5 (a) within the enclosed
brown line. Here, unit cell of size 𝑎 = 4607 atoms, = 2400 atoms, =
. , EG=20.5 meV, me*= 0.780mo, mh* =0.395mo and permittivity (ℇ) = 4.75 have

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been used for computation. Potential profile of 30 nm channel length back gate GALFET
is shown in Fig.6.6 (a) on different VDS with zero gate voltage. The SiO2 and h-BN
substrates’ effect on device performance has been shown in Fig.6.6 (b). As shown in
Fig.6.6 (b), there is an improved device performance on h-BN substrate as compared to
SiO2 substrate.

Figure 6.5 (a) Atomistic model of GAL with unit cell enclosed in brown line. The corresponding
neckwidth(W), hole radius (R) and Periodicity(p) are indicated with arrows. A small portion of unit cell is
zoomed in circle to show at atom level. (b) Schematic diagram of a back gated GALFET.

Figure 6.6 GALFET simulation along 30nm channel length with W =1.72nm and EG=20.5meV using
DD_MS method (a) Potential profile at a drain bias of 0V,0.2V,0.4V and 0.6V (b) ID-VDS characteristics
for SiO2 and h-BN substrates at 0.8V,1.2V and 1.6V.

The improved current value on h-BN substrate for the same channel length shows
the direct evidence of improved mobility and less scattering of electrons in channel. As

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shown in Fig.6.7, DD_ MS and NEGF _ MS methods are used for device simulation
around CNP. Puddle induced carrier density near CNP is having more influence on ID-
VGS characteristics of SiO2 than on h-BN. It is observed that the rate of shifting of CNP is
more in case of SiO2 substrate as compared to h-BN substrate for different VDS ranging
from 0.8V to 1.6 V as shown in Fig.6.7 (a). For GAL on h-BN substrate, the minimal
conductivity drastically reduces compared to GAL on SiO2 substrate, under the same
dimensions and bias conditions as shown in Fig.6.7 (b).

Figure 6.7 I-V characteristics of a GALFET along 30nm channel length with W = 1.72nm and EG =
20.5meV at 0.8V,1.2V and 1.6V bias (a) ID-VGS characteristics for SiO2 and h-BN substrates using
DD_MS method (b) ID-VGS characteristics for SiO2 and h-BN substrates using NEGF_MS method.

The minimum conductivity in the channel near CNP is explained based on

number of modes by NEGF_MS approach. The dependence of minimum conductivity
around CNP can be explained by puddle induced carrier density mode method. As shown
in Fig.6.3 (b), h-BN substrate shows 100 times minimum conductivity near CNP as
compared to SiO2. This implies that there is 100 times lesser puddle carrier concentration
in case of h-BN substrate. Those two methods used in Fig.6.7 clearly indicate puddle
concentration in GALFET. The rate of shifting of CNP has been clearly observed through
semi-classical drift-diffusion method and minimum conductivity near CNP has been
clearly observed through quantum-mode space method. Yagi et al interpreted that there is
a large possibility for magneto-resistance oscillation around CNP in case of h-BN

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substrate (Yagi et al., 2015). Higher value of ION/IOFF ratio is achieved in case of h-BN
substrate compared to SiO2. The slope around minimum conductivity point (CNP) gives
information about the mobility of electron in devices (Bolotina et al., 2008). In case of
Fig.6.7 (b), characteristics related to h-BN substrate showing large slope compared to
SiO2. Higher ION/IOFF ratio is achieved at VDS = 0.8 V for h-BN compared to SiO2 at same
value of VDS.

Figure 6.8 Channel resistance around CNP as a function of VGS for 30 nm channel length with GAL neck
width=1.72 nm, and EG =20.5meV.

FWHM near CNP is less in case of h-BN substrate as compared to SiO2

substrate, which shows less charge inhomogeneity in case of h-BN substrate as shown in
Fig.6.8. In this Fig. 6.8, the increased resistance value for GAL on h-BN substrate near
CNP is the direct evidence of lesser charge impurities present in GAL as compared to
GAL on SiO2 substrate for various values of VDS ranging from 0.8V to 1.6V. Similar
conclusions are made for graphene/h-BN compared to graphene/SiO2 (Ponomarenko et
al., 2011). For the same GAL channel, h-BN and SiO2 substrates show remarkable
change in electronic properties. The h-BN substrate enhanced the ION/IOFF ratio as
compared to SiO2 for GALFET devices. Our simulation result shows that h-BN is an

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ideal substrate for GAL electronic devices similar to graphene with h-BN substrate (Dean
et al., 2010).

6.3 COMPLIMENTARY GAL-FET BASED INVERTER

Complementary GAL-FET based inverter is designed using figures 6.2 and 6.3.
The inverter schematic and its static characteristics are shown in Fig. 6.9 (a) and (b). The
dimensions of the devices used are as follows: P-GAL-FET: LC =1.0µ m and WC = 2.0µm;
N-GAL-FET: LC =1.0µm and WC =1.0µm. The two gate electrodes of the two GAL-FETs
are tied together to form input VIN. The two drain electrodes of the two GAL-FETs are
tied together to form output terminal VOUT. Output is collected from VOUT terminal
(marked with green colour voltage marker). The VIN vs VOUT relation is shown as static
characteristic as shown in Fig. 6.9(b). When VIN < 1.0V, VOUT is 2.0V for a supply VDD
of 2.0V. When VIN < 1.0V, the N-GAL-FET is OFF and P-GAL-FET is ON. When VIN
>1.0V, the N-GAL-FET is ON and P-GAL-FET is OFF, hence VOUT is 0.0V. So, when
input is logic 0, output is logic 1.When input is logic 1, Output is logic 0.Hence, the
inverter operation is justified. Similar explanation applicable to VDD=2.5V as well.

Figure 6.9 (a) Schematic of complementary GAL-FET based logic inverter (b) Voltage transfer
characteristics of a complementary GAL-FET inverter for different supply voltages.

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6.4 CONCLUSIONS
We have simulated back gated GALFET with channel lengths from 1 micron to
30nm, with different substrates, SiO2 and h-BN. Our simulation results have good
agreement with recently published experiments. For complete understanding and better
accuracy of simulation results, both micron and nanoscale lengths are performed and
compared with different methods such as drift-diffusion-mode space and non-equilibrium
Green’s function frameworks.

The device dimensions considered for simulations and the experiment are similar
with neck width and hole periodicity of 6.3 nm and 16.3 nm respectively. A /
ratio of 1589.4 for = 642 meV and 1235.29 for = 294 meV at Vds=0.5V are
achieved for n-NPG-FET. After detailed theoretical study it has been confirmed that the
shape of the pores are hexagonal. Our device simulations will help in detail
understanding of the transport theory behind the experiments.

With the presence of h-BN substrate and transport gaps, the electrical
characteristics of the GALFETs are significantly enhanced, as manifested by enhanced
ION/IOFF current ratio, current saturation. Linear dependency of conductivity on carrier
density near CNP is the main point to recognize the puddle effect on device performance.
By comparing ID-VG result near CNP for different substrates, we have found that the rate
of shifting of CNP for SiO2 is more than h-BN for different drain voltages. The above
analysis shows the direct evidence of large puddle carrier concentration in case of GAL/
SiO2 FETs than GAL/ h-BN FETs. These results may open the route for logic
applications of semiconducting graphene.

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