T1-L4

BAPATLA ENGINEERING COLLEGE

(Autonomous)

COURSE PLAN

1. Department INFORMATION TECHNOLOGY

2. Program B.Tech.

3. Semester/Year III Sem / II Year

4. Course title /code Computer Organization & Architecture/ 18IT301

5. Prerequisite – Code and Title 18IT204 –Digital Logic Design

6. Number of hours tuition 64 (4 Periods/ Week.)

7. Date of Preparation 24-06-2019

8. Syllabus
UNIT - I (17Periods)
BASIC STRUCTURE OF COMPUTERS: Computer Types, Functional unit, Basic operational concepts, Bus
structures, Software, Performance, multiprocessors and multi computers. (8 Periods)
MACHINE INSTRUCTIONS AND PROGRAMS: Numbers, Arithmetic Operations and Characters, Memory
locations and addresses, Memory Operations, Instructions and Instruction Sequencing, Addressing Modes, Basic
Input/output Operations.(9 Periods)
UNIT - II (15 Periods)
INPUT/OUTPUT ORGANIZATION: Interrupts, Direct Memory Access, Buses, Interface Circuits, Standard I/O
Interfaces: PCI Bus, SCSI Bus, USB Bus. (15 Periods)
UNIT - III (17 Periods)
THE MEMORY SYSTEM: Some Basic Concepts, Semiconductor RAM Memories, Read-Only memories, Speed,
Size and Cost, Cache Memories, performance Considerations, Virtual memories, Memory management
Requirements, Secondary Storage. (9 Periods)
ARITHMETIC: Addition and Subtraction of Signed Numbers, Multiplication of Positive numbers, Signed
operand multiplication, Fast multiplication, Integer Division, Floating point numbers and operations.(8 Periods)
UNIT - IV (15 Periods)
BASIC PROCESSING UNIT: Some fundamental concepts, Execution of a complete instruction, Multiple –Bus
Organization, Hardwired control, Micro programmed control.(7 Periods)
PIPELINING: Basic Concepts, Data Hazards, Instruction hazards, Influence on Instruction Sets, Data path and
Control Considerations, Superscalar Operations, performance Considerations.(8 Periods)

1. Course Objectives
In this course the students are expected to be able to :
CO1: To conceptualize the basics of organizational and architectural issues of a digital computer and
Classify and compute the performance of machines, Machine Instructions.
CO2: Learn about various data transfer techniques in digital computer and the I/O interface.

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CO3: Estimate the performance of various classes of Memories, build large memories using small
memories for better performance and Relate to arithmetic for ALU implementation.
CO4: Understand the basics of hardwired and micro-programmed control of the CPU, pipelined
architectures , Hazards and Superscalar Operations

10. Learning Outcomes

UNIT - I
Chapter – I: BASIC STRUCTURE OF COMPUTERS
Syllabus: Computer Types, Functional unit, Basic operational concepts, Bus structures, Software,
Performance, multiprocessors and multi computers.
Learning Outcomes: After completion of the Chapter the student must be able to
1.1.1 What are the various Computer Types.
1.1.2 List the basic functional units of a computer.
1.1.3 Explain functional units in a computer.
1.1.4 Write about basic operational concepts.
1.1.5 Explain Bus structures.
1.1.6 Explain the role of system software in a computer.
1.1.7 Discuss various parameters for improving the performance of a computer
1.1.8 Write basic performance equation? How to improve T?
1.1.9 List and explain the parameters which affect the performance of a computer.
1.1.10 Define Reduced Instruction Set Computer.
1.1.11 What is mean by multicomputer?
1.1.12 What is the role of interface?
1.1.13 Explain the following
a Multiprocessors. b. Multi computers.

Chapter – II: MACHINE INSTRUCTIONS AND PROGRAMS

Syllabus: Numbers, Arithmetic Operations and Characters, Memory locations and addresses, Memory
Operations, Instructions and Instruction Sequencing, Addressing Modes, Basic Input/output Operations,
Learning Outcomes: After completion of the Chapter the student must be able to
1.2.1 Define arithmetic overflow
1.2.2 “2’s complement approach is preferable than sign magnitude for representing the fixed point
numbers” – Justify this statement.
1.2.3 Explain Memory Locations and addressing.
1.2.4 Write about instruction sequencing.
1.2.5 What is mean by effective address?
1.2.6 What is an index register?
1.2.7 What are the different fields found in instruction format?
1.2.8 What is the addressing mode? Explain different addressing modes in detail.
1.2.9 Write the purpose of SIN and SOUT status flags.
1.2.10 Explain the Basic i/o operations
1.2.11 Mention the commonly used condition code flags.
1.2.12 Define micro instruction

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 UNIT – II
Chapter – III: INPUT/OUTPUT ORGANIZATION
Syllabus: Interrupts, Direct Memory Access, Buses, Interface Circuits, Standard I/O Interfaces: PCI Bus,
SCSI Bus, USB Bus.
Learning Outcomes: After completion of the Chapter the student must be able to
2.3.1 What is memory mapped I/O?
2.3.2 What are the different kinds of I/O Communication techniques? What are the relative
advantages and disadvantages?
2.3.3 Define Polling.
2.3.4 Define Interrupt and Interrupt response.
2.3.5 Write various uses of interrupts.
2.3.6 What is Interrupt nesting? Briefly bring out the methods involved in the processor attending to
simultaneous requests?
2.3.7 What is DMA?
2.3.8 Explain the following with relevant figures.
a) DMA Controller. b) DMA Transfer
2.3.9 What are the different kinds of DMA transfers?
2.3.10 Explain the following with relevant figures.
a) Direct Memory Access b) Bus arbitration
2.3.11 With neat timing diagrams explain synchronous and asynchronous buses.
2.3.12 Write short note on Interface circuits
2.3.13 What is port.
2.3.14 Write short notes on PCI Bus.
2.3.15 List the data transfer signals used on the PCI bus.
2.3.16 Explain following interface standards in detail a) PCI b) SCSI c) USB

UNIT - III
Chapter – IV: THE MEMORY SYSTEM
Syllabus: Some Basic Concepts, Semiconductor RAM Memories, Read-Only memories, Speed, Size and
Cost, Cache Memories, performance Considerations, Virtual memories, Memory management
Requirements, Secondary Storage.
Learning Outcomes: After completion of the Chapter the student must be able to
3.4.1 What are the main challenges in design of Computer system in memory point of view?
3.4.2 List the type of RAMs and ROMs.
3.4.3 Compare RAM and ROM.
3.4.4 State the meaning of locality of reference
3.4.5 Define Cache Memory.
3.4.6 Write about Cache Hit, Cache Miss and Cache coherence problem
3.4.7 What is write-through Protocol?
3.4.8 With neat sketches explain cache memory mapping functions.
3.4.9 Discuss the various mapping schemes in cache design. Compare the schemes in terms of
cost and performance.
3.4.10 Define memory interleaving.
3.4.11 What are virtual and logical addresses?
3.4.12 What is translation lookaside buffer?
3.4.13 What is virtual memory?

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 3.4.14 What is virtual memory? Explain in detail.
3.4.15 What is a Memory Controller?
3.4.16 Write short notes on secondary storage.

Chapter – V: ARITHMETIC
Syllabus: Addition and Subtraction of Signed Numbers, Multiplication of Positive numbers, Signed
operand multiplication, Fast multiplication, Integer Division, Floating point numbers and operations.
Learning Outcomes: After completion of the Chapter the student must be able to
3.5.1 Explain the Addition and Subtraction of signed numbers.
3.5.2 Explain in detail the principle of carry look ahead adder. Show how 16-bit CLAs can be
constructed from 4-bit adders with an example.
3.5.3 Give Booth’s algorithm to multiply two binary numbers. Explain the working of the
algorithm taking an example
3.5.4 Multiply 11010 and 10110 using booth’s algorithm.
3.5.5 Perform the 2’s complement multiplication for the signed integer operands: (-13) * (-10)
using Booth’s recoding scheme.
3.5.6 Write the purpose of bit pair recoding of multiplier.
3.5.7 Explain Fast Multiplication
3.5.8 Perform the division of binary numbers 1000 by 11 using restoring and non-restoring
division methods.
3.5.9 Perform the restoring division for the binary numbers 1010 and 11. Draw the circuit
arrangement for binary division.
3.5.10 Describe floating point representation.
3.5.11 Explain about IEEE 754 single precision and double precision methods.

UNIT - IV
Chapter – VI: BASIC PROCESSING UNIT
Syllabus: Some fundamental concepts, Execution of a complete instruction, Multiple –Bus Organization,
Hardwired control, Micro programmed control.
Learning Outcomes: After completion of the Chapter the student must be able to
4.6.1 Describe steps in the execution of complete instruction.
4.6.2 What are various operations carried out for executing instructions?
4.6.3 What is the sequence of operations to add the contents of register R1 to those of R2 and store
the result in R3?
4.6.4 What is the sequence of operations to fetching a word from Memory.
4.6.5 Write the sequence of operations for storing a word in memory with the instruction
Mov R2, (R1).
4.6.6 Write the control sequence for execution of the instruction Add (R3), R1
4.6.7 Differentiate single channel and multi -channel bus
4.6.8 Explain the hardwired control unit with the help of block diagram.
4.6.9 What is the advantage of hardwired control unit?
4.6.10 Explain micro programmed control.
4.6.11 List out Various branching technique used in micro program control unit?
4.6.12 Write the micro instructions for ADD (Rsrc)+, Rdst. Explain each microinstruction in detail.
4.6.13 What is known as Multi-Phase clocking?
4.6.14 Compare Hardwired control and micro programmed control unit.

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 4.6.15 Why hardwired control unit is faster than the micro-program control unit? Justify your view.
4.6.16 What is the use of micro instruction with next address field?
4.6.17 Explain horizontal and vertical organizations in micro programmed control.

Chapter – VII: PIPELINING

Syllabus: Basic Concepts, Data Hazards, Instruction hazards, Influence on Instruction Sets, Data path and
Control Considerations, Superscalar Operation, performance Considerations.
Learning Outcomes: After completion of the Chapter the student must be able to
4.7.1 What is Pipelining
4.7.2 Describe Pipelining Concepts with examples.
4.7.3 Explain how unconditional branches affect pipeline.
4.7.4 With examples explain how branch prediction reduces the effect of branch instructions on
pipelining.
4.7.5 Define data hazard.
4.7.6 What are data hazards? Explain how data hazards effect pipelining.
4.7.7 Explain data hazard with example and how it can be eliminated.
4.7.8 Define Throughput and Throughput rate.
4.7.9 What do you mean by out-of order execution? Is it Desirable?
4.7.10 What are the steps required for a pipelined processor to process the instruction?
4.7.11 State the meaning of hit ratio.
4.7.12 Describe superscalar operation.

Seminar: Students chooses a topic part of Computer Organization and Architecture submit a report and
make a presentation to the class
Learning Outcomes: The student must be able to
4.8.1 Prepare a summary of a chosen topic or a journal article
4.8.2 Make a written communication in the form of a report
4.8.3 Prepare presentation material
4.8.4 Make oral presentation of the topic to the class
11. Teaching – Learning Methods

Lecture – cum – discussion with PPTs, Problem solving

12. Assessment Methods

Quizzes/Surprise Test, Home Assignments, Seminar, Mid Term Examination, End-Semester
Examination.

13. Lesson Plan

No. of Learning Teaching Assessment

Week Unit/module/ Topic(s)
Periods Outcomes Methods Methods
I a/ BASIC STRUCTURE OF Lecture – cum
4 COMPUTERS: Computer – discussion
1 1.1.1 to 1.1.4 Quiz/
Types, Functional unit, Basic with PPTs
operational concepts, Assignments
Bus structures, Software, Lecture – cum & Mid Exam-I
2 4 1.1.5 to 1.1.13 Performance, multiprocessors – discussion

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 and multi computers. with PPTs

I b/ MACHINE Lecture – cum

INSTRUCTIONS AND – discussion
PROGRAMS: Numbers, with PPTs
3 4 1.2.1 to1.2.3 Arithmetic Operations and
Characters, Memory locations
and addresses, Memory
Operations,
Quiz/Test-1 Lecture – cum
4 4 1.2.4 to 1.2.8 Instructions and Instruction – discussion
Sequencing, Addressing Modes, with PPTs
1.2.9 to 1.2.13 Basic Input/output Operations Lecture – cum
5 4 & II/ INPUT/OUTPUT – discussion
2.3.1 to 2.3.3 ORGANIZATION: Basics with PPTs
Lecture – cum
4 Interrupts, Direct Memory
6 2.3.4 to 2.3.10 – discussion
Access Quiz/
with PPTs
Assignments
Buses, Interface Circuits , Lecture – cum
4 & Mid Exam-I
7 2.3.11 to 2.3.15 Standard I/O Interfaces: PCI Bus – discussion
Quiz/ Test-2 with PPTs
Lecture – cum
4 Standard I/O Interfaces: SCSI
8 2.3.16 – discussion
Bus, USB Bus.
with PPTs
Mid Term Exam-I
III a/ THE MEMORY Lecture – cum
9 SYSTEM: Some Basic – discussion
4 3.4.1 to 3.4.3 Concepts, Semiconductor RAM with PPTs
Memories, Read-Only memories,
Speed, Size and Cost
Lecture – cum
4 Cache Memories, performance
10 3.4.4 to 3.4.14 – discussion
Considerations, Virtual memories
with PPTs Quiz/
Memory management Lecture – cum Assignments
Requirements, Secondary
3.4.15 to 3.4.16 – discussion & Mid Exam-
4 Storage.
11 & with PPTs, II
III b/ ARITHMETIC: Addition
3.5.1 to 3.5.2 and Subtraction of Signed
Problem
Numbers, Solving
Multiplication of Positive Lecture – cum
numbers, Signed operand – discussion
12 4 3.5.3 to 3.5.7 multiplication, Fast with PPTs,
multiplication. Problem
Quiz/Test-3 Solving
Integer Division, Floating point Lecture – cum –
3.5.8 to 3.5.11
4 numbers and operations. discussion with
13 &
IV a/ BASIC PROCESSING PPTs, Problem
4.6.1 to 4.6.5 UNIT: Some fundamental Solving
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 concepts,

Execution of a complete
Lecture – cum
4 instruction, Multiple –Bus
14 4.6.6 to 4.6.17 – discussion
Organization, Hardwired control,
Micro programmed control.
with PPTs
IV b/ PIPELINING: Basic
Concepts, Data Hazards, Lecture – cum
15 4 4.7.1 to 4.7.7 Instruction hazards, Influence on – discussion
Instruction Sets with PPTs Quiz/
Quiz/Test-4 Assignments
Data path and Control & Mid Exam-
Lecture – cum
4 Considerations, Superscalar II
16 4.7.8 to 4.7.12 – discussion
Operation, performance
Considerations.
with PPTs
Seminars shall be Report and
conducted in the Presentation by
4.8.1 to 4.8.4 Seminar Presentation
seminar period in Students
every week. evaluation
14. Resources

Text Book 1. “Computer Organization”, Carl Hamacher, ZvonkoVranesic,

SafwatZaky, Fifth Edition, McGraw Hill.

Reference Books 1. “Computer Architecture and Organization”, John P. Hayes, Third

Edition, McGraw Hill.
2. “Computer Organization and Architecture”, William Stallings, 6th
Edition, Pearson/PHI.
3. “Computer Systems Architecture”, M. Morris Mano, Third Edition,
Pearson/PHI.
Journals/Journal Articles

Other Resources such as Guest

Lecture, Field Study, etc.

Assessment Scheme

Type of Assessment Mode of Examination Marks %

Self-Learning Exercises/Home Essay type questions, numerical 10 10%
Assignments problems
Quizzes/ Surprise Test Objective type questions, Short 15 15%
45min duration answer questions
Seminar-Report and Oral presentation 15 minutes presentation with 5 5%
PPTs and Q/A
Mid Term Test Essay type questions, numerical 20 20%
One and half hour duration problems
Final Examination Three hours duration Essay type questions, numerical 50 50%
problems, case studies

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Self-learning Exercises (SLE)/Assignment:

Date of
S. No. Questions
Submission
a) What are the basic functional units of a computer? Explain the operational
concepts of a computer with a neat sketch. Mention the functions of different
1 processor registers. 04/07/2019
i)IR ii)MAR iii)MDR iv) PC
b) Explain the Bus Structure.
c) Explain the role of system software in a computer
a) Discuss various parameters for improving the performance of a computer.
2 15/07/2019
b) Explain the following a.
Multiprocessors b. Multi computers.
a) Explain Memory Locations and addressing.
b) What is the addressing mode? Explain different addressing modes in detail.
c) Registers R1 and R2 of a computer contain the decimal values 1200 and 4600
respectively. What is the effective address of the memory operand in each of the
following instructions
3 25/07/2019
i) Load 20(R1), R5 ii) Move #300, R5
iii) Store R5, 30 (R1,R2) iv) Add –(R2), R5
d) An instruction is stored at location 300 with its address field at location 301. The
address field has the value 400. A process register R1 contains the number 200.
Evaluate the effective address if the addressing mode of the instruction is
i) direct ii) immediate iii) relative (iv) register indirect
a) Explain the Basic i/o operations
4 b) Write short notes on Subroutine. 31/07/2019
c) What are the different kinds of I/O Communication techniques? What are the
relative advantages and disadvantages?
a) What is Interrupt nesting? Briefly bring out the methods involved in the processor
5 attending to simultaneous requests. 13/08/2019
b) Explain the following with relevant figures.
i) DMA Controller. ii) DMA Transfer
a) Differentiate RAM and ROM
6 b) Discuss the various mapping schemes in cache design. Compare the schemes in 26/08/2019
terms of cost and performance.
c) Write short notes on Cache Memories
7 a) What is virtual memory? Explain in detail. 09/09/2019
b) Write short notes on secondary storage.
a) Perform the 2’s complement multiplication for the signed integer operands:
(-13) * (-10) using Booth’s recoding scheme.
8 b) Perform the division of binary numbers 1000 by 11 using restoring and non- 16/09/2019
restoring division methods.
c) Describe floating point representation.
a) Write the control sequence for execution of the instruction Add (R3), R1
b) Write the micro instructions for ADD (Rsrc)+, Rdst. Explain each
9 microinstruction in detail. 23/09/2019
c) Why hardwired control unit is faster than the micro-program control unit? Justify
your view
a) Describe Pipelining Concepts with examples.
10 b) What are data hazards? Explain how data hazards effect pipelining and how can 03/10/2019
we eliminate them.
c) Describe superscalar operations

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