EXPT NO: 9

FLIP-FLOP CIRCUITS (SR, JK, T, D AND MASTER SLAVE JK) USING BASIC
GATES.

AIM

To setup and test the following flip flops.

1. Clocked SR Flip Flop

2. JK Flip Flop

3. D Flip Flop

4. T Flip Flop

5. Master slave Flip Flop

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7400, 7410, IC Trainer kit

THEORY

Flip Flop is the basic building block in any memory system since its output
will remain in its state until it is forced to change it by some means.

SR Flip Flop

Clocked SR Flip Flop: “S” and “R” stands for set and reset respectively. There are four
input combinations possible at the inputs. When S=R=0 the output will remains in its
last state. When S=1,R=0 , the the flip flop will set its output and when S=0, R= 1, then
the flip flop will reset. But S=R=1 is forbidden since the output will be intermediate.
When the flip flop switched ON, its output state will be uncertain. When initial state is
to be assigned, two separate inputs called preset and clear are used.
 JK Flip Flop
The intermediate output state of SRFF when S=R=1 is avoided by converting it into
JK flip flop. In this stage the JK flip flop will toggle its output( complement of the last
output). In all other input combinations the functions will be same as in SR flip flop.
MASTER SLAVE FLIPFLOP

It consist of clocked JK flip flop as a master and clocked SR flip flop as a slave,
the output of the master flip flop is fed as an input to the slave flip flop. Clock signal is
connected directly to the master flip flop, but it is connected through inverter to the
slave flip flop. Therefore, the information present at the JK input is transmitted to the
output of master flip flop on the positive clock pulse and it is held there until the
negative clock pulse occurs, after which it is allowed to pass through to the output of
slave flip flop. In all of the input conditions the slave copies what the master does.

D FLIPFLOP
It has only one input referred to as D input or delay input. The input data
appears at the output after a clock pulse applied. D flip flop can be derived from a JK
flip flop by using J input as the D input and J is inverted and fed to K input.
T FLIPFLOP
In T flip flop, T stands for toggle. The output toggles when a clock input is
applied.ie output of the flip flop changes state for an input pulses. T flip flop can
derive from JK flip flop by shorting J and K inputs.
D flip flop

JK Flip Flop

JK Flip Flop with Preset and Clr

MASTER SLAVE FLIP FLOP

D flip flop Using JK flipflop

T flip flop Using JK flipflop

PROCEDURE

1. Test all components and IC packages using multimeter and digital IC tester.

2. Set up the flip flops using gates and verify their truth tables.

RESULT

Designed and set up the following

1. Clocked SR Flip Flop

2. JK Flip Flop

3. D Flip Flop

4. T Flip Flop

5. Master slave Flip Flop