2019 6th International Conference on Control, Decision and

Information Technologies (CoDIT’19) | Paris, France / April 23-26, 2019

Design a Universal Remote Controlled Thermostat

Based on FPGA
Alghamdi, Ali S.
Department of Electrical Engineering
College of Engineering
Majmaah University
Majmaah 11952, Riyadh Region, Saudi Arabia
aalghamdi@mu.edu.sa

Abstract— The need to control the climate has become one of
the most important issues in the man daily life. At home, office,
and car …etc. It is required that the temperature stays within the
comfortable ranges. In this paper we introduce the design of a
thermostat, completely based on FPGA usage. Algorithmic state
machines, ASM, are used to control the system constituents.
Temperature setting is done via the infra-red remote control unit.
The system is further protected by a password, entered via the said
remote control unite, to prevent unauthorized people from
changing the temperature setting. The overall system consists of a
number of submodules. Digital submodules are converted into
FPGA based units and implemented using VHDL code.
Index Terms— temperature control, thermostat, remote
control signals, data recognition, algorithmic state machines,
ASM, finite state machine, FSM, FPGA, VHDL.
I. INTRODUCTION
Our main goal in this paper is to use VHDL and the FPGA
technology to manipulate a climate control system in such a
way to make the ambient temperature follow the user’s set
point. The system consists of a number of sub modules. Each
one is designed in the block diagram level, and then converted
to a VHDL file [1]. The overall system or better known as the
top level design will be a collection of all of the above-
mentioned modules.
The password is a 4-digit pin number applied via a keypad
that will communicate through infrared radiation with an FPGA
development board. The development board used in this paper
is the Digilent Spartan-3 prototyping board. It is equipped with
a Xilinx XC3S200 FGA.
Besides using the keypad to insert the PIN number, it is also
used to insert the temperature set point. The temperature is
measured using the AD595 thermocouple amplifier [2]. It is then
converted to a digital value using an 8-bit analog to digital
converter. The digitized temperature is then sent to the FPGA
chip to compare it with the user’s set point. The air
condition/furnace control command is then generated by the
FPGA chip. The board is also equipped with 4-digit 7- segment
display which is used to display both the set point and the
ambient temperature.
II. ALGORITHMIC STATE MACHINES
future) is, mainly dependent on the experience (knowing the
past) and the current input applied (knowing the present). The
history is saved in the memory units of the ASM (flip flops or
registers). The present is represented by the current inputs
applied. The future is next state to be decided by the ASM itself.
ASMs consist of state variables, inputs, and outputs. A state
machine accepts a sequence of inputs. Each input generates a
new internal state that is a function of the input and the previous
state. Each input also generates an output. Finite state machines
are state machines whose state variables, inputs, and outputs
can be enumerated. For example, an oil refinery can be modeled
by a state machine. A traffic signal can be modeled by a finite
state machine.
Finite state machines are of theoretic importance to
computer science because they can model many of the concepts
of interest in the discipline. Finite state machines are also called
finite automata.
III. SYSTEM ARCHITECTURE
Fig.1 shows the overall system functional units. In the center,
there is the ASM module and its supportive units. They are all
implemented using VHDL code. The code is compiled and
converted into a binary file. The file is sent to XC3S1000 chip
which is already mounted on a Digilent Spartan 3-1000
development board. The seven segment display and the LED
array are all mounted on the development board. They provide
us with the compulsory information about the ASM state
variables and input/output signal status for diagnosis purposes.
It is possible throughout the design and testing processes that
the ASM gets stuck in one of its sequential states. To identify
the said problem, we should have a good state tracking method
to get a clue about the condition(s) that are forcing the state
machine to get locked at a certain state. The development board
is also equipped with a number of toggle switches that supports
us to apply test signals to imitate certain input(s) or feedback
variable(s) [9]. The external infrared signal is created by any
infrared data transmitter. In this paper, the information source
selected is the SONY 15-2113 remote control unit. It is the
board information supply and the tool through which a user
sends information to the system (PIN code and temperature
setting).

The concept of algorithmic state machine [3] [4] [5] is

originally based on the fact of a circuit that remembers the
history. Remembering history is usually, useful in deciding the
future. The ability to make a right decision (knowing the

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Toggle
Switches
Temperatu 7-
re Sensor segment
Display

ASM and LED

7- its array
segment Supportive
Display
Modules
AC/Furnac
e
Control
Remote
IR replays
Control
Sensor
Unit

Fig. 1: ASM based IR code recognizer block diagram.

IV. SYSTEM MODULES

In this section we list the system modules with a description
for each. Four ASMs units.
a) Main_ASM module: This is the master state machine
controller. It controls the rest of the system constituents. It gives
commands and monitors the status of every module in the
system. Fig. 2 shows the state diagram of this unit. The
controller consists of 10 states. The system has one major reset
button to initialize the whole system.
State S1: In this state, MAIN_ASM, waits for a strobe from
the infrared code detector state machine module (ASM3).
While in this state, MAIN_ASM activates INS_PW signal
(insert password) to the user. It also resets all the supportive
counters. They are CNT (digit counter) and WRNG_CNT
(wrong password trial counter). It also selects the display mode
for the system (information on the four 7 segment displays).
MAIN_ASM stays in this state as long as the strobe signal
(STRB) is still low. This is an indication that ASM3 module is
still busy detecting and decoding the infrared signal it has
received from the remote control unit.
State S3: MAIN_ASM transfers to this state from S1 after
ASM3 activates the strobe signal STRB. This happens when
ASM3 finishes identifying the currently pressed remote control Fig. 2: Main controller ASM chart.
button. This transfer is accompanied by incrementing the digit
count CNT by 1. In this state, MAIN_ASM checks whether it
has received all the PIN code digits. If yes, it moves to state S5 State S7: MAIN_ASM gets into this state, every time a
and starts analyzing the received PIN code, otherwise, it moves wrong password is inserted. The wrong password counter
to state S4 and wait for the next digit. (WRNG_CNT) is incremented by 1 via a conditional output
State S4: In this state, MAIN_ASM waits for the next PIN signal (WRNG_CNT<=WRNG_CNT+1). Depending on the
digit and monitors SRTB signal. It stays in this state as long as value of WRNG_CNT counter, the next state is decided. It is S8
STRB signal is low (ASM3 is busy decoding the pressed remote if the counter exceeds the accepted limit of number of trials.
button). It moves to S3 otherwise. Otherwise, it is S3 to let the user give another attempt.
State S5: It is the state of comparing the inserted password State S8: It is the state of 4 failed password attempts. The
with that stored in the system memory (password register). The FPGA gets into hibernation for a relatively long period of time
MAIN_ASM transfers to state S7 if the two passwords match. (about 1 minute). During this period of time, the user will not
It transfers to state S6 otherwise. State S6: MAIN_ASM stays be able to try another password. It is a waiting state. After the
in this state for a while. A delay timer is initialized via a delay is over, MAIN_ASM proceeds towards S3 again.
conditional output signal, DELAY1<=X"00000000". In this State S9: MAIN_ASM gets into this state after a correct
state, a good password signal is activated and displayed to the password insertion. It is the state where temperature set point is
user (GD_PW<=’1’). The next state is state S9. selected by the user. The temperature set point is a two digit
BCD number. State S9 converts the said number into its
equivalent binary one. This is done by multiplying the tens digit

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by 10 then adding it to the ones digit. This state also resets the
timer counter DELAY1to 0.
State S10: This state is continuation to state S9. Here, the user
will be given few minutes to change the temperature setting
before being asked to insert the password again. This is possible
as long as ASM_MAIN is in state S10. As DELAY1 reaches its
count end, ASM_MAIN transfers back to state S1. The whole
system, then, would function as a pure temperature controller.
Any attempt to change the temperature setting, would be
preceded by password insertion and checking.
b) ADC_CONT module: This module controls and
synchronizes the operations of the analog to digital converter
unite AD7013 [6] [10]. Fig. 3 shows the state diagram of
ADC_CONT module. The state machine here is not a slave
machine. This means that is does not follow the commands of
another one. It is designed in such a way to make the ADC work
continuously without any break or halt.
State S5: It is the default state. Here ADC_CONT waits for
predefined period of time before giving the conversion order.
State S6: ADC_CONT reaches this state after the waiting
period of S5 is over (TMR counter reaches its full count). In this
state, the timer TMR is initialized to 0.
State S1: In this state, the “start conversion” command is
issued (activated by assorting signal CONV for certain period
of time equal to the count PRD2). Also the counter TMR is
incremented every clock cycle. Once the count exceeds PRD2
value, the ADC_CONT transfers to state S7.
State S7: CONV Signal is set to 0 (inactive). The CONV
signal level transfer from 0 in S6 to 1 in S1 and back to 0 in S7
initiates the conversion of the analog signal currently applied to
the ADC. The chip select (CS) and Read (RD) signals are Fig. 3: Main controller ASM chart.
deactivated in states S5, S6, S1, S7, S3 and S4 to prevent reading
any immature or invalid data from the ADC unit. This is very important to make the conversion on line and in a
State S2: In this state the ADC unit gets engaged with the real time manner.
conversion process. ADC_CONT keeps checking the BUSY c) ASM _TMP_CNTRL module: This is the third state
signal of the ADC unit. No reading is allowed in this state. Once machine module in the system. It is responsible for controlling
the ADC unit finishes the conversion, it deactivates the BUSY the furnace and the air condition units (govern these units by
signal. This causes ADC_CONT to transfer to state D1 (delay issuing appropriate ON and OFF commands). The control
state and stays there for 5 clock cycles). Then it transfers to state process is completely automatic. No man interaction is needed
S3. to change the system stetting between summer and winter
State S3: In this state ADC_CONT reads the converted data seasons. Traditional temperature controllers usually require
and saves it in its internal register DATA. This is the only that such an interaction. It is a button or switch to select the current
allows activation for the RD and CS signals. appliance to be controlled (A/C or furnace).
State S4: it is the last state in the sequence of this state Figure 4 shows the state distribution and their corresponding
machine. Here the contents of the internal register DATA are actions for ASM_TEMP_CNTRL module.
transferred to the ADC_CONT port and made available for the State S1: It is the initial state in this module. This machine is
other system constituents. ADC_CONT returns back to its initialized by the main reset button. One can notice that both of
initial state S5 to start another conversion process. It is well the furnace HT and the Air condition (A/C) are turned off. The
noticed that ADC_CONT is a free running unit. This means that machine stays in this state as long as the current temperature
it does not need a command from a higher hierarchy to start or and the temperature set point are the same. If the temperature
finalize job. All this is done automatically through the state drops below the set point, the machine jumps to state S3.
flow of the machine itself.

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Fig. 4: Temperature controller state machine ASM chart.
State S3: In this state, the heat signal (HT) is activated to turn
the furnace on, whereas AC signal is deactivated to turn the A/C
off. The machine would stay in this state as long as the
measured temperature is less than the set point value. Once the
furnace is turned on, it will cause the temperature to rise with
time.
State S4: Once the temperature rises beyond the set point, the
machine transfers to state S4. In this state both of HT and AC
signals are deactivated. With time, the temperature would drop
if the current season is winter. This would cause the machine to
jump back to sate S3. HT signal is reactivated again. This
switching between S3 and S4 continues for cold weather
conditions. As the season turns gradually towards spring and
then towards summer, we will reach the case where the
temperature keeps rising even when the furnace is off. This
usually happens during season switching from cold to hot.
V. CONCLUSION AND FUTURE WORK
When this idea was first discovered and researched as a
project, it was all too good to be true. The first thought was,
“Hasn’t this been done before” and the answer is no, not really.
There are similar things out there but nothing that is mass
produced and nothing with all the features that this thermostat
can include. Secondly, it seems like a relatively simple idea,
maybe too simple. Looking deeper, the VHDL programming
is actually a very complex final product. There was much
research to do on hardware, and new circuits to be designed.
This project required hours upon hours of writing program code
as well as testing. The scariest part was that the last thing we
could do is attempt to interface our circuit with a real home
climate control. The password protected thermostat has all the
necessary elements of a great senior project.
There was a lot of program code involved in this project, and
the only way to keep organized was through the use of
flowcharts and block diagrams. The code was written in
CoDIT’19 | Paris, France - April 23-26, 2019
functional blocks but piecing them together and understand
how they all work is at least as important as being able to write
the code itself. A large project like this teaches the importance
of planning, diagramming and commenting, as well as
thoroughly testing every step of the way. Had this not been
done at any stage, it would have been easy to lose track of where
we were or make it very difficult to debug any problems that
came up. Because of the use of functional block coding, we
could test and debug each function separately making it easy to
find and fix problems as they arose. This project was a ton of
work, but it was also very rewarding. As an engineer, there is
nothing better than designing, creating, and showing off a new
product. It is a relief but mostly a feeling of accomplishment
to achieve a working prototype like this.
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