International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)
Design of Circuit for Battery Charging of Electric
Vehicles
From Renewable Energy Sources
Abhinav Bhattacharjee, Sangit Saha
P.G. students: Power Electronics and Drives
VIT University
Vellore, Tamil Nadu, India
abhinav.joydeep2015@vit.ac.in, sangit.saha2015@vit.ac.in
Abstract—Electric vehicles and plug-in hybrid electric
vehicles are two concepts that are gaining popularity in order to
reduce our dependence on fossil fuels. In this paper, a full bridge,
current fed, interleaved, isolated DC-DC converter is proposed
for battery charging of electric vehicles from solar PV or fuel
cells. It boosts voltage of around 36 V to 270 V. Interleaving leads
to lesser input current ripple, a factor crucial for sources like
solar PVs and fuel cells and lesser stress on switches. The concept
of soft switching is used to reduce switching losses. Simulation
results are presented for a power level of 3.45 kW. A scaled
down, 200 W hardware model of the circuit was built and tested.
A closed loop feedback system was also designed using k factor
method to provide constant output voltage.
Keywords— electric, vehicle, hybrid, battery, charger, micro
grid, renewable, energy
I. INTRODUCTION
Electric vehicles and plug-in hybrid electric vehicles are
mostly charged from the domestic electricity supply available
from the grid. There are two kinds of power sockets in India,
ones that can supply 5 A and ones which can give 15 A
current. Using the 5 A charging socket, it’s possible to get a
charging power of 1.2 kW considering a voltage of 230 V.
This is known as Level 1 charging. Similarly, using a 15 A
socket, the charging power is 3.45 kW and this is known as
Level 2 charging. Over the last few years, a new charging
technology has been developed called DC fast charging. In
DC fast charging, DC power is directly fed to the vehicle and
to the batteries. These DC fast charging stations can fully
charge the batteries of most electric vehicles in less than half
an hour. All these DC fast charging standards combined are
known as Level 3 charging.
In the near future, DC micro grids will start to get more
popular and we can expect homes or colonies to have their
own DC micro grid which is fed from renewable energy
sources. [1] These grids will primarily be low voltage grids. In
this scenario, we will need a battery charger for that can
charge the vehicle when it is parked at home, from the low
voltage DC micro grid. The proposed converter tackles this
challenge. The battery voltage of most existing electric
978-1-5386-1887-5/17/$31.00 ©2017 IEEE
330
Elangovan D, Arunkumar G
Associate Professors: Energy and Power Electronics Dept.
VIT University
Vellore, Tamil Nadu, India
elangovan.devaraj@vit.ac.in, g.arunkumar@vit.ac.in
vehicles and plug-in hybrid electric vehicles ranges from
around 200 V to 360 V. For the converter proposed in the
paper, an intermediate charging voltage of 270 V is assumed.
A low input voltage of 36 V is taken, considering the worst
case scenario. A power level that corresponds with existing
Level 2 charging system is taken. Therefore our basic
objective is to design a DC-DC converter that will boost 36 V
to 270 V at a power level of 3.45 kW.
Since the converter has a high voltage gain, the first pre
requisite that it must have is electrical isolation between the
input and output sides. There are many isolated DC-DC
converters to choose from. The simplest one is the flyback
converter which is basically a buck boost converter with a
transformer for isolation. [2] However, this converter is not
suitable for heavy loads because it has a single switch which is
put under too much stress and hence, doesn’t perform as well
as desired. The next two topologies are of half bridge boost
converter [3] and full bridge boost converter [4]. These exist
in voltage fed and current fed versions. The difference being
the presence of an input inductor in the current fed version
which is absent in the voltage fed counterpart. The next
topology is of interleaved converters. [5] Interleaving
basically means giving the input current additional parallel
paths so that the entire current doesn’t pass through a single
inductor and switch.
Considering the positive and negative aspects of all these
topologies and keeping in mind the needs of our application,
we can zero in on the topology of choice. The basic
requirements of our application are:
• High voltage gain
• Electrical isolation between the input and output side
• Low input current ripple
• High power density
• Good efficiency
Keeping in mind the above factors, the topology that
would suit the application best would be the interleaved,
current fed, full bridge, isolated DC-DC converter. The
schematic diagram of the converter is shown in Fig. 1. Since
the input voltage of the converter is less and power level is
 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)

pretty high, the input current will be close to 100 A. second leg are shorted. Therefore input inductor L2 gets
Interleaving helps in this large input current getting shared charged and there is no conduction in the transformer or the
between the two sets of input side inverters. By operating the diode bridge rectifier of the second leg. The load is supplied
two inverters with a phase shift of 90 degrees, we can cancel from the rectifier of the first leg and the capacitor Co2.
out the ripple in the input currents of the two inverters which
is a crucial feature when used with fuel cell or solar panel as
input. [6] [7] Therefore, sum total input current has negligible
ripple content. The output of the inverters is given to two high
frequency transformers which provide the electrical isolation
of the output and input sides. The output of the transformers is
connected to two full bridge diode rectifiers connected in
series. The load is connected across there two rectifiers. Since
the rectifiers are in series, the overall voltage gain is doubled
compared to a non-interleaved full bridge converter. The
magnetic components, i.e. the inductors and the transformers
add the major part of bulk to the circuit. In order to achieve
high power density, it is crucial that magnetic size is kept low
without sacrificing on the power level. This is possible only
when the circuit is operated at a high switching frequency.
Therefore, a high switching frequency of 100 kHz is selected
for the circuit. Switching losses play a major role in Fig. 2. Mode 1 conduction path
determining the overall efficiency of the circuit. To minimize
switching losses, the concept of soft switching is used and
zero current switching is implemented for all the switches.
Hence as we can see, the choice of converter suits the
application well.

Fig. 3. Mode 2 conduction path

Fig. 1. Illustration of the proposed converter

II. MODELING OF THE CONVERTER

There are four basic modes of operation of the converter.
There are some sub modes which illustrate the zero current
switching process in detail which will be discussed later. Fig.
2 shows the first mode in which all the 4 switches of the first
leg are conducting, thereby charging the input inductor L1.
Since the source is shorted across the inductor, the transformer
has zero current flowing through it and the load is supplied by
capacitor Co1 and the second rectifier. At the same time,
switches M5 and M8 of the second leg are conducting because Fig. 4. Mode 3 conduction path
the two inverters are operated with a phase shift of 90 degrees.
The non-conducting paths are shown dotted. Fig. 4 shows the third mode of conduction. Here again,
like the first mode, all the switches of the first leg are
The second mode of operation is shown in Fig. 3. This conducting while switches M6 and M7 of the second leg are
mode is vice-versa of the first mode. In this switches M1 and conducting. Therefore it is similar to Mode 1 except that the
M4 are conducting in the first leg while all the switches of the

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 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)
current direction in the transformer and rectifier of the second
leg are reversed.
Fig. 5. Mode 4 conduction path
Fig. 5 shows the fourth mode of conduction. This is very
similar to the second mode. The second leg has all the
switches on while the first leg feeds the load via switches M2
and M3 which are on. The conduction path is illustrated in fig.
The theoretical waveforms of the gate pulses for the four
diagonal sets of switches of the two inverters, the overall input
current ‘Iin’, the input current of the two legs ILin1 and ILin2 are
shown in fig. It is seen that by using a 90o phase shift between
the two input legs, the ripple in the input currents of the two
legs can be made to almost cancel each other. Perfect ripple
cancellation happens for a duty cycle of 75%. For any value of
duty cycle other than this, the magnitude of ripple is reduced
but it cannot be eliminated totally.
The output voltage equation of the converter is:
(1)
Where, Vg: input voltage, Vo: output voltage, n: transformer
turns ratio, D: duty cycle
For our circuit, Vo = 270 V, Vg = 39.8 V, n = 2. Therefore
substituting the above values in equation, we can get the duty
cycle ‘D’ which comes to:
Equation to find value of input inductor is given by:
(2)
Where, L: inductor value, ǻIL: percentage ripple current of
average inductor current, f: frequency
For this circuit, D = 0.7051, f = 100 kHz, Vg = 39.8 and ǻIL
can be assumed as 1% of average value of inductor current.
Hence we get ‘L’ value as:
The equation to find value of output capacitor is given by:
332
(3)
Where, R: Load resistance, ǻVO: Output voltage ripple
For our circuit, we have R = 22.09, VO = 270 V, D = 0.7051, f
= 100 kHz and we can assume ǻVO = 2V. Therefore, ‘C’
value is given by:
Next, we will describe the soft switching process in more
detail. There are two types of soft switching processes. One is
zero current switching, known as ZCS in short which happens
when the switch is turned off. The second is zero voltage
switching, known as ZVS which happens when the switch is
turned on. The basic principle behind both these processes is
that there should be no overlap between current through the
switch and voltage across the switch when switching transition
happens. For this circuit, zero current switching is used
because it is simple to execute and requires lesser extra
components. The transformers used are designed such that
their leakage inductance can be used along with an external
capacitor connected across the primary side of the transformer
to make the LC tank circuit. This helps in saving space as we
don’t need to connect two additional inductors in the circuit.
Fig. 7 shows some voltage and current waveforms that
are important to understand the soft switching process. It
shows the gate pulse of the switch whose behavior during
switching we shall study, the current through the switch and
the voltage across the switch. It also shows the current through
the transformer leakage inductance and voltage across the
capacitor connected across the primary of the transformer.
This helps to study the behavior of the LC tank circuit. The
gate pulse given to the opposite set of switches is also added
for reference. For the sake of simplicity, only one leg of the
circuit is considered to study the soft switching process. The
operation of the other leg remains the same.
The process starts at time t=t1. The first stage is between
time t1 and t2 when gate pulse is given to the second set of
switches which leads to decrease in the leakage inductance
current of the transformer from its steady state value iin to zero
by the end of the stage. The conduction paths in the first stage
between time t1 and t2 is shown in Fig. 6. The non-conducting
paths are shown dotted.
Fig. 6. Stage 1 conduction path
 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)
Fig. 7. Theoretical waveforms to illustrate the soft switching process
The second stage is when the capacitor connected across
the transformer starts to discharge and the direction of ilk is
reversed. By the end of this stage, the switch current through
M1 and M4 also reaches zero. The conduction paths are
shown in Fig. 8.
Fig. 8. Stage 2 conduction path
In Stage three, ilk reaches the maximum negative value. By
the end of this stage, the capacitor voltage VCk reaches zero.
The current through switch M1 becomes negative and
conduction happens through the body diode of the switch. The
conduction paths are shown in Fig. 9.
333
Fig. 9. Stage 3 conduction path
Stage 4 is of a very small duration where the only
significant occurrence is that by the end of this stage at t=t5,
the gate pulses to switches M1 and M4 are taken off. By the
end of stage five at t-t6, the capacitor voltage VCk settles at its
negative peak and the switch current of M1 and M4 settle at
zero. The current through the leakage inductance ilk settles at
the input current iin and at the end of this stage, the body
diodes of switches M1 and M4 stop conducting and the switch
voltage builds up across them. Thus completing the process of
zero current switching. The conduction path of stage 4 and 5
are the same and are shown in Fig. 10.
Fig. 10. Stage 4 and stage 5 conduction path
Fig. 11 shows the conduction path for stage 6. In this
stage, the soft switching process is complete and switches M2
and M3 have taken over the input current from switches M1
and M4. This stage continues till the next cycle which begins
at t=t7 when switches M1 and M4 are turned on again and the
whole process repeats.
Fig. 11. Stage 6 conduction path
III. SIMULATION RESULTS
Simulation of the circuit was done using PSIM version
9.1.1 software. The simulation was done for full designed
power level of the circuit that is 3.45 kW. First, testing was
done using a normal battery of 36 V and output was verified.
Later simulation was done using a solar panel as input. The
specification sheet of the solar panel selected is shown in fig.
The solar panel has the following specifications:
• Brand and Model: Sun Power 215 Solar Panel
• Maximum Power: 215 W
• VMPP: 39.8 V
 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)

• IMPP: 5.40 A 50
Input Voltage

• VOC: 48.3 V 40

30

• ISC: 5.80 A 20

10

To meet the power demand of the circuit, we need to 0

calculate the number of panels that should be connected in 100

Input Current

series and parallel. Since the input voltage required is 36 V, 80

one panel in series is enough to satisfy the voltage. Now, the

60

40

input current of the circuit would be the power level divided 20

by input voltage. This comes out to be: 3450/39.8 = 86.01 A. 0

0.02 0.04 0.06 0.08 0.1

Therefore we need to connect 16 panels in parallel.

Time (s)

Fig. 14. Input voltage and current

Since the version of PSIM that was used didn’t have
battery models, the simulations were done with resistive load
which was specified according to the charging power that the Output Voltage
300
circuit was designed for. The simulation circuit designed in 250

PSIM is shown below in Fig. 12. 200

150

Leg1InputCurrent = 43.3452
100
InputCurrent = 87.43948 OutputCurrent = 12.45934
SwitchCurrent = 42.28716
235uH 50
A A A A
V
SwitchVoltage = 0.00042287 0

0.5uH
Output Current
20
100uF 1.2uF 20uF
15
InputVoltage = 39.28078

10

5
Leg2InputCurrent = 44.07993
235uH 22.09
A 0
OutputVoltage = 275.22689
0.02 0.04 0.06 0.08 0.1
Time (s)
0.5uH

1.2uF 20uF
Fig. 15. Output voltage and current

Fig. 16 shows the gate pulse applied to a switch, the

Fig. 12. Simulation circuit in PSIM current through it and the voltage across it. By observing the
waveforms, it is clear that zero current switching is obtained
as the switch voltage doesn’t build up before the switch
Fig. 13 shows the gate pulses given to the top and bottom current goes to zero. Therefore, there is no overlap between
legs of the switches. The first pulse corresponds to the pulses the switch current and voltage when the switch turns off and
given to switches M1 and M4. The second pulse is the one switching losses are considerably reduced.
given to switches M2 and M3. This is having a 180 degree
phase from the first pulse. Similarly, the third pulse is given to Switch Pulse

switches M5 and M8 and is having a 90 degree phase shift 1

0.8
0.6
from the first pulse to enhance ripple cancellation in the input 0.4
0.2

current. The fourth pulse is the one given to switches M6 and 0

M7 and has a 180 degree phase shift from the third pulse.
Switch Current
80

40
Switch 1 Pulse
0
0.8
-40
0.4
0 Switch Voltage
Switch 2 Pulse 80
40
0.8
0
0.4
0 0.01771 0.01772 0.01773
Switch 5 Pulse
Time (s)

0.8
0.4
Fig. 16. Switch pulse, switch current and switch voltage in simulation
0

0.8
Switch 6 Pulse
One of the main benefits of going for the interleaved
0.4
0 topology is the input current ripple reduction which an
0.01222 0.01223 0.01224 0.01225
Time (s)
important necessity for using renewable energy sources like
Fig. 13. Gate pulses solar PV or fuel cells as source. This is shown in Fig. 17. The
total input current is shown along with the input current of the
two legs. It can be seen that the ripple of both the legs is
Fig. 14 shows the input voltage and current of the effectively cancelled out. The overall input current has an
converter. The output voltage and current of the converter are exponential wave shape rather than a linearly rising and falling
shown in Fig. 15. It is seen that the voltage settles at a steady one because there is an input capacitor which charges and
state value of §270 V quickly with very little ripple. discharges.

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 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)

87.4492
Overall Input Current
about the voltage and current overshoots while starting, turn
on and turn off times. The maximum values of the parameters
87.449

87.4488

87.4486

87.4484
are seen on the screenshot too.
Leg 1 Input Current

43.8

43.6

43.4
Leg 2 Input Current
44

43.8

43.6

43.4
0.01295 0.012952 0.012954 0.012956 0.012958 0.01296
Time (s)

Fig. 17. Input current ripple cancellation

The various simulation parameters have been tabulated in

Table I.
TABLE I. SIMULATION PARAMETERS
Parameter Value
Input Voltage (Panel VMPP) 39.8
Output Voltage 275 V
Power 3.45 kW Fig. 18. Full hardware circuit setup in lab for testing
Input Inductors 235 μH
Input Capacitor 100 μF
Output Capacitor 20 μF
Equivalent Load Resistance 22 Ÿ
Transformer Turns Ratio 1:2

IV. HARDWARE RESULTS

A scaled down hardware prototype of the circuit having a
power level of 200 W was built and tested due to lack of
facilities and equipment available in the lab for high power
testing. Simulation was done again with the reduced power
level and the maximum current and voltage that each
component was subjected to was noted. Components were
Fig. 19. Basic input and output parameters for turn on and off cycle
selected after considering a suitable factor of safety over these
current and voltage values. The circuit was built on a plywood Fig. 20 shows the same basic input and output parameters
base by screwing and bolting the various components on the but only the steady state values of the same. This is used to
base. calculate the efficiency of the converter. It is seen that an input
voltage of 38 V produces an output voltage of 269 V. The
Gate pulses were designed using Simulink in MATLAB input current of the converter is 5.3 A while the output current
and generated using dSpace. The pulses were fed to the is 680 mA.
switches using driver board having Opto-isolators. Lamp load
having the required equivalent resistance for 200 W power
level was used. A total of 4 bulbs having a power rating of 60
W at 230 V were used with two bulbs connected in series and
two in parallel. Input to the circuit was given via a
programmable DC supply unit. The waveforms and results
were viewed on a MSO (Mixed Storage Oscilloscope). One
programmable DC supply unit was used to give the input
voltage for the converter while another was used to provide
the biasing voltage for the driver board IC. Two current probes
and two voltage probes were used to measure the different
parameters and observe the waveforms. Fig. 18 shows the
entire hardware test setup inside the lab.
The duty cycle of the gate pulses is 70% and frequency is Fig. 20. Basic input and output parameters in steady state
100 kHz. The basic input and output parameters of voltage and The switch pulse, current and voltage are shown in Fig. 21.
current are shown in Fig. 19. This figure shows the entire This clearly illustrates the zero current switching obtained. It
cycle of turning of the converter, letting it run in steady state can be seen that the switch voltages rises only when switch
for some time and then turning it off. It gives a clear idea current is zero and hence there is no overlap between voltage

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 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)

and current, consequently no switching loss when the switch is
turned off. However, a slight issue that occurred was that the
body diode of the switch wasn’t able to carry the entire
negative current in the intermediate stages of soft switching
and as a result soft spikes in voltage were noted. Therefore it
is recommended to connect few external diodes in anti-parallel
with each switch so as to enable it to carry the negative
current.
VGS
ZCS
IDS
VDS
that will keep the output voltage constant irrespective of the
variations in the input voltage. The controller is developed
using the k factor method and by taking help of the SmartCtrl
feature of PSIM.
The first step in designing the controller is to choose the
desired bandwidth and phase margin. The guidelines for this
are that bandwidth should be 1/10th or lesser of switching
frequency while a phase margin of 30o to 60o is desirable.
Next, we need to use the get the bode plot of the open loop
circuit. We can make use of the AC Sweep block available in
PSIM to do this job. In the AC Sweep block, we can set the
frequency range for which we want the Bode plot and the
amplitude of the perturbation signal.
Once we put in these values and run the simulation, we get
the bode plot of the open loop circuit. Next, we need to find
the phase of the existing open loop circuit, known as ĭsys from
the bode plot. The Bode plot obtained is shown in Fig. 22. ĭsys
is the angle that corresponds to the crossover frequency on the
phase plot. For this circuit, a crossover frequency of 250 Hz is
selected. It can be seen that ĭsys obtained is -135o.

Fig. 21. Switch pulse, switch current and switch voltage in hardware Next, we need to calculate the phase boost required to be
provided by the controller, known as ĭboost. This is given by
The details of all the hardware components used are the formula:
tabulated below in Table II.
ĭboost = Phase margin desired - ĭsys – 90o (4)
amp(Vo)

TABLE II. HARDWARE PARAMETERS 0

-10
-20
Parameter/Component Value/Rating -30

Input Voltage 39.8 V -40

-50
Output Voltage 270 V -60

Power 200 W phase(Vo)

Input Inductor 10 mH / 10 A 0
-50
-100
Output Capacitor 20 μF / 1 kV -150
-200
Equivalent Load Resistance 400 Ÿ -250
-300

Transformer 1 : 2 turns ratio, 100 V, 60 A / -350

100 500 1000 5000 10000
200 V, 30 A Frequency (Hz)

Transformer Leakage Inductance 0.5 μH
Switch IRF640 / 200 V, 18 A
Diode MUR1560 / 600 V, 15 A
Opto-coupler IC HPCL 3120
As can be seen from the readings obtained in Fig, the input
power to the circuit is: 38 V * 5.3 A = 201.4 W while the
output power is 269 V * 0.680 A = 182.9 W. Therefore, we
get an overall efficiency figure of: 182.9/201.4 = 91%.
To conclude, satisfactory results have been obtained in the
hardware model testing. The efficiency obtained is decent and
will rise further when the circuit is mounted on a PCB instead
of the crude plywood board. There were no major issues noted
while testing. The circuit can easily be used for higher power
applications by using the right components.
V. CLOSED LOOP FEEDBACK SYSTEM
In order to make the converter suitable for real world
applications, it needs to possess certain additional features.
For this circuit, a closed loop voltage controller is developed
Fig. 22. Bode plot of the open loop system
The 90o term comes because every controller, be it type 1,
type 2 or type 3 has a pole at origin. For this circuit, we select
a bandwidth of 250 Hz, ĭsys = 135o and a phase margin of 60o.
Therefore, the ĭboost required can be given by 105o. Since
ĭboost required is more than 90o, we need a type 3 controller.
The controller is designed using the SmartCtrl feature of
PSIM. The Bode plot obtained is imported into Smartctrl.
Once we select the switching frequency and desired output
voltage, a window opens where we need to select the type of
controller, the type of voltage sensor and the phase margin and
bandwidth required. Once we do this, SmartCtrl automatically
designs the Op-Amp based controller for the given parameters.
The controller obtained from SmartCtrl and connected to the
circuit to complete the closed loop feedback system for
constant voltage is shown in Fig. 23. The AC sweep setup
used to perturb the duty cycle to get the Bode plot is also seen.

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 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)

InputCurrent Leg1InputCurrent
OutputCurrent
SwitchCurrent ac
235uH
A A A A
V
SwitchVoltage
Vg1 Vg2 Input Voltage
0.5uH
50
1.2uF 48
46
V
Vg2 Vg1 44
Leg2InputCurrent 42
235uH 22.09
Vo
A 40
OutputVoltage
Vg2 Vg1
0.5uH
Output Voltage

300
1.2uF
250
200
150
Vg1 Vg2 100
Type-3 controller
50
From power
circuit voltage
C3 0
File -50
Vg1 R1 C1
AC
Sweep
Ra
R2 C2 0 0.02 0.04 0.06 0.08 0.1
Vg2
0.97*Vp Time (s)
0 Vg2
R11 R Q
Rb
Vref fsw S Q Vg1
To switch Fig. 26. Output voltage with 45 V input voltage
controller
fsw

VI. CONCLUSION
Fig. 23. Closed loop voltage controller designed in PSIM This paper focuses on providing solutions for the need of
With this, the constant voltage closed loop feedback integrating renewable energy resources in our day to day and
system is ready to be tested. First we test it with the rated reducing our dependence on fossil fuels. The targeted area is
input voltage. The results can be seen in Fig. 24. It is seen that the transportation sector where the aim is to use solar PV and
the output voltage is almost constant barring a small ripple. fuel cells to provide energy. A DC-DC converter is designed
Also it is noted that the voltage is limited to 270 V and doesn’t which can be used for battery charging of electric vehicles and
exceed it. Next we test the circuit with an input voltage lesser plug-in hybrid electric vehicles from a low voltage solar panel
than the rated voltage. This condition can be expected often if layout or fuel cells. It is seen that the important requirements
a solar panel is used to provide the input voltage. In case of of this system are met by the proposed converter. Satisfactory
cloudiness in the sky, the voltage output of the solar panel can results were obtained in simulation of the circuit for the full
reduce. In this case, the converter should be able to adjust the rated power of 3.45 kW with a solar panel as input. Testing of
duty cycle such that the output voltage remains as desired. It is the hardware prototype also gave good results with no major
seen in Fig. 25 that this is achieved. Now next, the converter is issues. An efficiency of 91% was obtained for the hardware
tested with an input voltage higher than rated voltage. This model which is very encouraging. Simulations of the type 3
condition can occur in case of any fault or during light load controller designed using the k factor method also gave
conditions. Fig. 26 shows the performance of the converter satisfactory results. As a continuation of the work, the closed
with 45 V input. It can be seen that the output voltage doesn’t loop voltage controller can be implemented and tested in
exceed 270 V in any case. hardware. This was not done due to paucity of time.
Input Voltage

40

30
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150
100
Electr. Power Appl, pp. 643 –656.
50
0 [7] Woojin Choi (2004). New approaches to improve the performance of the
-50
PEM based fuel cell power systems, A&M university, Texas, pp. 3,17,
0 0.02 0.04
Time (s)
0.06 0.08 0.1
22.
Fig. 25. Output voltage with 35 V input voltage

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