2008 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO.
5, MAY 2016
Design and Implementation of High-Speed All-Pass Transformation-Based
Variable Digital Filters by Breaking the Dependence
of Operating Frequency on Filter Order
Abhishek Ambede and A. P. Vinod
Abstract— All-pass transformation (APT)-based variable digital
filters (VDFs), also known as frequency warped VDFs, are typically
used in various audio signal-processing applications. In an APT-based
VDF, all-pass filter structures of appropriate order are used to replace
the delay elements in a prototype filter structure. The resultant filter can
provide variable frequency responses with unabridged control over cutoff
frequencies on the fly, without updating the filter coefficients. In this
brief, we briefly review the first- and second-order APT-based VDFs
along with their hardware implementation architectures, and provide
generalized design procedures to realize them as per required specifica-
tions. We also propose the modified pipelined hardware implementation
architectures for both the first- and second-order APT-based VDFs.
Field-programmable gate array implementation results of different
first- and second-order APT-based VDF designs for both nonpipelined
and pipelined implementation architectures are presented. An analysis
of the results shows that the proposed pipelined implementation archi-
tectures result in high-speed VDFs, achieving high operating frequencies
that are independent of the prototype filter order, for both the first- and
second-order APT-based VDF designs.
Index Terms— All-pass transformation (APT), frequency
warping, pipelining, variable digital filter (VDF).
I. I NTRODUCTION
The design and implementation of digital filters for signal
processing applications has always been a major area of research.
To achieve hardware efficient and operationally flexible realizations
of digital filters, numerous research works have proposed digital
filters, which can provide variable frequency responses on the fly,
by controlling a small set of parameters. Such filters are termed
variable digital filters (VDFs). Table I presents a comparison of
different VDF design techniques proposed in the literature, which
provide control of cutoff frequency [1]–[12]. When low complexity
VDFs with unabridged control over cutoff frequency are desired,
the all-pass transformation (APT) technique is employed [10]. The
APT-based VDFs, also known as frequency warped VDFs, are widely
used in applications, such as audio equalization, the design of warped
adaptive filters and discrete Fourier transform-based filter banks, and
hearing aids [12]–[16]. Combination of the APT technique with
coefficient decimation techniques [2]–[4] to achieve low complexity
implementations of the first- and second-order APT-based VDFs was
recently proposed in [17] and [18].
In this brief, we present a brief review of the first- and second-order
APT-based VDFs along with their hardware implementation archi-
tectures. We provide generalized design procedures to design these
VDFs and propose the modified pipelined hardware implementation
architectures to achieve high-speed filter realizations. The hardware
implementation results obtained for multiple first- and second-order
Manuscript received May 16, 2015; revised August 16, 2015; accepted
September 25, 2015. Date of publication October 26, 2015; date of current
version April 19, 2016.
The authors are with the School of Computer Engineering, Nanyang
Technological University, Singapore 639798 (e-mail: abhishek7@e.ntu.edu.sg;
asvinod@ntu.edu.sg).
Digital Object Identifier 10.1109/TVLSI.2015.2485302
1063-8210 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
APT-based VDF designs using the conventional nonpipelined as well
as the proposed pipelined implementation architectures are presented
and analyzed. To the best of our knowledge, this is the first work
that addresses the implementation of high-speed APT-based VDFs.
The rest of this brief is organized as follows. Section II provides a
brief review of first- and second-order APT-based VDFs. Generalized
design procedures to realize first- and second-order APT-based VDFs
are provided in Section III. Section IV presents the design exam-
ples and the corresponding hardware implementation results for the
APT-based VDFs. The proposed pipelined implementation architec-
tures for realizing the first- and second-order APT-based VDFs are
also presented in Section IV along with the corresponding hardware
implementation results. Finally, the conclusion is drawn in Section V.
II. A LL -PASS T RANSFORMATION -BASED
VARIABLE D IGITAL F ILTERS
In an APT-based VDF, the all-pass filter structures of appropriate
order are used to replace the delay elements in a prototype filter archi-
tecture. The resultant filter can provide variable frequency responses
with unabridged control over cutoff frequency on the fly, without
updating the filter coefficients. Fig. 1(a) shows the generalized
implementation architecture of an APT-based VDF. It is a transposed
direct form a finite-impulse response filter architecture in which
every delay element is replaced by P(z), which denotes an all-pass
filter structure of appropriate order. To reduce the implementation
complexity of the VDF, only half of the symmetric prototype filter
coefficients are implemented.
A. First-Order APT-Based VDFs
In the first-order APT-based VDFs, the delay elements in a
prototype filter architecture are replaced by the first-order all-pass
filter structures [11]. If H (z), A(z), and G(z) are the z-domain
representations of a prototype filter, the first-order all-pass filter, and
the first-order warped version of H (z), respectively, then
G(z) = H (A(z)) (1)
where A(z) = [(z −1 − α)/(1 − α.z −1 )], |α| < 1 and is real.
Therefore, for the first-order APT-based VDFs, P(z) = A(z)
in Fig. 1(a). Fig. 1(b) shows the implementation architecture
for A(z) [11]. α is called the first-order warping coefficient, and
its value determines the cutoff frequency in the resultant frequency
responses. For a low-pass prototype filter, if −1 < α < 0, the
resultant cutoff frequencies are higher than the original cutoff
frequency. Similarly, for 0 < α < 1, the resultant cutoff frequencies
are lower than the original cutoff frequency. For α = 0, the original
frequency response of the prototype filter is obtained. Variable
high-pass frequency responses can be obtained using a low-pass
prototype filter by substituting P(z) = −A(z) in Fig. 1(a) [10].
Variable low-pass and high-pass frequency responses with the desired
cutoff frequencies can thus be obtained using the same low-pass
prototype filter.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 5, MAY 2016 2009

TABLE I
C OMPARISON OF VDF D ESIGN T ECHNIQUES

to determine cutoff frequencies in the resultant frequency responses.

Variable low-pass, high-pass, bandpass, and bandstop frequency
responses can all be obtained using a single low-pass prototype
filter. Variable bandstop frequency responses can be obtained by
substituting P(z) = −B(z) in Fig. 1(a) [10]. Unlike the first-order
APT-based VDFs, availability of two separately tunable parame-
ters (β2 and β3 ) in the second-order APT-based VDFs enables
independent control of both frequency edges in the bandpass
and bandstop frequency responses that are obtained. Thus, any
desired center frequency location and bandwidth can be achieved
in the variable frequency responses obtained using the second-order
APT-based VDFs.

III. D ESIGN P ROCEDURES

A. First-Order APT-Based VDFs
Step 1 (Prototype Filter Design): Design the prototype filter to
meet the desired frequency response specifications and obtain its
coefficients using a suitable filter design tool.
Step 2 (Implementation of VDF): Implement the prototype filter
coefficients using the hardware implementation architecture shown
in Fig. 1(a). Substitute P(z) blocks in Fig. 1(a) by the first-order
all-pass filter structure shown in Fig. 1(b).
Step 3 (Obtaining Variable Frequency Responses): Let f c1 be the
cutoff frequency of the prototype filter. If f c2 is the cutoff frequency
of the desired frequency response, the required value of α can be
computed using the formula
sin[( f c1 − f c2 )π/2]
α= . (3)
sin[( f c1 + f c2 )π/2]

B. Second-Order APT-Based VDFs

Step 1 (Prototype Filter Design): Design the prototype filter to
meet the desired frequency response specifications and obtain its
Fig. 1. (a) APT-based VDF: hardware implementation architecture.
(b) First-order all-pass filter: hardware implementation architecture. coefficients using a suitable filter design tool.
(c) Second-order all-pass filter: hardware implementation architecture. Step 2 (Implementation of VDF): Implement the prototype filter
coefficients using the hardware implementation architecture shown
B. Second-Order APT-Based VDFs in Fig. 1(a). Substitute P(z) blocks in Fig. 1(a) by the second-order
all-pass filter structure shown in Fig. 1(c).
For the second-order APT-based VDFs, every delay element Step 3 (Obtaining Variable Frequency Responses): If f c1 is the
in a prototype filter architecture is replaced by a second-order cutoff frequency of a low-pass prototype filter, fcl and fcu are the
all-pass filter structure [10]. If H (z), B(z), and F(z) are the z-domain lower and upper cutoff frequencies in the desired frequency response,
representations of a prototype filter, the second-order all-pass filter, the following formulas show the computation of the required values
and the second-order warped version of H (z), respectively, then of β2 and β3 :
F(z) = H (B(z)) (2) cos[( f cu + f cl )π/2]
k1 = (4)
where B(z) = [(z −2 −β2 z −1 +β3 )/(1 −β2 z −1 +β3 z −2 )], |β3 | < 1, cos[( f cu − f cl )π/2]
and both β2 and β3 are real. k2 = cot[( f cu − f cl )π/2] × tan[ f c1 π/2] (5)
Therefore, for the second-order APT-based VDFs, P(z) = B(z) 2k1 k2
β2 = (6)
in Fig. 1(a). Fig. 1(c) shows the implementation architec- k2 + 1
ture for B(z) [11]. β2 and β3 are called the second-order k2 − 1
β3 = . (7)
warping coefficients, and their values can be independently varied k2 + 1
2010 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 5, MAY 2016
Fig. 2. (a) Variable low-pass frequency responses obtained using the
first-order APT-based VDF. (b) Variable bandpass frequency responses
obtained using the second-order APT-based VDF.
IV. D ESIGN E XAMPLES
A. Illustrative Example
The flexibility of first- and second-order APT-based VDFs to
provide variable frequency responses with unabridged control over
cutoff frequency is illustrated in this section with the help of a design
example.
Let the desired passband and stopband peak ripple specifications
be 0.05 and −45 dB, respectively. Using the MATLAB filter design
tool, two half-band low-pass prototype filters of orders 48 and 96
were obtained having transition bandwidths 0.1 and 0.05, respectively.
Following the design procedures given in Sections III-A and III-B,
respectively, a first-order APT-based VDF was realized using the
prototype filter of order 48, and a second-order APT-based VDF was
realized using the prototype filter of order 96. Fig. 2(a) shows few
different low-pass frequency responses that were obtained from the
first-order APT-based VDF using (3). Similarly, Fig. 2(b) shows few
different bandpass frequency responses that were obtained from the
second-order APT-based VDF using (4)–(7).
B. Implementation Results
In this section, hardware implementation results for the
first- and second-order APT-based VDFs are presented. Similar
to the illustrative example presented in Section IV-A, the desired
passband and stopband peak ripple specifications were chosen as
0.05 and −45 dB, respectively. To study the trends in resource
utilization, power consumption, and operating frequency with respect
to the prototype filter order, three half-band low-pass filters of
orders 24, 48, and 96 were designed with the transition band-
widths 0.2, 0.1, and 0.05, respectively, using the MATLAB filter
design tool. The passband and stopband ripple specifications
Fig. 3. (a) APT-based VDF: modified pipelined hardware implementation
architecture. (b) First-order all-pass filter: modified pipelined hardware imple-
mentation architecture. (c) Second-order all-pass filter: modified pipelined
hardware implementation architecture.
of all the three filters were kept identical. In addition, the transition
bandwidths were selected such that proportionate filter orders are
achieved to enable easy understanding of the observed trends. These
three low-pass filters were subsequently used as prototype filters to
design three first-order and three second-order APT-based VDFs.
Let VDF-I-A, VDF-I-B, and VDF-I-C denote the first-order
APT-based VDFs and VDF-II-A, VDF-II-B, and VDF-II-C denote
the second-order APT-based VDFs designed with prototype filters of
orders 24, 48, and 96, respectively.
All six APT-based VDFs were implemented in Xilinx Virtex-6
(xc6vlx240t-1ff1156) field-programmable gate array (FPGA) using
the conventional implementation architectures shown in Fig. 1(a)–(c).
For all the VDF implementations discussed in this design
example, the bit-lengths for the different computational blocks
were kept constant. These bit-lengths were selected by verify-
ing that the resultant frequency responses satisfied the desired
passband and stopband peak ripple specifications. In addition,
digital signal processing block inference was disabled since
the fixed filter coefficients and the complex VDF architec-
tures do not gain any significant benefits from their use [19].
Table II shows the implementation results for the six VDFs obtained
after placement and routing. It was observed that as the prototype
filter order increased, the maximum operating frequencies of the
first- and second-order APT-based VDFs decreased proportionately.
This was due to increase in length of the resultant critical data
paths. This dependence of operating frequency of the APT-based
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 5, MAY 2016
TABLE II
FPGA I MPLEMENTATION R ESULTS : F IRST - AND S ECOND -O RDER APT-BASED VDF D ESIGNS
TABLE III
FPGA I MPLEMENTATION R ESULTS : P IPELINED F IRST - AND S ECOND -O RDER APT-BASED VDF D ESIGNS
VDFs on the prototype filter order can be a major bottleneck if high
operating frequencies are desired along with the stringent perfor-
mance specifications, which necessitate the use of higher order
prototype filters. To eliminate the dependence of operating frequency
on the prototype filter order, we propose modified hardware imple-
mentation architectures, as shown in Fig. 3(a)–(c). When compared
with the conventional architectures in Fig. 1(a)–(c), the proposed
architectures contain additional delay elements (registers), which
enable pipelined implementations and provide constant critical data
paths that are independent of the prototype filter order [20].
To compare the proposed pipelined implementation architectures
[Fig. 3(a)–(c)] with the conventional nonpipelined architectures
[Fig. 1(a)–(c)], the six APT-based VDFs were reimplemented in the
same FPGA using the pipelined architectures. To ensure that there
is fair comparison and no difference in factors, such as coefficient
sensitivity and roundoff noise, the same design options were selected
during placement and routing for both nonpipelined as well as the
pipelined implementations. (For all the implemented designs, the
word-length and fraction-length for filter coefficients and multiplier
blocks were kept constant at 16 and 14, respectively, whereas those
for adder and subtractor blocks were kept constant at 26 and 24,
respectively.) Table III shows the pipelined implementation results
of the six APT-based VDFs. Note that in Table III, VDF-I-A-P
denotes pipelined version of VDF-I-A and so on. For the pipelined
implementations of both the first- and second-order APT-based VDFs,
the same critical data path comprising of two adders and one
multiplier was observed. It is independent of the different orders of
prototype filters used and is fixed for all the implemented designs,
which can also be verified from Fig. 3(a)–(c). The same critical data
path length in the pipelined implementations thus resulted in similar
maximum operating frequencies for all the six APT-based VDFs,
as can be noted from Table III. The average maximum frequency
achieved for the pipelined APT-based VDFs was 100.04 MHz.
It can be concluded that maximum operating frequency of the first-
and the second-order-APT-based VDFs can be independent of the
prototype filter order if the proposed pipelined hardware implemen-
tation architectures are used. Thus, implementation of high-speed
APT-based VDFs can be achieved using the proposed architectures
for higher order prototype filters as well. From Tables II and III,
it can be noted that for both the first-and second-order APT-based
VDFs, the pipelined implementations show slightly higher values
of number of occupied slices and dynamic power when compared
with the nonpipelined implementations. These increased values are
2011
due to usage of additional pipelining registers in the pipelined
implementation architectures. This is an expected tradeoff between
significant advantages for the maximum operating frequencies and
marginal increase in number of occupied slices (and thus dynamic
power) for the different VDF designs. It is to be noted that the
static power (device start-up and configuration power) is a property
of the FPGA device used and is constant at 3.45 W for all the
implemented VDF designs. The proposed pipelined hardware imple-
mentation architectures lead to a latency of 2 N clock periods in the
implementations of both the first- and second-order APT-based VDFs.
However, as the pipelined VDF implementations achieve significantly
high operating frequencies, this latency is negligible as it contributes
to only a minor initial delay for the arrival of the first output.
V. C ONCLUSION
In this brief, we proposed the generalized design procedures and
modified pipelined hardware implementation architectures for the
first- and second-order APT-based VDFs. Multiple first- and second-
order APT-based VDFs were designed, and their FPGA imple-
mentation results obtained using the conventional nonpipelined and
the proposed pipelined implementation architectures were presented.
An analysis of the results showed that the proposed pipelined imple-
mentation architectures enabled high operating frequencies that were
independent of the different prototype filter orders, for both the first-
and second-order APT-based VDF designs. An average maximum
operating frequency of 100.04 MHz was obtained. The objective of
the work presented in this brief was to achieve implementation of
high-speed APT-based VDFs. The scope of the work presented in
this brief was, therefore, limited to design and FPGA implemen-
tation of APT-based VDFs using the conventional and proposed
implementation architectures, and their comparative analysis with
respect to the parameters—resource utilization, power consumption,
and operating frequency. The future work will involve an analysis
of the pipelined APT-based VDF implementations based on factors,
such as coefficient sensitivity and roundoff noise.
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