module updownmod(clk,rst,count);

input clk,rst;
output [2:0] count;
reg [1:0] state;
reg [3:0] count;
parameter ZEROA=2'b00, UPA=2'b01, ZEROB=2'b10, UPB=2'b11;
always @ (posedge clk or posedge rst)
begin
if(rst) state<=ZEROA;
else
case(state)
ZEROA:state<=UPA;
UPA:state<=(count==7)?ZEROB:UPA;
ZEROB:state<=UPB;
UPB:state<=(count==15)?ZEROA:UPB;
endcase
end
always @ (posedge clk or posedge rst)
begin
if(rst) count<=0;
else
case(state)
ZEROA:count<=0;
UPA:count<=count+1;
ZEROB:count<=10;
UPB:count<=count+1;
endcase
end
endmodule